Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device manufacturing method that can prevent a decrease in the impurity concentration in an n-type well region directly below wiring and prevent the occurrence of a leak path.SOLUTION: A manufacturing method for a semiconductor device includes the steps of forming a well region of a second conductivity type on the upper surface side of a semiconductor substrate of a first conductivity type, forming a plurality of channel formation regions of the first conductivity type on the upper surface side of the well region, forming a plurality of drift regions of the second conductivity type alternately with the plurality of channel formation regions on the upper surface side of the well region, forming a plurality of gate electrodes on the upper surface side of the channel formation regions via a gate insulating film, and forming wiring above the well region. The step of forming the well region includes forming a plurality of slit-shaped first ion implantation regions having different widths, forming a second ion implantation region at an end side of the relatively narrow first ion implantation region and at a position overlapping the wiring, and forming the well region by heat treatment.SELECTED DRAWING: Figure 8A

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a lateral MOSFET in which a plurality of source regions and drain regions are arranged alternately along the lateral direction (gate length direction) perpendicular to the longitudinal direction of the gate electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-233056 Summary of the Invention [Problem to be solved by the invention]

[0004] In semiconductor devices such as lateral MOSFETs, an n-type well region that constitutes a breakdown voltage structure is provided on the upper surface side of a p-type semiconductor substrate. When forming the n-type well region, n-type impurity ions are implanted in multiple slits to adjust the impurity concentration of the n-type well region, and the implanted n-type impurities are activated by heat treatment to form a single n-type well region.

[0005] However, if there are thin sections in the slit-shaped ion implantation region, the implanted n-type impurities may not be diffused sufficiently laterally, resulting in the formation of a locally low impurity concentration region in the n-type well region.If wiring overlaps this low impurity concentration region, a channel will form on the surface of the low impurity concentration region, creating a leakage path.

[0006] In view of the above problems, the present disclosure aims to provide a semiconductor device and a manufacturing method thereof that can prevent a decrease in the impurity concentration of an n-type well region directly below wiring and prevent the occurrence of a leak path. [Means for solving the problem]

[0007] According to one aspect of the present disclosure, there is provided a semiconductor substrate having a first conductivity type, a well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, a plurality of channel formation regions of the first conductivity type provided on the upper surface side of the well region and extending parallel to each other in one direction in a plan view, a plurality of drift regions of a second conductivity type provided on the upper surface side of the well region alternately with the plurality of channel formation regions and extending parallel to each other in one direction, a carrier supply region of the second conductivity type provided on the upper surface side of each of the plurality of channel formation regions, a carrier receiving region of the second conductivity type provided on the upper surface side of each of the plurality of drift regions, and a carrier supply region. The semiconductor device comprises a plurality of gate electrodes extending parallel to one another in one direction and provided via a gate insulating film on the upper surface side of a channel formation region sandwiched between a supply region and a well region, and wiring provided above the well region and extending in a direction perpendicular to the one direction at end sides of the plurality of channel formation regions and plurality of drift regions in the one direction, wherein the impurity concentration of the well region at the end side of the channel formation region sandwiched between adjacent drift regions and at a position overlapping with the wiring is equal to or higher than the impurity concentration of the well region at the end side of the plurality of drift regions and at a position overlapping with the wiring.

[0008] The gist of the method for manufacturing a semiconductor device is that the step of forming the well region includes forming a plurality of first ion implantation regions, each extending parallel to one another in one direction and having different widths, by ion implanting impurities of a second conductivity type, and forming a second ion implantation region, extending in a direction perpendicular to the one direction, at an end side of a first ion implantation region having a relatively narrow width among the plurality of first ion implantation regions and at a position overlapping the wiring, and laterally diffusing the impurities implanted in the first ion implantation region and the second ion implantation region by heat treatment to form the well region. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide a semiconductor device and a manufacturing method thereof that can prevent a decrease in the impurity concentration in the n-type well region directly below the wiring and prevent the occurrence of a leak path. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along the line AA′ in FIGS. 2 and 3. [Figure 5] FIG. 4 is a cross-sectional view taken along line BB′ in FIGS. 2 and 3. [Figure 6] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8A] 1A and 1B are plan views illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Figure 8B] 1A and 1B are plan views illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Figure 9] FIG. 8C is a cross-sectional view taken along line AA′ in FIGS. 8A and 8B. [Figure 10] FIG. 8C is a cross-sectional view taken along line BB′ in FIGS. 8A and 8B. [Figure 11] FIG. 7 is a cross-sectional view continuing from FIG. 6 for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 12 is a cross-sectional view taken along line AA' in FIGS. 8A and 8B at the stage of FIG. 11. FIG. [Figure 13] 12 is a cross-sectional view taken along line BB' in FIGS. 8A and 8B at the stage of FIG. 11. FIG. [Figure 14] 12 is a cross-sectional view continuing from FIG. 11 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 15] FIG. 15 is a cross-sectional view continuing from FIG. 14 for illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16]FIG. 16 is a cross-sectional view continuing from FIG. 15 for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] FIG. 2 is a cross-sectional view of a semiconductor device according to a first comparative example. [Figure 18] 5A and 5B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first comparative example. [Figure 19] FIG. 10 is a plan view illustrating a method for manufacturing a semiconductor device according to a second comparative example. [Figure 20] FIG. 10 is a plan view illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 21] FIG. 10 is a plan view illustrating a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, first to third embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios are included between the drawings. Furthermore, the first to third embodiments shown below exemplify devices and methods for embodying the technical idea of ​​the present disclosure, and the technical idea of ​​the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0012] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field-effect transistor (FET) or static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). In addition, the anode region serves as the carrier supply region in a diode, static induction (SI) thyristor, or gate turn-off (GTO) thyristor. In addition, the term "carrier receiving region" refers to a semiconductor region that receives majority carriers constituting the main current, such as the drain region of a FET or SIT, or the collector region of an IGBT. In a diode, SI thyristor, or GTO thyristor, the cathode region functions as the carrier receiving region.

[0013] Furthermore, the definitions of directions such as up and down in this specification are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] In this specification, the first conductivity type is p-type and the second conductivity type is n-type. However, the conductivity types may be reversed, with the first conductivity type being n-type and the second conductivity type being p-type. The "+" and "-" affixed to "n" and "p" indicate a semiconductor region with a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without the "+" and "-" affixed. However, semiconductor regions with the same "n" and "n" affixed do not necessarily have the same impurity concentration. Furthermore, in the following description, components and regions with the "first conductivity type" and "second conductivity type" affixed refer to components and regions made of semiconductor materials, even if not otherwise explicitly stated.

[0015] (First embodiment) <Structure of semiconductor device> As an example of the semiconductor device according to the first embodiment, a lateral n-channel metal oxide semiconductor field effect transistor (MOSFET) is shown. In the semiconductor device according to the first embodiment, as shown in FIG. 1, a plurality of transistor cells T1 to T6 are arranged in an array. Although FIG. 1 shows an example of an arrangement of six transistor cells T1 to T6, the number of transistor cells arranged is not particularly limited. The withstand voltage of the semiconductor device according to the first embodiment is, for example, about 60 V or more.

[0016] The semiconductor device according to the first embodiment includes a first conductivity type (p-type) semiconductor substrate 1. The semiconductor substrate 1 is formed of a semiconductor substrate such as a silicon (Si) substrate. The semiconductor substrate 1 may also be formed of a semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), diamond, or the like. The semiconductor substrate 1 may also be a p-type semiconductor region (semiconductor layer) formed on the upper surface of a p-type or n-type semiconductor substrate.

[0017] The upper surface (upper portion) of the semiconductor substrate 1 is provided with a second conductivity type (n - A deep N-type well region (DNW) 2 is provided. A plurality of p-type channel formation regions (well regions) 3a-3d are provided spaced apart on the upper surface side (upper part) of the well region 2. A plurality of n-type drift regions 4a-4c having a higher impurity concentration than the well region 2 are provided spaced apart on the upper surface side (upper part) of the well region 2. The plurality of drift regions 4a-4c are provided alternately with the plurality of channel formation regions 3a-3d.

[0018] The upper surface (top) of the channel forming region 3a is + Contact regions 7a and n +A carrier supply region (source region) 8a is provided on the semiconductor substrate 1. The contact region 7a and the source region 8a are in contact with each other. The impurity concentration of the contact region 7a is higher than the impurity concentration of the channel formation region 3a. The contact region 7a is connected to a source electrode 22 provided on the upper surface of the interlayer insulating film 32 through a via 22a that penetrates the interlayer insulating film 32 provided on the upper surface of the semiconductor substrate 1. The source region 8a is connected to the source electrode 22 through a via 22b that penetrates the interlayer insulating film 32. The source electrode 22 is covered with a protective insulating film 33 that is provided on the upper surface of the interlayer insulating film 32.

[0019] The interlayer insulating film 32 may be, for example, a non-doped silicon oxide film (SiO2 film) called "NSG" that does not contain phosphorus (P) or boron (B). Alternatively, the interlayer insulating film 32 may be a silicon oxide film doped with phosphorus (PSG film), a silicon oxide film doped with boron (BSG film), a silicon oxide film doped with boron and phosphorus (BPSG film), a silicon nitride film (Si3N4 film), or a laminate film of these. The protective insulating film 33 may be, for example, a resin such as polyimide.

[0020] The upper surface (upper portion) of the drift region 4a is provided with n-type impurity layers having a higher impurity concentration than the drift region 4a. + A carrier-receiving region (drain region) 9a is provided in the interlayer insulating film 32. The drain region 9a is connected to a drain electrode 23 provided on the upper surface of the interlayer insulating film 32 via a via 23a that penetrates the interlayer insulating film 32. An insulating film (element isolation insulating film) 31 is provided on both side surfaces of the drift region 4a and the drain region 9a.

[0021] The element isolation insulating film 31 is made of an oxide film such as a local insulating film (LOCOS film) formed selectively (locally) by the local oxidation of silicon (LOCOS) method.

[0022] A gate electrode 11a is provided via a gate insulating film 10a on the upper surface side of the channel formation region 3a sandwiched between the source region 8a and the drain region 9a and the well region 2. Sidewall insulating films 12a are provided on both side surfaces of the gate electrode 11a.

[0023] The gate insulating film 10a may be, for example, a silicon oxide film (SiO2 film), a silicon oxynitride film (SiON film), a strontium oxide film (SrO film), a silicon nitride film (Si3N4 film), an aluminum oxide film (Al2O3 film), a magnesium oxide film (MgO film), an yttrium oxide film (YO3 film), a hafnium oxide film (HfO2 film), a zirconium oxide film (ZrO2 film), a tantalum oxide film (Ta2O5 film), or a bismuth oxide film (Bi2O3 film), or a composite film formed by stacking two or more of these films.The gate electrode 11a may be made of a polysilicon layer (doped polysilicon layer) doped with a high concentration of p-type impurities such as boron (B) or n-type impurities such as phosphorus (P), or a high-melting-point metal.

[0024] The upper surface (top) of the channel forming region 3b is + Type carrier supply region (source region) 8b, p + contact region 7b, and + A carrier supply region (source region) 8c is provided. The source region 8b and the contact region 7b are in contact with each other. The contact region 7b and the source region 8c are in contact with each other. The source region 8b is connected to a source electrode 24 provided on the upper surface side of the interlayer insulating film 32 through a via 24a that penetrates the interlayer insulating film 32. The impurity concentration of the contact region 7b is higher than the impurity concentration of the channel formation region 3b. The contact region 7b is connected to the source electrode 24 through a via 24b that penetrates the interlayer insulating film 32. The source region 8c is connected to the source electrode 24 through a via 24c that penetrates the interlayer insulating film 32. The source electrode 24 is covered with a protective insulating film 33.

[0025] A gate electrode 11b is provided via a gate insulating film 10b on the upper surface side of the channel formation region 3b sandwiched between the drain region 9a and the source region 8b and the well region 2. Sidewall insulating films 12b are provided on both side surfaces of the gate electrode 11b.

[0026] The upper surface (top) of the drift region 4b is provided with an n-type impurity layer having a higher impurity concentration than the drift region 4b. + A carrier-receiving region (drain region) 9b is provided in the drift region 4b. The drain region 9b is connected to a drain electrode 25 provided on the upper surface of the interlayer insulating film 32 via a via 25a that penetrates the interlayer insulating film 32. An element isolation insulating film 31 is provided on both side surfaces of the drift region 4b and the drain region 9b.

[0027] A gate electrode 11c is provided via a gate insulating film 10c on the upper surface side of the channel formation region 3b sandwiched between the source region 8c and the drain region 9b and the well region 2. Sidewall insulating films 12c are provided on both side surfaces of the gate electrode 11c.

[0028] The upper surface (top) of the channel forming region 3c is + Type carrier supply region (source region) 8d, p + Type contact regions 7c and n + A carrier supply region (source region) 8e is provided. The source region 8d and the contact region 7c are in contact with each other. The contact region 7c and the source region 8e are in contact with each other. The source region 8d is connected to a source electrode 26 provided on the upper surface side of the interlayer insulating film 32 through a via 26a that penetrates the interlayer insulating film 32. The impurity concentration of the contact region 7c is higher than the impurity concentration of the channel formation region 3c. The contact region 7c is connected to the source electrode 26 through a via 26b that penetrates the interlayer insulating film 32. The source region 8e is connected to the source electrode 26 through a via 26c that penetrates the interlayer insulating film 32. The source electrode 26 is covered with a protective insulating film 33.

[0029] A gate electrode 11d is provided, via a gate insulating film 10d, on the upper surface side of the channel formation region 3c sandwiched between the drain region 9b and the source region 8d and the well region 2. Sidewall insulating films 12d are provided on both side surfaces of the gate electrode 11d.

[0030] The upper surface (upper portion) of the drift region 4c is provided with an n-type impurity layer having a higher impurity concentration than the drift region 4c. + A carrier-receiving region (drain region) 9c is provided in the drift region 4c. The drain region 9c is connected to a drain electrode 27 provided on the upper surface of the interlayer insulating film 32 through a via 27a that penetrates the interlayer insulating film 32. An element isolation insulating film 31 is provided on both side surfaces of the drift region 4c and the drain region 9c.

[0031] A gate electrode 11e is provided via a gate insulating film 10e on the upper surface side of the channel formation region 3c sandwiched between the source region 8e and the drain region 9c and the well region 2. Sidewall insulating films 12e are provided on both side surfaces of the gate electrode 11e.

[0032] The upper surface (top) of the channel forming region 3d is + Type carrier supply region (source region) 8f and p + A contact region 7d is provided on the upper surface of the interlayer insulating film 32. The source region 8f and the contact region 7d are in contact with each other. The source region 8f is connected to a source electrode 28 provided on the upper surface of the interlayer insulating film 32 through a via 28a that penetrates the interlayer insulating film 32. The impurity concentration of the contact region 7d is higher than the impurity concentration of the channel formation region 3d. The contact region 7d is connected to the source electrode 28 through a via 28b that penetrates the interlayer insulating film 32. The source electrode 28 is covered with a protective insulating film 33.

[0033] A gate electrode 11f is provided via a gate insulating film 10f on the upper surface side of the channel formation region 3d sandwiched between the drain region 9c and the source region 8f and the well region 2. Sidewall insulating films 12f are provided on both side surfaces of the gate electrode 11f.

[0034] Transistor cell T1 includes a contact region 7a, a source region 8a, a drain region 9a, and a gate electrode 11a. Transistor cell T2 has a structure that is symmetrical to transistor cell T1 with respect to the drain region 9a. Transistor cell T2 includes a contact region 7b, a source region 8b, a drain region 9a, and a gate electrode 11b. The drain region 9a is shared by transistor cells T1 and T2.

[0035] The transistor cell T3 has a structure that is symmetrical to the transistor cell T2 with respect to the contact region 7b. The transistor cell T3 includes the contact region 7b, a source region 8c, a drain region 9b, and a gate electrode 11c. The contact region 7b is shared by the transistor cells T2 and T3.

[0036] The transistor cell T4 has a structure that is symmetrical to the transistor cell T3 with respect to the drain region 9b. The transistor cell T4 includes a contact region 7c, a source region 8d, a drain region 9b, and a gate electrode 11d. The drain region 9b is shared by the transistor cells T3 and T4.

[0037] The transistor cell T5 has a structure that is symmetrical to the transistor cell T4 with respect to the contact region 7c. The transistor cell T5 includes the contact region 7c, a source region 8e, a drain region 9c, and a gate electrode 11d. The contact region 7c is shared by the transistor cells T4 and T5.

[0038] The transistor cell T6 has a structure symmetrical to the transistor cell T5 with respect to the drain region 9c. The transistor cell T6 includes a contact region 7d, a source region 8f, a drain region 9c, and a gate electrode 11f. The drain region 9c is shared by the transistor cells T5 and T6.

[0039] A p-type well region 5 having a higher impurity concentration than the semiconductor substrate 1 is provided on the upper surface side (upper portion) of the semiconductor substrate 1, outside the well region 2. + 1. A mold contact region 6 is provided. The contact region 6 is connected to substrate contact electrodes 21, 29 provided on the upper surface of the interlayer insulating film 32 through vias 21a, 29a that penetrate the interlayer insulating film 32. The substrate contact electrodes 21, 29 may be connected to each other on the front and back sides of FIG. 1. The substrate contact electrodes 21, 29 are covered with a protective insulating film 33. An element isolation insulating film 31 is provided on both side surfaces of the well region 5 and the contact region 6.

[0040] Fig. 2 is a plan view of a portion of the semiconductor device according to the first embodiment shown in Fig. 1. The cross section taken along line CC' in Fig. 2 corresponds to a portion including transistor cells T1 to T4 on the left side of the cross section in Fig. 1. Fig. 2 does not illustrate the interlayer insulating film 32, protective insulating film 33, vias 21a, 22a, 22b, 23a, 24a to 24c, 25a, substrate contact electrode 21, source electrodes 22 and 24, and drain electrodes 23 and 25 shown in Fig. 1.

[0041] As shown in FIG. 2, the gate electrodes 11a to 11d have a striped planar pattern extending parallel to one another in one direction (the vertical direction in FIG. 2). Gate wiring 42 is provided above the ends of the gate electrodes 11a to 11d. The gate wiring 42 has a striped planar pattern extending in a direction (the horizontal direction in FIG. 2) perpendicular to the extension direction of the gate electrodes 11a to 11d. The gate wiring 42 is electrically connected to the gate electrodes 11a to 11d. Note that the gate electrodes 11e and 11f shown in FIG. 1 also have striped planar patterns extending parallel to one another in one direction (the vertical direction in FIG. 2) like the gate electrodes 11a to 11d, and are electrically connected to the gate wiring 42.

[0042] The wiring 41 is provided at a distance from the gate wiring 42. The wiring 41 has a striped planar pattern extending parallel to the extension direction of the gate wiring 42 (the left-right direction in FIG. 2). The wiring 41 may be, for example, a source wiring connected to the source electrodes 22, 24, 26, and 28 shown in FIG. 1. Alternatively, the wiring 41 may be a drain wiring connected to the drain electrodes 23, 25, and 27 shown in FIG. 1. The wiring 41 may be a wiring to which a potential other than that of a source wiring or a drain wiring is applied.

[0043] The element isolation insulating film 31 has openings 31a to 31e. In FIG. 2, the hidden portions of the openings 31a and 31c in the element isolation insulating film 31 directly below the gate electrodes 11a to 11c are schematically shown by dashed lines. The contact region 7a and the source region 8a are exposed in the opening 31a in the element isolation insulating film 31. The drain region 9a is exposed in the opening 31b in the element isolation insulating film 31. The contact region 7b and the source regions 8a and 8c are exposed in the opening 31c in the element isolation insulating film 31. The drain region 9b is exposed in the opening 31d in the element isolation insulating film 31. The contact region 6 is exposed in the opening 31e in the element isolation insulating film 31.

[0044] 3 is a plan view showing a position similar to the plane of the semiconductor device according to the first embodiment shown in FIG. - The p-type well region 2, p-type channel forming regions 3a and 3b, p-type connection region 3e, and p-type well region 5 are schematically shown by solid lines.

[0045] As shown in FIG. 3, the well region 2 has a substantially rectangular planar pattern. The channel formation regions 3a and 3b are provided inside the well region 2. The channel formation regions 3a and 3b have a striped planar pattern extending in the extension direction of the gate electrodes 11a to 11d (the vertical direction in FIG. 3). The connection region 3e is connected to the ends of the channel formation regions 3a and 3b in the extension direction. The connection region 3e has a striped planar pattern extending in a direction perpendicular to the extension direction of the gate electrodes 11a to 11d (the horizontal direction in FIG. 3). Like the channel formation regions 3a and 3b, the channel formation regions 3c and 3d shown in FIG. 1 also have a striped planar pattern extending in the extension direction of the gate electrodes 11a to 11d (the vertical direction in FIG. 3) and are connected to the connection region 3e. The well region 5 has a ring-shaped planar pattern surrounding the periphery of the well region 2.

[0046] 1 also have a striped planar pattern extending in the direction in which the gate electrodes 11a to 11d extend (the vertical direction in FIG. 3), although this is not shown in FIG. 3. The ends of the drift regions 4a to 4c are located inside the well region 2.

[0047] 3, the position of the end of the well region 2, which is on the end side in the extension direction of the gate electrode 11a and the channel formation region 3a and overlaps with the wiring 41, is indicated by a dashed line area A1. The position of the end of the well region 2, which is on the end side in the extension direction of the gate electrode 11b and the channel formation region 3b and overlaps with the wiring 41, is indicated by a dashed line area A2. The position of the end of the well region 2, which is on the end side in the extension direction of the gate electrode 11c and the channel formation region 3b and overlaps with the wiring 41, is indicated by a dashed line area A3.

[0048] In the semiconductor device according to the first embodiment, the impurity concentration of the well region 2 at positions indicated by dashed-line regions A2 and A3 is equal to or higher than the impurity concentration of the well region 2 at positions other than those indicated by dashed-line regions A2 and A3 that overlap with the wiring 41. For example, the impurity concentration of the well region 2 at positions indicated by dashed-line regions A2 and A3 is equal to or higher than the impurity concentration of the well region 2 at positions indicated by dashed-line region A1. Furthermore, the impurity concentration of the well region 2 at positions indicated by dashed-line regions A2 and A3 is equal to or higher than the impurity concentration of the well region 2 at the end sides in the extension direction of the drift regions 4a to 4c and at positions that overlap with the wiring 41.

[0049] 4 shows a cross section taken along line AA' passing through the gate electrode 11a in FIGS. 2 and 3. As shown in FIGS. 3 and 4, the end of the channel formation region 3a is located outside the end of the gate electrode 11a in the extension direction of the gate electrode 11a. The end of the well region 2 is located outside the end of the channel formation region 3a and overlaps with the wiring 41. An element isolation insulating film 31 is provided on the upper surface side of the end of the channel formation region 3a and the end of the well region 2. A dashed line area A1 surrounds the surface of the end of the well region 2.

[0050] 5 shows a cross section taken along line BB' passing through the gate electrode 11b in FIGS. 2 and 3. As shown in FIGS. 3 and 5, the end of the channel formation region 3b is located outside the end of the gate electrode 11b in the extension direction of the gate electrode 11b. The end of the well region 2 is located outside the end of the channel formation region 3b and overlaps with the wiring 41. An element isolation insulating film 31 is provided on the upper surface side of the end of the channel formation region 3b and the end of the well region 2. The dashed line area A2 surrounds the surface of the end of the well region 2.

[0051] 3 to 5 is adjusted so that the impurity concentration of well region 2 at positions indicated by dashed-line regions A2 and A3 is equal to or higher than the impurity concentration of well region 2 at positions other than those indicated by dashed-line regions A2 and A3 that overlap with wiring 41. Therefore, even if a potential is applied to wiring 41, it is possible to prevent the formation of a channel on the surface of well region 2 at positions indicated by dashed-line regions A2 and A3, thereby preventing the occurrence of a leak path.

[0052] <Method of manufacturing a semiconductor device> Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described. Here, the description will be mainly focused on the cross section of the semiconductor device shown in Fig. 1. Note that the method for manufacturing the semiconductor device described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be implemented within the scope of the spirit of the claims.

[0053] First, a p-type semiconductor substrate 1 (see FIG. 6) is prepared. A photoresist film is applied to the upper surface of the semiconductor substrate 1, and the photoresist film is patterned using photolithography. The patterned photoresist film is used as an ion implantation mask to implant n - Then, n-type impurity ions such as phosphorus (P) are implanted to form a well region 2. Thereafter, the photoresist film is removed.

[0054] Next, a photoresist film is applied to the upper surface of the semiconductor substrate 1, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as boron (B) are implanted to form p-type channel formation regions 3a to 3d and p-type well region 5. Thereafter, the photoresist film is removed.

[0055] Next, a photoresist film is applied to the upper surface of the semiconductor substrate 1, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as phosphorus (P) are implanted to form n-type drift regions 4a-4c. The photoresist film is then removed. Note that the order of the ion implantation to form the well region 2, the ion implantation to form the p-type channel formation regions 3a-3d and the p-type well region 5, and the ion implantation to form the n-type drift regions 4a-4c is not limited.

[0056] Figure 6 shows the - Regions (ion-implanted regions) 2a to 2g into which n-type impurity ions are implanted to form the n-type well region 2 are schematically shown by dashed lines. - 6 is shown superimposed on the n-type well region 2. For example, up to a breakdown voltage of about 50 V, one ion implantation region is formed to form the well region 2. On the other hand, for a breakdown voltage of about 60 V or more, the impurity concentration of the well region 2 needs to be lowered, so multiple ion implantation regions of n-type impurities to form the well region 2 are formed in a slit shape. Then, by heat treatment, the implanted n-type impurities are diffused laterally to form one well region 2.

[0057] As shown in Figures 6 and 7, ion implantation region 2a is formed with a width w11 at a position overlapping channel formation region 3a. Ion implantation region 2b is formed with a width w21 wider than w11 at a position overlapping drift region 4a. Ion implantation region 2c is formed with a width w31 narrower than w11 and w21 at a position overlapping channel formation region 3b. Ion implantation region 2d is formed with a width w22 approximately equal to w21 at a position overlapping drift region 4b. Ion implantation region 2e is formed with a width w32 approximately equal to w31 at a position overlapping channel formation region 3c. Ion implantation region 2f is formed with a width w23 approximately equal to w21 and w22 at a position overlapping drift region 4c. Ion implantation region 2g is formed with a width w12 approximately equal to w11 at a position overlapping channel formation region 3d.

[0058] 8A is a plan view at the stage of FIG. 6, and ion implantation regions 2a-2d, 2x are schematically shown by dashed lines and hatched diagonally downward to the right. Furthermore, in FIG. 8A, ion implantation regions 3x-3z for forming p-type channel formation regions 3a, 3b and p-type connection region 3e, and ion implantation region 5x for forming p-type well region 5 are schematically shown by dashed lines. Furthermore, in FIG. 8A, gate electrodes 11a-11d, wiring 41, and gate wiring 42, which will be formed in a later process, are also schematically shown by dashed lines.

[0059] The ion implantation regions 2a to 2d have a stripe-shaped planar pattern extending in the direction in which the gate electrodes 11a to 11d extend (the vertical direction in FIG. 8A).

[0060] The ion implantation region 2x is formed on the end side of the ion implantation region 2c, which has a relatively narrow width w31 among the ion implantation regions 2a to 2d, so as to overlap with the wiring 41. The ion implantation region 2x has a striped planar pattern extending in a direction (left-right direction in FIG. 8A) perpendicular to the extension direction of the ion implantation region 2c. The ion implantation region 2x and the ion implantation region 2c form a T-shaped planar pattern. The ion implantation region 2x is separated from the ion implantation regions 2b and 2d.

[0061] The length L1 of the ion implantation region 2x in the extension direction can be adjusted as appropriate within the range of separation from the ion implantation regions 2b and 2d. The width w2 of the ion implantation region 2x in the direction perpendicular to the extension direction can be adjusted as appropriate. Note that FIG. 8A illustrates an example in which the width w2 of the ion implantation region 2x is narrower than the width w1 of the wiring 41, but the width w2 of the ion implantation region 2x may be the same as or wider than the width w1 of the wiring 41. Also, FIG. 8A illustrates an example in which the entire ion implantation region 2x overlaps the wiring 41, but it is also possible for only a portion of the ion implantation region 2x to overlap the wiring 41, with the other portion of the ion implantation region 2x being located outside the wiring 41.

[0062] 6 also have a striped planar pattern extending in the extension direction of the gate electrodes 11a-11d (the vertical direction in FIG. 8A), similar to the ion implantation regions 2a-2d. Furthermore, an ion implantation region similar to the ion implantation region 2x is connected to the end of the ion implantation region 2e, which has a relatively narrow width w32. Furthermore, the ion implantation region 5x for forming the p-type well region 5, which is not hatched with diagonal lines slanting downward to the right, has a circular planar pattern.

[0063] In Figure 8A, the ion implantation regions 2a to 2d, 2x are hatched with diagonal lines slanting downward to the right, whereas in Figure 8B, the ion implantation regions 3x to 3z for forming p-type channel formation regions 3a, 3b and p-type connection region 3e are schematically shown with diagonal lines slanting downward to the right.

[0064] The ion implantation regions 3x and 3y have a striped planar pattern extending in the extension direction of the gate electrodes 11a to 11d (the vertical direction in FIG. 8B). The ion implantation region 3z has a planar pattern including striped portions extending in the extension direction of the ion implantation regions 3x and 3y (the vertical direction in FIG. 8B) and striped portions extending in a direction perpendicular to the extension direction of the ion implantation regions 3x and 3y (the horizontal direction in FIG. 8B).

[0065] A cross section taken along line AA' in Figures 8A and 8B is shown in Figure 9. As shown in Figure 9, ion implantation regions 3x and 3z for forming a p-type channel formation region 3a and a p-type connection region 3e, and an ion implantation region 5x for forming a p-type well region 5 are formed in the upper part of the semiconductor substrate 1.

[0066] 10 shows a cross section taken along line BB' in FIGS. 8A and 8B. As shown in FIG. 10, ion implantation regions 3y and 3z for forming p-type channel formation regions 3a and 3e, and an ion implantation region 5x for forming a p-type well region 5 are formed in the upper part of the semiconductor substrate 1. Furthermore, an n - An ion implantation region 2x for forming a mold well region 2 is formed.

[0067] After the ion implantation for forming the well region 2, the ion implantation for forming the p-type channel formation regions 3a to 3d and the p-type well region 5, and the ion implantation for forming the n-type drift regions 4a to 4c, the p-type impurities and n-type impurities ion-implanted into the semiconductor substrate 1 are activated by heat treatment. As a result, the n-type impurities in the ion implantation regions 2a to 2g diffuse laterally, and one n-type impurity is formed on the upper surface side of the semiconductor substrate 1, as shown in FIG. -A well region 2 of a certain type is formed. Also, on the upper surface side of the well region 2, p-type channel formation regions 3a to 3d and n-type drift regions 4a to 4c are formed. Further, a p-type well region 5 is formed outside the well region 2 on the upper surface side of the semiconductor substrate 1. The cross-section taken along the A-A' line of FIGS. 8A and 8B at the stage of FIG. 11 corresponds to FIG. 12. Also, the cross-section taken along the B-B' line of FIGS. 8A and 8B at the stage of FIG. 11 corresponds to FIG. 13.

[0068] Note that the heat treatment for forming the well region 2, the heat treatment for forming the channel formation regions 3a to 3d and the well region 5, and the heat treatment for forming the drift regions 4a to 4c are not carried out together, and may be performed individually for each ion implantation.

[0069] Next, as shown in FIG. 14, an element isolation insulating film 31 is formed on the upper surface side of the semiconductor substrate 1 by the LOCOS method or the like. Next, a gate insulating film is formed on the upper surface side of the semiconductor substrate 1 by a thermal oxidation method or a chemical vapor deposition (CVD) method or the like. Further, a polysilicon layer (doped polysilicon layer) doped with a high concentration of n-type impurities or p-type impurities is deposited by a CVD method using a dopant gas or the like. Thereafter, a part of the doped polysilicon layer and the gate insulating film is selectively removed by photolithography technology and dry etching to form gate insulating films 10a to 10f and gate electrodes 11a to 11f (see FIG. 15). Further, sidewall insulating films 12a to 12f are formed on the side surfaces on both sides of the gate electrodes 11a to 11f by a CVD method and dry etching or the like. As a result, as shown in FIG. 15, gate electrodes 11a to 11f are formed on the upper surface side of the semiconductor substrate 1 via the gate insulating films 10a to 10f, and sidewall insulating films 12a to 12f are formed on the side surfaces on both sides of the gate electrodes 11a to 11f.

[0070] Next, by photolithography technology, ion implantation and heat treatment, as shown in FIG. 16, on the upper surface side of the channel formation regions 3a to 3d, + n-type source regions 8a to 8d and p + -type contact regions 7a to 7d are formed. Also, on the upper surface side of the drift regions 4a to 4c, n +The p-type drain regions 9a to 9c are formed on the upper surface side of the well region 5. + A mold contact area 6 is formed.

[0071] Next, an interlayer insulating film 32 is deposited by CVD or the like to cover the gate electrodes 11a-11f. Then, portions of the interlayer insulating film 32 are selectively removed by photolithography, dry etching, or the like to form contact holes exposing the top surfaces of the source regions 8a-8d, drain regions 9a-9c, contact regions 7a-7d, and contact region 6. Furthermore, the contact holes are filled with a metal film by sputtering, photolithography, dry etching, or the like to form vias 21a, 22a, 22b, 23a, 24a-24c, 25a, 26a-26c, 27a, 28a, 28b, 29a, substrate contact electrodes 21 and 29, source electrodes 22, 24, 26, 28, and drain electrodes 23, 25, and 27. A protective insulating film 33 is then formed to cover the substrate contact electrodes 21 and 29, source electrodes 22, 24, 26, 28, and drain electrodes 23, 25, and 27. In this way, the semiconductor device according to the first embodiment shown in FIG. 1 is completed.

[0072] Here, a semiconductor device according to a first comparative example will be described. FIG. 17 is a cross-sectional view of the semiconductor device according to the first comparative example. As shown in FIG. 17, the semiconductor device according to the first comparative example differs from the semiconductor device according to the first embodiment shown in FIG. 1 in that it is a lateral MOSFET that is not arrayed. The semiconductor device according to the first comparative example comprises a p-type semiconductor substrate 101 and an n-type semiconductor substrate 102 provided on the upper surface side of the semiconductor substrate 101. - The semiconductor device includes a p-type well region 102. On the upper surface side of the well region 102, p-type channel formation regions 103a and 103b are provided so as to be spaced apart from each other.

[0073] On the upper surface side of the channel forming region 103a, p + Contact regions 107a and n +A source region 108a is provided in the contact region 107a. The contact region 107a is connected to a source electrode 122 through a via 122a that penetrates an interlayer insulating film 132. The source region 108a is connected to the source electrode 122 through a via 122b that penetrates the interlayer insulating film 132. The source electrode 122 is covered with a protective insulating film 133.

[0074] An n-type drift region 104 is provided in the center of the upper surface of the well region 102. + A drain region 109 is provided in the drift region 104. The drain region 109 is connected to the drain electrode 123 through a via 123a that penetrates an interlayer insulating film 132. An element isolation insulating film 131 is provided on both side surfaces of the drift region 104 and the drain region 109.

[0075] A gate electrode 111a is provided via a gate insulating film 110a on the upper surface side of the well region 102 and the channel formation region 103a sandwiched between the source region 108a and the drain region 109. Sidewall insulating films 112a are provided on both side surfaces of the gate electrode 111a.

[0076] On the upper surface side of the channel forming region 103b, n + The source region 108b and p + A contact region 107b is provided on the source electrode 124. The source region 108b is connected to the source electrode 124 through a via 124a that penetrates the interlayer insulating film 132. The contact region 107b is connected to the source electrode 124 through a via 124b that penetrates the interlayer insulating film 132.

[0077] A gate electrode 111b is provided via a gate insulating film 110b on the upper surface side of the channel formation region 103b sandwiched between the drain region 109 and the source region 108b and the well region 102. Sidewall insulating films 112b are provided on both side surfaces of the gate electrode 111b.

[0078] The transistor cell T11 includes a contact region 107a, a source region 108a, a drain region 109, and a gate electrode 111a. The transistor cell T12 has a structure that is symmetrical to the transistor cell T11 with respect to the drain region 109. The transistor cell T12 includes a contact region 107b, a source region 108b, a drain region 109, and a gate electrode 111b. The drain region 109 is shared by the transistor cells T11 and T12.

[0079] A p-type well region 105 is provided on the upper surface side of the semiconductor substrate 101, outside the well region 102. + A mold contact region 106 is provided. The contact region 106 is connected to the substrate contact electrode 121 through a via 121a that penetrates an interlayer insulating film 132. An element isolation insulating film 131 is provided on both side surfaces of the well region 105 and the contact region 106.

[0080] In contrast to the semiconductor device according to the first comparative example shown in FIG. 17, FIG. - 1 is a cross-sectional view schematically showing ion implantation regions 102a-102c for forming the well region 102 during the manufacture of the semiconductor device according to the first comparative example, instead of the well region 102 of FIG. 1. The ion implantation region 102a is formed with a width w41 so as to overlap the channel formation region 103a. The ion implantation region 102b is formed with a width w42 wider than the width w41 so as to overlap the drift region 104. The ion implantation region 102c is formed with a width w43 similar to the width w41 so as to overlap the channel formation region 103b.

[0081] 6 and 7, in the semiconductor device according to the first embodiment, the widths w31 and w32 of the ion implantation regions 2c and 2e at positions that overlap with the channel formation regions 3b and 3c among the ion implantation regions 2a to 2f are narrower than the widths w41 and w42 of the ion implantation regions 102a to 102c in the semiconductor device according to the first comparative example. Therefore, in the semiconductor device according to the first embodiment, the n-type impurities contained in the ion implantation regions 2c and 2e cannot be sufficiently diffused laterally by heat treatment, and regions with a locally low impurity concentration are formed in the well region 2.

[0082] Next, a semiconductor device according to a second comparative example will be described. The semiconductor device according to the second comparative example has in common with the semiconductor device according to the first embodiment that it is an array of lateral MOSFETs. Figure 19 is a plan view for explaining a method for manufacturing the semiconductor device according to the second comparative example, and corresponds to the plan view for explaining the method for manufacturing the semiconductor device according to the first embodiment shown in Figure 8A.

[0083] In the manufacturing method of the semiconductor device according to the second comparative example, as shown in FIG. - In the ion implantation step for forming the mold well region 2, ion implantation regions 2a to 2d are formed, but the ion implantation region 2x connected to the ion implantation region 2c is not formed, which is different from the method for manufacturing the semiconductor device according to the first embodiment shown in FIG. 8A.

[0084] 19, the position of the end of gate electrode 11a and the end of well region 2 immediately below wiring 41 is indicated by dashed line area A1. The position of the end of gate electrode 11b and the end of well region 2 immediately below wiring 41 is indicated by dashed line area A2. The position of the end of gate electrode 11c and the end of well region 2 immediately below wiring 41 is indicated by dashed line area A3.

[0085] In the semiconductor device according to the second comparative example, the ion-implanted regions 2a, 2b, and 2d are thicker than the ion-implanted region 2c, and therefore the n-type impurities diffuse sufficiently laterally by heat treatment. As a result, the impurity concentration at the end of the well region 2 corresponding to the position indicated by the dashed-line region A1 between the ion-implanted regions 2a and 2b does not decrease, and no channel is formed on the surface of the end of the well region 2, even directly under the wiring 41.

[0086] On the other hand, because ion implantation region 2c is narrower than ion implantation regions 2a, 2b, and 2d, the n-type impurities do not diffuse sufficiently laterally by heat treatment. Therefore, the impurity concentration at the end of well region 2, corresponding to the gap between ion implantation regions 2b and 2c, indicated by dashed-line region A2, is lower than the impurity concentration at the end of well region 2, indicated by dashed-line region A1. Furthermore, the impurity concentration at the end of well region 2, corresponding to the gap between ion implantation regions 2c and 2d, indicated by dashed-line region A3, is lower than the impurity concentration at the end of well region 2, indicated by dashed-line region A1. Therefore, when a potential is applied to wiring 41, a channel is formed on the surface of the relatively low-impurity-concentration region of well region 2, indicated by dashed-line regions A2 and A3, which becomes a leakage path.

[0087] In contrast, in the semiconductor device according to the first embodiment, as shown in FIG. 8A , in the ion implantation step for forming well region 102, ion implantation region 2x is formed at the end of ion implantation region 2c, which is narrower than ion implantation regions 2a, 2b, and 2d. As a result, the impurity concentration at the end of well region 2, indicated by dashed-line region A2 and corresponding to the gap between ion implantation regions 2b and 2c, is equal to or higher than the impurity concentration at the end of well region 2, indicated by dashed-line region A1. Furthermore, the impurity concentration at the end of well region 2, indicated by dashed-line region A3 and corresponding to the gap between ion implantation regions 2c and 2d, is equal to or higher than the impurity concentration at the end of well region 2, indicated by dashed-line region A1. Therefore, even if a potential is applied to wiring 41, the formation of a channel on the surface of well region 2 at the positions indicated by dashed-line regions A2 and A3 can be prevented, thereby preventing the occurrence of a leakage path.

[0088] (Second embodiment) 20 is a plan view for explaining the method for manufacturing a semiconductor device according to the second embodiment, and corresponds to the plan view for explaining the method for manufacturing a semiconductor device according to the first embodiment shown in FIG. 8A. As shown in FIG. 20, the method for manufacturing a semiconductor device according to the second embodiment includes the steps of: - 8A in that an ion implantation region 2x is formed apart from an ion implantation region 2c in the ion implantation step for forming the mold well region 2. The other steps in the method for manufacturing a semiconductor device according to the second embodiment are substantially the same as those in the method for manufacturing a semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0089] According to the method for manufacturing a semiconductor device in accordance with the second embodiment, as in the method for manufacturing a semiconductor device in accordance with the first embodiment, by forming ion implantation regions 2x, it is possible to prevent a decrease in the impurity concentration of well region 2 at positions indicated by dashed line regions A2 and A3 in Figures 3 to 5. Therefore, even if a potential is applied to wiring 41, it is possible to prevent the formation of a channel on the surface of well region 2 at positions indicated by dashed line regions A2 and A3, thereby preventing the occurrence of a leak path.

[0090] (Third embodiment) 21 is a plan view for explaining the method for manufacturing a semiconductor device according to the third embodiment, and corresponds to the plan view for explaining the method for manufacturing a semiconductor device according to the first embodiment shown in FIG. 8A. As shown in FIG. 21, the method for manufacturing a semiconductor device according to the third embodiment includes the steps of: - This method differs from the method for manufacturing a semiconductor device according to the first embodiment shown in FIG. 8 in that, in the ion implantation step for forming the mold well region 2, ion implantation regions 2y and 2z are formed spaced apart from the ion implantation region 2c. The ion implantation regions 2y and 2z are formed spaced apart from each other. The other steps in the method for manufacturing a semiconductor device according to the third embodiment are substantially the same as those in the method for manufacturing a semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0091] According to the method for manufacturing a semiconductor device in accordance with the third embodiment, similarly to the method for manufacturing a semiconductor device in accordance with the first embodiment, by forming ion implantation regions 2y and 2z, it is possible to prevent a decrease in the impurity concentration of well region 2 at the positions indicated by dashed-line regions A2 and A3 in Figures 3 to 5. Therefore, even if a potential is applied to wiring 41, it is possible to prevent the formation of a channel on the surface of well region 2 at the positions indicated by dashed-line regions A2 and A3, thereby preventing the occurrence of a leak path.

[0092] (Other embodiments) As described above, the present disclosure has been described with reference to the first to third embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0093] For example, in the semiconductor device manufacturing methods according to the first to third embodiments, as shown in Fig. 7, among the ion implantation regions 2a to 2g, the ion implantation regions 2c and 2e at positions overlapping with the channel formation regions 3b and 3c are relatively narrow, but this is not limiting. For example, the ion implantation regions 2b, 2d, and 2f overlapping with the drift regions 4a to 4c may be relatively narrow. In this case, an ion implantation region similar to the ion implantation region 2x shown in Fig. 8A may be formed on the end side of the relatively narrow ion implantation regions 2b, 2d, and 2f.

[0094] Furthermore, although a lateral MOSFET has been exemplified as the semiconductor device according to the first to third embodiments, the present invention is also applicable to a lateral IGBT.

[0095] Furthermore, the configurations disclosed in the first to third embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0096] 1,101...Semiconductor substrate 2,102...Well area 2a~2d,2x~2z,102a~102c...Ion implantation area 3a to 3d, 103a, 103b...Channel formation region (well region) 3e…Connection area 3x~3z…Ion implantation area 4a~4c, 104...Drift region 5,105...well area 5x...Ion implantation area 6, 7a to 7d, 106, 107a, 107b...contact area 8a to 8f, 108a, 108b... Carrier supply region (source region) 9a to 9c, 109... Carrier receiving region (drain region) 10a to 10f, 110a, 110b...Gate insulating film 11a to 11f, 111a, 111b...gate electrodes 12a to 12f, 112a, 112b...Sidewall insulating film 21, 29, 121...Substrate contact electrodes 21a, 22a, 22b, 23a, 24a to 24c, 25a, 26a to 26c, 27a, 28a, 28b, 29a, 121a, 122a, 122b, 123a, 124a, 124b...Via 22, 24, 26, 28, 122, 124...Source electrodes 23, 25, 27, 123...Drain electrode 31,131...Element isolation insulating film 31a~31e...Opening 32,132...Interlayer insulating film 33,133...Protective insulating film 41...Wiring 42...Gate wiring A1~A3…area T1 to T6, T11, T12...Transistor cells

Claims

1. a semiconductor substrate of a first conductivity type; a second conductivity type well region provided on the upper surface side of the semiconductor substrate; a plurality of channel formation regions of a first conductivity type provided on an upper surface side of the well region and extending parallel to each other in one direction in a plan view; a plurality of drift regions of a second conductivity type provided alternately with the plurality of channel formation regions on an upper surface side of the well region and extending parallel to each other in the one direction; a second conductivity type carrier supply region provided on an upper surface side of each of the plurality of channel formation regions; a second conductivity type carrier receiving region provided on an upper surface side of each of the plurality of drift regions; a plurality of gate electrodes provided via a gate insulating film on an upper surface side of the channel formation region sandwiched between the carrier supply region and the well region, the gate electrodes extending parallel to each other in the one direction; wiring provided above the well region and extending in a direction perpendicular to the one direction on end sides of the plurality of channel formation regions and the plurality of drift regions in the one direction; Equipped with the impurity concentration of the well region at a position overlapping the wiring on the end side of the channel formation region sandwiched between adjacent drift regions is equal to or higher than the impurity concentration of the well region at a position overlapping the wiring on the end side of the plurality of drift regions.

2. Two transistor cells each including the adjacent gate electrodes share the carrier supply region and are arranged symmetrically with respect to the carrier supply region. The semiconductor device according to claim 1 .

3. Two transistor cells each including the adjacent gate electrodes share the carrier receiving region and are arranged symmetrically with respect to the carrier receiving region. The semiconductor device according to claim 1 .

4. 2. The method for manufacturing a semiconductor device according to claim 1, The step of forming the well region includes: by ion-implanting impurities of a second conductivity type, a plurality of first ion-implanted regions in the form of slits each having a different width and extending parallel to one another in the one direction, and a second ion-implanted region extending in a direction perpendicular to the one direction is formed at an end side of the first ion-implanted region having a relatively narrow width among the plurality of first ion-implanted regions and at a position overlapping the wiring, The impurities implanted into the first ion implantation region and the second ion implantation region are laterally diffused by heat treatment to form the well region. A method for manufacturing a semiconductor device, comprising:

5. The first ion implantation region having a relatively narrow width is formed at a position overlapping the channel formation region sandwiched between the adjacent drift regions. The method for manufacturing a semiconductor device according to claim 4 .

6. The second ion implantation region is formed so as to connect to an end of the first ion implantation region having a relatively narrow width. The method for manufacturing a semiconductor device according to claim 4 or 5.

7. The second ion implantation region is formed spaced apart from an end of the first ion implantation region having a relatively narrow width. The method for manufacturing a semiconductor device according to claim 4 or 5.

8. The second ion implantation regions are formed in a plurality of locations spaced apart from one another in a direction perpendicular to the one direction. The method for manufacturing a semiconductor device according to claim 4 or 5.

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