Compound semiconductor and method for manufacturing the same

Abstract

To provide a technique of adjusting the concentration of impurities in a compound semiconductor.SOLUTION: The present invention relates to a compound semiconductor having a crystal structure including a first element and a second element, and the compound semiconductor includes: a third element substituted for the first element to make the compound semiconductor of a first conductivity type; and a fourth element substituted for the second element to make the compound semiconductor of the first conductivity type.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This specification discloses techniques relating to compound semiconductors and methods for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device using a compound semiconductor. In Patent Document 1, impurity ions are implanted into a predetermined area of ​​a semiconductor layer to form a semiconductor device having multiple semiconductor regions in the semiconductor layer. Specifically, nitrogen ions are implanted as an impurity into a SiC semiconductor layer to form an n-type semiconductor region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2022-136894 Summary of the Invention [Problem to be solved by the invention]

[0004] When nitrogen ions are implanted into a SiC semiconductor layer as in Patent Document 1, carbon (carbon vacancies) in the SiC crystal are replaced with nitrogen, making the SiC semiconductor layer n-type. In order to increase the impurity concentration (n-type impurity concentration) of the SiC semiconductor layer, it is necessary to increase the nitrogen concentration during ion implantation. However, increasing the nitrogen concentration during ion implantation can cause crystal defects during ion implantation, which can degrade the characteristics of the semiconductor device. Therefore, there is a need for a technology that can adjust the impurity concentration of a compound semiconductor while suppressing the degradation of the characteristics of the semiconductor device. The present specification aims to provide a technology for adjusting the impurity concentration of a compound semiconductor. [Means for solving the problem]

[0005] The compound semiconductor device disclosed in this specification has a crystal structure containing a first element and a second element. This compound semiconductor contains, within the crystal structure, a third element that substitutes for the first element and gives the compound semiconductor a first conductivity type, and a fourth element that substitutes for the second element and gives the compound semiconductor the first conductivity type.

[0006] In the compound semiconductor, both the first and second elements constituting the crystalline structure of the compound semiconductor are partially substituted with impurity elements (third and fourth elements). Therefore, when the impurity concentration of the compound semiconductor is the same, fewer atomic vacancies (substitution sites) of the first element are required compared to, for example, a compound semiconductor in which only the lattice sites of the first element are substituted with the third element, and a shortage of atomic vacancies of the first element is suppressed. The impurity concentration of the third element ion-implanted into the compound semiconductor can be reduced, thereby suppressing crystal defects in the compound semiconductor. As a result, deterioration in the characteristics of semiconductor devices using the compound semiconductor can be suppressed.

[0007] The manufacturing method disclosed in this specification relates to a method for manufacturing a compound semiconductor having a crystal structure containing a first element and a second element. This manufacturing method includes a film formation step of forming a growth layer containing, as an impurity, a third element that is substitutable for the first element and that gives the compound semiconductor a first conductivity type, an ion implantation step of ion-implanting, into the growth layer formed by the film formation step, a fourth element that substitutes for the second element and gives the compound semiconductor the first conductivity type, and an annealing step of heating the compound semiconductor.

[0008] Another manufacturing method disclosed in this specification relates to a method for manufacturing a compound semiconductor having a crystal structure containing a first element and a second element. This manufacturing method includes a first ion implantation step of ion-implanting a third element into a semiconductor substrate, the third element being capable of substituting for the first element and imparting a first conductivity type to the compound semiconductor, a second ion implantation step of ion-implanting a fourth element into the area into which the third element has been ion-implanted, the fourth element being capable of substituting for the second element and imparting a first conductivity type to the compound semiconductor, and an annealing step of heating the compound semiconductor.

[0009] According to the above-described manufacturing method, the compound semiconductor can be made to have the first conductivity by substituting the third element for the lattice site of the first element, and the compound semiconductor can be made to have the first conductivity by substituting the fourth element for the lattice site of the second element. The concentration of impurities ion-implanted into the compound semiconductor can be reduced, and crystal defects in the compound semiconductor can be suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] 1 shows a cross-sectional view of a semiconductor device. [Figure 2] 1 shows the crystal structure of the compound semiconductor that constitutes the semiconductor device. [Figure 3] 1 shows the crystal structure of a conventional compound semiconductor that constitutes a semiconductor device. [Figure 4] 1 shows a manufacturing method of a compound semiconductor according to a first embodiment. [Figure 5] 2 shows a method for manufacturing a compound semiconductor according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the compound semiconductor disclosed in the present specification as an example, the dopant concentration ratio of the third element to the fourth element may be 1:9 to 9:1 in the crystal structure.

[0012] According to this configuration, it is possible to prevent a shortage of atomic vacancies for both the first element and the second element.

[0013] In one example of the compound semiconductor disclosed herein, the first element may be Si and the second element may be C.

[0014] According to this configuration, crystal defects can be suppressed in a high-voltage SiC semiconductor, and a semiconductor device having high voltage resistance and excellent electrical characteristics (for example, low on-resistance) can be realized.

[0015] The semiconductor device disclosed in this specification may have a semiconductor region made of any of the above-mentioned compound semiconductors provided in a part of a semiconductor substrate, in other words, a semiconductor region not made of any of the above-mentioned compound semiconductors provided in the semiconductor substrate.

[0016] With this configuration, for example, a semiconductor region made of the compound semiconductor can be provided only in a specific region of the semiconductor substrate, avoiding a high-concentration impurity region that is in contact with an electrode. For example, when forming a high-concentration impurity region, it is not necessary to substitute multiple substitution sites with impurity elements, which reduces the manufacturing cost (manufacturing time) of the semiconductor device.

[0017] (Semiconductor Devices) A semiconductor device 10 will be described with reference to FIG. 1. The semiconductor device 10 is a vertical semiconductor device and includes a semiconductor substrate 14, a source electrode 12 and a gate electrode 4 provided on the front surface of the semiconductor substrate 14, and a drain electrode 28 provided on the back surface of the semiconductor substrate 14. The semiconductor substrate 14 is made of SiC. SiC is an example of a compound semiconductor. In the semiconductor device 10, a source region 8, a body region 6, a drift region 23, a p-type column region 22, an n-type column region 24, and a drain region 26 are formed by ion-implanting n-type and p-type impurities into the n-type semiconductor substrate 14. The drift region 23 is formed by a region of the semiconductor substrate 14 in which the source region 8, the body region 6, the p-type column region 22, and the drain region 26 are not formed. In other words, the n-type column region 24 is part of the drift region 23.

[0018] P-type body regions 6 are distributed on the surface of the semiconductor substrate 14. In addition, n +The semiconductor device 10 has a n-type source region 8. The source region 8 is separated from the drift region 23 by the body region 6. A source electrode 12 is electrically connected to the source region 8. A gate electrode 4 is provided on the surface of the body region 6, separating the source region 8 and the drift region 23, via a gate insulating film 2. The semiconductor device 10 is a planar gate MOSFET. The source region 8 and the body region 6 are formed by ion implanting n-type or p-type impurities into the semiconductor substrate 14 from the surface of the semiconductor substrate 14.

[0019] The back surface of the semiconductor substrate 14 is + An n-type drain region 26 is provided in the semiconductor substrate 14. The drain region 26 is formed by ion-implanting n-type impurities into the semiconductor substrate 14 from the rear surface of the semiconductor substrate 14.

[0020] A p-type column region 22 is formed below the body region 6. The p-type column region 22 extends in the thickness direction of the semiconductor substrate 14 (i.e., the direction connecting the front surface and the back surface). An n-type column region 24, into which no impurities have been introduced, is formed between the p-type column regions 22, 22. The p-type column region 22 and the n-type column region 24 form a superjunction structure 20. The superjunction structure 20 is formed in the middle portion of the semiconductor substrate 14 in the thickness direction, i.e., between the body region 6 and the drain region 26. The p-type column region 22 is formed by ion-implanting p-type impurities into the semiconductor substrate 14 from the surface of the semiconductor substrate 14. Furthermore, as will be described in detail later, in the n-type column region 24 (drift region 23), some of the silicon (Si) vacancies are substituted with phosphorus (P) and some of the carbon (C) vacancies are substituted with nitrogen (N).

[0021] In the semiconductor device 10, when a voltage exceeding the threshold voltage is applied to the gate electrode 4, an inversion layer (channel) is formed on the surface of the body region 6 facing the gate electrode 4. Electrons supplied from the source electrode 12 to the source region 8 pass through the inversion layer and are supplied to the drift region 23. The electrons supplied to the drift region 23 move toward the drain region 26 and are discharged from the drain electrode 28. This turns the semiconductor device 10 on. When the application of voltage to the gate electrode 4 is stopped (i.e., when the voltage applied to the gate electrode 4 is made lower than the threshold voltage), the inversion layer formed in the body region 6 disappears, and the supply of electrons from the source region 8 to the drift region 23 stops. This turns the semiconductor device 10 off. The semiconductor device 10 is a normally-off MOSFET that turns on when a voltage exceeding the threshold voltage is applied to the gate electrode 4.

[0022] As described above, the semiconductor device 10 has a superjunction structure 20 formed in the semiconductor substrate 14. Therefore, when the semiconductor device 10 is turned off, a depletion layer extends from the interface between the p-type column region 22 and the n-type column region 24 into the p-type column region 22, and also into the n-type column region 24. In the semiconductor device 10, the length (horizontal length in FIG. 1 ) and impurity concentration of the p-type column region 22 in the direction perpendicular to the thickness direction (width direction) and the length and impurity concentration of the n-type column region 24 in the width direction are controlled to ensure a charge balance condition between the p-type column region 22 and the n-type column region 24. While the semiconductor device 10 is turned off, the semiconductor substrate 14 (i.e., the portion where the superjunction structure 20 is formed) can be almost completely depleted. Therefore, the semiconductor device 10 has a high breakdown voltage.

[0023] (Crystal structure of the n-type column region) The crystal structure of the n-type column region 24 (drift region 23) will be described with reference to Figures 2 and 3. Figure 2 shows a portion of the crystal structure of the n-type column region 24 of the semiconductor device 10. Figure 3 shows a portion of the crystal structure of the n-type column region of a conventional semiconductor device. In Figures 2 and 3, (a) shows a state in which n-type impurities have been substituted into substitution sites, and (b) shows a state in which no n-type impurities have been introduced.

[0024] As shown in Fig. 2, in the semiconductor device 10, silicon vacancies are substituted with phosphorus, and carbon vacancies are substituted with nitrogen. In Fig. 2, three silicon vacancies are substituted with phosphorus, and two carbon vacancies are substituted with nitrogen. The substitution of silicon vacancies with phosphorus makes the n-type column region 24 n-type. The substitution of carbon vacancies with nitrogen also makes the n-type column region 24 n-type.

[0025] In the semiconductor device 10, the phosphorus concentration (atoms / cm -3 ) and nitrogen concentration (atoms / cm -3 ) (i.e., dopant concentration ratio) is adjusted to be 1:9 to 9:1. Also, a semiconductor region (n-type column region 24) in which silicon vacancies are substituted with phosphorus and carbon vacancies are substituted with nitrogen is provided in a part of the semiconductor substrate 14. In other words, the crystal structure in which silicon vacancies are substituted with phosphorus and carbon vacancies are substituted with nitrogen (crystal structure shown in FIG. 2(a)) exists only in the n-type column region 24 and does not exist in, for example, the source region 8, the body region 6, the p-type column region 22, and the drain region 26.

[0026] As shown in Figure 3, in the conventional semiconductor device, only the carbon vacancies are substituted with nitrogen, and the silicon vacancies are not substituted. In Figure 3, five carbon vacancies are substituted with nitrogen. In the conventional semiconductor device, the n-type column region is made n-type by substituting the carbon vacancies with nitrogen.

[0027] As described above, both the semiconductor device 10 and the conventional semiconductor device have five vacancies substituted with impurities (phosphorus and nitrogen). Therefore, the impurity concentrations in the n-type column regions of the semiconductor device 10 and the conventional semiconductor device are approximately equal. However, while the semiconductor device 10 substitutes two carbon vacancies with nitrogen, the conventional semiconductor device substitutes five carbon vacancies with nitrogen. Therefore, in the case of the conventional semiconductor device, carbon vacancies tend to become insufficient when nitrogen ions are implanted into the SiC semiconductor, so the nitrogen doping concentration (dose) must be higher than in the semiconductor device 10. As a result, the conventional semiconductor device is more susceptible to crystal defects in the SiC semiconductor. In other words, the semiconductor device 10 is less likely to have crystal defects in the SiC semiconductor (in the n-type column region 24) than the conventional semiconductor device.

[0028] Another advantage of the semiconductor device 10 will be described. As described above, the semiconductor device 10 is less likely to have crystal defects in the SiC semiconductor than conventional semiconductor devices. As a result, the semiconductor device 10 can suppress degradation of electrical characteristics, such as an increase in on-resistance. That is, the semiconductor device 10 can adjust the impurity concentration in the semiconductor substrate 14 (p-type column region 22) while suppressing specific device degradation. Furthermore, nitrogen has a higher ionization energy than phosphorus. Therefore, nitrogen ion implantation requires a lower beam current and a longer ion implantation time than phosphorus ion implantation. A longer ion implantation time shortens the replacement cycle of parts (consumable parts) of the manufacturing equipment (ion implantation equipment). As a result, the manufacturing cost of the semiconductor device increases. The semiconductor device 10 can extend the replacement cycle of parts of the manufacturing equipment, thereby reducing manufacturing costs.

[0029] (Method of manufacturing a semiconductor device: First embodiment) A method for manufacturing the semiconductor device 10 will be described with reference to FIG. 4. As described above, the source region 8, the body region 6, the drain region 26, and the p-type column region 22 are formed by ion implanting n-type or p-type impurities into the semiconductor substrate 14. These ion implantation techniques are well known, and therefore will not be described here. Below, only the method for manufacturing the n-type column region 24 (drift region 23) will be described.

[0030] First, silicon source gas, carbon source gas, and nitrogen source gas are supplied onto the substrate, and an SiC growth layer containing nitrogen as an impurity is epitaxially grown on the substrate (film formation process: step S2). By supplying the nitrogen source gas, an n-type SiC growth layer in which carbon vacancies are substituted with nitrogen is formed.

[0031] Next, phosphorus ions are implanted as an impurity into the SiC growth layer (ion implantation step: step S4). The concentrations of the nitrogen source gas and phosphorus (doping concentration) are adjusted so that the concentrations of phosphorus and nitrogen contained in the SiC growth layer are 1:9 to 9:1.

[0032] Next, the substrate and the SiC growth layer are heated to anneal the SiC growth layer (annealing step: step S6). In the annealing step, the substrate and the SiC growth layer are heated to a temperature at which phosphorus and nitrogen are activated. By performing the annealing step, phosphorus is substituted into silicon vacancies, and an n-type semiconductor (n-type SiC semiconductor) having the crystal structure shown in FIG. 2(a) is formed.

[0033] According to the above manufacturing method, it is possible to suppress a shortage of carbon vacancies compared to, for example, an n-type SiC semiconductor in which only carbon vacancies are substituted with nitrogen. Therefore, it is possible to suppress the doping concentration during ion implantation, and it is possible to suppress the occurrence of crystal defects in the n-type column region 24 (drift region 23). In this embodiment, carbon is an example of the first element, silicon is an example of the second element, nitrogen is an example of the third element, and phosphorus is an example of the fourth element.

[0034] As a modification of this embodiment, a silicon source gas, a carbon source gas, and a phosphorus source gas may be used in the film formation process, and nitrogen ions may be implanted in the ion implantation process. In this case, an n-type semiconductor (n-type SiC semiconductor) having the crystal structure shown in FIG. 2(a) can be formed by performing an annealing process. In this modification, silicon is an example of the first element, carbon is an example of the second element, phosphorus is an example of the third element, and nitrogen is an example of the fourth element.

[0035] (Method of manufacturing semiconductor device: Second embodiment) Another method for manufacturing the semiconductor device 10 will be described with reference to Fig. 5. In this embodiment, too, only the method for manufacturing the n-type column region 24 (drift region 23) will be described.

[0036] First, an i-type SiC substrate (semiconductor substrate) is prepared, and nitrogen ions are implanted as an impurity into the SiC substrate (first ion implantation step: step S12). Next, phosphorus ions are implanted as an impurity into the SiC substrate (second ion implantation step: step S14). In the second ion implantation step, phosphorus ions are implanted into the same range as the range into which nitrogen was implanted in the first ion implantation step. In addition, in the first and second ion implantation steps, the concentrations of nitrogen and phosphorus (doping concentrations) are adjusted to be 1:9 to 9:1.

[0037] Next, the SiC substrate is annealed (annealing step: step S16). In the annealing step, the SiC substrate is heated to a temperature at which phosphorus and nitrogen are activated. By performing the annealing step, phosphorus is substituted for silicon vacancies and nitrogen is substituted for carbon vacancies, resulting in the formation of an n-type semiconductor (n-type SiC semiconductor) having the crystal structure shown in FIG. 2(a).

[0038] The above manufacturing method also makes it possible to suppress a shortage of carbon vacancies compared to, for example, an n-type SiC semiconductor in which only carbon vacancies are substituted with nitrogen. Therefore, the above manufacturing method also makes it possible to suppress the doping concentration during ion implantation and to suppress the occurrence of crystal defects in the n-type column region 24 (drift region 23). In this embodiment, carbon is an example of the first element, silicon is an example of the second element, nitrogen is an example of the third element, and phosphorus is an example of the fourth element.

[0039] In this embodiment, the order of steps S12 and S14 is arbitrary, and step S12 may be performed after step S14. In this case, step S14 is the first ion implantation step, step S12 is the second ion implantation step, silicon is an example of the first element, carbon is an example of the second element, phosphorus is an example of the third element, and nitrogen is an example of the fourth element.

[0040] In step S12, an n-type or p-type SiC substrate may be used instead of the i-type SiC substrate. When an n-type SiC substrate is used in step S12, the SiC substrate has an impurity concentration lower than the target impurity concentration (the impurity concentration of the n-type column region 24).

[0041] In the above examples, instead of SiC, compound semiconductors such as gallium nitride (GaN) and gallium arsenide (GaAs) can be used. That is, the technology disclosed in this specification is applicable to any type of compound semiconductor as long as it has two or more substitution sites.

[0042] In the above examples, a semiconductor device in which the crystal structure of the n-type column region is substituted with two types of impurities that make the compound semiconductor n-type has been described. However, the technology disclosed in this specification can also be applied to a semiconductor device in which the crystal structure of the p-type column region is substituted with two types of impurities that make the compound semiconductor p-type. Alternatively, the technology can be applied to a semiconductor device in which the crystal structure of the n-type column region is substituted with two types of impurities that make the compound semiconductor n-type, and the crystal structure of the p-type column region is substituted with two types of impurities that make the compound semiconductor p-type.

[0043] When both the n-type column region and the p-type column region are each substituted with two types of impurities, both the n-type column region and the p-type column region may be manufactured by the method described in the first embodiment. Alternatively, both the n-type column region and the p-type column region may be manufactured by the method described in the second embodiment. Alternatively, one of the n-type column region and the p-type column region may be manufactured by the method described in the first embodiment, and the other may be manufactured by the method described in the second embodiment.

[0044] Furthermore, the technology disclosed in this specification can also be applied to semiconductor regions other than the n-type column region and the p-type column region (for example, the body region).

[0045] In the above embodiments, a planar gate MOSFET has been described. However, the technology disclosed in this specification can be applied to various semiconductor devices, such as trench gate MOSFETs, planar gate or trench gate IGBTs, etc. It can also be applied to semiconductor devices that do not have a superjunction structure.

[0046] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A compound semiconductor having a crystal structure containing a first element and a second element, A compound semiconductor containing, in the crystal structure, a third element that is substituted for the first element and that gives the compound semiconductor a first conductivity type, and a fourth element that is substituted for the second element and that gives the compound semiconductor a first conductivity type. (Configuration 2) 2. The compound semiconductor according to configuration 1, wherein the dopant concentration ratio of the third element to the fourth element in the crystal structure is 1:9 to 9:1. (Configuration 3) 3. The compound semiconductor according to claim 1, wherein the first element is Si and the second element is C. (Configuration 4) A semiconductor device in which a semiconductor region made of the compound semiconductor according to any one of configurations 1 to 3 is provided in a part of a semiconductor substrate. (Configuration 5) A method for manufacturing a compound semiconductor having a crystal structure containing a first element and a second element, comprising: a film formation step of forming a growth layer containing, as an impurity, a third element that is substitutable for the first element and that makes the compound semiconductor a first conductivity type; an ion implantation step of ion-implanting a fourth element into the grown layer formed in the film formation step, the fourth element substituting for the second element to make the compound semiconductor a first conductivity type; an annealing step of heating the compound semiconductor; A manufacturing method comprising the steps of: (Configuration 6) A method for manufacturing a compound semiconductor having a crystal structure containing a first element and a second element, comprising: a first ion implantation step of ion-implanting a third element into a semiconductor substrate, the third element being capable of substituting the first element and causing the compound semiconductor to have a first conductivity type; a second ion implantation step of ion-implanting a fourth element into the area into which the third element has been ion-implanted, the fourth element being capable of substituting for the second element and causing the compound semiconductor to have a first conductivity type; an annealing step of heating the compound semiconductor; A manufacturing method comprising the steps of:

[0047] Although the embodiments of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0048] 10: Semiconductor device, 24: Compound semiconductor, S2: Film formation process, S4: Ion implantation process, S6, S16: Annealing process, S12: First ion implantation process, S14: Second ion implantation process

Claims

1. A compound semiconductor having a crystal structure containing a first element and a second element, A compound semiconductor including, in the crystal structure, a third element that is substituted for the first element and that gives the compound semiconductor a first conductivity type, and a fourth element that is substituted for the second element and that gives the compound semiconductor a first conductivity type.

2. 2. The compound semiconductor according to claim 1, wherein the dopant concentration ratio of the third element to the fourth element in the crystal structure is 1:9 to 9:

1.

3. 2. The compound semiconductor according to claim 1, wherein the first element is Si and the second element is C.

4. A semiconductor device, comprising: a semiconductor region made of the compound semiconductor according to claim 1 provided in a part of a semiconductor substrate.

5. A method for manufacturing a compound semiconductor having a crystal structure containing a first element and a second element, comprising: a film formation step of forming a growth layer containing, as an impurity, a third element that is substitutable for the first element and that makes the compound semiconductor a first conductivity type; an ion implantation step of ion-implanting a fourth element into the grown layer formed in the film formation step, the fourth element substituting for the second element to make the compound semiconductor a first conductivity type; an annealing step of heating the compound semiconductor; A manufacturing method comprising the steps of:

6. A method for manufacturing a compound semiconductor having a crystal structure containing a first element and a second element, comprising: a first ion implantation step of ion-implanting a third element into a semiconductor substrate, the third element being capable of substituting the first element and causing the compound semiconductor to have a first conductivity type; a second ion implantation step of ion-implanting a fourth element into the area into which the third element has been ion-implanted, the fourth element being capable of substituting for the second element and causing the compound semiconductor to have a first conductivity type; an annealing step of heating the compound semiconductor; A manufacturing method comprising the steps of:

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