Semiconductor device

Abstract

To provide a technique of suppressing the shift of a threshold value voltage.SOLUTION: A semiconductor device includes: a GaN layer formed of p-type GaN single crystal and having a channel surface; an AlN layer disposed on a surface of the channel surface; a gate insulating film disposed on a surface of the AlN layer; and a gate electrode disposed in a surface of the gate insulating film. The channel surface has an angle of at least 39° with respect to a polar surface of the GaN single crystal of the GaN layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices using gallium nitride (GaN) are known. For example, Patent Document 1 discloses a semiconductor device having a gate structure including a gate insulating film and a gate electrode in a structure in which an aluminum nitride (AlN) layer is disposed on the polar plane (c-plane) of p-type GaN. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-201715 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-described gate structure has a problem in that the threshold voltage shifts to the negative side in response to negative gate voltage stress. [Means for solving the problem]

[0005] One embodiment of a semiconductor device disclosed in this specification includes a GaN layer made of p-type GaN single crystal and having a channel surface. The semiconductor device includes an AlN layer disposed on the surface of the channel surface. The semiconductor device includes a gate insulating film disposed on the surface of the AlN layer. The semiconductor device includes a gate electrode disposed on the surface of the gate insulating film. In the semiconductor device, the channel surface forms an angle of 39° or more with respect to the polar plane of the GaN single crystal of the GaN layer.

[0006] The inventors discovered that in a gate structure in which an AlN layer, a gate insulating film, and a gate electrode are stacked in this order on the channel surface, the negative shift in gate voltage relative to a negative gate voltage is caused by the energy band near the gate. Specifically, when the valence band discontinuity at the heterointerface between the gate insulating film and the AlN layer is located slightly above the Fermi level, holes accumulate in the valence band discontinuity, causing the interface to become positively charged. The more positive charges accumulate, the more the threshold voltage shifts negatively.

[0007] In the semiconductor device structure disclosed herein, the channel plane has an angle of 39° or more with respect to the polar plane of the GaN single crystal. A crystal plane within this angle range can make the polarization charge at the interface between the AlN layer and the channel plane zero or negative. This allows the electric field in the AlN layer (i.e., the tilt of the band diagram) to be relaxed. As a result, even when a negative gate voltage is applied, the valence band discontinuity at the heterointerface between the gate insulating film and the AlN layer can be positioned below the Fermi level. This makes it possible to suppress the occurrence of a negative gate voltage shift due to hole accumulation. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first embodiment. [Figure 2] 10 is a graph showing transfer characteristics of a semiconductor device of a comparative example. [Figure 3] FIG. 10 is a band diagram of a semiconductor device of a comparative example. [Figure 4] 1 is a band diagram of a semiconductor device 1 of the present specification. [Figure 5] 1 is a band diagram when a large negative gate voltage is applied to the semiconductor device 1 of the present specification. [Figure 6] 10 is a band diagram when a large negative gate voltage is applied to the semiconductor device 1 of the comparative example. FIG. [Figure 7] FIG. 10 is a schematic cross-sectional view of a semiconductor device 101 according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0009] (Configuration of semiconductor device 1) 1 shows a schematic cross-sectional view of a semiconductor device 1 according to this embodiment. The semiconductor device 1 is a lateral MOSFET with a planar gate. The semiconductor device 1 includes a semiconductor substrate 10. The semiconductor substrate 10 has a stacked structure of an n-type GaN substrate 11, an n-type GaN layer 12, and a p-type GaN layer 13. The n-type GaN layer 12 and the p-type GaN layer 13 are layers formed on the n-type GaN substrate 11 by epitaxial growth.

[0010] An n-type GaN source region 14 and an n-type GaN drain region 15 are disposed on top of the p-type GaN layer 13. The drain region 15 is disposed away from the source region 14. The source region 14 and the drain region 15 are regions formed by ion implantation. The top surface 13s of the p-type GaN layer 13 has a channel surface CS. The channel surface CS is a surface on which an inversion layer is formed. The channel surface CS is located between the source region 14 and the drain region 15.

[0011] The upper surface 13s of the p-type GaN layer 13 and the channel plane CS are nonpolar planes of the GaN single crystal. In this specification, a nonpolar plane refers to a crystal plane that has an angle of 39° to 90° (±1°) with respect to the polar plane (c-plane) of GaN. It is known that the polarization charge at the interface between AlN and GaN is zero or negative for crystal planes in this range (see, for example, T. Takeuchi et al., “Theoretical Study of Orientation Dependence of Piezoelectric Effects in Wurtzite-Strained GaInN / GaN Heterostructure and Quantum Wells,” Jpn. J. Appl. Phys. Vol. 39 (2000) pp. 413-416). In this example, the channel plane CS was a plane near the m-plane or a-plane. Specifically, the channel plane CS was a crystal plane at an angle of ±1° from the m-plane, which is a stable crystal plane that can be manufactured.

[0012] A gate structure 20 is disposed on the surface of the channel surface CS. The gate structure 20 includes a crystalline AlN layer 21, a gate insulating film 22, and a gate electrode 23. The AlN layer 21 is disposed on the surface of the channel surface CS. The gate insulating film 22 is disposed on the surface of the AlN layer 21. The gate electrode 23 is disposed on the surface of the gate insulating film 22.

[0013] The AlN layer 21 may contain impurities of less than 10%. Even when the AlN layer 21 containing such impurities is used, the high channel mobility (100 cm) required for a MOSFET can be achieved. 2 It has been confirmed that a resistance of 1 / Vs or more can be achieved. The AlN layer 21 in this example is a film containing 5% or less of oxygen and carbon. The thickness of the AlN layer 21 is preferably 1 nm or more. The reason for this will be described later. In this example, the thickness of the AlN layer 21 is 3 nm.

[0014] The region near the surface of the gate insulating film 22, including the interface between the gate insulating film 22 and the AlN layer 21, is preferably amorphous. More preferably, the entire gate insulating film 22 is amorphous. By providing an amorphous region, it is possible to suppress the occurrence of leakage current through grain boundaries. This makes it possible to improve the reliability of the gate insulating film 22.

[0015] Various materials such as AlSiO, SiO2, and Al2O3 can be used for the gate insulating film 22. Preferably, AlSiO, a mixed film of SiO2 and Al2O3, is used. By using amorphous AlSiO, it is possible to form a high-quality gate insulating film 22 that has a lower gate leakage current, is more resistant to heat treatment processes, has a longer life, and has fewer electron traps than when using SiO2 or Al2O3. In this example, the gate insulating film 22 is made of amorphous AlSiO with a thickness of 40 nm. The (Si / (Al+Si)) composition ratio of AlSiO is 22%.

[0016] The source electrode 24 is in contact with the upper surface of the source region 14. The drain electrode 25 is in contact with the upper surface of the drain region 15.

[0017] The semiconductor device 1 of this embodiment can achieve high channel mobility. Furthermore, the threshold voltage can be controlled to be positive by balancing the thickness of the AlN layer 21 and the p-type Mg acceptor dopant.

[0018] (assignment) A problem with a semiconductor device of a comparative example having the above-described gate structure 20 will be described. In the semiconductor device of the comparative example, the upper surface 13s and the channel surface CS of the p-type GaN layer 13 are polar planes (c-planes). This is because GaN crystal growth is more difficult on semipolar and nonpolar planes than on polar planes. However, when the gate structure 20 is applied to the channel surface CS of a polar plane, there is a problem in that the threshold voltage shifts negatively in response to negative gate voltage stress. This problem will be described with reference to FIG. 2.

[0019] 2 shows the transfer characteristics of a semiconductor device of a comparative example. That is, the transfer characteristics are those when the channel plane CS is a polar plane in the semiconductor device 1 of FIG. 1. The acceptor concentration of the p-type GaN layer 13 is 10 17 cm -3 The horizontal axis of FIG. 2 is gate voltage, and the vertical axis is drain current. Graphs G1 to G5 show the current-voltage characteristics when the gate voltage is swept from a certain negative voltage to 1V. In each of graphs G1 to G5, the negative voltages at the start of measurement are -4V, -6V, -8V, -10V, and -12V. Each of graphs G1 to G5 also has a threshold voltage VT1 to VT5.

[0020] As can be seen from Figure 2, sweeping the gate voltage more negative than -4V causes the threshold voltage to shift in the negative direction. It can also be seen that the amount of shift increases as the negative gate voltage sweep increases. Generally, during the switching-off operation of a power device, a negative gate voltage of about -10V is applied to ensure safe and fast switching. Therefore, it can be seen that the threshold voltage shifts in the negative direction within the general operating range.

[0021] (Solution) The present inventors have found that the negative fluctuation of the gate voltage (see FIG. 2) occurring in the semiconductor device of the comparative example is due to the energy band near the gate. This will be explained in detail using FIG. 3. FIG. 3 is a band diagram when a gate voltage Vg=-5.5V is applied to the semiconductor device of the comparative example (channel surface CS is a polar surface) from which the transfer characteristics of FIG. 2 were obtained. The thickness of the AlN layer 21 was 3 nm, and the thickness of the gate insulating film 22 (AlSiO) was 40 nm. In FIG. 3, the meanings of the symbols are as follows: E g : Band gap, E f : Fermi level, ψ s : Work function, σ, which represents the Fermi level of the GaN surface pol : polarization charge sheet density at the AlN / GaN interface, Wd: depletion layer width, ΔE V (AlSiO / AlN): Difference in the top edge of the valence band between AlSiO and AlN, ΔE V(AlN / GaN): The difference in the top of the valence band between AlN and GaN.

[0022] A valence band discontinuity VBD exists at the interface between the gate insulating film 22 and the AlN layer 21. The heterostructure of the crystalline AlN layer 21 and the p-type GaN layer 13 has spontaneous polarization. The spontaneous polarization at this interface is larger in a polar plane (c-plane) than in a non-polar plane (e.g., m-plane, a-plane, etc.). Therefore, the electric field in the AlN layer 21 is large, and the band tilt becomes large (see region R1). As a result, when the thickness of the AlN layer 21 exceeds a predetermined value, the valence band discontinuity VBD rises above the Fermi level E even at a low negative gate voltage Vg of about −5.5 V. f In other words, in Figure 3, the interface of the valence band discontinuity VBD reaches the Fermi level E f As a result, the Fermi level E f is pinned (see pinning point PG). In this situation, holes accumulate in the valence band discontinuity VBD, and the interface becomes positively charged. Then, by increasing the negative gate voltage or maintaining this bias state for a long time, the amount of accumulated positive charges increases, and the threshold voltage shifts in the negative direction.

[0023] Therefore, in the semiconductor device 1 of this specification, the channel surface CS is a nonpolar surface. The effect thereof will be explained using Fig. 4. Fig. 4 is a band diagram when a gate voltage Vg = -5.5V is applied to the semiconductor device 1 of this specification (where the channel surface CS is a nonpolar surface). The meanings of the symbols in Fig. 4 are the same as those in Fig. 3 described above, and therefore explanations will be omitted.

[0024] The spontaneous polarization at the interface between the crystalline AlN layer 21 and the p-type GaN layer 13 can be made smaller in the semiconductor device 1 of this specification than in the semiconductor device of the comparative example described above. Therefore, the electric field in the AlN layer 21 is small, so the band tilt can be made small (see region R2). As a result, even under conditions equivalent to those of the semiconductor device of the comparative example shown in FIG. 3 (i.e., conditions in which the thickness of the AlN layer 21 is 3 nm and the gate voltage Vg is −5.5 V), the valence band discontinuity VBD is close to the Fermi level E fIn other words, in Figure 4, the interface IF of the valence band discontinuity VBD does not reach the Fermi level E f As a result, the Fermi level E f Therefore, it is possible to suppress the occurrence of a negative gate voltage shift due to hole accumulation.

[0025] (Thickness range of AlN layer 21) The range of the thickness of the AlN layer 21 in the semiconductor device 1 of this specification (where the channel plane CS is a nonpolar plane) will be examined using a band diagram. As shown in FIG. 5, consider the case where a large negative gate voltage Vg=-10 V is applied to the semiconductor device 1 of this specification. As described above, the semiconductor device 1 of this specification has the effect of suppressing the band tilt of the AlN layer 21 (see region R3). However, when the thickness of the AlN layer 21 is increased to 10 nm, the interface of the valence band discontinuity VBD becomes too close to the Fermi level E f (See point P1). As a result, the Fermi level E f In this case, the thickness ratio of the AlN layer 21 (10 nm) to the gate insulating film 22 (40 nm) is 0.25.

[0026] That is, in the semiconductor device 1 of this specification, under the condition of gate voltage Vg=−10V, if the thickness ratio of the gate insulating film 22 to the AlN layer 21 is greater than 0.25, a negative gate voltage shift may occur. As described above, the large negative gate voltage Vg=−10V can be considered a typical value used in switching-off operations. Therefore, it can be said that it is generally preferable to set the thickness ratio of the gate insulating film 22 to the AlN layer 21 to 0.25 or less. Furthermore, considering the influence of film thickness variations and residual charges, it can be said that it is more preferable to set the thickness ratio to 0.2 or less.

[0027] 4, the thickness ratio between the gate insulating film 22 (40 nm) and the AlN layer 21 (3 nm) is 0.075, which is within the above-mentioned numerical range.

[0028] Since the AlN layer 21 is formed by atomic layer deposition, the thickness of the AlN layer 21 can be controlled in 1 nm increments. Therefore, it is quite possible to control the thickness ratio to 0.25 or less, even taking into account manufacturing variations. For example, if the upper limit of the thickness of the AlN layer 21 is 10 nm, and the design thickness is about 5 nm, the thickness ratio can be controlled to 0.25 or less with a sufficient margin.

[0029] (Effect of thickening the AlN layer 21) In the semiconductor device 1 of this specification (where the channel surface CS is a nonpolar plane), the AlN layer 21 can be made thicker than in the semiconductor device of the comparative example (where the channel surface CS is a polar plane (c-plane)). The effect thereof will be described.

[0030] As shown in the band diagram of FIG. 6, consider the case where a large negative gate voltage Vg=−10 V is applied to the semiconductor device of the comparative example. In the semiconductor device of the comparative example, as described above, the band gradient of the AlN layer 21 becomes large (see region R4). Therefore, when the thickness of the AlN layer 21 increases to 2.2 nm, the interface of the valence band discontinuity VBD becomes smaller than the Fermi level E f (see point P2). Therefore, in the semiconductor device of the comparative example, the Fermi level E f In order to avoid this pinning, it is necessary to make the thickness of the AlN layer 21 extremely thin, to 2 nm or less. However, such an extremely thin AlN crystal layer is difficult to put into practice in terms of manufacturing variations and reproducibility.

[0031] On the other hand, as explained in the band diagram of FIG. 5, in the semiconductor device 1 of this specification, the band tilt of the AlN layer 21 can be suppressed (see region R3). Therefore, even when a large negative gate voltage Vg=−10 V is applied, the upper limit of the film thickness of the AlN layer 21 can be increased to approximately 10 nm. This suppresses manufacturing variations in the AlN layer 21, making it possible to form an AlN layer 21 with high reproducibility. This makes it possible to realize a high-quality gate structure 20.

[0032] (Effect of Amorphization of AlN Layer 21) In the semiconductor device 1 of this specification (where the channel surface CS is a nonpolar plane), the amorphous state of the AlN layer 21 can be maintained more effectively than in the semiconductor device of the comparative example (where the channel surface CS is a polar plane (c-plane)). The effect of this will be described.

[0033] After the amorphous gate insulating film 22 (AlSiO) is formed, a heat treatment process must be performed to reduce defects in the gate insulating film 22. During this heat treatment process, partial crystallization of the gate insulating film 22 (AlSiO) may occur in the region near the interface between the gate insulating film 22 and the crystalline AlN layer 21. If a crystallized layer exists, excess positive fixed charges are generated, making it difficult to control the threshold voltage.

[0034] The present inventors have found the following: In a semiconductor device of a comparative example in which the gate insulating film 22 is disposed on the channel surface CS, which is a polar plane (c-plane), the AlSiO is partially crystallized by heat treatment at 900°C or higher, and the amorphous state cannot be maintained. On the other hand, in the semiconductor device 1 of the present specification in which the gate insulating film 22 is disposed on the channel surface CS, which is a nonpolar plane, partial crystallization of AlSiO can be suppressed even when heat treatment at 950°C is performed.

[0035] Therefore, in the semiconductor device 1 of the present specification, a higher heat treatment temperature (950°C) can be applied than in the semiconductor device of the comparative example, and defects in AlSiO can be reduced more than in the semiconductor device of the comparative example. As a result, it is possible to simultaneously suppress leakage current by maintaining AlSiO in an amorphous state and reduce excess positive fixed charges in AlSiO. [Example]

[0036] (Configuration of semiconductor device 101) FIG. 7 shows a schematic cross-sectional view of a semiconductor device 101 according to a second embodiment. The semiconductor device 101 is a vertical MOSFET equipped with a trench gate. Note that a specific wiring structure is not shown in FIG. 7. The semiconductor device 101 includes a semiconductor substrate 110. The semiconductor substrate 110 has a structure in which an n-type GaN substrate 111, an n-type GaN drift layer 112, and a p-type GaN layer 113 are stacked. The impurity concentrations and film thicknesses of the n-type GaN drift layer 112 and the p-type GaN layer 113 can be set appropriately according to the required specifications of the semiconductor device 101. For example, in the case of a design with a breakdown voltage of 1200 V, the n-type GaN drift layer 112 has a Si donor concentration of 1.5×10 16 cm -3 For example, in the p-type GaN layer 113, when a normally-off operation is possible, the Mg acceptor concentration can be set to 10 17 cm -3 It may be more than that.

[0037] The upper surface 113s of the p-type GaN layer 113 is a polar plane (c-plane) of the GaN single crystal. An n-type GaN source region 114 is disposed on the upper surface 113s, and a trench TR is formed therein. The trench TR extends from the upper surface of the source region 114 to the n-type GaN drift layer 112. A surface 113i of the p-type GaN layer 113 is exposed on the inner wall of the trench TR. The surface 113i forms a channel plane CS2. The channel plane CS2 is a nonpolar plane of the GaN single crystal. Preferably, the channel plane CS2 is an m-plane or an a-plane at an angle of 90°±1° from the c-plane. The trench TR having such a channel plane CS2 has an inner wall that is approximately perpendicular to the upper surface 113s. Therefore, the width of the trench TR in the x-direction can be reduced compared to a tapered trench. This enables miniaturization of the semiconductor device 101.

[0038] A gate structure 120 is disposed inside the trench TR. The gate structure 120 includes a crystalline AlN layer 121, a gate insulating film 122, and a gate electrode 123. The AlN layer 121 is disposed on the surface of the inner wall of the trench TR. The gate insulating film 122 is disposed on the surface of the AlN layer 121. The gate electrode 123 is disposed on the surface of the gate insulating film 122. The AlN layer 121, the gate insulating film 122, and the gate electrode 123 are similar to the AlN layer 21, the gate insulating film 22, and the gate electrode 23 of Example 1, and therefore detailed description thereof will be omitted.

[0039] The source electrode 124 is in contact with the upper surface of the source region 114. The source region 114 and the gate electrode 123 are insulated from each other by an interlayer insulating film 126. A drain electrode 125 is disposed on the back surface of the n-type GaN substrate 111.

[0040] (effect) A typical GaN substrate has a polar surface (c-plane). This is because a polar surface has a lower residual impurity concentration in the crystal than a non-polar surface, has excellent flatness during crystal growth, and is easy to fabricate. In the semiconductor device 101 of Example 2, by combining a GaN substrate having a polar surface with a trench gate structure, a non-polar surface (e.g., m-plane, a-plane) can be exposed on the inner wall of the trench TR. This makes it possible to form a MOSFET using a typical GaN substrate, with the channel surface CS2 being a non-polar surface.

[0041] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically useful.

[0042] (Variation) The technology described in this specification can be applied to semiconductor devices with various configurations. For example, it can be applied to a planar gate vertical D-MOSFET. In this case, a GaN wafer with a nonpolar principal surface such as the m-plane or a-plane can be used.

[0043] The p-type GaN layers 13 and 113 are examples of GaN layers.

[0044] Aspects of the present technology are listed below. [Aspect 1] a GaN layer made of p-type GaN single crystal and having a channel surface; an AlN layer disposed on the surface of the channel surface; a gate insulating film disposed on the surface of the AlN layer; a gate electrode disposed on a surface of the gate insulating film; Equipped with The semiconductor device, wherein the channel plane has an angle of 39° or more with respect to a polar plane of the GaN single crystal of the GaN layer. [Aspect 2] 2. The semiconductor device according to aspect 1, wherein the channel plane is a plane near an m-plane or a-plane of a GaN single crystal. [Aspect 3] 3. The semiconductor device according to aspect 1 or 2, wherein a region near the surface of the gate insulating film, including the interface between the gate insulating film and the AlN layer, is amorphous. [Aspect 4] 4. The semiconductor device according to any one of aspects 1 to 3, wherein the gate insulating film is AlSiO. [Aspect 5] 5. The semiconductor device according to any one of aspects 1 to 4, wherein a ratio of the thickness of the AlN layer to the thickness of the gate insulating film is 0.25 or less. [Aspect 6] 6. The semiconductor device according to any one of aspects 1 to 5, wherein the AlN layer has a thickness of 1 nm or more. [Aspect 7] the GaN layer is disposed on an upper surface of an n-type GaN drift layer; an n-type GaN source region is disposed on the top surface of the GaN layer; a trench is formed extending from an upper surface of the source region to the drift layer; the AlN layer, the gate insulating film, and the gate electrode are stacked in this order on the surface of the inner wall of the trench; the top surface of the GaN layer is a polar plane of the GaN single crystal; The surface of the inner wall of the trench is the channel surface. The semiconductor device according to any one of aspects 1 to 6. [Explanation of symbols]

[0045] 1: semiconductor device 10: semiconductor substrate 13: p-type GaN layer 21: AlN layer 22: gate insulating film 23: gate electrode CS: channel surface

Claims

1. a GaN layer made of p-type GaN single crystal and having a channel surface; an AlN layer disposed on the surface of the channel surface; a gate insulating film disposed on the surface of the AlN layer; a gate electrode disposed on a surface of the gate insulating film; Equipped with The semiconductor device, wherein the channel plane has an angle of 39° or more with respect to a polar plane of the GaN single crystal of the GaN layer.

2. 2. The semiconductor device according to claim 1, wherein said channel plane is a plane near an m-plane or a-plane of a GaN single crystal.

3. 2. The semiconductor device according to claim 1, wherein a region near the surface of said gate insulating film, including an interface between said gate insulating film and said AlN layer, is amorphous.

4. 4. The semiconductor device according to claim 3, wherein said gate insulating film is made of AlSiO.

5. 5. The semiconductor device according to claim 4, wherein a ratio of a thickness of said AlN layer to a thickness of said gate insulating film is 0.25 or less.

6. 6. The semiconductor device according to claim 5, wherein the AlN layer has a thickness of 1 nm or more.

7. the GaN layer is disposed on an upper surface of an n-type GaN drift layer; an n-type GaN source region is disposed on the top surface of the GaN layer; a trench is formed extending from an upper surface of the source region to the drift layer; the AlN layer, the gate insulating film, and the gate electrode are stacked in this order on the surface of the inner wall of the trench; the upper surface of the GaN layer is a polar surface of the GaN single crystal; The surface of the inner wall of the trench is the channel surface. The semiconductor device according to any one of claims 1 to 6.

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