Method of manufacturing silicon carbide semiconductor device

Abstract

To provide a method of manufacturing a silicon carbide semiconductor device capable of suppressing damage to an SiC wafer caused by plasma discharge.SOLUTION: A method of manufacturing a silicon carbide semiconductor device includes: a first step of preparing a silicon carbide semiconductor wafer, in which a first semiconductor layer of a first conductivity type of a lower impurity concentration than that of a departure wafer of the first conductivity type is provided on the side of a front face of the departure wafer; a second step of forming semiconductor regions of the first conductivity type and a second conductivity type inside of the first semiconductor layer by means of ion implantation; a third step of forming a trench on the side of a front face of the silicon carbide semiconductor wafer; a fourth step of forming a carbon film on the front face of the silicon carbide semiconductor wafer; a fifth step of performing cycle purge on the silicon carbide semiconductor wafer; a sixth step of extracting the silicon carbide semiconductor wafer; and a seventh step of activating the semiconductor regions which are formed by the ion implantation.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] This disclosure relates to methods for manufacturing silicon carbide semiconductor devices. [Background technology]

[0002] Conventionally, a technique for depositing a protective film of a diamond-like carbon film or an organic film on a surface and then annealing the surface is known (see, for example, Patent Document 1 below). Also known is a technique for maintaining the substrate in an atmospheric state until the thermal expansion of the substrate is saturated, then evacuating the inside of a furnace, and then supplying gases that are raw materials for film formation into the furnace, and forming a thin film on the surface of the substrate by a chemical reaction (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3760688 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-857947 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional methods for manufacturing silicon carbide semiconductor devices have had the problem that when sputtering a silicon carbide (SiC) wafer using plasma discharge, the SiC wafer is damaged and defects are formed. An object of this disclosure is to provide a method for manufacturing a silicon carbide semiconductor device that can suppress damage to the SiC wafer caused by plasma discharge. [Means for solving the problem]

[0005] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a method for manufacturing a silicon carbide semiconductor device according to this disclosure has the following features. First, a first step is performed to prepare a silicon carbide semiconductor substrate having a first semiconductor layer of a first conductivity type provided on the front surface side of a starting substrate of a first conductivity type, the first semiconductor layer having a lower impurity concentration than the starting substrate. Next, a second step is performed to form semiconductor regions of first conductivity type and second conductivity type in the first semiconductor layer by ion implantation. Next, a third step is performed to form a trench on the front surface side of the silicon carbide semiconductor substrate. Next, a fourth step is performed to form a carbon film on the front surface of the silicon carbide semiconductor substrate. Next, a fifth step is performed to cycle purge the silicon carbide semiconductor substrate. Next, a sixth step is performed to remove the silicon carbide semiconductor substrate. Next, a seventh step is performed to activate the semiconductor regions formed by ion implantation.

[0006] According to the disclosure above, after carbon film deposition, cycle purging is performed to remove unstable foreign matter accumulated in the target and chamber. This reduces the amount of foreign matter in the chamber and prevents the foreign matter from adhering to the SiC wafer. This suppresses abnormal discharge during plasma ignition, preventing chipping of parts of the trench sidewalls and improving yield. [Effects of the Invention]

[0007] The method for manufacturing a silicon carbide semiconductor device according to the present disclosure has the effect of suppressing damage to the SiC wafer caused by plasma discharge. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to an embodiment; [Figure 2] 1A to 1C are cross-sectional views (part 1) schematically showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 3] 5A and 5B are cross-sectional views (part 2) schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 4]10A and 10B are cross-sectional views (part 3) schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 5] 10A and 10B are cross-sectional views (part 4) schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 6] 5 is a cross-sectional view (part 5) schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 7] 10 is a cross-sectional view (part 6) schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 8] 7 is a cross-sectional view schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment (part 7). FIG. [Figure 9] 8 is a cross-sectional view schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment (part 8). FIG. [Figure 10] 1 is a flowchart showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11] 1 is a schematic diagram of a sputtering apparatus used in a method for manufacturing a silicon carbide semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Summary of Embodiments of the Present Disclosure> In order to solve the above-mentioned problems and achieve the object of the present disclosure, a method for manufacturing a silicon carbide semiconductor device according to this disclosure has the following features. First, a first step is performed to prepare a silicon carbide semiconductor substrate having a first semiconductor layer of a first conductivity type provided on the front surface side of a starting substrate of a first conductivity type, the first semiconductor layer having a lower impurity concentration than the starting substrate. Next, a second step is performed to form semiconductor regions of first conductivity type and second conductivity type in the first semiconductor layer by ion implantation. Next, a third step is performed to form a trench on the front surface side of the silicon carbide semiconductor substrate. Next, a fourth step is performed to form a carbon film on the front surface of the silicon carbide semiconductor substrate. Next, a fifth step is performed to cycle purge the silicon carbide semiconductor substrate. Next, a sixth step is performed to remove the silicon carbide semiconductor substrate. Next, a seventh step is performed to activate the semiconductor regions formed by ion implantation.

[0010] According to the disclosure above, after carbon film deposition, cycle purging is performed to remove unstable foreign matter accumulated in the target and chamber. This reduces the amount of foreign matter in the chamber and prevents the foreign matter from adhering to the SiC wafer. This suppresses abnormal discharge during plasma ignition, preventing chipping of parts of the trench sidewalls and improving yield.

[0011] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the fifth step, cycle purging is performed while the silicon carbide semiconductor substrate is left in the film formation chamber.

[0012] According to the above disclosure, foreign matter in an unstable state that has accumulated in the target or chamber can be removed during cycle purging.

[0013] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the fifth step, Ar gas or N 2 gas is used.

[0014] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the fifth step, a gas is introduced through a sputtering gas inlet.

[0015] According to the disclosure above, the introduced gas can remove unstable foreign matter deposited on the target or in the chamber.

[0016] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, the gas flow rate in the fifth step is greater than the gas flow rate in the fourth step.

[0017] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the fifth step, cycle purging is performed a plurality of times.

[0018] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, the silicon carbide semiconductor device is an FET, an IGBT, or a diode.

[0019] <Findings underlying this disclosure> First, we will explain the issues with conventional methods for manufacturing silicon carbide semiconductor devices. Silicon carbide (SiC) is expected to be a next-generation semiconductor material that will replace silicon (Si). Semiconductor elements using silicon carbide as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages compared to conventional semiconductor elements using silicon as the semiconductor material, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of conventional semiconductor elements using silicon as the semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, namely, the band gap of silicon is about three times larger than that of silicon, and its dielectric breakdown field strength is nearly one order of magnitude greater than that of silicon.

[0020] To date, commercially available silicon carbide semiconductor devices include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) with planar gate structures or trench gate structures.

[0021] The problem with SiC is that the diffusion coefficient of impurities in SiC is extremely small compared to Si. When forming an impurity layer by ion implantation, it is difficult to form it deep in the depth direction. When forming a structure in the vertical direction of the substrate, such as in a vertical MOSFET with a trench gate structure, the impurity layer is formed by combining ion implantation and epitaxial growth.

[0022] However, epitaxial growth can cause defects in the substrate, degrading the characteristics of the semiconductor device. Furthermore, epitaxial growth equipment requires process control and maintenance costs. For this reason, development is underway for silicon carbide semiconductor devices that do not use epitaxial growth, but instead form an impurity layer solely through ion implantation. This involves combining standard energy ion implantation (up to 900 KeV) with high-acceleration ion implantation (acceleration of 1 MeV or greater), which allows impurities to be implanted deeper.

[0023] In the manufacture of semiconductor devices, high temperatures of 1500°C or higher are required for annealing to activate impurities implanted into SiC. Annealing at high temperatures causes the Si on the SiC surface to evaporate, causing surface roughness. Therefore, surface roughness is suppressed by forming a protective film such as a carbon film on the surface and activating it. In the manufacturing process for vertical SiC-MOSFETs with trench gate structures, some models perform annealing to activate the dopants after forming the trench. Annealing is performed in an Ar (argon) atmosphere at high temperatures of 1600°C or higher. Since this is after forming a trench about 1 μm deep, there are uneven surfaces, so a carbon film of about 250 nm must be deposited to deposit evenly.

[0024] The PVD (Physical Vapor Deposition) method is effective for depositing carbon films, as it has a relatively high adhesiveness, but carbon has the characteristic that fewer atoms are sputtered by plasma compared to metals. Therefore, from the viewpoint of productivity, it is necessary to increase the RF (Radio Frequency) output as much as possible to shorten the processing time.

[0025] The sequence of carbon film sputtering in conventional processing is shown in Table 1. In conventional processing, for example, a SiC wafer is placed on a stage in the chamber of a sputtering device, and a carbon film is deposited for 15 minutes at a pressure of 0.5 Pa, an Ar flow rate of 60 sccm, and an RF power of 1500 W, followed by unloading from the chamber of the sputtering device.

[0026] [Table 1]

[0027] The sputtering method uses plasma discharge, but generally, when a plasma state is created, the most unstable state occurs when the plasma is ignited. In particular, if there is foreign matter adhering to the SiC wafer, using high power output when igniting the plasma can easily cause abnormal discharge originating from the foreign matter, which can damage the SiC wafer and cause defects. The source of foreign matter is deposits on the target or in the chamber. When high-power plasma hits deposits in an unstable state, they become foreign matter and adhere to the SiC wafer.

[0028] This defect is particularly noticeable when a trench is formed on the SiC wafer, and when abnormal discharge occurs, part of the sidewall of the trench is chipped off. It is presumed that this occurs when foreign matter adheres near the trench sidewall, causing damage to the trench sidewall due to abnormal discharge when plasma is ignited, resulting in part of the trench sidewall being chipped off.

[0029] In order to solve the above-mentioned problems, the present disclosure provides a method for manufacturing a silicon carbide semiconductor device that reduces foreign matter generated during sputtering, suppresses abnormal discharge originating from foreign matter generated during plasma ignition, and suppresses damage and defects on the SiC wafer.

[0030] (Embodiment) Preferred embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - appended to n or p indicate a higher or lower impurity concentration than layers or regions without these prefixes, respectively. In the following description of the embodiments and the accompanying drawings, similar components are given the same reference numerals, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of variations in manufacturing.

[0031] The semiconductor device according to the present disclosure is configured using a wide bandgap semiconductor. In the embodiments, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a trench SiC-MOSFET 50 as an example. Fig. 1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the embodiments. Fig. 1 shows only the active region of the trench MOSFET 50 through which a main current flows.

[0032] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment has n + The first main surface (front surface) of the starting substrate 1, for example, the (0001) surface (Si surface), is provided with n + type buffer layer 16 and a 1n - A silicon carbide epitaxial layer 2 is deposited.

[0033] n + The starting substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). + The mold buffer layer 16 has a thickness of, for example, 1 μm or more and 5 μm or less, and a nitrogen content of 1×10 17 / cm 3 More than 1×10 18 / cm 3It is a highly doped layer doped at a high concentration of n + The buffer layer 16 is a 1n-th - promotes the recombination of holes from the n-type silicon carbide epitaxial layer 2, + The concentration of holes reaching the starting mold substrate 1 is controlled to suppress the occurrence of stacking faults and the expansion of their area.

[0034] 1st n - The silicon carbide epitaxial layer 2 is + The starting substrate 1 is doped with a lower impurity concentration, for example, nitrogen. - The 1n-type drift layer - The n-type silicon carbide epitaxial layer 2 + The surface side opposite to the mold starting substrate 1 side is the 2nth - The 2n-th silicon carbide layer 6 is formed. - The silicon carbide layer 6 is + The starting substrate 1 is lower than the first n - The n-type silicon carbide epitaxial layer 2 is a high-concentration n-type drift layer that is doped with, for example, nitrogen at a higher impurity concentration than the n-type silicon carbide epitaxial layer 2. + Starting substrates 1 and n - The silicon carbide epitaxial layer 2 and the 2n-type - The silicon carbide layer 6 and the p-type base layer 3 described later are collectively referred to as a silicon carbide semiconductor substrate.

[0035] n + A back electrode (drain electrode) is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base) of the mold starting substrate 1. The back electrode constitutes the drain electrode. A drain electrode pad 14 is provided on the surface of the back electrode.

[0036] A trench gate structure is formed on the first main surface side (p-type base layer 3 side) of the silicon carbide semiconductor substrate. Specifically, the trench 18 is formed between the n-type + The second n-type insulating layer 1 is formed on the surface opposite to the p-type starting substrate 1 side through the p-type base layer 3. -The gate insulating film 9 is formed on the bottom and side walls of the trench 18 along the inner wall of the trench 18, and the gate electrode 10 is formed inside the gate insulating film 9 in the trench 18. The gate electrode 10 is formed by the gate insulating film 9. - Silicon carbide epitaxial layer 2, 2n - The gate electrode 10 is insulated from the p-type silicon carbide layer 6 and the p-type base layer 3. A part of the gate electrode 10 may protrude from above the trench 18 (on the source electrode pad 15 side) toward the source electrode pad 15.

[0037] 1st n - The silicon carbide epitaxial layer 2 and the 2n-th - The first p type silicon carbide layer 6 contains + Type region 4 and 2p + A mold region 5 is selectively provided. + The mold region 4 reaches a position deeper than the bottom of the trench 18 on the drain side. + The lower end (drain side end) of the mold region 4 is located closer to the drain side than the bottom of the trench 18. + The mold region 4 is provided between the trenches 18. As shown in FIG. + The type region 4 is p ++ contact region 8, but ++ It is also possible to have a configuration in which the first p + The upper surface of the mold region 4 is the 2nth - The p-type silicon carbide layer 6 has a surface layer formed thereon and is in contact with the lower surface of the p-type base layer 3 .

[0038] 2nd p. + The lower end of the mold region 5 is located closer to the drain side than the bottom of the trench 18. + The mold region 5 is formed at a position facing the bottom of the trench 18 in the depth direction z. + The width of the mold region 5 is wider than the width of the trench 18. The bottom of the trench 18 is + The p-type base layer 3 and the second p-type region 5 may be + 2nth region sandwiched between mold regions 5 -The second p + It may not be in contact with the mold region 5. + The top surface of the mold region 5 may be located closer to the drain side or the source side than the bottom of the trench 18. + Type region 4 and 2p + The mold region 5 is doped with, for example, aluminum (Al).

[0039] 1st p. + A part of the mold region 4 is extended to the trench 18 side to form a second p + In this case, the first p + A part of the mold region 4 is the first p + Type region 4 and 2p + The direction x in which the mold regions 5 are arranged (hereinafter referred to as the first direction) and the direction y perpendicular to the direction x (hereinafter referred to as the second direction) are - The silicon carbide layer 6 may have a planar layout in which the first p + Part of type region 4 and 2p + It is sufficient that a part of the mold region 5 is connected at least at one point. + Type region 5 and 1n - Holes generated when avalanche breakdown occurs at the junction of the silicon carbide epitaxial layer 2 can be efficiently evacuated to the source electrode 13, reducing the load on the gate insulating film 9 and improving reliability.

[0040] 1st n - A p-type base layer 3 is provided on the first main surface side of the silicon carbide epitaxial layer 2. The impurity concentration of the p-type base layer 3 is, for example, + The impurity concentration of the p-type base layer 3 may be lower than that of the n-type region 4. This makes it possible to prevent a decrease in breakdown voltage due to punch-through by suppressing the expansion of the depletion layer in the p-type base layer 3, even if the concentration is reduced to lower the threshold voltage. + Type source region 7 and p ++ The n-type contact region 8 is selectively provided. +Type source region 7 and p ++ The mold contact regions 8 abut each other.

[0041] Although only two trench MOS structures are shown in FIG. 1, many more trench MOS gate (insulated gate made of metal-oxide-semiconductor) structures may be arranged in parallel.

[0042] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the trench 18. The source electrode 13 is connected to the n-type semiconductor layer 11 through a contact hole opened in the interlayer insulating film 11. + Type source region 7 and p ++ The source electrode 13 is in contact with the mold contact region 8. The source electrode 13 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. A source electrode pad 15 is provided on the source electrode 13.

[0043] (Method for manufacturing silicon carbide semiconductor device according to embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Figures 2 to 9 are cross-sectional views schematically showing states during the manufacturing process of a silicon carbide semiconductor device according to an embodiment. Figure 10 is a flowchart showing the method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0044] First, as shown in Figure 2, we used n-type silicon carbide. + A first conductivity type starting substrate (a first conductivity type starting substrate) 1 is - n-type silicon carbide epitaxial layer (first semiconductor layer of first conductivity type) 2 and + A silicon carbide semiconductor substrate 30 on which a type buffer layer 16 is deposited is prepared (first step). + The starting substrate has a diameter of 150 mm. This silicon carbide semiconductor substrate 30 may be purchased or manufactured by + Purchase a substrate containing only the starting substrate 1 and grow n + The first buffer layer 16 and the first n -The n-type silicon carbide epitaxial layer 2 may be formed to form the above-mentioned silicon carbide semiconductor substrate 30. In this case, + On the first main surface of the starting substrate 1, an n-type impurity, for example, a silicon carbide n-type impurity, is doped. + The n type buffer layer 16 is then epitaxially grown. + A first n-type impurity, such as nitrogen atoms, is doped on the n-type buffer layer 16. - A silicon carbide epitaxial layer 2 is grown.

[0045] Next, the 1nth - A resist mask (not shown) having desired openings is formed on the surface of the silicon carbide epitaxial layer 2 by photolithography. Then, as shown in FIG. 3, p-type impurities, for example, aluminum atoms, are implanted by ion implantation to form a first n-type silicon carbide epitaxial layer. - The first p-type silicon carbide epitaxial layer 2 has a depth of about 0.6 μm. + Type area 4, 2nd p + For example, let's say mold area 5 is 3 × 10 18 / cm 3 The impurity concentration is

[0046] Next, the 1nth - A resist mask (not shown) having desired openings is formed by photolithography on the surface of the silicon carbide epitaxial layer 2. Then, as shown in FIG. 4, a second n-type epitaxial layer having a thickness of about 0.7 μm and doped with n-type impurities such as nitrogen by ion implantation is formed. - The silicon carbide layer 6 is formed by, for example, 2×10 17 / cm 3 The impurity concentration is

[0047] Next, n - A resist mask (not shown) having desired openings is formed on the surface of the silicon carbide epitaxial layer 2 by photolithography. Then, as shown in FIG. - P-type impurity ions are implanted into the silicon carbide epitaxial layer 2. As a result, a p-type base layer 3 having a thickness of about 0.5 μm is formed, for example, by implanting 3×1017 / cm 3 The impurity concentration is

[0048] Next, a resist mask (not shown) having desired openings is formed by photolithography on the surface of the p-type base layer 3. Then, as shown in FIG. - n-type impurity ions are implanted into a part of the silicon carbide epitaxial layer 2. As a result, an n-type silicon carbide epitaxial layer having a thickness of about 0.5 μm is formed. + The mold source layer 7 is, for example, 1×10 19 / cm 3 The impurity concentration is

[0049] Next, an ion implantation mask having predetermined openings is formed, and n + P-type impurities such as aluminum are ion-implanted into a part of the p-type source layer 7 and a part of the p-type base layer 3. As a result, as shown in FIG. ++ The contact area 8 is, for example, 1×10 20 / cm 3 The impurity concentration is

[0050] In this way, the n of the silicon carbide semiconductor substrate 30 - p-type impurity ions are implanted into the silicon carbide epitaxial layer 2 to form a p-type semiconductor region (p-type base layer 3, first p + Type area 4, 2nd p + Type regions 5 and p ++ In addition, n-type impurities are ion-implanted to form an n-type semiconductor region (second n-type contact region 8). - type silicon carbide layer 6 and n + A source region 7) is formed (step S1: second step).

[0051] Next, n + A trench forming mask having a predetermined opening is formed by photolithography on the surface of the source region 7, using, for example, an oxide film. Next, as shown in FIG. + The second p-type source region 7 and the p-type base layer 3 are penetrated. +A trench 18 is formed so as to reach the mold region 5 (third step). Next, the trench forming mask is removed. + Type source region 7 and p ++ After forming the contact region 8, the trench 18 is formed. + Type source region 7 and p ++ A mold contact region 8 may be formed.

[0052] 9, a carbon film 19 is formed on the surface of the silicon carbide semiconductor substrate 30 by sputtering (step S2: fourth process). In this embodiment, a trench 18 is formed, and a carbon film of about 250 nm is deposited to deposit evenly on the surface of the trench 18.

[0053] FIG. 11 is a schematic diagram of a sputtering apparatus used in a method for manufacturing a silicon carbide semiconductor device according to an embodiment. The sputtering apparatus shown is a single-wafer type apparatus that processes semiconductor wafers one by one. In the sputtering apparatus, a SiC wafer 31 is placed on a stage 32 in a chamber (film formation chamber) 35. Ar ions or N ions are collided with a C (carbon) target 34 under plasma discharge, and the target material dislodged by the collision is deposited on the opposing SiC wafer 31. The sputtering apparatus includes an adhesion shield 33, a valve 37 for controlling the injection of sputtering gas such as Ar gas or N gas, an exhaust system 36 for exhausting the sputtering gas, a sputtering gas inlet 38, and an automated load-lock (L / L) chamber 39. The SiC wafer 31 is a silicon carbide semiconductor substrate 30 having p-type and n-type semiconductor regions and trenches 18 formed therein.

[0054] In this embodiment, cycle purging is performed while the SiC wafer 31 remains in the deposition chamber (step S3: fifth process). The cycle purging involves multiple cycles of pressurization, in which an inert gas such as Ar gas or N2 gas is introduced into the chamber through the sputtering gas inlet 38, and evacuation, in which the inert gas such as Ar gas or N2 gas is exhausted through the exhaust system 36, without generating plasma after sputtering. This cycle of pressurization and evacuation is performed multiple times as a set. By introducing an inert gas such as Ar gas or N2 gas through the sputtering gas inlet 38, the introduced inert gas can remove unstable foreign matter deposited on the target or in the chamber. Furthermore, the flow rate of the inert gas during cycle purging is preferably greater than the flow rate during carbon film formation. Furthermore, the pressurization pressure during cycle purging is preferably greater than the pressure during carbon film formation.

[0055] Table 2 shows the carbon film sputtering sequence in the process of this embodiment. In the process of this embodiment, for example, SiC wafer 31 is loaded onto stage 32 in chamber 35 of the sputtering device, and a carbon film is deposited in step 1 at a pressure of 0.5 Pa, an Ar flow rate of 60 sccm, and an RF power of 1500 W for 15 minutes. Then, in step 2, chamber 35 is evacuated for about 5 seconds. Then, in step 3, pressure is increased to 100 Pa and an Ar flow rate of 1000 sccm for about 5 seconds, and steps 2 and 3 are repeated one or more times. After this, the process is performed in multiple steps, including unloading from the chamber of the sputtering device.

[0056] [Table 2]

[0057] The values ​​in Table 2 are examples, and in step 1, which deposits the carbon film, the pressure is preferably 0.1 Pa to 1.0 Pa, the Ar flow rate is 10 sccm to 100 sccm, the RF power is 1000 W to 2000 W, and the time is 10 minutes to 20 minutes. In step 2, which is vacuuming, the time is preferably 4 seconds to 60 seconds. In step 3, which is pressurizing, the pressure is preferably 50 Pa or higher, the Ar flow rate is 500 sccm or higher, and the time is preferably 4 seconds to 60 seconds. Here, Ar is used as an example, but the values ​​are the same for N2 and other inert gases.

[0058] In this way, by performing cycle purging, it is possible to remove foreign matter that has accumulated in an unstable state inside the target or chamber. During cycle purging, the SiC wafer 31 in the chamber can be either removed or left in place, and in this case, the cycle purging was performed while it was placed inside the stage 32. The SiC wafer 31 is then removed (step S4: sixth process). By placing it inside the stage 32, foreign matter on the SiC wafer 31 can be removed during cycle purging.

[0059] By performing cycle purging, foreign matter in the chamber is reduced and adhesion of foreign matter to the SiC wafer is suppressed. This suppresses abnormal discharge during plasma ignition, thereby preventing chipping of portions of the trench sidewalls and improving yield. Note that the trench here is not limited to trench 18 functioning as a gate trench, but includes all grooves provided on the front surface of silicon carbide semiconductor substrate 30.

[0060] Next, a heat treatment is performed in an inert gas atmosphere at about 1750° C. to activate the impurity regions formed by ion implantation (step S5: seventh step).

[0061] Next, n + Type source region 7 and p ++A gate insulating film 9 is formed along the surface of the contact region 8 and the bottom and sidewalls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1300°C in a gas atmosphere containing oxygen. Alternatively, this gate insulating film 9 may be formed by a deposition method using a chemical reaction such as high temperature oxidation (HTO).

[0062] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 18 to form the gate electrode 10.

[0063] Next, an insulating film is formed on the surface of the gate electrode 10. For example, this is annealed in an oxygen atmosphere at 1000°C to form a thermal oxide film. Next, the surface is protected with a protective film, for example, formed of a photoresist. Next, the insulating film formed on the back surface, the gate electrode, and the gate insulating film are all removed by dry etching. Next, the protective film formed on the surface is removed in an ashing and stripping process. In this case, stripping was performed by ashing in oxygen plasma and cleaning with SPM.

[0064] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. Next, the interlayer insulating film 11 and the gate insulating film 10 are patterned by photolithography. + Type source region 7 and p ++ A contact hole is formed to expose the contact region 8. Next, a conductive film, such as nickel, that will become the source electrode 13 is formed in the contact hole and on the interlayer insulating film 11 by, for example, sputtering. Next, a heat treatment at about 700°C is performed to selectively react the conductive film with silicon carbide, and then the unreacted portion of the conductive film is selectively removed to leave the source electrode 13 only in the contact hole, and the n + Type source region 7 and p ++ The mold contact region 8 is brought into contact with the source electrode 13 .

[0065] Next, a metal film that will become the source electrode pad 15 is formed, for example, by sputtering, on the source electrode 13 on the front surface of the silicon carbide semiconductor substrate and on the interlayer insulating film 11. At this time, a barrier metal (not shown) made of titanium or titanium nitride may be formed first. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5.5 μm. The electrode pad may be made of, for example, aluminum containing 1% silicon (Al-Si). Next, the metal film is selectively removed to form the source electrode pad 15.

[0066] Next, n + After the front surface of the starting mold substrate 1 is covered with a protective film (not shown) for protection, + The starting substrate 1 is polished from the back side to form a n + The starting mold substrate 1 may be thinned to the product thickness.

[0067] Next, n + On the second main surface of the starting substrate 1, a conductive film, for example, a molybdenum film and a nickel film, which will become a drain electrode (not shown), are successively formed by, for example, a sputtering method. After that, a heat treatment such as laser annealing is performed to form an n + The drain electrode is formed by reacting the starting mold substrate 1 with a conductive film to form an ohmic junction.

[0068] Next, on the surface of the drain electrode, films of, for example, titanium, nickel and gold are formed in this order as drain electrode pad 14. In this manner, the silicon carbide semiconductor device shown in FIG.

[0069] As described above, according to the embodiment, after carbon film deposition, cycle purging is performed to remove unstable foreign matter accumulated in the target and chamber. This reduces the amount of foreign matter in the chamber and prevents the foreign matter from adhering to the SiC wafer. This suppresses abnormal discharge during plasma ignition, preventing chipping of the trench sidewall and improving yield.

[0070] The present disclosure can be modified in various ways without departing from the spirit and scope of the present disclosure. In the above-described embodiments, for example, the dimensions and impurity concentrations of each component are set in various ways according to the required specifications. Furthermore, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. Furthermore, while each embodiment has been described using a MOSFET, the present disclosure is not limited to this and can also be applied to an IGBT, a FET with a trench structure, or a diode. Furthermore, each of the above-described embodiments can also be applied to wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN). [Industrial Applicability]

[0071] INDUSTRIAL APPLICABILITY As described above, a method for manufacturing a silicon carbide semiconductor device according to the present disclosure is useful for high-voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0072] 1n + Starting substrate 2 1stn - Silicon carbide epitaxial layer 3 p-type base layer 4 1st p. + type area 5 2nd p. + type area 6 2nd n - mold silicon carbide layer 7n + Type Source Area 8 p ++ Mold contact area 9 Gate insulating film 10 gate electrode 11 Interlayer insulating film 13 Source electrode 14 Drain electrode pad 15 Source electrode pad 16n + Mold buffer layer 18 Trench 19 Carbon film 30 Silicon carbide semiconductor substrate 31 SiC wafers 32 stages 33 Anti-adhesion plate 34 C Target 35 Chambers 36 Exhaust system 37 Valve 38 Sputtering gas inlet 39 Automatic transport load lock (L / L) chamber 50 Trench type SiC-MOSFET

Claims

1. a first step of preparing a silicon carbide semiconductor substrate having a first conductivity type starting substrate and a first semiconductor layer of the first conductivity type having a lower impurity concentration than the starting substrate provided on a front surface side of the starting substrate; a second step of forming semiconductor regions of a first conductivity type and a second conductivity type in the first semiconductor layer by ion implantation; a third step of forming a trench on the front surface side of the silicon carbide semiconductor substrate; a fourth step of forming a carbon film on the front surface of the silicon carbide semiconductor substrate; a fifth step of cycle purging the silicon carbide semiconductor substrate; a sixth step of removing the silicon carbide semiconductor substrate; a seventh step of activating the semiconductor region formed by ion implantation; 2. A method for manufacturing a silicon carbide semiconductor device, comprising:

2. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the fifth step, cycle purging is performed while the silicon carbide semiconductor substrate is left in the film formation chamber.

3. In the fifth step, Ar gas or N 2 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a gas is used.

4. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the fifth step, a gas is introduced through a sputtering gas inlet.

5. 2 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein a gas flow rate in the fifth step is greater than a gas flow rate in the fourth step.

6. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the fifth step, cycle purging is performed a plurality of times.

7. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is an FET, an IGBT, or a diode.

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