Semiconductor structure including conductive junction interface, and related manufacturing process

Abstract

To provide a structure in which a single crystal semiconductor functional layer and a semiconductor carrier substrate are included and electrically joined on a conductive junction interface.SOLUTION: A semiconductor structure (100) includes: a functional layer (10) extending on a principal plane (x, y) and made of a single crystal semiconductor material; a carrier substrate (30) made of a semiconductor material; and an interface region (20) between the functional layer (10) and the carrier substrate (30) extending in parallel on the principal plane (x, y). The structure (100) should be noticed in including nodes (21) in the interface region (20), is conductive while including a metal material forming ohmic contact with the functional layer (10) and the carrier substrate (30), has a thickness equal to or less than 10 nm along an axis (z) vertical to the principal plane (x, y), and is separated or joined. The separation nodes (21) are separated from each other by a direct contact region (22) between the functional layer (10) and the carrier substrate (30).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor materials for microelectronic components. In particular, the present invention relates to a structure comprising a monocrystalline semiconductor layer and a semiconductor carrier substrate joined at an electrically conductive bonding interface. The present invention also relates to a process for manufacturing such a structure. [Background technology]

[0002] It is common to form semiconductor structures by transferring a thin, high-crystalline-quality semiconductor functional layer onto a semiconductor carrier substrate with a low crystalline quality. One well-known thin-layer transfer solution is the Smart Cut™ process, which uses photo-ion implantation and direct bonding at the bonding interface. In addition to the economic benefits associated with the slimming of the high-quality material of the functional layer, the semiconductor structure may also offer advantageous properties, such as those related to the thermal or electrical conductivity or mechanical compatibility of the carrier substrate.

[0003] For example, in the field of power electronics, it may be advantageous to establish electrical conduction between the functional layer and the carrier substrate in order to form vertical components. For example, in the case of structures comprising a functional layer made of monocrystalline silicon carbide and a carrier substrate made of lower-quality silicon carbide (whether monocrystalline or polycrystalline), the bonding interface must exhibit the lowest possible resistivity, preferably below 1 mΩ cm. 2 or 0.1 mΩ cm 2 is less than.

[0004] Some prior art solutions propose direct semiconductor-semiconductor bonding between the functional layer and the carrier substrate to establish vertical electrical conduction, however, obtaining a good quality interface through such bonding can be difficult. In Non-Patent Document 1, direct bonding (SAB "surface activated bonding") is performed after activating the surface by bombardment with argon. Such a treatment before bonding produces a very high density of lateral bonds, promotes the formation of covalent bonds at the bonding interface, and therefore produces high bonding energy. However, this method has the drawback of producing an amorphous layer at the bonding surface, which adversely affects the vertical electrical conduction between the thin layer and the carrier substrate. To overcome this problem, particularly in Patent Document 1, heavy doping of the surface is proposed.

[0005] Other prior art solutions propose forming conductive bonds based on metal layers deposited on the surfaces to be joined. For example, publications such as "Non-Patent Document 2" and "Patent Document 2" describe the deposition of a tungsten layer and a silicon layer to form a conductive intermediate layer based on tungsten disilicide (WSi2). One drawback of this method can result from the formation of voids in this intermediate layer due to the shrinkage of the silicide relative to the initially deposited material. This, in particular, can affect the quality of the surface semiconductor layer and the entire semiconductor structure, to the point of making it unusable for the intended application. In addition, it is difficult to reduce the resistivity of the junction interface to the level required by some applications that require very good vertical electrical conduction.

[0006] Subject of the Invention The present invention relates to an alternative solution to the prior art and aims to overcome the above-mentioned drawbacks in whole or in part. In particular, the present invention relates to a structure comprising a monocrystalline semiconductor functional layer and a semiconductor carrier substrate, which are joined at an electrically conductive bonding interface. The present invention also relates to a process for producing such a structure. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] European Patent No. 3168862 [Patent Document 2] U.S. Patent No. 7,208,392 [Non-patent literature]

[0008] [Non-Patent Document 1] F.Mu.et al.ECS Transactions,86(5)3-21,2018 [Non-patent document 2] Letertre.“Slicon Carbide and related materials”,Materials Science Forum.Vol389-393,April,2002 Summary of the Invention

[0009] The present invention relates to a semiconductor structure comprising a functional layer made of monocrystalline semiconductor material extending in a main plane, a carrier substrate made of semiconductor material, and an interface region between the functional layer and the carrier substrate extending parallel to the main plane, the interface region being such that: - comprises a metallic material that is electrically conductive and forms ohmic contact with the functional layer and the carrier substrate, - has a thickness along an axis (z) perpendicular to the major plane (x, y) of less than or equal to 30 nm, - separated or joined, where separated nodes are notable in that they include nodes that are separated from one another by areas of direct contact between the functional layer and the carrier substrate.

[0010] According to other advantageous and non-limiting features of the present invention, the methods may be employed singly or in any technically feasible combination.

[0011] the functional layer and the carrier substrate are made of the same semiconductor material and have the same doping type; the semiconductor material of the functional layer is selected from silicon carbide, silicon, gallium nitride, and germanium; the semiconductor material of the carrier substrate is selected from silicon carbide, silicon, gallium nitride and germanium and has a monocrystalline, polycrystalline or amorphous structure; the metallic material of the nodule is selected from the group consisting of tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper; In the mid-plane of the interface area, the degree of nodule coverage is between 1% and 70% Nodules: 0.1mΩcm 2 less than 0.01 mΩcm, preferably 0.01 mΩcm 2 To obtain an interfacial region resistivity of 0.1 mΩ cm 2 less than 0.01 mΩcm, preferably 0.01 mΩcm 2 and having a resistivity of: The nodules (21) have a thickness of 20 nm or less, or 10 nm or less.

[0012] The invention also relates to a power component manufactured on and / or in a functional layer of a semiconductor structure as described above and comprising at least one electrical contact on and / or in a carrier substrate at the level of the back side of the semiconductor substrate.

[0013] Finally, the invention relates to a process for manufacturing the structure described above, comprising the following steps:

[0014] a) providing a functional layer made of a monocrystalline semiconductor material having a free surface to be bonded; b) providing a carrier substrate made of a semiconductor material having a free surface to be bonded; c) depositing a film made of a metallic material capable of forming ohmic contact with the functional layer and the carrier substrate, the film having a thickness of less than or equal to 20 nm on the free surface to be bonded of the functional layer and / or on the free surface to be bonded of the carrier substrate in a non-oxidizing controlled atmosphere; d) forming intermediate structures comprising an operation of directly bonding the free surfaces of the functional layer and the carrier substrate to be bonded, each intermediate structure comprising an encapsulated film derived from one or more films deposited in step c) under a non-oxidizing controlled atmosphere, e) Annealing the intermediate structure at a temperature above the critical temperature to induce splitting of the encapsulated film into conductive nodes that form ohmic contacts with the functional layer and the carrier substrate, and to form interfacial regions.

[0015] According to other advantageous and non-limiting features of the present invention, the methods may be employed singly or in any technically feasible combination.

[0016] the functional layer and the carrier substrate are made of the same semiconductor material and have the same doping type; Step a) is a manufacturing process including implanting optical species into a donor substrate to form a front surface of the donor substrate and a buried weakened surface separating the functional layer; Step a) comprises the formation of a donor substrate (1) by epitaxially growing a donor layer on an initial substrate, the implantation of which is carried out later in the manufacturing process; step d) comprises, after direct bonding resulting in a bonded assembly comprising a donor substrate and a carrier substrate, a separation at the level of the embedded weakened surface, to form, on the one hand, an intermediate structure comprising the functional layer, the encapsulating membrane and the carrier substrate, and, on the other hand, a manufacturing process for forming the remainder of the donor substrate; a manufacturing process comprising, before the deposition step c), a step c') of deoxidation of the free bonded surface of the functional layer and / or the free bonded surface of the carrier substrate, a manufacturing process in which the deposition of step c) and the direct bonding of step d) are carried out in one step in the same equipment; a manufacturing process in which the thickness of the film deposited in step c) is 10 nm or less, or 5 nm or less, or 2 nm or less; Steps c) and d) are manufacturing processes carried out in a vacuum; a manufacturing process in which the deposition step c) is carried out at ambient temperature using sputtering techniques; a manufacturing process in which the semiconductor material of the functional layer is selected from silicon carbide, silicon, gallium nitride, and germanium; The semiconductor material of the carrier substrate is selected from the group consisting of silicon carbide, silicon, gallium nitride, and germanium, and has a monocrystalline, polycrystalline, or amorphous structure; The metal material of the film is selected from the group consisting of tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper; A manufacturing process in which the critical temperature is between 500°C and 1800°C, the critical temperature depending on the nature of the metallic material of the encapsulating film and the semiconductor material(s) of the functional layer and carrier substrate. [Brief explanation of the drawings]

[0017] Further features and advantages of the present invention will become apparent from the following detailed description of the invention, which proceeds with reference to the accompanying drawings. [Figure 1] FIG. 1 shows a structure according to the present invention. [Figure 2a] 1A-1D illustrate steps in a manufacturing process according to the present invention. [Figure 2b] 1A-1D illustrate steps in a manufacturing process according to the present invention. [Figure 2c] 1A-1D illustrate steps in a manufacturing process according to the present invention. [Figure 2d] 1A-1D illustrate steps in a manufacturing process according to the present invention. [Figure 2e] 1A-1D illustrate steps in a manufacturing process according to the present invention. [Figure 3a] 10A-10C illustrate variations of steps in a manufacturing process according to the present invention. [Figure 3b] 10A-10C illustrate variations of steps in a manufacturing process according to the present invention. [Figure 3c] 10A-10C illustrate variations of steps in a manufacturing process according to the present invention. [Figure 3d]10A-10C illustrate variations of steps in a manufacturing process according to the present invention. [Figure 4] 4 shows the current curve as a function of applied voltage measured using two electrodes formed on a structure according to the invention, with the current path passing through the interface region of the structure. For comparison, FIG. 4 also shows the current / voltage curves of a bulk substrate and a junction structure not according to the invention. [Figure 5] FIG. 1 shows a graph of the resistivity of the nodules in the interface region of a structure according to the invention and the extent of the coverage of said nodules to obtain different levels of resistivity of the interface region. [Figure 6] FIG. 10 is a graph of current as a function of voltage showing the variation of the resistivity of the interface depending on the thickness of a film made of a metallic material deposited before the formation of the intermediate structure. DETAILED DESCRIPTION OF THE INVENTION

[0018] In the description, the same reference numbers in the figures may be used for the same types of elements. The figures are schematic and, for clarity, are not drawn to scale. In particular, the thickness of layers along the z-axis is not drawn to scale relative to the lateral dimensions along the x- and y-axes, and the relative thicknesses of layers with respect to one another are not taken into account in the figures.

[0019] The present invention relates to a semiconductor structure 100 comprising a functional layer 10 made of a monocrystalline semiconductor material, a carrier substrate 30 made of a semiconductor material, and an interface region 20 (FIG. 1) between the functional layer 10 and the carrier substrate 30. Like the functional layer 10, the interface region 20 extends parallel to a major plane (x, y).

[0020] Advantageously, as is typical in the field of microelectronics, the semiconductor structure 100 takes the form of a circular wafer, the diameter of which is between 100 mm and 450 mm, and the total thickness of which is typically between 300 microns and 1000 microns, it being understood that in this case the carrier substrate 30 and the functional layer 10 also take such a circular shape. The (circular) front face 100a and rear face 100b of the wafer extend parallel to the main plane (x, y).

[0021] Many types of semiconductor structures 100 that allow vertical electrical conduction between the functional layer 10 and the carrier substrate 30 may be of interest for microelectronic applications. Accordingly, the nature of the materials that make up the functional layer 10 and the carrier substrate 30 may vary greatly. For example, the semiconductor material of the functional layer 10 can be selected from silicon carbide, silicon, gallium nitride, and germanium. Generally, the creation of components on the functional layer 10 requires that said layer 10 exhibits high crystallinity. It is therefore selected to be monocrystalline with a quality grade, type, and doping level that matches the target application. Further by way of example, the semiconductor material of the carrier substrate 30 may be selected from silicon carbide, silicon, gallium nitride, and germanium. It preferably exhibits a lower quality level, essentially for economic reasons, and a monocrystalline, polycrystalline, or amorphous structure. Its type and its doping level are selected to suit the target application.

[0022] The interface region 20 of the semiconductor structure 100 according to the present invention is notable for including electrically conductive nodes 21. Each of these nodes 21 comprises a metallic material capable of forming ohmic contact with the functional layer 10 and the carrier substrate 30. Without limitation, the metallic material of the nodes 21 may be selected from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper. As known to those skilled in the art, not all of these materials are capable of forming ohmic contact with all of the semiconductor materials mentioned as being capable of forming the functional layer 10 and / or the carrier substrate 30. Therefore, the metallic material of the nodes 21 is selected depending on the nature of the functional layer 10 and the carrier substrate 30. Some specific examples are described further below.

[0023] The nodes 21 of the interface region 20 further exhibit a low or very low thickness along an axis z perpendicular to the major plane (x, y), typically 30 nm or less, 20 nm or less, 10 nm or less, or 5 nm or less. The nodes 21 distributed in the interface region 20 are separated or joined, and the separated nodes are mainly separated from each other by direct contact regions 22 of the functional layer 10 with the carrier substrate 30, i.e. by direct bond regions 22 between the semiconductor material of the functional layer 10 and the semiconductor material of the carrier substrate 30. These regions 22 are hereinafter referred to as direct contact regions 22. Potentially, in some cases of semiconductor structure 100, there may be nanometer-thick cavities in these contact regions 22, but the cavities occupy less than 20%, or less than 10%, or even less than 5% of the area of ​​the major plane (x, y) occupied by the contact regions 22. Also, their thickness is less than the thickness of the nodules 21.

[0024] The semiconductor structure 100 according to the invention ensures good electrical conductivity between the functional layer 10 and the carrier substrate 30 via its interface region 20. In particular, the nodules 21 distributed in the interface region 20 in a central plane P substantially parallel to the main plane (x, y) establish ohmic contact with the functional layer 10 and the carrier substrate 30 and are at least partly formed by a metallic material that is a very good electrical conductor. They therefore allow effective vertical electrical conduction. Between the separated nodes 21, the direct contact areas 22 could potentially allow electrical conduction, but this is less effective than with the nodes 21. However, these direct contact areas 22 ensure the mechanical continuity of the interface area 20 and provide excellent mechanical strength between the functional layer 10 and the carrier substrate 30. It should be noted that the quality of the functional layer 10 is therefore not affected by potential voids or interface defects, and that the aforementioned cavities, if present, have dimensions and densities that do not adversely affect the quality and mechanical strength of the functional layer 10.

[0025] At the mid-plane P of the interface region 20, the extent of coverage of the nodules 10 is typically between 1% and 70%, preferably between 10% and 60%.

[0026] Preferably, the node 21 has a resistance of 0.1 mΩcm. 2 Less than or equal to 0.01mΩcm 2 The resistivity is: Ωcm 2 Unit resistivity is used here for the nodes 21 (or more generally the interface regions 20) due to their very low thickness. The resistivity of the node 21 includes the resistivity of the metallic material forming the node 21, the specific contact resistance between the node 21 and the functional layer 10, and the specific contact resistance between the node 21 and the carrier substrate 30. It is these contact resistances that dominate the overall vertical resistance. Therefore, the surface resistivity is expressed in Ωcm 2 It is reasonable to express the specific contact resistance as 4E15 / cm. The specific contact resistance may vary depending on the nature and / or doping of the materials of the functional layer 10 and the carrier substrate 30, respectively. 3 The specific contact resistance of a node made of nickel (Ni) with silicon carbide (SiC) characterized by an N-type doping (nitrogen or phosphorus dopant) level of 3 mΩ cm 2 On the other hand, 1E19 / cm 3 The N-type doping level is approximately 0.003 mΩ cm 2 is.

[0027] The graph of Figure 5 shows the change in resistivity of interface region 20 as a function of the resistivity of nodes 21 and their extent at mid-plane P. As noted above, the target resistivity of interface region 20 for power applications is 1 mΩ cm. 2 or less, or 0.1mΩcm 2 The following is the result.

[0028] According to one advantageous embodiment, the functional layer 10 and the carrier substrate 30 are formed from the same semiconductor material and feature the same doping type, allowing effective vertical electrical conduction between components produced in and / or on the functional layer 10 and components and / or electrodes produced on the back surface 30b of the carrier substrate 30 of the structure 100.

[0029] According to a first example, the semiconductor structure 100 according to the invention comprises a functional layer 10 made of high quality monocrystalline silicon carbide, where high quality is typically less than 1 cm 2 Less than 1 micropipe (MP) per 1cm 2 Fewer than 500 threading screw dislocations (TSDs) per cm 2 Less than 5000 threading edge dislocations (TEDs) per cm 2 The SiC of the functional layer 10 has less than 8×10 18 / cm 3 The semiconductor structure 100 also includes a carrier substrate 30 made of low-quality monocrystalline or polycrystalline silicon carbide, characterized by N-type doping with a resistivity of the order of 20 mΩcm. The nodules 21 are made of tungsten (W), and they may have a thickness of the order of 5 nm and a resistivity ranging between 15% and 25%. The resistivity of the interface region 20 of such a structure 100 is 0.05 mohm.cm. 2 That is, 0.1 mΩ cm 2 The following is the result.

[0030] According to a second example, the semiconductor structure 100 according to the invention has a capacitance of 1×10 19 / cm 3 and a functional layer 10 made of high-quality single-crystal silicon carbide featuring P-type doping at 5 × 10 19 / cm 3 and a carrier substrate 30 made of low-quality monocrystalline or polycrystalline silicon carbide characterized by P-type doping at 1000 . The nodules 21 of the interface region 20 are made of titanium (Ti), which has a thickness of the order of 6 nm and a resistivity range of the order of 30% to 40%. The resistivity of the interface region 20 of such a structure 100 is 1 mΩ cm. 2 Lower than.

[0031] According to a third example, the semiconductor structure 100 according to the invention has a capacitance of 5×10 19 / cm 3 Functional layers made of high-quality single-crystal silicon carbide characterized by N-type doping at 10, and 5 x 1019 / cm 3 The structure 100 includes a carrier substrate 30 made of low-quality monocrystalline or polycrystalline silicon carbide characterized by N-type doping. The nodules 21 are made of aluminum (Al), and they have a thickness of the order of 3 nm and a resistivity range of the order of 5% to 15%. The resistivity of the interface region 20 of such a structure 100 is 1 mΩ cm. 2 Lower than.

[0032] Of course, this list of examples is not exhaustive, and many other semiconductor structures 100 according to the present invention can be produced based on various combinations of materials for the functional layer 10, the nodes 21, and the carrier substrate 30, while observing the conditions described above for the interface region 20.

[0033] In particular, power components may be produced on and / or in the functional layer 10 of the semiconductor structure 100 according to the invention. These components may include at least one electrical contact on and / or in the carrier substrate 30, in particular at the level of the back surface 100b of the semiconductor structure 100. By way of non-limiting example, these power components may include transistors, diodes, thyristors, or passive components (capacitors, inductors, etc.), etc.

[0034] The present invention also relates to a process for producing a semiconductor structure 100 as described above.

[0035] The manufacturing process first comprises step a) of providing a functional layer 10 made of monocrystalline semiconductor material (FIG. 2a), which in this step a) has a free face 10a, also called front face 10a, intended to be bonded in a later step of the process, and a rear face 10b opposite said front face 10a.

[0036] According to one advantageous embodiment, the functional layer 10 results from the transfer of a surface layer from a donor substrate 1, in particular a layer transfer based on the Smart Cut process. Thus, step a) may comprise the act of implanting optical species, for example hydrogen, helium or a combination of these two species, into the donor substrate 1 in order to form a front surface 10a of the donor substrate 1 and a buried weakened surface 11 separating the front surface 10a of the donor substrate 1 (Figure 3a). According to one variant of this embodiment, step a) involves the formation of a donor substrate 1 by epitaxially growing a donor layer 1' on the initial substrate prior to the injection of photospecies (FIG. 3b). This variant makes it possible to form a donor layer 1' that exhibits the structural and electrical properties required for the target application. In particular, excellent crystalline quality can be obtained by epitaxy, and the in situ doping of the donor layer 1' can be precisely controlled. Photospecies are then injected into the donor layer 1' to form the buried weakened surface 11.

[0037] Alternatively, the functional layer 10 provided in step a) may of course be formed using other known techniques for transferring thin layers.

[0038] The manufacturing process according to the invention then comprises step b) of providing a carrier substrate 30 made of semiconductor material (FIG. 2b), which has a free face 30a, also called the front face 30a, intended to be bonded in a later step of the process, and also has a rear face 30b.

[0039] As described above in the description of the semiconductor structure 100, the functional layer 10 may be formed from one or more materials selected from among silicon carbide, silicon, gallium nitride, and germanium, and the carrier substrate 30 may be formed from one or more materials selected from among silicon carbide, silicon, gallium nitride, and germanium, preferably of lower quality, whether single crystalline, polycrystalline, or amorphous. According to one particular embodiment, the functional layer 10 and the carrier substrate 30 are made from the same semiconductor material and are characterized by the same doping type (N or P).

[0040] The manufacturing process then comprises a step c) of depositing a film 2 made of a metallic material on the free surface 10a to be bonded of the functional layer 10, or on the free surface 30a to be bonded of the carrier substrate 30, or on both the free surfaces 10a, 30a to be bonded, as shown in Fig. 2c. The metallic material is selected because it is suitable for forming an ohmic contact with the functional layer 10 and the carrier substrate 30. Depending on the nature of the functional layer 10 and the carrier substrate 30, it may be selected from the following non-limiting list of materials: tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, copper.

[0041] The thickness of the film 2 is 20 nm or less, preferably 10 nm or less, or 5 nm or less. For example, the deposited film 2 can have a thickness of 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 8 nm, 10 nm or 15 nm. It should be noted that when the film 2 is deposited on both free surfaces 10a, 30a, the total deposited thickness, i.e. the total thickness of the film 2 deposited on each of the free surfaces 10a, 30a, is preferably 20 nm or less, or 10 nm or less. The total thickness of the deposited film 2 must be kept low to allow the film to be split into nodules 21 in later steps of the process.

[0042] The film 2 is deposited in a non-oxidizing controlled atmosphere. It is important that the metal film 2 is not subject to any oxidation or damaged by contaminants from the surrounding atmosphere. Typically, the deposition in step c) is carried out in a controlled atmosphere for 10 -6 This is done in a high vacuum of less than 100 Pa. Depending on the nature of the film 2 to be deposited, step c) is carried out at ambient or low temperature, advantageously by sputtering deposition techniques using neutral elements or elements that are not destructive to remain in the deposited metal (Ar, Si, N, etc.) to bombard a metal target.

[0043] According to one particular embodiment, the manufacturing process according to the invention comprises, before the deposition step c), a step c') of deoxidation of the free surface to be bonded of the functional layer 10 and / or the free surface to be bonded 30a of the carrier substrate 30. Such a step allows the removal of any native oxides present on the surface of the functional layer 10 and / or the carrier substrate 30, which facilitates the formation of an ohmic contact with a metallic material in a later step of the process. Deoxidation can be carried out by wet (e.g. removal by attack with HF) or dry (dry etching or annealing in a reducing atmosphere) chemical treatment.

[0044] Next, the manufacturing process includes step d) of forming an intermediate structure 150, which includes directly bonding the free surfaces 10a, 30a to be bonded of the functional layer 10 and the carrier substrate 30, respectively, at the bonding interface 15 (Figure 2d). This direct bonding is preferably carried out by molecular adhesion bonding, which consists in bringing the surfaces 10a, 30a to be bonded into contact in a non-oxidizing controlled atmosphere. It can be a direct bond between the functional layer 10 and the membrane 2 when this membrane is deposited only on the carrier substrate 30, or a direct bond between the carrier substrate 30 and the membrane 2 when this membrane is deposited only on the functional layer 10, or a direct bond between two membranes 2 when they are deposited on the functional layer 10 and on the carrier substrate 30. Direct bonding is performed under controlled atmosphere, especially at 10 -6 It is preferable to carry out the process in a high vacuum of 100 Pa or less.

[0045] Advantageously, the deposition of step c) and the direct bonding of step d) are carried out one after the other without breaking the vacuum, either in situ or in a multi-chamber apparatus, such as the Canon BV7000 atomic diffusion bonding apparatus, which allows for sequential metal deposition and direct bonding while maintaining a controlled atmosphere.

[0046] With reference to the preferred embodiment shown in FIGS. 3a-3d, step d) involves directly bonding the free surface 10a to be bonded of the functional layer 10 to the free surface 30a to be bonded of the carrier substrate 30, resulting in a bonded assembly 200 comprising the donor substrate 1, the carrier substrate 30, and the bonding interface 15 (FIG. 3c). Step d) further involves separation at the level of the embedded weakened surface 11 to form, on the one hand, an intermediate structure 150 comprising the functional layer 10, one or more membranes 2, and the carrier substrate 30, and, on the other hand, the remainder of the donor substrate 1″ (FIG. 3d). Such separation can be carried out during a thermal treatment, which allows the cavities and microcracks created by the implanted species to grow in the embedded weakened layer 11. Separation can also be carried out by applying mechanical stress or otherwise through a combination of thermal and mechanical stress, as is well known with reference to the Smart Cut process. A sequence of cleaning, smoothing, polishing or etching of the separated surface 10b of the functional layer 10 and / or the remaining separated surface 1''a of the donor substrate 1'' may be carried out to restore good surface quality, particularly in terms of roughness, defect density, and other contamination.

[0047] Regardless of the process implementation, at the completion of step d), the intermediate structure 150 has a front surface 10b on the side of the functional layer 10, a back surface 30b on the side of the carrier substrate 30, and a membrane 2' encapsulated between the functional layer 10 and the carrier substrate 30. It should be noted that the encapsulated membrane 2' corresponds to the membrane 2 if this membrane is deposited on only one of the free surfaces 10a, 30a to be joined, or to both membranes 2 deposited on the functional layer 10 and on the carrier substrate 30, respectively.

[0048] The manufacturing process according to the invention then includes step e) of annealing the intermediate structure 150 at a temperature above the critical temperature to split the encapsulated film 2' into conductive nodes 21 and form interface regions 20. Step e) results in the formation of the semiconductor structure 100. Here, the critical temperature refers to the temperature at which ohmic contact is achieved between the metal of the encapsulated film 2′, the semiconductor of the functional layer 10, and the semiconductor of the carrier substrate 30, and is, for example, 400°C to 650°C for an Al / Si pair, or 950°C to 1100°C for a Ni / SiC pair. Furthermore, the critical temperature must be high enough to allow the joining of the direct contact areas 22 between the nodes 21. Typically, this is between 500° C. and 1800° C., depending on the nature of the metallic material and the nature of the semiconductor material or materials of the semiconductor structure 100 .

[0049] Above this critical temperature, the system comprising the encapsulated film 2' and the semiconductor surface of the functional layer 10 and carrier substrate 30 in contact with said film 2' optimizes its surface energy by clustering the encapsulated film 2' into nodules 21 and establishing ohmic contact with the semiconductor surface, and by creating direct contact areas 22 between the semiconductor surface of the functional layer 10 and the semiconductor surface of the carrier substrate 30, respectively.

[0050] Furthermore, because the encapsulated film 2' is very thin, metallic materials known to be stable only at low or medium temperatures can be used in the semiconductor structure 100 according to the invention, which can be subjected to treatments at high temperatures (900°C to 1100°C) or very high temperatures (1200°C to 1800°C), in particular because they are clustered into nodules 21 of small size and very low thickness, which do not cause degradation of the structure 100, and in particular of the functional layer 10. Reference can be made, for example, to the case of nodules 21 made of nickel or titanium in a structure 100 comprising a functional layer 10 and a carrier substrate 30 made of SiC, and intended to undergo epitaxy at temperatures between 1600°C and 1800°C.

[0051] The above-described manufacturing process thus makes it possible to obtain a semiconductor structure 100 that provides vertical electrical conduction between the functional layer 10 and the carrier substrate 30 via the interface region 20. The very thin nodes 21 are made mainly of metal and therefore exhibit very low resistivity. Furthermore, the presence of direct contact regions 22 between the separating nodes 21 avoids any problems with the mechanical strength or more generally the reliability of the functional layer 10 and / or the components produced on or within this layer. Finally, since the invention is based on bonding via a metal film 2, the increase in interface resistivity associated with the direct bonding of semiconductor materials with different crystalline properties is not an issue for vertical electrical conduction in the structure 100, since the nodes 21 ensure said conduction.

[0052] Example implementation: The donor substrate 1 is made of high quality single crystal 4HSiC and has a diameter of 150 mm. The donor substrate 1 is N-doped with a resistivity of about 20 mohm.cm. It has a resistivity of 5E16 / cm 2 and an energy of 95 keV through the front surface 1a, which is the "C" plane. Around the implantation depth, a buried weakened surface 11 is defined, which together with the front surface 10a of the donor substrate 1 delimits the functional layer 10. The carrier substrate 30 is made of lower quality single crystal 4HSiC with the same diameter as the donor substrate 1. It is N-doped and has a resistivity of about 20 mΩcm. The two substrates 1, 30 are subjected to a cleaning treatment to remove particles and other surface contaminants, the treatment preferably being chosen so that the surfaces of the substrates 1, 30 are not subject to oxidation (no native oxides are present). The substrates 1 and 30 are introduced into a first deposition chamber and integrated into the direct bonding apparatus. A tungsten film 2 having a thickness of 0.5 nm is deposited on each of the front surfaces 10a and 30a (free surfaces to be bonded) of the substrates 1 and 30 in a vacuum. -6 The solution is deposited by sputtering at 1000 kJ / cm 2 Pa and ambient temperature. The substrates 1, 30 are introduced into a second bonding chamber so that they are bonded at their front faces 10a, 30a by direct contact of the deposited film 2 on the donor substrate 1 and the carrier substrate 30, respectively. The atmosphere in the bonding chamber is the same as the atmosphere in the deposition chamber, which prevents any oxidation or passivation of the surface of the film 2. After bonding, the bonded assembly 200 includes the donor substrate 1 connected to the carrier substrate 30 via the bonded interface 15, and an encapsulated membrane 2' formed from two membranes 2 deposited and embedded between the two substrates 1, 30. The encapsulated membrane 2' has a thickness of about 1 nm. The bonded assembly 200 is subjected to a heat treatment at a temperature of about 900° C. for 30 minutes in order to induce separation at the embedded weakened plane 11. The result is then an intermediate structure 150 comprising a functional layer 10 having a thickness of 500 nm, arranged on an encapsulating membrane 2′, which is itself arranged on a carrier substrate 30. A cleaning and polishing process is applied to the surface 10b of the functional layer 10 in order to restore a sufficient level of defect density and roughness. Finally, an anneal at 1700° C. for 30 minutes is applied to the intermediate structure 150, which has previously been provided with a protective layer on its front surface 10b (which is also the free surface 10b of the functional layer 10 of the intermediate structure 150). Once this anneal is complete, the structure 100 according to the invention is obtained, with the interface region 20 formed, and the nodes 21 made of tungsten, separated by the direct contact region 20 between the functional layer 10 and the carrier substrate 30, provide the structure 100 with excellent vertical conductivity, almost identical to that of a bulk SiC substrate, exhibiting a resistivity of 20 mΩcm. This is evident in the graph of FIG. 4, which shows the curve of the current as a function of the voltage I(V) for a simple component including two metal contact electrodes. In the case of the structure 100 according to the invention, the I(V) measurement is performed at the two electrodes, with the current path passing through the interface region 20. The interface region 20 has a resistivity of 0.1 mΩcm. 2 It has the following resistivity: The nodules 21 in this structure 100 have a thickness of about 5 nm and an average diameter of about 20 nm. The extent of coverage of the nodules 21 at the mid-plane of the interface region 20 is about 20%.

[0053] 4 shows, for comparison, the I(V) curves of a structure based on a direct SiC / SiC bond with heavy doping (nitrogen implantation) of the bond surface as a "bond not according to the invention," in which the SiC substrate has the same resistivity as in the previously described structure 100. The improvement in resistivity of the interface region provided by the present invention is evident in FIG.

[0054] Under the same experimental conditions as those described above, it has been observed that the resistivity of the interface region 20 can be further reduced with an encapsulated film 2' thickness of around 2 nm or 3 nm. Figure 6 shows the effect of encapsulated film 2' thicknesses ranging from 0.4 nm to 2 nm on the I(V) curve, with the I(V) curve for the encapsulated film 2' with a thickness of 2 nm being very close to that obtained with the bulk SiC substrate.

[0055] Of course, the present invention is not limited to the described embodiments and examples, and alternative embodiments can be introduced without departing from the scope of the invention as defined by the claims.

Claims

1. a functional layer (10) made of monocrystalline semiconductor material, extending in a major plane (x, y); a carrier substrate (30) made of semiconductor material, and an interface region (20) between the functional layer (10) and the carrier substrate (30), the interface region extending parallel to the main plane (x, y); A semiconductor structure (100) comprising: The interface region (20) comprising a metallic material that is electrically conductive and forms ohmic contact with the functional layer (10) and the carrier substrate (30); a thickness of 10 nm or less along an axis (z) perpendicular to the major plane (x, y); Separate or joined nodes (21), the separated nodes (21) being separated from each other by areas of direct contact (22) between the functional layer (10) and the carrier substrate (30). A semiconductor structure (100) comprising:

2. The semiconductor structure (100) of claim 1, wherein the functional layer (10) and the carrier substrate (30) are made of the same semiconductor material and have the same doping type.

3. The semiconductor structure (100) of claim 1, wherein the semiconductor material of the functional layer (10) is selected from the group consisting of silicon carbide, silicon, gallium nitride, and germanium.

4. The semiconductor structure (100) of claim 1, wherein the semiconductor material of the carrier substrate (30) is selected from silicon carbide, silicon, gallium nitride, and germanium and has a monocrystalline, polycrystalline, or amorphous structure.

5. 2. The semiconductor structure (100) of claim 1, wherein the metallic material of the nodules (21) is selected from the group consisting of tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper.

6. The semiconductor structure (100) of claim 1, wherein in the mid-plane (P) of the interface region (20), the extent of coverage of the nodules (21) is between 1% and 70%.

7. The node (21) has a resistance of 0.1 mΩcm 2 To obtain a resistivity of said interface region (20) of less than 0.1 mΩ cm 2 The semiconductor structure (100) of claim 1 having a resistivity less than 100 .mu.m.

8. The semiconductor structure (100) of claim 1, wherein the nodule (21) has a thickness of 5 nm or less.

9. A power component manufactured on and / or in the functional layer (10) of the semiconductor structure (100) according to any one of claims 1 to 8, comprising: A power component with at least one electrical contact on and / or in said carrier substrate (30) at the level of the backside of said semiconductor structure (100).

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