Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device and a manufacturing method of the same, which are capable of achieving both miniaturization and high breakdown voltage.SOLUTION: In a semiconductor device, a device region 10 includes: a semiconductor substrate 1 including a buried region BR, an element region ER located on the buried region BR, and a trench 20 surrounding the element region ER in a plan view; an insulating part 30 covering a surface 20a of the trench 20; and a conductive part 40 located in the trench 20 and surrounded by the insulating part 30 in the plan view. The trench 20 includes: a first opening region 21 located above the buried region BR in a thickness direction; and a second opening region 22 located below the first opening region 21 and the element region ER in the thickness direction and adjacent to the buried region BR in a planar direction. The insulating part 30 includes: a first portion located in the first opening region 21; and a second portion located in the second opening region 22, in which a thickness T2 of the second portion in the planar direction is larger than a thickness T1 of the first portion in the planar direction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device with a trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-32332

[0004] [overview] An object according to one aspect of the present disclosure is to provide a semiconductor device that can achieve both miniaturization and high breakdown voltage, and a method for manufacturing the semiconductor device.

[0005] A semiconductor device according to one aspect of the present disclosure comprises a semiconductor substrate including a buried region, an element region located on the buried region, and a trench surrounding the element region in a planar view; an insulating portion covering the surface of the trench; and a conductive portion located within the trench and surrounded by the insulating portion in a planar view, wherein the trench includes a first opening region located above the buried region in a thickness direction of the semiconductor substrate and a second opening region located below the first opening region in the thickness direction and adjacent to the buried region in a planar direction perpendicular to the thickness direction, and the insulating portion includes a first portion located within the first opening region and a second portion located within the second opening region, and the thickness of the second portion in the planar direction is greater than the thickness of the first portion in the planar direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of a main part of FIG. [Figure 3]FIG. 3 is a schematic cross-sectional view taken along line III-III shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line IV-IV shown in FIG. [Figure 5A] FIG. 5A is a schematic cross-sectional view for explaining an example of a method for manufacturing a trench structure of a semiconductor device according to the embodiment. [Figure 5B] FIG. 5B is a schematic cross-sectional view for explaining an example of a method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 5C] FIG. 5C is a schematic cross-sectional view for explaining an example of a method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 5D] FIG. 5D is a schematic cross-sectional view for explaining an example of a method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 5E] FIG. 5E is a schematic cross-sectional view for explaining an example of a method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 5F] FIG. 5F is a schematic cross-sectional view for explaining an example of a method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 5G] FIG. 5G is a schematic cross-sectional view for explaining an example of a method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 6A] FIG. 6A is a schematic cross-sectional view for explaining another example of the method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 6B] FIG. 6B is a schematic cross-sectional view for explaining another example of the method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 6C] FIG. 6C is a schematic cross-sectional view for explaining another example of the method for manufacturing the trench structure of the semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a diagram showing the simulation results of the electric field distribution. [Figure 8] FIG. 8 is a graph showing the results of a simulation of the relationship between the thickness of the insulating portion included in the DTI and the substrate breakdown voltage. [Figure 9]FIG. 9 is an enlarged view of a main part of a device region according to a reference example. [Figure 10] FIG. 10 is a schematic cross-sectional view taken along line XX shown in FIG.

[0007] [Detailed explanation] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, identical elements or elements having the same functions will be designated by the same reference numerals, and duplicate explanations will be omitted. In this specification, the term "same" and similar words are not limited to "completely identical." Furthermore, since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of the components shown may differ from the actual dimensions.

[0008] Fig. 1 is a schematic plan view showing a semiconductor device according to this embodiment, Fig. 2 is an enlarged view of a main part of Fig. 1, and Fig. 3 is a schematic cross-sectional view taken along line III-III shown in Fig. 2.

[0009] 1, the semiconductor device 100 includes, for example, a chip-shaped integrated circuit (IC) device. The semiconductor device 100 may be referred to as an SSI (Small Scale IC), an MSI (Middle Scale IC), an LSI (Large Scale IC), a VLSI (Very Large Scale IC), an ULSI (Ultra Large Scale IC), or the like, based on the number of circuit elements integrated therein. In this embodiment, the semiconductor device 100 includes a rectangular parallelepiped chip 101 (semiconductor chip).

[0010] The chip 101 has a first main surface 3, which is the main surface, and a second main surface 4, which is the back surface. The chip 101 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D, which connect the first main surface 3 and the second main surface 4. Hereinafter, the thickness direction of the chip 101 corresponds to the Z-axis direction, the direction perpendicular to the thickness direction corresponds to the X-axis direction, and the direction perpendicular to the Z-axis and X-axis directions corresponds to the Y-axis direction. Also, below, a view from the Z-axis direction is referred to as a planar view, and the directions extending in the X-axis and Y-axis directions are referred to as planar directions. The direction toward the first main surface 3 in the Z-axis direction is referred to as the upward direction, and the direction toward the second main surface 4 in the Z-axis direction is referred to as the downward direction.

[0011] The first main surface 3 and the second main surface 4 each extend perpendicular to the Z-axis direction. In plan view, the planar shape of the first main surface 3 and the planar shape of the second main surface 4 are each quadrilateral, but are not limited to this. The first side surface 5A and the second side surface 5B each extend along the X-axis direction in plan view. The third side surface 5C and the fourth side surface 5D each extend along the Y-axis direction in plan view.

[0012] The semiconductor device 100 includes multiple device regions 10. A gap is provided between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the chip 101. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape. Various devices are formed in each device region 10. As shown in FIG. 2 , at least one device region 10 includes an element region ER surrounded by a trench structure TR in a plan view. Each element region ER may include at least one of a semiconductor switching device, a semiconductor rectifier device, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), and an IGBT (Insulated Gate Bipolar Junction Transistor).

[0013] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be used as the MISFET. The element region ER can also be a power transistor. A DMOS (Double-Diffused MOSFET) can be used as the power MOSFET. The DMOS can be a vertical type (VDMOS) or a lateral type (LDMOS). MISFETs with drain-source voltages of high voltage (HV: for example, 100V to 1000V), medium voltage (MV: for example, 30V to 100V), and low voltage (LV: for example, 1V to 30V) are also known. In addition, optical devices such as light-emitting elements and light-receiving elements can be used as the element region ER formed in the device region 10.

[0014] In this embodiment, the semiconductor material constituting the chip 101 is silicon (Si), but is not limited to this. Compound semiconductors can also be used as the semiconductor material constituting the chip 101. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. III-V compound semiconductors are, for example, Ga-containing semiconductors such as GaAs and GaN. IV-IV compound semiconductors are, for example, Si-containing semiconductors such as SiC and SiGe.

[0015] FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 2. As shown in FIG. 3, a device region 10 constituting a semiconductor device includes a semiconductor substrate 1 and a protective film 14 located on the semiconductor substrate 1. The semiconductor substrate 1 is composed of an underlying substrate 1A and an epitaxial crystal region 1B located on the underlying substrate 1A. The epitaxial crystal region 1B includes a first epitaxial layer 1B1 located on the underlying substrate 1A and a second epitaxial layer 1B2 located on the first epitaxial layer 1B1. The semiconductor substrate 1 also includes a buried region BR, an element region ER located on the buried region BR, and a trench 20 (described in detail below) surrounding the element region ER in a planar view. In one example, the buried region BR is formed in the underlying substrate 1A, the first epitaxial layer 1B1, and the second epitaxial layer 1B2, but is not limited to this.

[0016] The impurity concentration of the base substrate 1A is 1.0×10 15 cm -3 Over 1.0 x 10 19 cm -3 The thickness of the base substrate 1A may be 50 μm or more and 500 μm or less. Depending on the type of device, the material of the base substrate 1A may be an insulator such as Al2O3. In one example, the impurity concentration of the buried region BR is 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The impurity concentration of the first epitaxial layer 1B1 is 1.0×10 15 cm-3 Over 1.0 x 10 19 cm -3 The thickness of the first epitaxial layer 1B1 may be 1 μm or more and 20 μm or less. The impurity concentration of the second epitaxial layer 1B2 may be 1.0×10 15 cm -3 Over 1.0 x 10 19 cm -3 The second epitaxial layer 1B2 may have a thickness of 5 μm or more and 40 μm or less, or may have a thickness of 5 μm or more and 30 μm or less.

[0017] The structure of the element region is not particularly limited. The structure of the element region ER according to this embodiment will be described below with reference to FIG. 3. In this embodiment, the element region ER includes a transistor (HV-MISFET cell) to which a high voltage HV is applied. The element region ER includes a first well region 51 and a plurality of second well regions 52 located in the epitaxial crystal region 1B. A drain region 53 is formed in the first well region 51. A source region 54 and a contact region 56 are formed in each second well region 52. A gate insulating film 58 is located on the semiconductor substrate 1 between the drain region 53 and the source region 54. A gate electrode 59 is disposed on the gate insulating film 58. A planar gate structure 57 is formed by the gate insulating film 58 and the gate electrode 59.

[0018] A plurality of insulating portions 60 are provided on the semiconductor substrate 1. Some of the insulating portions 60 are located between the drain region 53 and the source region 54, in a region adjacent to the drain region 53. Each insulating portion 60 is formed, for example, by shallow trench isolation (STI). For example, each insulating portion 60 includes an insulator 62 buried in a shallow trench 61.

[0019] A drain potential VD is applied to the drain region 53 via a drain contact electrode 63. A source potential VS is applied to the source region 54 via a source contact electrode 64 and a contact region 56. A gate potential VG is applied to the gate electrode 59 via a gate contact electrode 65. When the gate potential VG is applied, a channel 55 is formed in a portion of the surface layer of the semiconductor substrate 1 that overlaps with the gate electrode 59. Charges flowing through the channel 55 drift in the region below the insulating portion 60 adjacent to the drain region 53, and the source region 54 and the drain region 53 can be electrically connected.

[0020] In this example, the semiconductor regions constituting the semiconductor device have a first conductivity type of n-type and a second conductivity type of p-type, but these conductivity types are interchangeable. An exemplary p-type impurity (trivalent element) is boron (B). An exemplary n-type impurity (pentavalent element) is phosphorus (P) or arsenic (As). The material of the semiconductor substrate 1 in this example is Si. In this embodiment, the base substrate 1A exhibits p-type, the first epitaxial layer 1B1 exhibits p-type, the second epitaxial layer 1B2 exhibits n-type, and the buried region BR exhibits n-type. The first well region 51 exhibits n-type, the second well region 52 exhibits p-type, the drain region 53 exhibits n-type, the source region 54 exhibits n-type, and the contact region 56 exhibits p-type.

[0021] The impurity concentrations and thicknesses of the first well region 51, the second well region 52, the drain region 53, the source region 54, and the contact region 56 can be set to common values.

[0022] The insulator 62 embedded in the insulating portion 60 includes an insulator (inorganic insulator) such as silicon oxide (SiO2) or silicon nitride (Si3N4). The material of the protective film 14 is, for example, an insulator (inorganic insulator) such as silicon oxide or silicon nitride. The thickness of the protective film 14 is not particularly limited.

[0023] Next, the trench structure TR will be described in detail. Fig. 4 is a schematic cross-sectional view taken along line IV-IV in Fig. 2. As shown in Figs. 2 to 4, the trench structure TR is an isolation structure for electrically isolating the element region ER from other device regions 10, and is composed of deep trench isolation (DTI) provided in the semiconductor substrate 1. The trench structure TR has a ring shape in plan view and surrounds the element region ER. Therefore, the element region ER is surrounded by the trench structure TR and the buried region BR. In addition, the trench structure TR is spaced apart from the element region ER. The trench structure TR includes a trench 20, and an insulating portion 30 and a conductive portion 40 located within the trench 20.

[0024] The trench 20 is an opening (deep trench) provided in the semiconductor substrate 1, and extends in the Z-axis direction from the first main surface 3 toward the second main surface 4. In this embodiment, the trench 20 penetrates the interface between the base substrate 1A and the epitaxial crystal region 1B. The trench 20 includes a first opening region 21 located above the buried region BR in the Z-axis direction, a second opening region 22 located below the first opening region 21 and the element region ER in the Z-axis direction, and a third opening region 23 located below the second opening region 22 in the Z-axis direction.

[0025] The first opening region 21 is a frame-shaped opening extending from the first main surface 3 to the second opening region 22 in the Z-axis direction and is provided in at least the second epitaxial layer 1B2. The upper end 21a of the first opening region 21 is located on the first main surface 3 of the semiconductor substrate 1. The lower end 21b of the first opening region 21 may be located lower than the element region ER in the Z-axis direction. The lower end 21b may be located higher than the upper end BR1 of the buried region BR. In one example, the lower end 21b is located lower than the center of the second epitaxial layer 1B2 in the Z-axis direction. From the viewpoints of miniaturizing the device region 10 and ensuring the element isolation function of the trench structure TR, the width W1 of the first opening region 21 in the planar direction is, for example, 1.0 μm or more and 4.0 μm or less. The width W1 is constant, but is not limited to this. For example, the width W1 may narrow or widen as it goes downward in the Z-axis direction. A first point 21c of the first opening region 21 that is closest to the center of the element region ER in the horizontal direction coincides with the position of the dashed line BL1 shown in Fig. 2. Furthermore, a second point 21d of the first opening region 21 that is farthest from the center of the element region ER in the horizontal direction coincides with the position of the dashed line BL2 shown in Fig. 2.

[0026] The second opening region 22 is a frame-shaped opening extending from the lower end 21b of the first opening region 21 to the base substrate 1A in the Z-axis direction, and is provided in the base substrate 1A, the first epitaxial layer 1B1, and the second epitaxial layer 1B2. The second opening region 22 is adjacent to the buried region BR in the planar direction. The upper end 22a of the second opening region 22 is located below the element region ER in the Z-axis direction. In other words, the element region ER is located above the second opening region 22 in the Z-axis direction. In one example, the upper end 22a is connected to the lower end 21b of the first opening region 21 and is located above the upper end BR1 of the buried region BR in the Z-axis direction. Therefore, the first opening region 21 and the second opening region 22 are connected to each other. In addition, the lower end 22b of the second opening region 22 is below the lower end BR2 of the buried region BR in the Z-axis direction. In this case, in the trench 20, only the second opening region 22 is adjacent to the buried region BR in the planar direction, but this is not limited to this. As is clear from the above description, the entire second opening region 22 is located below the element region ER in the Z-axis direction. This prevents the second opening region 22 from reaching the element region ER.

[0027] The second opening region 22 is wider than the first opening region 21 in the planar direction. In other words, the width W2 of the second opening region 22 in the planar direction is larger than the width W1. For example, the width W2 is 1.5 to 3.0 times the width W1. From the viewpoint of achieving the element isolation function of the trench structure TR, the width W2 may be 1.5 μm to 12 μm. The width W2 is substantially constant. A third point 22c of the second opening region 22 closest to the center of the element region ER in the horizontal direction coincides with the position of the dashed line BL3 shown in FIG. 2. Furthermore, a fourth point 22d of the second opening region 22 farthest from the center of the element region ER in the horizontal direction coincides with the position of the dashed line BL4 shown in FIG. 2.

[0028] The third opening region 23 is a frame-shaped opening extending downward from the lower end 22b of the second opening region 22 in the Z-axis direction and is provided in the base substrate 1A. The upper end 23a of the third opening region 23 is connected to the lower end 22b of the second opening region 22. Therefore, the second opening region 22 and the third opening region 23 are connected to each other. The lower end 23b of the third opening region 23 may be located above the second main surface 4 in the Z-axis direction. From the perspective of processing time for the trench 20, the lower end 23b of the third opening region 23 may be located near the lower end 22b of the second opening region 22. The width W3 of the third opening region 23 in the planar direction is smaller than the widths W1 and W2, and is, for example, 0.5 μm to 2.0 μm. The width W3 is substantially constant, but is not limited to this. For example, the width W3 may be narrower downward in the Z-axis direction.

[0029] The insulating portion 30 is a frame-shaped insulator that covers the surface 20a of the trench 20 in a plan view, and extends downward from the first main surface 3 in the Z-axis direction. The insulating portion 30 includes a first portion 31 located in the first opening region 21 and a second portion 32 located in the second opening region 22. The insulating portion 30 also has an opening 33 that is frame-shaped in a plan view, extending along the Z-axis direction and filled with a conductive portion 40.

[0030] The first portion 31 is a frame-shaped insulator extending from the first main surface 3 to the second portion 32 in the Z-axis direction, and covers the sidewall of the first opening region 21. The upper end 31a of the first portion 31 coincides with, for example, the upper end 30a of the insulating part 30 and / or the upper end 21a of the first opening region 21. The lower end 31b of the first portion 31 coincides with, for example, the lower end 21b of the first opening region 21. The thickness T1 of the first portion 31 in the planar direction is, for example, not less than 0.2 μm and not more than 2.0 μm. The thickness T1 is constant, but is not limited to this. The thickness T1 can vary appropriately depending on the shape of the first opening region 21.

[0031] The second portion 32 is a frame-shaped insulator extending downward from the lower end 31b of the first portion 31 in the Z-axis direction and covers the sidewall of the second opening region 22. The upper end 32a of the second portion 32 coincides with, for example, the upper end 22a of the second opening region 22. The lower end 32b of the second portion 32 coincides with, for example, the lower end 30b of the insulating portion 30 and / or the lower end 22b of the second opening region 22. Therefore, the upper end 32a is located below the element region ER in the Z-axis direction. The upper end 32a is located above the upper end BR1 of the buried region BR in the Z-axis direction, but this is not limited thereto. The lower end 32b is located below the lower end BR2 of the buried region BR in the Z-axis direction. In this embodiment, the upper end 32a is located above the upper end BR1 of the buried region BR, and the lower end 32b is located below the lower end BR2 of the buried region BR in the Z-axis direction. This makes it possible to preferably achieve a high breakdown voltage for the semiconductor device 100. The thickness T2 of the second portion 32 in the planar direction is greater than the thickness T1, for example, 1.2 to 2.5 times the thickness T1. The thickness T2 is, for example, 0.5 μm to 5.0 μm. Therefore, the insulating portion 30 is thicker at the lower side than at the upper side. The thickness T2 is substantially constant. In this embodiment, a portion of the second portion 32 overlaps the element region ER in the Z-axis direction. In one example, the second portion 32 includes a first region 32c that overlaps the first portion 31 in the Z-axis direction and a second region 32d that does not overlap the first portion 31 in the Z-axis direction. As shown in FIG. 3 , a portion of the second region 32d overlaps the element region ER in the Z-axis direction. This prevents the element region ER from being narrowed in the planar direction due to the formation of the trench structure TR, while achieving a high breakdown voltage for the semiconductor device 100.

[0032] The conductive portion 40 is a frame-shaped conductor surrounded by the insulating portion 30 in a plan view and extends from the first main surface 3 to the second main surface 4 in the Z-axis direction. The conductive portion 40 fills the opening 33. The upper end 40a of the conductive portion 40 is exposed from the insulating portion 30 at the first main surface 3 and can be connected to wiring or the like (not shown). The lower end 40b of the conductive portion 40 is connected to a portion of the semiconductor substrate 1 located below the buried region BR. In this embodiment, the lower end 40b is located below the second portion 32 in the Z-axis direction and is in contact with the semiconductor substrate 1. More specifically, the lower end 40b is located within the third opening region 23 and in contact with the base substrate 1A. This aligns the potential of the conductive portion 40 with the potential of the base substrate 1A. The conductive portion 40 includes, for example, but is not limited to, polysilicon doped with impurities. The conductive portion 40 may include a conductive material such as tungsten or copper instead of polysilicon. The impurities may be p-type impurities or n-type impurities.

[0033] Next, an example of a method for manufacturing the trench structure TR of the semiconductor device 100 according to this embodiment will be described with reference to FIGS. 5A to 5G. Each of FIGS. 5A to 5G is a schematic cross-sectional view for explaining an example of a method for manufacturing the trench structure TR of the semiconductor device 100 according to this embodiment. As shown in FIG. 5A and other figures, this manufacturing method uses a semiconductor substrate 1 that is configured by an underlying substrate 1A and an epitaxial crystal region 1B and includes a buried region BR. An element region ER may already be formed in this semiconductor substrate 1. A mask M in which an opening OP is formed is located on a first main surface 3 of the semiconductor substrate 1. The mask M has a multi-layer structure, but is not limited to this. As shown in FIG. 5A, the mask M includes a first insulating film M1, a second insulating film M2, and a third insulating film M3 that are stacked in this order. The first insulating film M1 is, for example, a silicon oxide film (SiO α The second insulating film M2 is, for example, a silicon nitride film (SiN β The third insulating film M3 is, for example, a silicon oxide film. α and β are each a real number equal to or greater than 0.

[0034] First, as shown in FIG. 5A, a frame-shaped first opening region 21 is formed by etching the semiconductor substrate 1 (first step). In the first step, the first opening region 21 surrounding the element region ER or the region where the element region ER will later be formed is formed in the semiconductor substrate 1. In the first step, a portion of the second epitaxial layer 1B2 is etched. For example, a protective film 71 can be formed on the sidewall of the first opening region 21 by using a deep etching technique such as the Bosch process using F radicals. In one example, scallops generated by etching the second epitaxial layer 1B2 adhere to the sidewall of the first opening region 21, forming the protective film 71 composed of the scallops. Using this protective film 71, the bottom of the first opening region 21 can be selectively removed. This allows the first opening region 21 to be formed with a high aspect ratio. In the first step, the lower end 21b of the first opening region 21 is allowed to reach the vicinity of the upper end BR1 of the buried region BR by adjusting the etching period, etc. When the protective film 71 is formed with the scallops, the protective film 71 has a stepped shape.

[0035] Next, as shown in FIG. 5B , a second opening region 22 is formed below the first opening region 21 (second process). In the second process, the semiconductor substrate 1 is isotropically etched through the first opening region 21 to form the second opening region 22 that is connected to the first opening region 21. The isotropic etching is performed using the same etchant as in the first process, with adjustment of the etching conditions, for example. When plasma etching or the like is used, the etching conditions include, for example, the bias application period, the etching period, the etchant supply amount, and the etchant supply timing. By performing the isotropic etching, the second opening region 22 having a width W2 larger than the width W1 of the first opening region 21 is formed below the first opening region 21. In the second process, the upper end 22a of the second opening region 22 is located above the upper end BR1 of the buried region BR, and the lower end 22b of the second opening region 22 is located above the lower end BR2 of the buried region BR.

[0036] Next, as shown in FIGS. 5C to 5F, an insulating portion 30 is formed to cover the surfaces of the first opening region 21 and the second opening region 22 (step 3). In step 3, as shown in FIG. 5C, the protective film 71 is first removed, and then an oxide film 72 is formed on each of the surfaces of the first opening region 21 and the second opening region 22 (step 3A). In step 3A, the oxide film 72 is formed, for example, by thermal oxidation of silicon. Subsequently, as shown in FIG. 5D, the oxide film 72 is thickened (step 3B). In step 3B, a silicon oxide film is deposited on the oxide film 72 by, for example, plasma CVD using TEOS (tetraethoxysilane). This thickens the oxide film 72. If the oxide film 72 were thickened only in step 3B, the first opening region 21 would be filled before the second opening region 22 was filled with the oxide film 72. For this reason, for example, Step 3B may be stopped before the first opening region 21 is filled, and anisotropic etching may be performed on a portion of the oxide film 72 (Step 3C). As a result, as shown in FIG. 5E, the portion of the oxide film 72 in the second opening region 22 that overlaps with a region 21e in the first opening region 21 that is not filled with the oxide film 72 is selectively removed. In Step 3C, a mask different from mask M may be used. In this case, the size of the region 21e can be adjusted appropriately. In Step 3C, the base substrate 1A that overlaps the removed region of the oxide film 72 in the second opening region 22 may be etched. In this case, a third opening region 23 may be formed.

[0037] The steps 3B and 3C are alternately repeated. This further thickens the oxide film 72. As a result, as shown in FIG. 5F, the insulating portion 30 formed from the thickened oxide film 72 is embedded in the first opening region 21 and the second opening region 22. This results in the formation of the insulating portion 30 including a first portion 31 located in the first opening region 21 and having a thickness T1, and a second portion 32 located in the second opening region 22 and having a thickness T2. In addition, the trench 20 including the first opening region 21, the second opening region 22, and the third opening region 23 is formed. In one example, the steps 3B and 3C may be repeated five or more times, or ten or more times. In the third step, the regions of the first opening region 21 and the second opening region 22 where the conductive portion 40 will be formed later are not embedded in the insulating portion 30. Furthermore, the third opening region 23 is exposed from the insulating portion 30.

[0038] Next, as shown in FIG. 5G, a conductor 80 is formed (fourth step). In the fourth step, a conductor is deposited on the surfaces defining the voids in the trench 20 and on the surface of the mask M by CVD, sputtering, or the like. This forms the conductor 80 that fills the trench 20 and is formed on the mask M. In this embodiment, polysilicon doped with impurities, which is the conductor 80, is formed by CVD using monosilane. Next, the conductor 80 on the mask M and at least a portion of the mask M are removed. For example, the conductor 80 on the mask M and at least a portion of the mask M are removed by CMP. Here, the CMP conditions for removing the conductor 80 and the CMP conditions for removing the mask M may be different from each other. This forms the conductor 40 located inside the first opening region 21 and the second opening region 22 and surrounded by the insulating portion 30 in a plan view, as shown in FIG. 4. In this manner, a semiconductor substrate 1 including a trench structure TR is manufactured.

[0039] Next, another example of the method for manufacturing the trench structure of the semiconductor device according to this embodiment will be described with reference to Figures 6A to 6C. Each of Figures 6A to 6C is a schematic cross-sectional view for explaining another example of the method for manufacturing the trench structure of the semiconductor device according to this embodiment. In this another example, the first step and the second step are performed. Therefore, steps different from the above example will be described below.

[0040] In the above-described alternative example, the number of repetitions of the steps 3B and 3C performed in the above-described example is smaller than that in the above-described example. As a result, as shown in FIG. 6A , the second opening region 22 is not sufficiently filled with the insulating portion 30A, and an annular depression DE is formed in the second portion 32A of the insulating portion 30A in a planar view. The depression DE is a portion recessed toward the buried region BR in the planar direction and is formed in the center of the second portion 32A in the Z-axis direction. The space defined by the depression DE is a space that communicates with the regions in the first opening region 21 and the second opening region 22 where the conductive portion 40A will be formed later. The thickness of the second portion 32A where the depression DE is formed is non-uniform. The minimum thickness T3 of the second portion 32A is greater than the thickness T1, e.g., 0.5 μm or more and 4.0 μm or less.

[0041] Next, as shown in FIG. 6B, a conductor 80A is formed (Step 4A) using a method similar to the above-described Step 4 performed in the above example. That is, a conductive material is deposited on the surfaces defining the voids in the trench 20 and on the surface of the mask M. In Step 4A, the conductor 80A is formed before all of the voids in the second opening region 22 are filled. Therefore, in Step 4A, a portion of the recess DE is filled with the conductor 80A, and a void C (seam) surrounded by the conductor 80A is provided in the second opening region 22. In other words, the void C, which is an area not filled with the conductor 80A, is provided in the second opening region 22. Next, as in the above example, the conductor 80A on the mask M and at least a portion of the mask M are removed. As a result, as shown in FIG. 6C, a conductive portion 40A is formed that is located inside the first opening region 21 and the second opening region 22 and is surrounded by the insulating portion 30A in a planar view. A cavity C surrounded by the conductive portion 40A continues to exist within the second opening region 22. In this manner, the trench structure TRA is manufactured. The time required to form such a trench structure TRA is shorter than the time required to form the trench structure TR shown in FIG. 4. Therefore, by utilizing the above-described alternative example, the productivity of the semiconductor device 100 can be improved compared to the above-described example.

[0042] Next, the relationship between the trench structure and the substrate breakdown voltage will be described with reference to FIGS. 7 and 8. FIG. 7 is a diagram showing the results of a simulation of the electric field distribution. In FIG. 7, the closer to white the color, the higher the electric field strength (higher the potential). Regions P+Sub, P-Epi, B, N-Epi, and DTI shown in FIG. 7 correspond to the base substrate 1A, the first epitaxial layer 1B1, the buried region BR, the second epitaxial layer 1B2, and the trench structure TR, respectively, in this embodiment. The thickness T4 of the insulating portion IP included in DTI in FIG. 7 is set to a predetermined value. FIG. 8 is a graph showing the results of a simulation of the relationship between the thickness of the insulating portion included in DTI and the substrate breakdown voltage. In FIG. 8, the horizontal axis represents the thickness T4 of the insulating portion IP, and the vertical axis represents the substrate breakdown voltage. Thus, FIG. 8 shows the change in the substrate breakdown voltage when the thickness T4 of the insulating portion IP is changed.

[0043] As shown in Figure 7, the electric field strength changes suddenly from the insulating part IP to region B included in the DTI. Also, as shown in Figure 8, the substrate breakdown voltage improves as the thickness T4 increases. From the simulation results described above, it can be inferred that the larger the thickness T4, the more gradual the change in electric field strength (potential change) from the insulating part IP to region B becomes, and the substrate breakdown voltage can be improved.

[0044] The simulation results and the above-described speculations reveal a tendency for the thicker the insulating portion included in the trench structure that may contact the buried region to have a higher substrate breakdown voltage. Based on this tendency, the device region structures shown in FIGS. 9 and 10 are proposed. FIG. 9 is an enlarged view of a key portion of the device region according to a reference example. FIG. 10 is a schematic cross-sectional view taken along line XX in FIG. 9. As shown in FIGS. 9 and 10, the thickness of the insulating portion 130 included in the trench structure TR00 formed in the device region 200 according to the reference example is constant and significantly greater than the thickness T4 of the insulating portion IP shown in FIG. 7. This reduces the change in electric field intensity (potential change) from the insulating portion 130 to the buried region BR, potentially improving the substrate breakdown voltage. In addition, the trench structure TR00 can be easily formed. However, if the size of the device region 200 in a planar view is fixed, forming the trench structure TR00 will result in a narrowing of the element region ER00 in the planar direction. Furthermore, the size of the trench structure TR00 in the planar direction increases in accordance with the size of the element region ER00 in the planar direction. Therefore, in the above-described reference example, it can be said that it is difficult to achieve both a high breakdown voltage and a small size of the semiconductor device.

[0045] In contrast, in the semiconductor device 100 manufactured by the manufacturing method according to this embodiment, the trench 20 includes a first opening region 21 located above the buried region BR in the Z-axis direction and a second opening region 22 located below the first opening region 21 and the element region ER in the Z-axis direction and adjacent to the buried region BR in the planar direction. The insulating portion 30 includes a first portion 31 located within the first opening region 21 and a second portion 32 located within the second opening region 22. The thickness T2 of the second portion 32 in the planar direction is greater than the thickness T1 of the first portion 31 in the planar direction. This allows for gradual change in electric field intensity (potential change) from the insulating portion 30 to the buried region BR without affecting the narrowing of the element region ER in the planar direction due to the formation of the trench structure TR. In other words, a high breakdown voltage of the semiconductor device 100 can be achieved while preventing narrowing of the element region ER in the planar direction due to the formation of the trench structure TR. Therefore, according to this embodiment, it is possible to provide a semiconductor device 100 that can achieve both miniaturization and high breakdown voltage, and a method for manufacturing the same.

[0046] Although the embodiments of the present disclosure have been described above, the present disclosure can also be embodied in other forms.

[0047] In the above embodiment, trench 20 includes first opening region 21, second opening region 22, and third opening region 23, but is not limited to this. For example, trench 20 does not have to include third opening region 23. In this case, bottom end 40b of conductive portion 40 may coincide with bottom end 30b of insulating portion 30. Even in this case, electrical connection can be made between conductive portion 40 and base substrate 1A.

[0048] In the above embodiments, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric vehicles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for a solar cell, a wind power generator, or other power generation device. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, etc.

[0049] Although the embodiments according to one aspect of the present disclosure have been described in detail above, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims. As explained above, various embodiments of the present disclosure can be defined as follows:

[0050] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0051] [A1] a semiconductor substrate including a buried region, an element region located on the buried region, and a trench surrounding the element region in a plan view; an insulating portion covering the surface of the trench; a conductive portion located within the trench and surrounded by the insulating portion in a plan view; Equipped with the trench includes a first opening region located above the buried region in a thickness direction of the semiconductor substrate, and a second opening region located below the first opening region and the element region in the thickness direction and adjacent to the buried region in a planar direction perpendicular to the thickness direction; the insulating portion includes a first portion located in the first opening region and a second portion located in the second opening region; a thickness of the second portion in the planar direction is greater than a thickness of the first portion in the planar direction; Semiconductor device.

[0052] [A2] The semiconductor device according to [A1], wherein, in the thickness direction, the upper end of the second portion is located above the upper end of the buried region, and the lower end of the second portion is located below the lower end of the buried region.

[0053] [A3] The semiconductor device according to [A1] or [A2], wherein the second opening region has a cavity surrounded by the conductive portion.

[0054] [A4] The semiconductor device according to any one of [A1] to [A3], wherein the conductive portion is connected to a portion of the semiconductor substrate that is located below the buried region.

[0055] [A5] The semiconductor device according to any one of [A1] to [A4], wherein the conductive portion is located lower than the second portion in the thickness direction and includes a lower end that contacts the semiconductor substrate.

[0056] [A6] The semiconductor device according to any one of [A1] to [A5], wherein a part of the second portion overlaps the element region in the thickness direction.

[0057] [A7] the second portion includes a first region that overlaps the first portion in the thickness direction and a second region that does not overlap the first portion in the thickness direction, The semiconductor device according to any one of [A1] to [A6], wherein a portion of the second region overlaps with the element region in the thickness direction.

[0058] [A8] forming a frame-shaped first opening region by etching a semiconductor substrate; forming a second opening region below the first opening region by isotropic etching of the semiconductor substrate through the first opening region; forming an insulating portion covering surfaces of the first opening region and the second opening region; forming a conductive portion located inside the first opening region and the second opening region and surrounded by the insulating portion in a plan view; Equipped with the semiconductor substrate includes a buried region adjacent to the second opening region in a planar direction perpendicular to a thickness direction of the semiconductor substrate, and an element region located above the second opening region in the thickness direction; the insulating portion includes a first portion located in the first opening region and a second portion located in the second opening region; a thickness of the second portion in a planar direction perpendicular to the thickness direction is greater than a thickness of the first portion in the planar direction; A method for manufacturing a semiconductor device.

[0059] [A9] The method for manufacturing a semiconductor device according to [A8], wherein in the step of forming the first opening region, a protective film is formed on a sidewall of the first opening region when etching the semiconductor substrate.

[0060] [A10] The method for manufacturing a semiconductor device according to [A9], wherein in the step of forming the insulating portion, the insulating portion is formed after removing the protective film.

[0061] [A11] The method for manufacturing a semiconductor device according to [A9] or [A10], wherein the protective film has a stepped shape.

[0062] [A12] In the step of forming the insulating portion, forming an oxide film by thermally oxidizing each of a surface of the first opening region and a surface of the second opening region; The method for manufacturing a semiconductor device according to any one of [A8] to [A11], wherein the oxide film is thickened.

[0063] [A13] In the step of forming the insulating portion, a recess recessed toward the buried region in the planar direction is formed in the second portion, The method for manufacturing a semiconductor device according to any one of [A8] to [A12], wherein in the step of forming the conductive portion, a part of the recess is filled with the conductive portion.

[0064] [A14] The method for manufacturing a semiconductor device according to [A13], wherein a cavity surrounded by the conductive portion is provided in the second opening region.

[0065] [A15] A method for manufacturing a semiconductor device according to any one of [A8] to [A14], wherein, in the thickness direction, the upper end of the second portion is located above the upper end of the buried region, and the lower end of the second portion is located below the lower end of the buried region.

[0066] [A16] The method for manufacturing a semiconductor device according to any one of claims [A8] to [A15], wherein a part of the second portion overlaps with the element region in the thickness direction.

[0067] [A17] the second portion includes a first region that overlaps the first portion in the thickness direction and a second region that does not overlap the first portion in the thickness direction, The method for manufacturing a semiconductor device according to any one of [A8] to [A16], wherein a part of the second region overlaps with the element region in the thickness direction. [Explanation of symbols]

[0068] 1...Semiconductor substrate 1A...Base substrate 1B...Epitaxial crystal region 1B1...first epitaxial layer 1B2: Second epitaxial layer 3...First main surface 4...Second main surface 10,200...Device area 14...Protective film 20...Trench 20a…Surface 21...First opening area 21a…Top end 21b…lower end 21c...1st Place 21d...Second place 22…Second opening area 22a…Top end 22b…lower end 22c...3rd place 22d…4th Place 23...Third opening area 23a…Top end 23b…lower end 30, 30A, 130, IP...insulation section 30a…Top end 30b…lower end 31…Part 1 31a…Top end 31b…lower end 32,32A…Second part 32a…Top end 32b…lower end 32c…first area 32d…Second area 40, 40A...Conductive part 40a…Top end 40b…lower end 53...Drain region 54...Source region 55...Channel 58...Gate insulating film 59...Gate electrode 80,80A...conductor 100...Semiconductor device 101...Chip (semiconductor chip), BR...Buried region BR1…Top end BR2…lower end C...Cavity (seam) DE…depression ER, ER00...element area T1, T2, T4...Thickness T3: Minimum thickness TR, TR00, TRA...trench structure W1, W2, W3...width.

Claims

1. a semiconductor substrate including a buried region, an element region located on the buried region, and a trench surrounding the element region in a plan view; an insulating portion covering the surface of the trench; a conductive portion located within the trench and surrounded by an insulating portion in a plan view; Equipped with the trench includes a first opening region located above the buried region in a thickness direction of the semiconductor substrate, and a second opening region located below the first opening region and the element region in the thickness direction and adjacent to the buried region in a planar direction perpendicular to the thickness direction; the insulating portion includes a first portion located in the first opening region and a second portion located in the second opening region; a thickness of the second portion in the planar direction is greater than a thickness of the first portion in the planar direction; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein, in the thickness direction, an upper end of said second portion is located above an upper end of said buried region, and a lower end of said second portion is located below a lower end of said buried region.

3. The semiconductor device according to claim 1 , wherein the second opening region is provided with a cavity surrounded by the conductive portion.

4. The semiconductor device according to claim 1 , wherein the conductive portion is connected to a portion of the semiconductor substrate that is located below the buried region.

5. The semiconductor device according to claim 1 , wherein the conductive portion is located lower than the second portion in the thickness direction and includes a lower end that contacts the semiconductor substrate.

6. The semiconductor device according to claim 1 , wherein a part of the second portion overlaps the element region in the thickness direction.

7. the second portion includes a first region that overlaps the first portion in the thickness direction and a second region that does not overlap the first portion in the thickness direction, The semiconductor device according to claim 1 , wherein a portion of the second region overlaps with the element region in the thickness direction.

8. forming a frame-shaped first opening region by etching a semiconductor substrate; forming a second opening region below the first opening region by isotropic etching of the semiconductor substrate through the first opening region; forming an insulating portion covering surfaces of the first opening region and the second opening region; forming a conductive portion located inside the first opening region and the second opening region and surrounded by the insulating portion in a plan view; Equipped with the semiconductor substrate includes a buried region adjacent to the second opening region in a planar direction perpendicular to a thickness direction of the semiconductor substrate, and an element region located above the second opening region in the thickness direction; the insulating portion includes a first portion located in the first opening region and a second portion located in the second opening region; a thickness of the second portion in a planar direction perpendicular to the thickness direction is greater than a thickness of the first portion in the planar direction; A method for manufacturing a semiconductor device.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the step of forming the first opening region, a protective film is formed on a sidewall of the first opening region when etching the semiconductor substrate.

10. The method for manufacturing a semiconductor device according to claim 9 , wherein in the step of forming the insulating portion, the insulating portion is formed after removing the protective film.

11. The method for manufacturing a semiconductor device according to claim 9 , wherein the protective film has a stepped shape.

12. In the step of forming the insulating portion, forming an oxide film by thermally oxidizing each of a surface of the first opening region and a surface of the second opening region; 11. The method for manufacturing a semiconductor device according to claim 8, wherein the oxide film is thickened.

13. In the step of forming the insulating portion, a recess recessed toward the buried region in the planar direction is formed in the second portion, 11. The method for manufacturing a semiconductor device according to claim 8, wherein in the step of forming the conductive portion, a part of the recess is filled with the conductive portion.

14. The method for manufacturing a semiconductor device according to claim 13 , wherein the second opening region is provided with a cavity surrounded by the conductive portion.

15. 11. The method for manufacturing a semiconductor device according to claim 8, wherein, in the thickness direction, an upper end of the second portion is located above an upper end of the buried region, and a lower end of the second portion is located below a lower end of the buried region.

16. 11. The method for manufacturing a semiconductor device according to claim 8, wherein a part of the second portion overlaps the element region in the thickness direction.

17. the second portion includes a first region that overlaps the first portion in the thickness direction and a second region that does not overlap the first portion in the thickness direction, 11. The method for manufacturing a semiconductor device according to claim 8, wherein a portion of the second region overlaps with the element region in the thickness direction.

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