Method of manufacturing semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device capable of improving selectivity.SOLUTION: A method of manufacturing a semiconductor device according to an embodiment comprises forming a structure including an exposed first surface containing SiO2 and an exposed second surface containing SiN and provided at a position different from that of the first surface. The method further comprises selectively forming an insulating portion containing SiO2 on the first surface. Selective formation of the insulating portion on the first surface includes performing processing using an Si precursor containing an amino group and an alkoxy group, and an oxidizing agent containing O2 or H2O.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present embodiment relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In a structure having multiple exposed underlying surfaces containing different materials, it is sometimes necessary to selectively grow a material on one of the underlying surfaces, but ensuring selectivity can be difficult, resulting in mis-growth. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-1421 [Patent Document 2] US Patent Application Publication No. 2022 / 0235461 [Patent Document 3] US Patent Application Publication No. 2022 / 0246660 Summary of the Invention [Problem to be solved by the invention]

[0004] A method for manufacturing a semiconductor device that can improve selectivity is provided. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to the present embodiment includes forming a structure having an exposed first surface including SiO2 and an exposed second surface located at a position different from the first surface and including SiN. The method also includes selectively forming an insulating portion including SiO2 on the first surface. Selectively forming the insulating portion on the first surface includes performing a treatment using a Si precursor including an amino group and an alkoxy group and an oxidizing agent including O2 or HO. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 2 is a block diagram showing an example of the configuration of a memory; [Figure 2] FIG. 2 is a circuit diagram showing a circuit configuration of a memory cell array. [Figure 3] 1A and 1B are cross-sectional views illustrating a first structural example of a NAND string according to an embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line AB in FIG. 3. [Figure 5] FIG. 4 is an enlarged view showing a part of FIG. 3. [Figure 6] 1A and 1B are schematic cross-sectional views illustrating a first example of a method for forming a first example of a structure of a NAND string. [Figure 7] 1A and 1B are schematic cross-sectional views illustrating a first example of a method for forming a first example of a structure of a NAND string. [Figure 8] 1A and 1B are schematic cross-sectional views illustrating a first example of a method for forming a first example of a structure of a NAND string. [Figure 9] 1A and 1B are schematic cross-sectional views illustrating a first example of a method for forming a first example of a structure of a NAND string. [Figure 10] 1A and 1B are schematic cross-sectional views illustrating a first example of a method for forming a first example of a structure of a NAND string. [Figure 11] 1A and 1B are schematic cross-sectional views illustrating a first example of a method for forming a first example of a structure of a NAND string. [Figure 12] 1A and 1B are schematic cross-sectional views illustrating a first example of a method for forming a first example of a structure of a NAND string. [Figure 13] 1A and 1B are schematic cross-sectional views illustrating a first example of a method for forming a first example of a structure of a NAND string. [Figure 14] 10 is a graph for explaining an example of the dependency of the laminated film thickness on the number of cycles in the first example of the forming method. [Figure 15] 10A and 10B are cross-sectional views illustrating a second example method for forming the first example structure of the NAND string. [Figure 16]10A and 10B are cross-sectional views illustrating a second example method for forming the first example structure of the NAND string. [Figure 17] 10A and 10B are cross-sectional views illustrating a second structural example of a NAND string according to an embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view taken along line AB in FIG. [Figure 19] FIG. 18 is an enlarged view showing a part of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual, and the proportions of the various parts are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] In this specification, unless otherwise specified, the term "connect" includes not only a physical connection but also an electrical connection.

[0009] An example of the configuration of a semiconductor memory device (semiconductor device) will be described. Fig. 1 is a block diagram showing an example of the configuration of a memory. The memory includes a memory cell array 100, a command register 101, an address register 102, a sequencer 103, a driver 104, a row decoder 105, and a sense amplifier 106.

[0010] The memory cell array 100 includes a plurality of blocks BLK (BLK0 to BLK(L-1) (L is a natural number equal to or greater than 2)). A block BLK is a set of a plurality of memory cells that store data.

[0011] The command register 101 holds a command signal CMD received from the memory controller, which includes, for example, instruction data for causing the sequencer 103 to perform a read operation, a write operation, or an erase operation.

[0012] The address register 102 holds an address signal ADD received from the memory controller. The address signal ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select a block BLK, a word line WL, and a bit line BL, respectively.

[0013] The sequencer 103 controls the operation of the memory. For example, the sequencer 103 controls the driver 104, row decoder 105, sense amplifier 106, etc. based on a command signal CMD held in the command register 101 to perform operations such as read, write, and erase.

[0014] The driver 104 generates voltages used in read, write, and erase operations, etc. The driver 104 includes, for example, a DA converter. The driver 104 applies the generated voltage to a signal line corresponding to a selected word line WL based on, for example, a page address PA held in the address register 102.

[0015] The row decoder 105 selects one block BLK in the corresponding memory cell array 100 based on the block address BA held in the address register 102. Then, the row decoder 105 transfers, for example, a voltage applied to a signal line corresponding to the selected word line WL to the selected word line WL in the selected block BLK.

[0016] In a write operation, the sense amplifier 106 applies a desired voltage to each bit line BL in accordance with write data DAT received from the memory controller. In a read operation, the sense amplifier 106 determines the data stored in the memory cell based on the voltage of the bit line BL, and transfers the determination result to the memory controller as read data DAT.

[0017] The communication between the memory and the memory controller supports, for example, the NAND interface standard, using a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, and an input / output signal I / O.

[0018] The command latch enable signal CLE indicates that the input / output signal I / O received by the memory is a command signal CMD. The address latch enable signal ALE indicates that the received signal I / O is an address signal ADD. The write enable signal WEn is a signal that instructs the memory to input the input / output signal I / O. The read enable signal REn is a signal that instructs the memory to output the input / output signal I / O.

[0019] The ready / busy signal RBn is a signal that notifies the memory controller whether the memory is in a ready state where it can accept commands from the memory controller or in a busy state where it cannot accept commands.

[0020] The input / output signal I / O is, for example, an 8-bit signal, and can include signals such as a command signal CMD, an address signal ADD, and a write data signal DAT.

[0021] The memory and memory controller described above may be combined to form a single semiconductor memory device. Examples of such a semiconductor memory device include a memory card such as an SD card and a solid-state drive (SSD).

[0022] Next, a description will be given of an example of the circuit configuration of the memory cell array 100. Fig. 2 is a circuit diagram showing the circuit configuration of the memory cell array 100. Fig. 2 illustrates the block BLK0 as an example, but the other blocks BLK also have the same configuration.

[0023] The block BLK includes a plurality of string units SU. Each string unit SU includes a plurality of NAND strings NS. Although FIG. 2 illustrates three string units SU (SU0 to SU2), the number of string units SU is not particularly limited.

[0024] Each NAND string NS is connected to one of a plurality of bit lines BL (BL0 to BL(N-1) (N is a natural number equal to or greater than 2)). Each NAND string NS includes, for example, a memory transistor MT, a selection transistor ST1, and a selection transistor ST2. The memory transistor MT constitutes one memory cell MC. Each NAND string NS has a plurality of memory cells connected in series. A memory including such memory cells is also called a chain-type memory.

[0025] The memory transistor MT includes a control gate and a charge storage layer and is capable of retaining data in a non-volatile manner. The memory transistor MT may be a MONOS type that uses an insulating film for the charge storage layer, or an FG type that uses a conductive layer for the charge storage layer. In the following embodiments, the MONOS type will be described as an example.

[0026] The control gate of each memory transistor MT is connected to a corresponding word line WL. One of the source and drain of one of the memory transistors MT is connected to the other of the source and drain of another of the memory transistors MT. While FIG. 2 illustrates multiple memory transistors MT (MT0 to MT(M-1) (M is a natural number of 2 or greater)), the number of memory transistors MT is not particularly limited.

[0027] The selection transistor ST1 is used to select the string unit SU during various operations. The number of selection transistors ST1 is not particularly limited.

[0028] The selection transistor ST2 is used to select the string unit SU during various operations. The number of selection transistors ST2 is not particularly limited.

[0029] In each NAND string NS, the drain of the select transistor ST1 is connected to the corresponding bit line BL, the source of the select transistor ST1 is connected to one end of the memory transistors MT connected in series, and the other end of the memory transistors MT is connected to the drain of the select transistor ST2.

[0030] In the same block BLK, the source of the select transistor ST2 is connected to a source line SL. The gate of the select transistor ST1 of each string unit SU is connected to a corresponding select gate line SGD. The gate of the memory transistor MT is connected to a corresponding word line WL. The gate of the select transistor ST2 is connected to a corresponding select gate line SGS.

[0031] A plurality of NAND strings NS assigned the same column address CA are connected to the same bit line BL across a plurality of blocks BLK. A source line SL is connected across a plurality of blocks BLK.

[0032] Next, an example of the structure of the NAND string NS will be described.

[0033] The NAND string NS of the embodiment has, for example, either a first structural example or a second structural example described below. Each structural example will be described below.

[0034] (First example of the structure of the NAND string NS) 3 is a cross-sectional view illustrating a first structural example of a NAND string NS according to an embodiment, showing an X-axis, a Y-axis perpendicular to the X-axis, and a Z-axis perpendicular to the X-axis and Y-axis, and showing a portion of an X-Z cross section including the X-axis and Z-axis. FIG. 4 is a cross-sectional view taken along line AB in FIG. 3, showing a portion of an X-Y cross section including the X-axis and Y-axis.

[0035] As shown in FIGS. 3 and 4, the NAND string NS includes a stacked body 1, an insulator 2, a semiconductor layer 3, a memory layer 4, and an insulating portion 5.

[0036] The laminate 1 includes a conductive layer 11 and an insulating layer 12. The multiple conductive layers 11 and the multiple insulating layers 12 are alternately stacked along the Z-axis direction. The conductive layers 11 form the word lines WL and the gate electrodes of the memory transistors MT, and extend along the X-axis direction or the Y-axis direction. Examples of the conductive layers 11 include a conductive layer such as a tungsten layer. Examples of the insulating layers 12 include a silicon oxide layer. In the Z-axis direction, the surface 11a of the conductive layer 11 facing the memory layer 4 may be flush with the surface 120a of the insulating layer 12 facing the insulating portion 5. The conductive layer 11 may have a laminated structure of multiple layers. The laminated structure may include, for example, a tungsten layer, a titanium nitride layer, and an aluminum oxide layer.

[0037] The insulator 2 is provided, for example, along the stacking direction (Z-axis direction) of the conductive layer 11 and the insulating layer 12. The insulator 2 functions as a core insulator. The insulator 2 has, for example, a cylindrical shape. Examples of the insulator 2 include a silicon oxide layer. Note that the NAND string NS does not necessarily have to include the insulator 2.

[0038] As shown in FIG. 4, the semiconductor layer 3 surrounds the insulator 2 in the AB cross section. The semiconductor layer 3 penetrates the stack 1 along the Z-axis direction. The semiconductor layer 3 includes, for example, polysilicon. The semiconductor layer 3 forms a channel region of the memory transistor MT. The semiconductor layer 3 is electrically connected to the bit line BL and the source line SL. The outer periphery of the semiconductor layer 3 is covered with the memory layer 4.

[0039] The memory layer 4 is provided on the opposite side of the semiconductor layer 3 to the insulator 2. The memory layer 4 is provided between the conductive layer 11 and the semiconductor layer 3 in the X-axis direction or the Y-axis direction and between the insulating layer 12 and the semiconductor layer 3. As shown in FIG. 4 , the memory layer 4 surrounds the semiconductor layer 3 in the AB cross section.

[0040] The memory layer 4 has a block insulating film 41, a charge storage film 42, and a tunnel insulating film 43. The block insulating film 41 is provided between the insulating unit 5 and the semiconductor layer 3 in the X-axis direction or the Y-axis direction, and contains, for example, oxygen and silicon. The charge storage film 42 is provided between the tunnel insulating film 43 and the block insulating film 41 in the X-axis direction or the Y-axis direction, and contains, for example, nitrogen and silicon. The tunnel insulating film 43 is provided between the charge storage film 42 and the semiconductor layer 3, and contains, for example, oxygen, nitrogen, and silicon.

[0041] The insulating portion 5 extends from the insulating layer 12 toward the semiconductor layer 3 in the X-axis direction or the Y-axis direction. The insulating portion 5 is provided on the surface 120a. The insulating portion 5 is provided between the insulating layer 12 and the memory layer 4. The insulating portion 5 surrounds the semiconductor layer 3. The insulating portion 5 contains, for example, silicon and oxygen. When the insulating portion 5 contains the same material as the insulating layer 12, the interface between the insulating portion 5 and the insulating layer 12 may not be clearly visible even using a device such as a transmission electron microscope (TEM). In this case, the portion overlapping with the line segment connecting the surfaces of the upper and lower conductive layers 11 above and below the insulating layer 12 that face the block insulating film 41 may be considered to be the interface between the insulating portion 5 and the insulating layer 12.

[0042] FIG. 5 is an enlarged view of a portion of FIG. 3. In a cross section of a NAND string NS along the Z-axis direction, the NAND string NS includes a conductive layer 11, an insulating layer 12, a semiconductor layer 3, a memory layer 4, and an insulating portion 5. The interface between the block insulating film 41 and the charge storage film 42, the interface between the charge storage film 42 and the tunnel insulating film 43, and the interface between the tunnel insulating film 43 and the semiconductor layer 3 each have a first portion that overlaps with a central portion 12M of the insulating layer 12 in the Z-axis direction in the X-axis direction or the Y-axis direction, a second portion that overlaps with an end portion 12E of the insulating layer 12 in the Z-axis direction in the X-axis direction or the Y-axis direction, and a third portion that overlaps with a central portion 11M of the conductive layer 11 in the Z-axis direction. The central portion 11M is, for example, a region located at a depth half the thickness (length in the Z-axis direction) of the conductive layer 11 from the top or bottom surface of the conductive layer 11. The central portion 12M is, for example, a region located at a depth half the thickness (length in the Z-axis direction) of the insulating layer 12 from the top or bottom surface of the insulating layer 12. The end 12E is a region that contacts the end of the conductive layer 11 in the Z-axis direction. The second portions are provided above and below the first portion. Fig. 5 shows an example in which the interface between the block insulating film 41 and the charge storage film 42 has a portion P1 that overlaps with the central portion 12M of the insulating layer 12 in the Z-axis direction, a portion P2 that overlaps with the end 12E, and a portion P3 that overlaps with the central portion 11M.

[0043] At each interface, the second portion is closer to the insulating layer 12 in the X-axis direction or the Y-axis direction than the first portion. Each interface has a rounded or arched shape that protrudes toward the memory layer 4. Each interface is curved convexly toward the semiconductor layer 3 from the first portion to the upper and lower second portions. For example, as shown in FIG. 5, the interface between the block insulating film 41 and the charge storage film 42 is curved convexly toward the semiconductor layer 3 from portion P1 to upper and lower portions P2.

[0044] At each interface, the distance D1 between the second and third portions in the X-axis or Y-axis direction is preferably 0.5 nm or more and 5 nm or less. If it is less than 0.5 nm, it becomes difficult to suppress electrical interference between adjacent memory cells MC. If it exceeds 5 nm, for example, when a voltage is applied to the gate electrode WL, the electric field may concentrate in the central portion 11M, reducing the write efficiency.

[0045] The thickness (length in the X-axis or Y-axis direction) of the insulating section 5 is preferably 0.5 nm or more and 5 nm or less. This means that the thickness of the entire region of the insulating section 5, from its minimum thickness to its maximum thickness, may be 0.5 nm or more and 5 nm or less.

[0046] Next, a first example of a method for forming the first structural example of the NAND string NS in the method for manufacturing a semiconductor memory device will be described with reference to Figures 6 to 13. Figures 6 to 13 are cross-sectional schematic views for explaining the first example of a method for forming the first structural example of the NAND string NS, showing a part of the XZ cross section.

[0047] First, as shown in FIG. 6, insulating layers 110 and 12 are alternately stacked along the Z-axis direction to form a laminate 1a. The insulating layer 110 is a sacrificial layer. The sacrificial layer is a layer that will later form a space. Examples of the insulating layer 110 include a silicon nitride layer.

[0048] 7, the laminate 1a is processed to form an opening (memory hole MH) penetrating the laminate 1a along the Z-axis direction, a surface 110a, and a surface 120a. The surface 110a is provided in the insulating layer 110 and faces the memory hole MH. The surface 120a is provided in the insulating layer 12 and faces the memory hole MH. The laminate 1a can be processed using, for example, reactive ion etching (RIE).

[0049] 7, the surfaces 110a and 120a are exposed on the inner surface of the memory hole MH. The surface 110a is provided at a position different from the position of the surface 120a. The positions of the surfaces 110a and 120a are, for example, positions on the inner side surface of the memory hole MH. The surface 120a includes SiO2, and the surface 110a includes SiN.

[0050] Next, as shown in FIG. 8, an insulating portion 5 is selectively formed on the surface 120a of the insulating layer 12. The insulating portion 5 can be formed by, for example, selective growth. When the insulating portion 5 containing, for example, silicon oxide is formed by selective growth, the insulating portion 5 is formed using a gas containing a silicon (Si) precursor that can selectively adsorb to OH groups on the surface 120a of the insulating layer 12, which is a silicon oxide film, and an oxidizing agent. As the oxidizing agent, for example, O2 or HO is preferable. Note that the method for forming the insulating portion 5 is not limited to the above method. The insulating portion 5 can be formed by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0051] More specifically, in ALD, multiple ALD cycles are performed, where one ALD cycle consists of supplying a gas containing a Si precursor to a chamber of a semiconductor manufacturing device, evacuation / purging, supplying a gas containing an oxidant, and evacuation / purging.

[0052] The Si precursor includes, for example, an amino group and an alkoxy group. The Si precursor is, for example, an aminoalkoxysilane. More specifically, the Si precursor is, for example, diisopropylaminotriethoxysilane (DIPATEOS). However, as will be described later, the Si precursor is not limited thereto.

[0053] The supply of the Si precursor cleaves the amino groups of the Si precursor, causing the Si precursor to selectively adsorb to the OH groups of the SiO2. This is because the activation energy of the chemisorption reaction of the Si precursor is greater for NH groups than for OH groups. The alkoxy groups of the Si precursor are then oxidized by the supply of an oxidizing agent, converting the Si precursor to SiO2. The alkoxy groups contain oxygen (O) in their molecular structure and are oxidized by an oxidation process with relatively low oxidizing power. ALD using an oxidizing agent with low oxidizing power can suppress the oxidation of SiN on the surface 110a and prevent the NH groups on the surface 110a from being converted to OH groups. This makes it easier to selectively grow SiO2 on the surface 120a. In other words, selectivity can be improved.

[0054] The oxidizing agent is not limited to O2 or H2O, and may include a substance that has a low oxidizing power and makes it difficult for OH groups to be formed on the surface 110a (the outermost surface of the SIN).

[0055] 9, the block insulating film 41 is formed on the surface 110a and the surface of the insulating section 5. The block insulating film 41 can be formed by using, for example, CVD or ALD.

[0056] 10, a charge storage film 42 is formed on the surface of the block insulating film 41. The charge storage film 42 can be formed by using, for example, CVD or ALD.

[0057] 11, a tunnel insulating film 43 is formed on the surface of the charge storage film 42. The tunnel insulating film 43 can be formed by using, for example, CVD or ALD.

[0058] 12, a semiconductor layer 3 is formed on the surface of the tunnel insulating film 43, and an insulator 2 is formed on the surface of the semiconductor layer 3. The semiconductor layer 3 and the insulator 2 can be formed using, for example, CVD or ALD.

[0059] Next, as shown in FIG. 13, the insulating layer 110 is removed to form a space S, and then the conductive layer 11 is formed in the space S. The insulating layer 110 can be removed by wet etching or dry etching, for example. The conductive layer 11 can be formed by CVD or ALD, for example. Through the above steps, the first structural example of the NAND string NS can be formed.

[0060] FIG. 14 is a graph illustrating an example of the cycle number dependence of the stacked film thickness in the first exemplary formation method. The vertical axis represents the film thickness (Å) of SiO2 formed by ALD. The horizontal axis represents the number of ALD cycles. In the example shown in FIG. 14, aminoalkoxysilane is used as the Si precursor, O2 is used as the oxidizing agent, and the ALD processing temperature is approximately 400°C.

[0061] 14, the SiO on the surface 120a (SiO) is thicker than the SiO on the surface 110a (SiN). That is, the incubation on the surface 110a (SiN) is greater than that on the surface 120a (SiO). Also, as the number of ALD cycles increases, the thickness of the SiO on the surfaces 110a and 120a increases.

[0062] After about 10 ALD cycles, SiO begins to form on surface 110a (SiN). After about 10 ALD cycles, the difference in SiO thickness between surface 120a and surface 110a is, for example, 7.0 Å. After about 50 ALD cycles, the difference in SiO thickness between surface 120a and surface 110a is, for example, 9.1 Å. The first exemplary formation method can ensure the above-mentioned degree of selectivity.

[0063] As described above, in the first structural example of the NAND string NS of the embodiment, by forming the insulating portion 5, for example, during data write, the trapped electron density in the region of the charge storage film 42 that overlaps with the conductive layer 11 in the X-axis direction or the Y-axis direction can be increased, thereby suppressing electrical interference between adjacent memory cells MC. Furthermore, by forming the insulating portion 5 in a shape that is convexly curved toward the semiconductor layer 3, electric field concentration near the end 12E, for example, can be suppressed. Therefore, malfunction of the memory cells MC can be suppressed.

[0064] In the first example formation method, the Si precursor contains an amino group. This allows the Si precursor to selectively adsorb to the OH groups present on the surface 120a of the coexisting exposed surfaces 110a and 120a. Furthermore, because the Si precursor contains an alkoxy group, an oxidizing agent with low oxidizing power is used. This suppresses oxidation of SiN on the surface 110a and prevents the NH groups on the surface 110a from being replaced by OH groups. This makes it easier to selectively grow SiO2 on the surface 120a. In other words, selectivity can be improved.

[0065] Furthermore, the first example of the formation method does not require an additional step for increasing selectivity, and therefore, selectivity can be increased without complicating the process.

[0066] In addition, since the oxidizing power of the oxidizing agent is low, SiO2 can be grown by ALD at low temperatures. The processing temperature for ALD is, for example, 300°C to 600°C.

[0067] Furthermore, when the ligand of an amino group is an isopropyl group, the difference in activation energy of the chemisorption reaction between the OH group and the NH group is maximized. Therefore, from the viewpoint of selectivity, the amino group is preferably, for example, a dialkylamino group, and the dialkylamino group is preferably, for example, a diisopropylamino group.

[0068] The alkoxy group is, for example, a methoxy group or an ethoxy group.

[0069] The Si precursor may also be a monosilane containing an amino group and an alkoxy group (aminoalkoxysilane), or a disilane containing an amino group and an alkoxy group (aminoalkoxydisilane).

[0070] As a comparative example, aminosilane may be used as a Si precursor. In this case, an oxidizing agent containing oxygen radicals or ozone, which has a stronger oxidizing power than O or HO, is used. However, if the oxidizing power is strong, SiN on the surface 110a is oxidized, and the NH groups on the surface 110a are replaced with OH groups. As a result, SiO is likely to grow incorrectly on the surface 110a.

[0071] In contrast, in the first exemplary formation method, the Si precursor contains an alkoxy group. This allows ALD to be performed using an oxidizing agent with low oxidizing power. As a result, oxidation of SiN on the surface 110a can be suppressed, and the substitution of NH groups on the surface 110a with OH groups can be suppressed. This makes it easier to selectively grow SiO2 on the surface 120a. In other words, selectivity can be improved.

[0072] (Second Example of Method for Forming the First Example of the Structure of the NAND String NS) Next, a second example of a method for forming the first structural example of the NAND string NS in the method for manufacturing a semiconductor memory device will be described with reference to Figures 15 and 16. Figures 15 and 16 are schematic cross-sectional views for explaining the second example of a method for forming the first structural example of the NAND string NS, showing a part of the XZ cross section.

[0073] The second example of the formation method differs from the first example of the formation method in that a protective film 6 is formed.

[0074] First, similar to the first forming method example, memory holes MH are formed using the steps shown in FIGS. 6 and 7 . Then, as shown in FIG. 15 , a protective film 6 is formed on the surface 110 a. Then, as shown in FIG. 16 , an insulating portion 5 is selectively formed on the surface 120 a of the insulating layer 12. Selectivity can be enhanced by covering part of the surface with a protective film such as an insulating film and varying the thickness or composition of the remaining part of the surface. That is, the protective film 6 inhibits the adsorption of the Si precursor to the surface 110 a. For example, when forming an insulating portion 5 containing silicon oxide, the protective film 6 is formed by modifying the surface 110 a using an inhibitor that can selectively adsorb to NH groups present on the surface 110 a of the insulating layer 110, e.g., a silicon nitride film. Next, the insulating portion 5 is formed using a Si precursor that can selectively adsorb to OH groups on the surface 120 a of the insulating layer 12, a silicon oxide film, and an oxidizer at a low temperature at which the protective film 6 does not desorb from the surface 110 a. The Si precursor and oxidizer may be the same as those described in the first forming method example. The protective film 6 can be formed by using, for example, CVD or ALD, but may also be formed by using a technique such as coating.

[0075] More specifically, during one ALD cycle, before supplying the Si precursor, a gas containing Cl is supplied as an inhibitor, followed by evacuation and purging. Due to the activation energy relationship between OH groups and NH groups, Cl selectively adsorbs to NH groups, and the surface 110a is selectively terminated with SiCl. This further prevents the surface 110a from being oxidized to form OH groups. The Cl-containing gas may include, for example, chlorosilane or HCl. The chlorosilane may include, for example, SiCl, SiHCl, or SiHCl. The Cl-containing gas may be supplied in every ALD cycle, or in at least one ALD cycle among multiple ALD cycles.

[0076] 9 and subsequent steps are then performed. Note that the protective film 6 is formed by modifying the top surface and is therefore very thin, so it does not need to be removed. If a thick protective film 6 is formed, the protective film 6 may be removed by, for example, dry etching or wet etching.

[0077] In the second example of the formation method, by using a gas containing Cl as an inhibitor, it is possible to further suppress the adsorption of the Si precursor onto the surface 110a made of SiN, thereby improving the selectivity.

[0078] (Second example of the structure of the NAND string NS) 17 is a cross-sectional view illustrating a second example structure of a NAND string NS according to an embodiment, showing an X-axis, a Y-axis perpendicular to the X-axis, and a Z-axis perpendicular to the X-axis and Y-axis, and showing a portion of an X-Z cross section including the X-axis and Z-axis. FIG. 18 is a cross-sectional view taken along line AB in FIG. 17, showing a portion of an X-Y cross section including the X-axis and Y-axis.

[0079] As shown in FIGS. 17 and 18, the NAND string NS includes a stacked body 1, an insulator 2, a semiconductor layer 3, a memory layer 4, and an insulating portion 5.

[0080] 18, the semiconductor layer 3 surrounds the insulator 2 in the AB cross section. The semiconductor layer 3 penetrates the stacked body 1 along the Z-axis direction. For other descriptions of the semiconductor layer 3, the description of the semiconductor layer 3 shown in FIG. 3 can be used as appropriate.

[0081] The memory layer 4 is provided on the opposite side of the semiconductor layer 3 to the insulator 2. The memory layer 4 is provided between the conductive layer 11 and the semiconductor layer 3 in the X-axis direction or the Y-axis direction.

[0082] The memory layer 4 has a block insulating film 41, a charge storage film 42, and a tunnel insulating film 43. The block insulating film 41 is provided between the insulating unit 5 and the semiconductor layer 3 in the X-axis direction or the Y-axis direction. The charge storage film 42 is provided between the tunnel insulating film 43 and the block insulating film 41 in the X-axis direction or the Y-axis direction. The tunnel insulating film 43 is provided between the charge storage film 42 and the semiconductor layer 3. For other descriptions of the block insulating film 41, the charge storage film 42, and the tunnel insulating film 43, the descriptions of the block insulating film 41, the charge storage film 42, and the tunnel insulating film 43 shown in FIG. 3 can be used as appropriate.

[0083] The insulating portion 5 extends from the insulating layer 12 toward the semiconductor layer 3 in the X-axis direction or the Y-axis direction. The insulating portion 5 is provided on the surface 120a. The insulating portion 5 is provided between the insulating layer 12 and the memory layer 4. For other descriptions of the insulating portion 5, the description of the insulating portion 5 shown in FIG. 3 can be used as appropriate.

[0084] 19 is an enlarged view of a portion of FIG. 17. In a cross section of a NAND string NS along the Z-axis direction, the NAND string NS includes a conductive layer 11, an insulating layer 12, a semiconductor layer 3, a memory layer 4, and an insulating portion 5. The interface between the block insulating film 41 and the charge storage film 42, the interface between the charge storage film 42 and the tunnel insulating film 43, and the interface between the tunnel insulating film 43 and the semiconductor layer 3 each have a first portion that overlaps, in the X-axis direction or the Y-axis direction, with a central portion 12M of the insulating layer 12 in the Z-axis direction, a second portion that overlaps, in the X-axis direction or the Y-axis direction, with an end portion 12E of the insulating layer 12 in the Z-axis direction, and a third portion that overlaps with a central portion 11M of the conductive layer 11 in the Z-axis direction. The central portion 11M is a region located at a depth half the thickness (length in the Z-axis direction) of the conductive layer 11 from the top or bottom surface of the conductive layer 11. The central portion 12M is, for example, a region located at a depth of half the thickness (length in the Z-axis direction) of the insulating layer 12 from the upper or lower surface of the insulating layer 12. The end portion 12E is a region that contacts the end portion of the conductive layer 11 in the Z-axis direction. The second portions are provided above and below the first portion. FIG. 19 shows an example in which the interface between the block insulating film 41 and the charge storage film 42 has a portion P1 that overlaps with the central portion 12M in the Z-axis direction of the insulating layer 12, a portion P2 that overlaps with the end portion 12E, and a portion P3 that overlaps with the central portion 11M.

[0085] At each interface, the second portion is closer to the insulating layer 12 in the X-axis direction or the Y-axis direction than the first portion. Each interface has a rounded or arched shape that protrudes toward the memory layer 4. Each interface is curved convexly toward the semiconductor layer 3 from the first portion to the upper and lower second portions. For example, as shown in FIG. 19 , the interface between the block insulating film 41 and the charge storage film 42 is curved convexly toward the semiconductor layer 3 from portion P1 to upper and lower portions P2.

[0086] At each interface, the distance D1 between the second and third portions in the X-axis or Y-axis direction is preferably 2 nm or more and 7 nm or less. If it is less than 2 nm, it becomes difficult to suppress electrical interference between adjacent memory cells MC. If it exceeds 7 nm, the electric field depending on the voltage applied when writing data to the memory cell MC may concentrate in the central portion 11M, reducing the write efficiency.

[0087] The thickness of the insulating section 5 (the length in the X-axis or Y-axis direction) may decrease from the first portion to the second portion of each interface. The thickness of the insulating section 5 is preferably 2 nm or more and 7 nm or less. This means that the thickness of the entire region of the insulating section 5, from the portion where the thickness is smallest to the portion where the thickness is largest, may be 2 nm or more and 7 nm or less.

[0088] The thickness of the charge storage film 42 (the length of the charge storage film 42 in the X-axis or Y-axis direction) may increase from the first portion to the second portion of each interface. The thickness of the region of the charge storage film 42 overlapping the first portion is preferably smaller than the thickness of the insulating section 5. This allows the electron capture region of the charge storage film 42 to be larger, thereby suppressing, for example, degradation of write characteristics. The thickness of the charge storage film 42 is preferably, for example, 2 nm or more and 10 nm or less. If the thickness is less than 2 nm, the charge capture performance will deteriorate, and, for example, the write characteristics will deteriorate. If the thickness exceeds 10 nm, electrical interference between adjacent memory cells MC will increase.

[0089] The charge storage film 42 has a region 42a that overlaps the conductive layer 11 in the X-axis or Y-axis direction and a region 42b that overlaps the insulating portion 5 in the X-axis or Y-axis direction. In FIG. 19, the boundary between the region 42a and the region 42b is indicated by a two-dot chain line. The region 42b preferably has a thickness smaller than that of the region 42a in the X-axis or Y-axis direction. This can suppress electrical interference between adjacent memory cells MC. However, without being limited to this, the charge storage film 42 may be thinned to separate the multiple regions 42a without forming the region 42b.

[0090] In the second structural example of the NAND string NS in the manufacturing method of a semiconductor memory device, the insulating portion 5 is formed by the process shown in Figure 8 (first forming method example) or the process shown in Figures 15 and 16 (second forming method example).

[0091] As described above, in the second structural example of the NAND string NS, by forming the insulating portion 5, for example, during data write, the density of trapped electrons in the region of the charge storage film 42 that overlaps with the conductive layer 11 in the X-axis direction or the Y-axis direction can be increased, thereby suppressing electrical interference between adjacent memory cells MC. Furthermore, by forming the insulating portion 5 in a shape that is convexly curved toward the semiconductor layer 3, electric field concentration can be suppressed, for example, at the interface between the block insulating film 41 and the charge storage film 42. Furthermore, by increasing the thickness of the charge storage film 42 from the first portion to the second portion at each interface, a high-quality charge storage film 42 can be formed without increasing the aspect ratio of the memory hole MH, thereby suppressing, for example, deterioration of the charge retention characteristics. Therefore, malfunctions of the memory cells MC can be suppressed.

[0092] The components of the second structural example can be combined as appropriate with the components of the first structural example.

[0093] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0094] 1...laminated body, 1a...laminated body, 2...insulator, 3...semiconductor layer, 4...memory layer, 5...insulating portion, 6...protective film, 11...conductive layer, 11M...central portion, 12...insulating layer, 12E...edge, 12M...central portion, 13...inner groove, 41...block insulating film, 42...charge storage film, 43...tunnel insulating film, 44...insulating layer, 45...insulating layer, 100...memory cell array, 101...command register, 102...address register, 103...sequencer, 104...driver, 105...row decoder, 106...sense amplifier, 110...insulating layer, 110a...surface, 120a...surface.

Claims

1. SiO ２ and an exposed second surface at a location different from the location of the first surface, the second surface comprising SiN; On the first surface, SiO ２ Selectively forming an insulating portion including: It is equipped with Selectively forming the insulating portion on the first surface includes using a Si precursor containing an amino group and an alkoxy group, and ２ or H ２ A method for manufacturing a semiconductor device, comprising performing a treatment using an oxidizing agent containing O.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the Si precursor is an aminoalkoxysilane, an aminoalkoxydisilane, or diisopropylaminotriethoxysilane.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the amino group is a dialkylamino group.

4. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the dialkylamino group is a diisopropylamino group.

5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the alkoxy group is a methoxy group or an ethoxy group.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of said treatment is 300 to 600.degree.

7. the process is atomic layer deposition (ALD) including multiple repeated ALD cycles; The ALD cycle comprises: supplying a gas containing the Si precursor; purging the gas containing the Si precursor; supplying a gas containing the oxidant; purging the oxidant-containing gas; The method for manufacturing a semiconductor device according to claim 1 , comprising:

8. At least one of the plurality of ALD cycles includes, before supplying the gas containing the Si precursor, supplying a gas containing Cl; Purging the gas containing Cl; The method for manufacturing a semiconductor device according to claim 7 , further comprising:

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the gas containing Cl contains chlorosilane or HCl.

10. forming the structure SiO ２ and a second layer including SiN are alternately stacked in a first direction to form a stacked body; forming a hole penetrating the laminate in the first direction; This includes: The method for manufacturing a semiconductor device according to claim 1 , wherein the first surface and the second surface are exposed at inner surfaces of the hole.

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