Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of easily and largely securing contact between sintered metal and an interface to be joined.SOLUTION: A semiconductor device comprises a first member that is made of metal, and a second member that includes a semiconductor chip. The first and second members are joined together by sinter bonding. Irregularities are formed on an interface-to-be-joined of at least one of the first and second members. An interval between the irregularities is 10 μm or less.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] There is a need to improve the power cycle life of high-heat-resistant power semiconductor modules used in electric railways, electric vehicles, and industrial applications. To meet this need, an effective solution is to use sintered bonding, which has excellent heat resistance, to bond the semiconductor chip to the substrate instead of the conventional solder bonding.

[0003] Techniques relating to sinter bonding are disclosed in, for example, Patent Documents 1 and 2. FIG. 5 and paragraphs 0040 to 0044 of Patent Document 1 describe a technology in which dimples that exert an anchor effect are formed on the surface of a substrate using a laser, a paste-like sinterable metal bonding material is printed, the printed sinterable metal bonding material is dried, a semiconductor element is mounted on the dried sinterable metal bonding material and temporarily fixed, and then the substrate and semiconductor element are bonded by heating under pressure using the sinterable metal bonding material.

[0004] Furthermore, Patent Document 2 describes that by mixing flake particles, it is possible to suppress volume shrinkage during bonding and perform sintering without pressure. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 087920 [Patent Document 2] Patent Publication No. 2021-64612 Summary of the Invention [Problem to be solved by the invention]

[0006] In solder joints, the solder metal melts and spreads over the joint interface, ensuring contact at the interface during joining. On the other hand, in sinter bonding, the sintered metal does not melt but is bonded by diffusion while remaining in powder form, so it is more difficult to ensure contact at the interface than with solder.

[0007] In response to this, a common technique is to apply pressure to press the chip or wiring onto the powder, thereby ensuring contact at the interface, as described in Patent Document 1, for example. As another example, Patent Document 2 discloses a technology in which flake particles are mixed to suppress volumetric shrinkage during bonding, making it easier to ensure contact even without applying pressure.

[0008] However, even when pressure is applied, it may not be easy to ensure uniform contact with the solid powder. Also, due to concerns about damage to the chip, it is not possible to apply an unlimited amount of pressure.

[0009] Furthermore, even if volumetric shrinkage is suppressed by combining particles when no pressure is applied, it is still difficult to ensure contact at the interface compared to solder, in which the metal melts and actively spreads, or sintering technology, in which pressure is used to suppress some variation and ensure contact.

[0010] In order to solve the above-mentioned problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can easily ensure large contact between the sintered metal and the interface to be joined.

[0011] The above and other objects of the present invention and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0012] The first semiconductor device of the present invention comprises a first member made of metal and a second member including a semiconductor chip, the first member and the second member being joined by sintering bonding, and irregularities are formed at the joining interface of at least one of the first member and the second member, with the spacing between the irregularities being 10 μm or less.

[0013] The second semiconductor device of the present invention comprises a first member made of metal and a second member including a semiconductor chip, the first member and the second member being joined by sintering bonding, and the joining interface of at least one of the first member and the second member being composed of crystal grains having a grain size of 10 μm or less.

[0014] The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a first member made of metal and a second member including a semiconductor chip are joined by sinter bonding, in which irregularities with a spacing of 10 μm or less are formed at the joining interface of at least one of the first member and the second member, and then sintered metal is supplied to the joining interface where the irregularities have been formed, thereby performing sinter bonding. [Effects of the Invention]

[0015] According to the present invention, the bonding interface has fine irregularities spaced 10 μm or less apart, or is made up of crystal grains with a grain size of 10 μm or less. This promotes atomic diffusion during sinter bonding, activates interdiffusion between the sintered metal and the bonding interface, and makes the bonding contact denser. This results in a bonding layer that is resistant to peeling and has good thermal conductivity.

[0016] Problems, configurations, and effects other than those described above will become clear from the following description of the embodiments. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a schematic cross-sectional view showing the structure of a semiconductor module according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing an example of the structure of a joining interface of a semiconductor module according to a first embodiment. [Figure 3] FIG. 2 is a schematic diagram illustrating diffusion during sinter bonding. [Figure 4] A and B are cross-sectional views showing diffusion at the interface during typical sinter bonding. [Figure 5] 1A and 1B are cross-sectional views showing diffusion at an interface during sinter-bonding in a semiconductor device of the present invention. [Figure 6] This is an SEM image of the surface state of a Ni film after etching. [Figure 7] A: SEM image of a cross section of a normal Ni film after sinter bonding. B: SEM image of a cross section of a Ni film after sinter bonding with a textured surface. [Figure 8] FIG. 1 is a cross-sectional view illustrating the phenomenon explained by Wenzel's formula. [Figure 9] FIG. 10 is a cross-sectional view of a sintered joint of a conventional semiconductor module. [Figure 10] FIG. 10 is a cross-sectional view of a sintered joint of a semiconductor module according to a second embodiment. [Figure 11] 10A and 10B are cross-sectional views showing a method for manufacturing a semiconductor module according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] The following describes embodiments and examples of the present invention using text and drawings. However, the structures, materials, and other specific configurations shown in the present invention are not limited to the embodiments described here, and can be appropriately combined or improved within the scope of the present invention. Furthermore, elements not directly related to the present invention are omitted from the illustrations.

[0019] A first semiconductor device of the present invention comprises a first member made of metal and a second member including a semiconductor chip, the first member and the second member being joined by sintering. In the first semiconductor device of the present invention, at least one of the first member and the second member has an unevenness formed on the interface to be joined, and the unevenness is spaced apart by 10 μm or less.

[0020] A second semiconductor device of the present invention comprises a first member made of metal and a second member including a semiconductor chip, the first member and the second member being joined by sintering. In the second semiconductor device of the present invention, the interface to be joined of at least one of the first member and the second member is made up of crystal grains with a grain size of 10 μm or less.

[0021] The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a first member made of metal and a second member including a semiconductor chip are bonded by sinter bonding. The method for manufacturing a semiconductor device of the present invention involves forming irregularities with a spacing of 10 μm or less at the joining interface of at least one of the first and second members, and then supplying a sintered metal to the joining interface where the irregularities have been formed, thereby performing sintering joining.

[0022] According to the first semiconductor device and the method for manufacturing the semiconductor device of the present invention, the interface between at least one of the first and second members is provided with irregularities spaced 10 μm or less, which promotes atomic diffusion during sinter bonding, activates interdiffusion between the sintered metal and the interface, and densely bonds the bonding contacts, thereby providing a bonding layer that is resistant to peeling and has good thermal conductivity.

[0023] According to the second semiconductor device of the present invention, the interface between at least one of the first and second members is composed of crystal grains with a grain size of 10 μm or less. The small grain size of the crystal grains increases the number of crystal grain boundaries. This promotes atomic diffusion during sinter bonding, activating interdiffusion between the sintered metal and the interface, resulting in a denser bonded contact. This results in a bonded layer that is resistant to peeling and has good thermal conductivity.

[0024] In the first semiconductor device, the interval between the projections and recesses may be 0.1 μm or less. In this structure, since the grains of typical sintered metals are submicron in size, unevenness is created on average near all grains near the joining interface, which makes it easier to further improve the quality of the sintered bond.

[0025] In the first semiconductor device, the depth of the irregularities may be 0.1 μm or more. In this configuration, the depth of the irregularities is 0.1 μm or more, which makes it easier to form dense regions of sintered metal.

[0026] In the first semiconductor device, the opening diameter of the irregularities may be 10 μm or less. In this configuration, the opening diameter of the irregularities is 10 μm or less, which makes it difficult for sintered metal particles to enter the irregularities. This reduces the difference in thickness of the sintered metal between inside and outside the irregularities, allowing the pressure applied during sinter bonding to be transmitted evenly.

[0027] In the first semiconductor device, the opening diameter of the irregularities may be 0.01 μm or less. In this configuration, since the opening diameter of the irregularities is 0.01 μm or less, even if the sintered metal particles have a submicron diameter, the sintered metal particles are less likely to penetrate the irregularities. This means that there is almost no difference in the thickness of the sintered metal between inside and outside the irregularities, and the pressure applied during sintering bonding can be transmitted evenly.

[0028] In the first semiconductor device described above, the irregularities may be formed along the grain boundaries of the member. In this configuration, the asperities are formed along the grain boundaries of the members, which makes it easier for the sintered metal to enter the grain boundaries of the members, thereby making it easier to improve the quality of the sintered bond.

[0029] In the first semiconductor device described above, the region where the irregularities are formed may be configured to extend outward beyond the sinter-bonded region. In this configuration, unevenness is formed in the area extending outward from the sinter-bonded area, so when the sintered metal paste is heated to remove the solvent, the unevenness in the area extending outward from the sinter-bonded area can be used to make it easier to drain the solvent.

[0030] In the first semiconductor device described above, the sintered metal that sinter-bonds the first member and the second member may be copper. In this configuration, the copper diffusion rate is low, so sintering of the sintered bonding layer due to self-heating is unlikely to occur during operation of the semiconductor device after manufacture. Therefore, even if the sintered density of the sintered bonding layer is low when the first and second members are bonded, the reliability of the semiconductor device after manufacture can be maintained.

[0031] In the first semiconductor device, the bonded boundary having the irregularities formed thereon can be made up of crystal grains having a grain size of 10 μm or less. In this structure, the grain size is small, so the number of grain boundaries increases, which promotes atomic diffusion during sinter bonding, activates interdiffusion between the sintered metal and the bonded interface, and makes the bonded contacts denser. This results in a bonding layer that is less likely to peel and has good thermal conductivity.

[0032] In the above-described method for manufacturing a semiconductor device, when sinter-bonding is performed, a pressure of 0.01 MPa to 1.00 MPa may be applied, or bonding may be performed without applying pressure. In this configuration, bonding is performed with little or no pressure applied, so damage to the semiconductor chips and the like can be suppressed.

[0033] The first and second semiconductor devices described above each include a first member made of metal and a second member including a semiconductor chip, and the first member and the second member are joined by sintering. The first and second semiconductor devices further include wiring connected to the semiconductor chips, and constitute, for example, a semiconductor module.

[0034] In the above-described semiconductor device and method for manufacturing a semiconductor device, the first member made of metal may be a wiring (wiring layer or wiring film) made of metal, a metal plate, or the like. The metal of the wiring layer may be, for example, Cu, Al, etc. In some cases, Ni, Au, Ag, Pd, etc. are formed as a coating on the surface of the metal of the wiring layer. Furthermore, the first member may be a single-layer structure or a multi-layer structure. In either structure, the surface that comes into contact with the sintered metal of the sinter-bonding is the bonded interface.

[0035] In the above-described semiconductor device and method for manufacturing a semiconductor device, the second member including the semiconductor chip may have a structure in which a material to be bonded is formed on the outermost surface of the lower surface of the semiconductor chip, for example. The semiconductor chip may be made of various semiconductor materials such as silicon or SiC. The material to be bonded may be a metal such as Ni, Cu, Au, Ag, or Pd. The second member may be a single-layer structure or a laminate of multiple layers. In either structure, the surface that comes into contact with the sintered metal in the sinter-bonding is the bonded interface.

[0036] In the above-described semiconductor device and method for manufacturing the semiconductor device, metal powder such as Ag powder or Cu powder can be used as the sintered metal for sinter-bonding.

[0037] In the above-described semiconductor device and method for manufacturing the semiconductor device, the irregularities can be formed by etching, laser processing, ion milling, or the like.

[0038] Regarding the combination of the materials to be joined and the sintered metal, Au or Ag is often selected as the material to be joined for Ag powder, and Ni or Cu is often selected as the material to be joined for Cu powder, but the combinations are not limited to these.

[0039] In the first semiconductor device and the method for manufacturing the semiconductor device described above, the irregularities are formed on the interface to be joined of both or one of the first member and the second member. The spacing between the projections and recesses is 10 μm or less. Here, the "spacing" of the irregularities in the present invention is the distance between the centers of the recesses of adjacent irregularities when there are a plurality of irregularities. The smaller the spacing between the irregularities, the more desirable. For example, if the spacing is 0.1 μm or less, considering that the particles of typical sintered metals are submicron in diameter, the irregularities will be located near all particles on average near the bonding interface, making it easier to improve quality. On the other hand, from the viewpoint of thermal resistance, even on a slightly larger scale, if the junctions are dense, a sufficient path for heat dissipation can be secured, so a spacing of 10 μm or less as mentioned above is desirable.

[0040] Furthermore, if the opening diameter of the asperities is large, particles of the sintered metal before sintering will easily penetrate into the asperities. In this case, the difference in thickness of the sintered metal between inside and outside the asperities will be large, causing the amount of shrinkage during sintering to vary depending on the location, making it difficult to uniformly transmit pressure. Therefore, an opening diameter that makes it difficult for particles to penetrate is desirable. If the sintered metal particles are submicron in diameter, an opening diameter of 0.01 μm or less is desirable. However, considering the possibility of coarse particles on the order of microns in diameter being included, an opening diameter of approximately 10 μm or less may be acceptable.

[0041] Furthermore, if the depth of the irregularities (depth of the openings) is, for example, about 0.1 μm, it is easy to form a dense region of sintered metal, but this is not necessarily the case.

[0042] For example, Japanese Patent Application Laid-Open No. 2020-68360 discloses a technique for increasing the surface area and the anchor effect of etching the metal plate to deepen the grain boundaries of the metal plate when joining a metal plate and an electronic component with a bonding material, thereby increasing the adhesive strength. However, this technique describes that the opening width of the etched recess is approximately 3 μm to 10 μm, the recess depth is 2 μm to 20 μm, and the crystal grain size of the metal plate is 100 μm to 600 μm. Considering that the size of sintered particles is generally submicron in diameter, this technology involves arranging holes with depths several tens of times the particle size at large intervals of 100 μm to 600 μm, which is not on the same scale as the objective of the present invention, which is to obtain an overall uniform interface by promoting diffusion.

[0043] Furthermore, according to the present invention, the bonding quality at the interface can be improved, and therefore the pressure applied during sintering can be reduced accordingly. Therefore, the technology of the present invention is particularly effective when used in combination with a process using a minute pressure of 0.01 MPa to 1.00 MPa or a pressureless process that does not use pressure, as opposed to sinter bonding, which generally requires a pressure of the order of 10 MPa.

[0044] Generally, the sintered metal is the aforementioned silver or copper powder. Here, because the diffusion rate of copper is slower than that of silver, sintering of the sintered bonding layer due to self-heating is less likely to occur during operation of the manufactured semiconductor device. Therefore, even if the sintered density of the sintered bonding layer is low when the first and second members are completely bonded, the reliability of the manufactured semiconductor device can be maintained. For this reason, using copper as the sintered metal rather than silver allows for a lower pressure during sintering than conventional methods, ensuring the reliability of the manufactured semiconductor module even if the sintered density of the sintered bonding layer is low. Therefore, the technology of the present invention is particularly effective when copper is used as the sintered metal and when it is used in combination with a process that uses a small pressure. [Example]

[0045] Specific embodiments of the semiconductor device of the present invention will be described below with reference to the drawings. In each of the following embodiments, the semiconductor device of the present invention comprises a semiconductor chip and a wiring layer, and the semiconductor chip and the wiring layer are bonded by sintering to form a semiconductor module. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0046] Example 1 A semiconductor module according to a first embodiment will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor module according to a first embodiment.

[0047] As shown in Figure 1, the semiconductor module 20 of this embodiment has a semiconductor chip 1, a sintered metal layer 2, a substrate 3, a base plate 4, a sintered metal layer 5 under the substrate, wires 6, terminals 7, a case 8, a sealing resin 9, and a lid 10.

[0048] The substrate 3 includes an insulating substrate 3c, a wiring layer 3a provided on the front side of the insulating substrate 3c, and a backside metal layer 3b provided on the backside of the insulating substrate 3c. The wiring layer 3a is composed of multiple wiring patterns. The wiring layer 3a may be made of a conductive metal such as copper. The backside metal layer 3b may be made of copper.

[0049] The semiconductor chip 1 is bonded to the wiring layer 3a via the sintered metal layer 2. For example, a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a diode can be used as the semiconductor chip 1. For example, a sintered copper layer or a sintered silver layer can be used as the sintered metal layer 2. In FIG. 1, two semiconductor chips 1 are sinter-bonded to a wiring layer 3a via a sintered metal layer 2, respectively.

[0050] The base plate 4 functions as a heat dissipation member. The base plate 4 and the backside metal layer 3b of the substrate 3 are joined via an under-substrate sintered metal layer 5 below the substrate 3. A case 8 is adhered to the base plate 4, for example, via an adhesive (not shown).

[0051] The wires 6 are conductive wires that electrically connect the semiconductor chips 1 to each other, the wiring layers 3a to each other, or between the semiconductor chip 1 and the wiring layer 3a. One end of the terminal 7 is connected to the wiring layer 3a, and a part of the other end is drawn out to the outside of the case 8 to function as an external connection terminal.

[0052] The sealing resin 9 may be, for example, silicone gel or epoxy resin. A lid 10 is placed on the sealing resin 9, and the lid 10 is bonded to the case 8 via an adhesive (not shown).

[0053] 2 is a cross-sectional view showing an example of the structure of the bonded interface of the semiconductor module 20 of Example 1. In Example 1, particularly on the surface of the semiconductor chip 1 and the surface of the wiring layer 3a, which become the bonded interface of the semiconductor module 20, minute irregularities 11 and 12 as shown in FIG. 2, semiconductor chip 1 has a first layer 1A including semiconductor elements made of silicon or SiC and other electrode films, and a second layer 1B on the outermost surface on which a bonded material such as Ni is exposed, with fine irregularities 11 formed on the underside of second layer 1B. Furthermore, fine irregularities 12 are formed on the upper side of wiring layer 3a on which a bonded material such as Cu is exposed.

[0054] In FIG. 2, the minute irregularities 11, 12 are formed on both the second layer 1B of the semiconductor chip 1 and the wiring layer 3a, but the irregularities may be formed on only one of the second layer 1B and the wiring layer 3a.

[0055] In addition to the above-mentioned Ni, Cu, Au, Ag, Pd, etc. can be used as the bonding material for the outermost surface of the second layer 1B of the semiconductor chip 1. As the sintered metal for sinter bonding, Ag powder or Cu powder can be used. Regarding the combination of the sintered metal and the outermost material to be joined, Au or Ag is often selected for the outermost surface for Ag powder, and Ni or Cu is often selected for the outermost surface for Cu powder, but the combinations are not limited to these.

[0056] Furthermore, for example, a semiconductor chip 1 such as a power semiconductor element or a wiring layer 3a made of metal wiring may have a layer structure formed by plating or the like, and in such a case, unevenness is provided at least on the bonding interface on the outermost surface of the layer structure.

[0057] The semiconductor module 20 of the first embodiment can be manufactured, for example, as described below. First, fine irregularities are formed on the outermost surface of at least one of the semiconductor chip 1 and the wiring layer 3a. The fine irregularities can be formed by etching, laser processing, ion milling, or the like. Next, a paste supplying step is performed in which a paste of a sintering material that will become the sintered metal layer 2 is supplied to the wiring layer 3a by printing or using a dispenser. The paste is then heated to perform a pre-drying process to remove the solvent components contained in the paste. However, this pre-drying process can be omitted in some cases, and the solvent components can be removed by heating in the sintering process. Next, a chip mounting step is carried out in which the semiconductor chip 1 is mounted on the sintered material. Finally, a sintering process is carried out in which heat and pressure are applied to sinter-bond the parts. Depending on the bonding material used, it may be possible to sinter-bond the parts without applying pressure.

[0058] Here, the diffusion of atoms during sinter bonding will be explained. Sinter bonding can be understood as a phenomenon in which atoms constituting the sintered metal and atoms constituting the materials to be joined are exchanged with each other through diffusion, gradually becoming one. At this time, there are three main modes of atomic diffusion. One is surface diffusion, which is the fastest because it moves along the outermost surface where there are few obstacles. Next, there is grain boundary diffusion, which travels through grain boundaries. Although this diffusion is slower than surface diffusion, it is the second fastest diffusion because it travels through grain boundaries where other atoms are relatively scarce. The last is volume diffusion, which is the slowest, due to the diffusion of atoms through dense particles. Thus, sintering is a phenomenon that proceeds through three diffusion modes.

[0059] FIG. 3 is a schematic diagram illustrating diffusion during sinter bonding. FIG. 3 shows the state of diffusion when two sintered metals 21 and 22 are sinter-bonded, and atoms 23 constituting the sintered metals 21 and 22 are diffused in the above three modes. Arrows 31 indicate surface diffusion, in which atoms diffuse through the outermost surfaces of the particles of the sintered metals 21 and 22 . Arrows 32 indicate grain boundary diffusion, in which atoms diffuse near grain boundaries 24 of the particles of sintered metals 21 and 22 . Arrows 33 indicate volume diffusion, in which atoms diffuse inside the grains of the sintered metals 21 and 22 . As shown in the upper diagram of Figure 3, atoms 23 of sintered metals 21 and 22 diffuse through surface diffusion 31, grain boundary diffusion 32, and volume diffusion 33, and the two sintered metals 21 and 22 are joined at the grain boundary 23, as shown in the lower diagram of Figure 3.

[0060] Next, the bonding mechanism between the sintered metal and the interface to be bonded in a general sinter-bonding process, which serves as a comparison with the present invention, will be described with reference to FIGS. 4A and 4B. 4A and 4B are cross-sectional views showing diffusion at an interface during typical sinter bonding. 4A and 4B show the changes that occur when a member 14 having grain boundaries 24 is sinter-bonded to a sintered metal 13. The lower surface of the member 14 becomes the interface to be bonded to the sintered metal 13.

[0061] When the sintering temperature is reached by heating, as shown in Figure 4A, atoms 23 constituting the sintered metal 13 diffuse into the bonded interface through the contact points between the particles of the sintered metal 13 and the bonded interface of the component 14. Surface diffusion 31 is the fastest diffusion process, so it is dominant. However, some atoms 23 penetrate deep into the bonded interface through grain boundaries 24 included in the bonded interface. While volume diffusion also occurs slightly, it is slower than other modes and therefore not dominant. As a result, the sintered metal 13 spreads thinly across the bonded interface with the component 14, as shown in Figure 4B, while some penetrates deep into the component 14. This is believed to result in a bonded interface with a certain degree of strength. At the same time, atoms constituting the bonded interface also diffuse into the particles of the sintered metal 13, but this is not shown for simplicity.

[0062] In contrast to this, the bonding mechanism between the sintered metal and the interface to be bonded in the sinter bonding step of the semiconductor device of the present invention will be described with reference to FIGS. 5A and 5B. 5A and 5B are cross-sectional views showing diffusion at the interface during sinter-bonding in the semiconductor device of the present invention. 5A and 5B, similarly to Fig. 4A and 4B, changes are shown when a member 14 having grain boundaries 24 is sinter-bonded to a sintered metal 13. The lower surface of the member 14 becomes the interface to be bonded with the sintered metal 13.

[0063] As shown in Fig. 5A, the vicinity of grain boundary 24 of the interface to be joined of member 14 is processed to have irregularities 15 in the depth direction. The irregularities 15 shown in Fig. 5A are formed along grain boundary 24 so that they are deepest near grain boundary 24 of member 14. The member 14 in the state shown in FIG. 5A can be produced, for example, by selectively and deeply etching the vicinity of the grain boundary 24 at the interface to be joined of the member 14. When the bonded interface has such a structure, when the sintering temperature is reached by heating, the atoms 23 constituting the sintered metal 13 can penetrate to a certain extent in the depth direction of the member 14 through the surface of the irregularities 15 at the fastest speed of surface diffusion 31, as shown in Figure 5A. Furthermore, as shown in FIG. 5A, when the asperities 15 are deep near the grain boundaries 24, the asperities 15 are connected to the grain boundaries 24, allowing atoms 23 constituting the sintered metal 13 to penetrate deeper into the component 14 at the speed of grain boundary diffusion 32. This allows a considerable amount of sintered metal 13 to penetrate deeper into the component 14. This also means that the amount of contact between the sintered metal 13 and the component 14 to be joined increases, which in turn activates interdiffusion between the sintered metal 13 and the component 14 to be joined. As shown in FIG. 5B, the atoms constituting the joined interface (trapezoidal portion 25 surrounded by the dashed line in FIG. 5B) near the tip of the asperities 15 eventually disperse. This results in a sintered metal layer with a certain thickness, as indicated by the arrow in FIG. 5B.

[0064] The examples shown in Figures 5A and 5B show examples in which irregularities 15 are formed by deeply digging near the grain boundaries 24, but even if fine irregularities are simply provided rather than near the grain boundaries, the effect of penetration in the depth direction by surface diffusion can be obtained, and although the effect is somewhat inferior, the effect of improving reliability can be obtained compared to the case without processing.

[0065] The method for processing the recesses and projections is not limited to etching, and any method that can process the recesses and projections to the desired size, such as laser processing or ion milling, may be used.

[0066] The results of an actual prototype based on the above mechanism are shown below. The prototype this time was configured to bond sintered copper to a Ni film.

[0067] Here, the surface state of the Ni film after etching was observed using a scanning electron microscope (SEM). Figure 6 shows an SEM image of the surface state of the Ni film after etching. As shown in Figure 6, it can be seen that grooves with contour-like shapes are present on the surface, which are presumably the result of selective deep processing of, for example, grain boundaries by etching.

[0068] In addition, sinter-bonding was performed on a normal Ni film and the film shown in Figure 6, and the results of comparing the interface structures are shown in Figures 7A and 7B. Figure 7A is an SEM image of the cross section of a normal Ni film after sinter-bonding. Figure 7B is an SEM image of the cross section of a Ni film after sinter-bonding with a textured surface. 7A and 7B, it can be seen that the bonding state at the interface with the irregularities is such that the contact points between the sintered copper and Ni are denser, resulting in an interface structure that is less likely to peel and has excellent heat dissipation properties.

[0069] In the semiconductor module 20 of this embodiment, fine irregularities are formed at the interface to be bonded on either or both of the semiconductor chip 1 and the wiring layer 3a, which are sinter-bonded by the sintered metal layer 2. These fine irregularities promote atomic diffusion during sinter-bonding, activating interdiffusion between the sintered metal and the interface to be bonded, and resulting in a dense bonded contact point. This results in a bonding layer that is resistant to peeling and has good thermal conductivity.

[0070] Example 2 Next, a semiconductor module according to a second embodiment will be described. The semiconductor module of the second embodiment has the same configuration as the semiconductor module 20 of the first embodiment shown in FIG. Furthermore, in the semiconductor module of Example 2, as will be described in detail later, the fine irregularities formed at the bonded interface are configured to extend to an area outside the sinter-bonded area.

[0071] Before describing the configuration of the semiconductor module of Example 2, the wettability of the solvent used to apply the sintered metal to the interface to be joined in sinter-joining will be described.

[0072] Generally, a rough surface with irregularities has the property of enhancing wettability compared to a flat surface, which can be expressed by the Wenzel equation shown below in Equation (1).

[0073] cosθw=rcоsθ (1) (θw: contact angle on rough surface, θ: contact angle on flat surface, r: area ratio of rough surface to flat surface)

[0074] FIG. 8 is a cross-sectional view illustrating the phenomenon explained by Wenzel's equation. The top two figures in FIG. 8 illustrate the phenomenon in the case of a hydrophilic surface, and the bottom two figures in FIG. 8 illustrate the phenomenon in the case of a hydrophobic surface. In the top and bottom figures in FIG. 8, the left figure illustrates the case where the surface is flat, and the right figure illustrates the case where the surface is roughened by unevenness. Note that the right figure omits the illustration of the unevenness of the rough surface.

[0075] As shown in the upper part of Figure 8, on a hydrophilic surface with good wettability (θ<90°), the rough surface on the right has a smaller contact angle (θw<θ) than the flat surface on the left, making the rough surface more likely to wet. On the other hand, as shown in the bottom panel of Figure 8, on a hydrophobic surface with poor wettability (θ>90°), the contact angle is larger on the rough surface on the right than on the flat surface on the left (because θw>θ), making the rough surface less wettable.

[0076] Next, a conventional semiconductor module in which the interface to be joined by sinter bonding is a flat surface will be compared with a semiconductor module of Example 2 in which the interface to be joined by sinter bonding is a rough surface having irregularities. FIG. 9 is a cross-sectional view of a sintered-bonded portion of a conventional semiconductor module, in which the interface to be sintered is a flat surface. FIG. 10 is a cross-sectional view of a sinter-bonded portion of a semiconductor module according to Example 2, in which the interface to be sinter-bonded is a rough surface having irregularities. Figures 9 and 10 show, in order from the left to the right of the three figures, the changes in state when a first component (e.g., the wiring layer 3a shown in Figure 1) 43 and a second component (e.g., including the semiconductor chip 1 shown in Figure 1) are sintered and bonded using sintered metal powder 41. In Figures 9 and 10, the left diagram shows a state in which a paste in which sintered metal powder 41 is dispersed in a solvent 42 is supplied onto a first member 43, and a second member 44 is placed on top of the paste.

[0077] In the conventional semiconductor module shown in FIG. 9, the solvent 42 evaporates when heated during the sintering and bonding process, and as shown in the central diagram, the evaporated solvent 42 escapes through the gaps in the sintered metal powder 41. However, the solvent 42 can only escape through the gaps in the sintered metal powder 41, and the gaps in the sintered metal powder 41 are narrow. For this reason, if heating is performed quickly to shorten the time for the sinter-bonding process, the remaining solvent 42 that has not been completely escaped will gasify, increasing the internal pressure and causing the sintered metal powder 41 to be ejected, forming voids. When voids are formed in the sinter-bonded portion, the strength of the sinter-bond is weakened, and the reliability of the bond is reduced.

[0078] In the semiconductor module of Example 2 shown in FIG. 10, asperities 45 and 46 are formed at the joining interfaces of the first member 43 and the second member 44, respectively, which strengthens the wetting power of the solvent 42 and allows the solvent 42 to be actively discharged along the surfaces of the asperities 45 and 46, thereby preventing the solvent 42 from remaining.

[0079] 10, the area where the irregularities 45, 46 are provided is expanded outward from the area where the sinter-bonding paste is supplied and sinter-bonded. This makes it easier for the solvent 42 to be discharged than when the area where the irregularities 45, 46 are provided is the same size as the area where the sinter-bonding paste is supplied.

[0080] In the configuration of Example 2, it is more preferable that the solvent 42 to be dried and the surface having the irregularities 45, 46 be made of the easily wettable materials described in FIG. 8. This allows the solvent to be actively expelled from the bonding surface while remaining liquid along the surface, allowing the solvent to be expelled and dried more quickly than with a flat surface. This configuration not only promotes diffusion at the bonding interface, but also prevents unbonded joints and reduced bonding strength due to residual solvent, thereby further improving product reliability.

[0081] As described above, we have demonstrated a technology that can improve the quality of the bonded interface by providing unevenness on the bonded interface and promoting diffusion in the depth direction at the interface. A similar idea could be developed by utilizing crystal grain refinement technology to create a state with many grain boundaries at the interface, rather than creating minute irregularities on the surface. An embodiment in which this method is adopted will be described below as Example 3.

[0082] Example 3 A semiconductor module according to a third embodiment will be described with reference to FIGS. 11A and 11B. The semiconductor module of the third embodiment has the same configuration as the semiconductor module 20 of the first embodiment shown in FIG. 11A and 11B are cross-sectional views showing a method for manufacturing a semiconductor module according to the third embodiment.

[0083] 11A and 11B, in the semiconductor module of Example 3, the intervals between the grain boundaries 24 of the member 14 joined to the sintered metal 13 are shortened to increase the number of grain boundaries 24. In order to increase the number of grain boundaries 24 in this manner, a technique for refining crystal grains is used. In this example, any method may be used as the technique for refining crystal grains.

[0084] In this embodiment, by increasing the number of grain boundaries 24 in the member 14, as shown in FIG. 11B, the number of paths through which the sintered metal 13 can penetrate by grain boundary diffusion 32 in the depth direction of the member 14 increases, thereby achieving an improvement in the quality of the bonding interface. More specifically, if the size of the crystal grains after refinement is 10 μm or less and the bonded interface is made up of crystal grains of 10 μm or less, the effect of improving the quality of the bonded interface is enhanced.

[0085] It is also possible to combine a configuration in which the crystal grains at the bonded interface are refined, as in the semiconductor module of Example 3, with a configuration in which fine irregularities are formed at the bonded interface, as in the semiconductor modules of Examples 1 and 2.

[0086] The present invention is not limited to the configurations described in the above-mentioned embodiments and examples, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each example may be combined and applied. [Explanation of symbols]

[0087] 1 semiconductor chip, 1A first layer, 1B second layer, 2 sintered metal layer, 3 substrate, 3a wiring layer, 3b backside metal layer, 3c insulating substrate, 4 base plate, 5 sintered metal layer under substrate, 6 wire, 7 terminal, 8 case, 9 sealing resin, 10 lid, 11, 12, 15, 45, 46 unevenness, 13, 21, 22 sintered metal, 14 component, 20 semiconductor module, 23 atom, 24 grain boundary, 31 surface diffusion, 32 grain boundary diffusion, 33 volume diffusion, 41 sintered metal powder, 42 solvent, 43 first component, 44 second component

Claims

1. a first member made of metal; a second member including a semiconductor chip; the first member and the second member are joined by sintering, The interface between at least one of the first member and the second member is formed with irregularities, and the intervals between the irregularities are 10 μm or less. Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the interval between said projections and recesses is 0.1 [mu]m or less.

3. 2. The semiconductor device according to claim 1, wherein the depth of said irregularities is 0.1 [mu]m or more.

4. 2. The semiconductor device according to claim 1, wherein the opening diameter of the irregularities is 10 [mu]m or less.

5. 2. The semiconductor device according to claim 1, wherein the opening diameter of said irregularities is 0.01 [mu]m or less.

6. 2. The semiconductor device according to claim 1, wherein the irregularities are formed along the grain boundaries of the material.

7. 2. The semiconductor device according to claim 1, wherein the region where the projections and recesses are formed extends outward beyond the sinter-bonded region.

8. 2. The semiconductor device according to claim 1, wherein the sintered metal used to sinter-bond said first member and said second member is copper.

9. 2. The semiconductor device according to claim 1, wherein the interface to be joined, on which the irregularities are formed, is composed of crystal grains having a grain size of 10 [mu]m or less.

10. a first member made of metal; a second member including a semiconductor chip; the first member and the second member are joined by sintering, The interface to be joined of at least one of the first member and the second member is composed of crystal grains with a grain size of 10 μm or less. Semiconductor device.

11. A method for manufacturing a semiconductor device in which a first member made of metal and a second member including a semiconductor chip are bonded by sintering, the method comprising: forming projections and recesses at intervals of 10 μm or less on the interface to be joined of at least one of the first member and the second member; Thereafter, sintered metal is supplied to the interface to be joined where the irregularities have been formed, and sinter joining is carried out. A method for manufacturing a semiconductor device.

12. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the sinter-bonding is performed by applying a pressure of 0.01 MPa to 1.00 MPa or by bonding without applying pressure.

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