Nitride semiconductor device

Abstract

To provide a nitride semiconductor device capable of operating at a highspeed.SOLUTION: A nitride semiconductor device 1 includes: a substrate 10; a drift layer 12; a p-type block layer 14; a foundation layer 16; an electron transit layer 22 and an electron supply layer 24; a p-type semiconductor layer 26 that is provided above the electron supply layer 24 at a position overlapping a bottom surface 20a and a side surface 20b of a vertical conduction opening 20 in plan view; a gate electrode 32 that is provided above the electron supply layer 24 at a position overlapping the foundation layer 16 in plan view; a first source electrode 36 that is provided so as to cover a source opening 30 provided at a position away from the gate electrode 32 and that is electrically connected to the block layer 14; a drain electrode 38 that is provided below the substrate 10; and a second source electrode 34 that is provided above the p-type semiconductor layer 26 and that is electrically connected to the p-type semiconductor layer 26 and the first source electrode 36. A part of the lower surface of the p-type semiconductor layer 26 is located above the opening surface of the vertical conduction opening 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Nitride semiconductors, typified by GaN, are wide-gap semiconductors with a large band gap, characterized by a large breakdown field and a higher electron saturation drift velocity than compound semiconductors such as GaAs or Si semiconductors. For example, the band gaps of GaN and AlN are 3.4 eV and 6.2 eV, respectively, at room temperature. For this reason, research and development of power transistors using nitride semiconductors, which are advantageous for achieving higher output and / or higher voltage resistance, is currently being actively conducted.

[0003] In addition, in AlGaN / GaN heterostructures, spontaneous polarization and piezoelectric polarization on the (0001) plane generate a high concentration of two-dimensional electron gas (2DEG) at the heterointerface, and even in the undoped state, the density is 1×10 13 cm -2 The sheet carrier concentration can be obtained as high as 1000 ppm or more.

[0004] Patent Documents 1 and 2 and Non-Patent Document 1 disclose vertical FETs (Field Effect Transistors) formed using GaN-based semiconductor materials. In the vertical FETs disclosed in Patent Documents 1 and 2, a channel made of two-dimensional electron gas generated at an AlGaN / GaN heterointerface is opened and closed by a gate voltage, thereby achieving transistor operation. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6511645 [Patent Document 2] Patent No. 6755892 [Non-patent literature]

[0006] [Non-Patent Document 1] Zhu et al., “Vertical GaN Power Transistor With Intrinsic Reverse Conduction and Low Gate Charge for High-Performance Power Conversion”, IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 7, No. 3, September 2019 Summary of the Invention [Problem to be solved by the invention]

[0007] Conventional nitride semiconductor devices use a V-shaped gate structure to achieve high breakdown voltage. This gate structure increases the opposing area between the gate and drain, resulting in increased gate-drain capacitance. As a result, there is room for improvement in increasing the operating speed.

[0008] Therefore, the present disclosure provides a nitride semiconductor device capable of high-speed operation. [Means for solving the problem]

[0009] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer, a second nitride semiconductor layer provided above the first p-type nitride semiconductor layer, an electron transit layer and an electron supply layer provided in this order from below so as to cover a side surface and a bottom surface of a first opening that penetrates the second nitride semiconductor layer and the first p-type nitride semiconductor layer to reach the first nitride semiconductor layer, and an upper surface of the second nitride semiconductor layer, a second p-type nitride semiconductor layer provided above the electron supply layer at a position that overlaps the bottom surface and side surface of the first opening in a plan view of the substrate, and the electron supply layer. a gate electrode provided above the second p-type nitride semiconductor layer at a position overlapping the second nitride semiconductor layer in a planar view of the substrate; a first source electrode provided at a position away from the gate electrode in a planar view of the substrate so as to cover a second opening that penetrates the electron supply layer and the electron transit layer and reaches the first p-type nitride semiconductor layer, the first source electrode being electrically connected to the first p-type nitride semiconductor layer; a drain electrode provided below the substrate; and a second source electrode provided above the second p-type nitride semiconductor layer and electrically connected to the second p-type nitride semiconductor layer and the first source electrode, wherein a portion of the lower surface of the second p-type nitride semiconductor layer is located above the opening surface of the first opening. [Effects of the Invention]

[0010] According to the present disclosure, a nitride semiconductor device capable of high-speed operation can be provided. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to the first embodiment. [Figure 2A] FIG. 2A is a cross-sectional view illustrating a parasitic capacitance between the gate and the drain of a nitride semiconductor device according to a comparative example. [Figure 2B]FIG. 2B is a cross-sectional view illustrating the gate-drain parasitic capacitance of the nitride semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a first modification of the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a nitride semiconductor device according to the second embodiment. [Figure 5] FIG. 5 is a cross-sectional view of a nitride semiconductor device according to the third embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a nitride semiconductor device according to the fourth embodiment. [Figure 7] FIG. 7 is a cross-sectional view of a nitride semiconductor device according to the fifth embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a nitride semiconductor device according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] (Findings that formed the basis of this disclosure) The present inventors have found that the conventional nitride semiconductor devices described in the "Background Art" section have the following problems.

[0013] Vertical transistors are advantageous over lateral transistors in terms of high voltage and large current operation, but are disadvantageous in terms of high speed operation, as will be explained below.

[0014] A vertical transistor has a structure in which a substrate is disposed between the source and drain. Therefore, in a vertical transistor, the drain current flowing between the source and drain mainly flows in a direction perpendicular to the main surface of the substrate. In contrast, a lateral transistor has a structure in which the source and drain are disposed side by side in a direction parallel to the main surface of the substrate. Therefore, in a lateral transistor, the drain current mainly flows in a direction parallel to the main surface of the substrate.

[0015] [Table 1]

[0016] Table 1 shows a comparison of the gate-drain parasitic capacitance Cgd between lateral and vertical transistors. When compared at the same device size with the same on-resistance Ron, the gate-drain parasitic capacitance Cgd of vertical transistors is about two orders of magnitude larger than that of lateral transistors. This is due to the fact that the parallel plate capacitance between the gate and drain is large due to the structure of vertical transistors, and it is also difficult to provide a field plate to terminate the electric field lines from the drain to the source. If the parasitic capacitance Cgd is large, the rise characteristics of the drain current deteriorate, making it difficult for the transistor to operate at high speed.

[0017] In Patent Document 1, a p-type GaN layer and a gate electrode are provided along the inside of a gate opening. The junction between the slope and bottom of the gate opening is a region where an electric field is likely to concentrate. The p-type GaN layer is provided in this region, which alleviates the electric field. This allows the device to withstand a high voltage. However, the area between the p-type GaN layer and the gate electrode increases due to the electric field alleviation, making it impossible to reduce the parasitic capacitance Cgd.

[0018] Patent Document 2 discloses a structure in which the gate electrode is disposed above the outer edge of the gate opening, rather than inside the gate opening. Patent Document 2 shows that this configuration can lower the gate drive voltage and reduce drive loss. However, with this structure, all electric field lines from the drain to the gate are directed toward the gate, so this does not lead to a reduction in parasitic capacitance Cgd.

[0019] Furthermore, Non-Patent Document 1 describes the calculation results of reducing gate capacitance by providing a Schottky electrode connected to the source electrode on the regrown AlGaN layer in a vertical transistor. The Schottky junction connected to the source acts as a Schottky diode in reverse conduction mode. It has been shown that the threshold value of this diode can be reduced, thereby reducing conduction loss. However, when the Schottky electrode on the regrown AlGaN layer is used as a field plate, the reverse characteristics of the Schottky characteristics have a larger leakage current and a lower breakdown voltage than the reverse characteristics of a pn diode. This leads to issues such as reduced transistor reliability.

[0020] In view of the above problems, the present disclosure has an object to provide a nitride semiconductor device capable of high-speed operation by reducing the parasitic capacitance Cgd while suppressing a decrease in reliability.

[0021] To achieve the above object, each aspect of the nitride semiconductor device of the present disclosure has the following configuration.

[0022] A nitride semiconductor device according to a first aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer, a second nitride semiconductor layer provided above the first p-type nitride semiconductor layer, an electron transit layer and an electron supply layer provided in this order from below so as to cover a side surface and a bottom surface of a first opening that penetrates the second nitride semiconductor layer and the first p-type nitride semiconductor layer to reach the first nitride semiconductor layer, and an upper surface of the second nitride semiconductor layer, a second p-type nitride semiconductor layer provided above the electron supply layer at a position that overlaps the bottom surface and side surface of the first opening in a plan view of the substrate, and a gate electrode provided above the supply layer at a position overlapping the second nitride semiconductor layer in a planar view of the substrate; a first source electrode provided at a position away from the gate electrode in a planar view of the substrate, the first source electrode penetrating the electron supply layer and the electron transit layer and covering a second opening reaching the first p-type nitride semiconductor layer, the first source electrode being electrically connected to the first p-type nitride semiconductor layer; a drain electrode provided below the substrate; and a second source electrode provided above the second p-type nitride semiconductor layer and electrically connected to the second p-type nitride semiconductor layer and the first source electrode, wherein a portion of a lower surface of the second p-type nitride semiconductor layer is located above an opening surface of the first opening.

[0023] In the nitride semiconductor device according to this embodiment, both the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer are electrically connected to the first source electrode. Therefore, each of the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer is fixed to the potential applied to the first source electrode (i.e., the source potential). This allows the electric field lines extending from the drain electrode to terminate at the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer, thereby reducing the gate-drain parasitic capacitance Cgd. Therefore, according to this embodiment, a nitride semiconductor device capable of high-speed operation can be realized.

[0024] Furthermore, in the nitride semiconductor device according to this embodiment, the reverse characteristics of a pn diode due to the two-dimensional electron gas (n) generated at the interfaces between the second p-type nitride semiconductor layer (p) and the electron supply layer and electron transit layer can be utilized, thereby suppressing an increase in leakage current and a decrease in breakdown voltage, thereby suppressing a decrease in the reliability of the nitride semiconductor device.

[0025] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the side surface of the first opening is inclined with respect to the bottom surface of the first opening, the upper surface of the electron supply layer includes a flat portion along the bottom surface of the first opening, an inclined portion along the side surface of the first opening, and an outer edge portion extending from an upper end of the inclined portion in a direction away from the flat portion, and the lower surface of the second p-type nitride semiconductor layer continuously covers at least a portion of the flat portion, the inclined portion, and a portion of the outer edge portion.

[0026] This allows the second p-type nitride semiconductor layer to cover a wide, continuous area of ​​the top surface of the electron supply layer, from the flat portion to the outer edge. The second p-type nitride semiconductor layer can be arranged up to the vicinity of the gate electrode provided above the outer edge, which enhances the termination effect of the electric field lines and thus enhances the effect of reducing the parasitic capacitance Cgd.

[0027] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the first or second aspect, wherein, in a plan view of the substrate, the second p-type nitride semiconductor layer overlaps the first p-type nitride semiconductor layer.

[0028] As a result, the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer overlap each other in a plan view of the substrate, making it possible to make the gate electrode invisible from the drain electrode side, thereby further enhancing the effect of reducing the parasitic capacitance Cgd.

[0029] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to third aspects, further comprising a third p-type nitride semiconductor layer provided between the gate electrode and the electron supply layer and spaced apart from the second p-type nitride semiconductor layer.

[0030] This reduces the carrier concentration directly below the gate electrode and shifts the threshold voltage of the transistor to the positive side, making it possible to easily realize the nitride semiconductor device according to this embodiment as a normally-off FET.

[0031] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fourth aspects, further comprising an insulating film provided between the gate electrode and the electron supply layer.

[0032] This allows the nitride semiconductor device according to this embodiment to be realized as a MISFET (Metal-Insulator-Semiconductor FET). Since it is not necessary to provide a semiconductor layer between the gate electrode and the electron supply layer, the number of epitaxial growth steps can be reduced, simplifying the manufacturing process and reducing costs. The simplification of the manufacturing process leads to improved yields and improved reliability of the manufactured nitride semiconductor devices.

[0033] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fifth aspects, wherein the electron supply layer has an impurity region provided at a position overlapping the gate electrode in a plan view of the substrate.

[0034] This reduces the carrier concentration directly below the gate electrode, shifting the threshold voltage of the transistor to the positive side. Therefore, the nitride semiconductor device according to this embodiment can be easily realized as a normally-off FET. The impurity region can be locally formed by, for example, ion implantation. The number of epitaxial growth steps can be reduced, simplifying the manufacturing process and reducing costs.

[0035] A nitride semiconductor device according to a seventh aspect of the present disclosure is the nitride semiconductor device according to any one of the first to sixth aspects, wherein the electron supply layer has a recess at a position that overlaps the gate electrode in a plan view of the substrate.

[0036] This reduces the carrier concentration directly below the gate electrode, shifting the threshold voltage of the transistor to the positive side. Therefore, the nitride semiconductor device according to this embodiment can be easily realized as a normally-off FET. The recessed portion can be locally formed by, for example, etching. The number of epitaxial growth steps can be reduced, simplifying the manufacturing process and reducing costs.

[0037] A nitride semiconductor device according to an eighth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to seventh aspects, wherein the distance between the second p-type nitride semiconductor layer and the drain electrode is shorter than the distance between the first p-type nitride semiconductor layer and the drain electrode.

[0038] This makes it easier for the electric field caused by the voltage applied between the source and drain to concentrate on the underside of the second p-type nitride semiconductor layer than on the first p-type nitride semiconductor layer. If the side surface of the first opening is inclined, the side surface of the first p-type nitride semiconductor layer will have an acute angle and will be vulnerable to electric field concentration. According to this aspect, the electric field is more likely to concentrate on the underside of the second p-type nitride semiconductor layer, thereby increasing the breakdown voltage of the nitride semiconductor device.

[0039] A nitride semiconductor device according to a ninth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to eighth aspects, wherein the second p-type nitride semiconductor layer is provided with a third opening that penetrates the second p-type nitride semiconductor layer and reaches the electron supply layer, and the second source electrode is in contact with the electron supply layer at a bottom surface of the third opening.

[0040] As a result, a JBS (Junction Barrier Schottky) structure that combines a pn diode and a Schottky diode is formed near the third opening. The JBS structure has a lower threshold voltage than a pn diode alone. Therefore, when the nitride semiconductor device operates in reverse conduction mode, the threshold voltage is lowered, thereby reducing the driving voltage. This makes it possible to reduce conduction loss in reverse conduction mode.

[0041] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0042] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0043] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0044] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0045] In this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may also be referred to as the "lateral direction."

[0046] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided is considered to be "upper" or "upper side", and the side of the substrate on which the drain electrode is provided is considered to be "lower" or "lower side".

[0047] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0048] In this specification, unless otherwise specified, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0049] In addition, in this specification, "A and B overlap in a plan view" means that at least a part of A overlaps with at least a part of B. In other words, this includes cases where only a part of A overlaps with only a part of B, where all of A overlaps with B, where all of B overlaps with A, and where A and B completely overlap with each other.

[0050] Also, in this specification, ordinal numbers such as "first" and "second" do not mean the number or order of components, unless otherwise specified, and are used for the purpose of avoiding confusion and distinguishing between components of the same kind.

[0051] Also, in this specification, AlGaN refers to ternary mixed crystal Al x Ga 1-x N (0 < x < 1). Hereinafter, a multi-component mixed crystal is abbreviated with the arrangement of the respective component symbols, for example, AlInN, GaInN, etc. For example, Al x Ga 1-x-y In y N (0 < x < 1, 0 < y < 1, and 0 < x + y < 1) is abbreviated as AlGaInN.

[0052] (Embodiment 1) [Configuration] First, the configuration of the nitride semiconductor device according to Embodiment 1 will be described with reference to FIG. 1.

[0053] FIG. 1 is a cross-sectional view of a nitride semiconductor device 1 according to the present embodiment. In FIG. 1, each component such as a semiconductor layer and an electrode is shaded to represent a cross-section.

[0054] As shown in FIG. 1, the nitride semiconductor device 1 according to the present embodiment is a so-called vertical field effect transistor (FET). Specifically, in the nitride semiconductor device 1, current mainly flows in a direction perpendicular to the main surface of the substrate 10 between the drain electrode 38 and the first source electrode 36.

[0055] The nitride semiconductor device 1 is a device having a stacked structure of nitride semiconductor layers mainly containing nitride semiconductors such as GaN and AlGaN. Note that "A mainly contains B" means that the substance with the largest content among the substances contained in A is B. For example, the content of B in A is 50% or more.

[0056] The nitride semiconductor device 1 according to this embodiment is, for example, a normally-on FET. In the nitride semiconductor device 1, for example, the first source electrode 36 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 38. The potential applied to the drain electrode 38 is, for example, not limited to, 100 V or more and 1200 V or less. When the nitride semiconductor device 1 is in an off state, a negative potential (for example, −5 V) is applied to the gate electrode 32. When the nitride semiconductor device 1 is in an on state, 0 V or a positive potential (for example, +5 V) is applied to the gate electrode 32. Note that the nitride semiconductor device 1 may be a normally-off FET.

[0057] 1, the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a block layer 14, an underlayer 16, a vertical conduction opening 20, an electron transit layer 22, an electron supply layer 24, a p-type semiconductor layer 26, a source opening 30, a gate electrode 32, a second source electrode 34, a first source electrode 36, and a drain electrode 38. A two-dimensional electron gas (2DEG) 25 that functions as a channel is generated at the interface between the electron transit layer 22 and the electron supply layer 24.

[0058] Each of the components of the nitride semiconductor device 1 will be described in detail below.

[0059] The substrate 10 is made of a nitride semiconductor and has a rectangular shape in plan view, for example, but is not limited to this.

[0060] The substrate 10 has a thickness of 300 μm and a carrier concentration of 1×10 18 cm -3 n + The substrate is made of n-type GaN. Note that n-type and p-type refer to the conductivity type of the semiconductor. + The n-type indicates a state in which a semiconductor is heavily doped with n-type dopants. - The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopants, a so-called light doping.+ type and n - Both types are examples of n-type, and may be referred to as n-type without distinction. + type and p - The same is true for types.

[0061] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0062] The drift layer 12 is an example of a first nitride semiconductor layer provided above the substrate 10. The drift layer 12 is, for example, a n-type nitride semiconductor layer having a thickness of 8 μm. - The drift layer 12 is a film made of GaN. The donor concentration of the drift layer 12 is, for example, 1×10 15 cm -3 More than 1×10 17 cm -3 As an example, 16 cm -3 The carbon concentration (C concentration) of the drift layer 12 is, for example, 1×10 15 cm -3 Over 2×10 17 cm -3 The following is the result.

[0063] The drift layer 12 is provided, for example, in contact with the upper surface (main surface) of the substrate 10. The drift layer 12 is formed on the main surface of the substrate 10 by crystal growth, for example, by a metal organic vapor phase epitaxy (MOVPE) method, a hydride vapor phase epitaxy (HVPE) method, or the like.

[0064] The block layer 14 is an example of a first p-type nitride semiconductor layer provided above the drift layer 12. The block layer 14 has a thickness of 400 nm and a carrier concentration of 1×10 17 cm -3The blocking layer 14 is a film made of p-type GaN. The blocking layer 14 is provided in contact with the upper surface of the drift layer 12. The blocking layer 14 is formed on the drift layer 12 by crystal growth using, for example, an MOVPE method, an HVPE method, or the like.

[0065] Although the block layer 14 is formed by crystal growth, it may be formed by, for example, implanting magnesium (Mg) into the formed i-GaN. Furthermore, the block layer 14 may be an insulating layer obtained by implanting iron (Fe) or boron (B) instead of a p-type nitride semiconductor layer.

[0066] The block layer 14 suppresses leakage current between the first source electrode 36 and the drain electrode 38. For example, when a reverse voltage is applied to the pn junction formed between the block layer 14 and the drift layer 12, specifically when the drain electrode 38 has a higher potential than the first source electrode 36, a depletion layer extends to the drift layer 12. This enables the nitride semiconductor device 1 to have a high breakdown voltage. In this embodiment, the drain electrode 38 has a higher potential than the first source electrode 36 in both the off state and the on state, except in the case of reverse conduction. This allows the nitride semiconductor device 1 to have a high breakdown voltage.

[0067] 1, in this embodiment, the block layer 14 is in contact with the first source electrode 36. Therefore, the block layer 14 is fixed to the source potential applied to the first source electrode 36. As a result, the block layer 14 can shield the electric field lines extending from the drain electrode 38, which will be described in detail later, and can contribute to reducing the parasitic capacitance Cgd between the gate and the drain.

[0068] The underlayer 16 is an example of a second nitride semiconductor layer provided above the block layer. The underlayer 16 is a high-resistance layer having a higher resistance than the block layer 14. The underlayer 16 is, for example, a 200 nm-thick film made of undoped GaN (i-GaN). The underlayer 16 is provided in contact with the block layer 14. The underlayer 16 is formed on the block layer 14 by crystal growth using, for example, MOVPE or HVPE.

[0069] The underlayer 16 is assumed to be an undoped semiconductor layer, but may be an insulating or semi-insulating layer. Here, "undoped" means that it is not doped with a dopant such as Si or Mg that changes the polarity of GaN to n-type or p-type. In this embodiment, the underlayer 16 may be doped with carbon (C). For example, the carbon concentration of the underlayer 16 is higher than the carbon concentration of the block layer 14.

[0070] For example, the carbon concentration of the underlayer 16 is 3×10 17 cm -3 That's all, but 1 x 10 18 cm -3 In this case, the concentration of silicon (Si) or oxygen (O) serving as n-type impurities is lower than the carbon concentration. For example, the silicon concentration or oxygen concentration of the underlayer 16 is 5×10 16 cm -3 Below, 2 x 10 16 cm -3 The following may also be used: As for the type of ions implanted into the underlayer 16 and the block layer 14, ion species other than those mentioned above can also be used to obtain the same effect as long as they are capable of increasing the resistance of the semiconductor layer.

[0071] Furthermore, a layer for suppressing diffusion of p-type impurities such as Mg from the block layer 14 may be provided on the upper surface of the base layer 16. For example, a 20 nm thick AlGaN layer may be provided on the block layer 14.

[0072] The vertical conductive opening 20 is an example of a first opening that penetrates the underlayer 16 and the block layer 14 and reaches the drift layer 12. A bottom surface 20a of the vertical conductive opening 20 is part of the upper surface of the drift layer 12. As shown in FIG. 1 , the bottom surface 20a is located below the lower surface of the block layer 14. The lower surface of the block layer 14 corresponds to the interface between the block layer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the major surface of the substrate 10. When the nitride semiconductor device 1 is on, a drain current flows between the drain electrode 38 and the first source electrode 36 through the bottom surface 20a of the vertical conductive opening 20.

[0073] In this embodiment, the vertical conductive opening 20 is formed so that the opening area increases as it becomes farther from the substrate 10. Specifically, the side surface 20b of the vertical conductive opening 20 is inclined obliquely. The opening surface of the vertical conductive opening 20 is larger than the bottom surface 20a. As shown in FIG. 1 , the cross-sectional shape of the vertical conductive opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0074] The opening surface of the vertical conductive opening 20 is an example of the opening surface of the first opening. The outline of the opening surface of the vertical conductive opening 20 corresponds to the upper end of the side surface 20b. In the cross section shown in FIG. 1, the line segment connecting the upper end of the left side surface 20b and the upper end of the right side surface 20b corresponds to the opening surface. The upper end of the side surface 20b is the intersection of the upper surface of the base layer 16 and the side surface of the base layer 16. The opening surface of the vertical conductive opening 20 may be considered to be at the same height as the upper surface of the base layer 16. The "height" is expressed as the distance from the main surface of the substrate 10.

[0075] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 90°, but may be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, thereby improving the film quality of the electron transit layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the more effectively the vertical conduction opening 20 is prevented from becoming too large, thereby enabling the nitride semiconductor device 1 to be made smaller.

[0076] Vertical conduction opening 20 is formed by successively depositing drift layer 12, block layer 14, and base layer 16 in this order on the main surface of substrate 10, and then removing a portion of base layer 16 and block layer 14 to partially expose drift layer 12. At this time, by removing a surface portion of drift layer 12 by a predetermined thickness (e.g., 300 nm), bottom surface 20a of vertical conduction opening 20 is formed below the lower surface of block layer 14.

[0077] As a method for removing the underlayer 16 and the block layer 14, dry etching such as inductively coupled plasma etching (ICP) is often used, and a chlorine-based gas is used as the process gas.

[0078] The electron transit layer 22 is an example of a first regrown layer provided to cover the upper surface of the underlayer 16 and the side surface 20b and bottom surface 20a of the vertical conductive opening 20. Specifically, a portion of the electron transit layer 22 is provided along the bottom surface 20a and side surface 20b of the vertical conductive opening 20, and another portion of the electron transit layer 22 is provided on the upper surface of the underlayer 16. The electron transit layer 22 is, for example, a 150 nm-thick film made of undoped GaN. Note that although the electron transit layer 22 is assumed to be undoped, it may be partially made n-type by, for example, doping with Si.

[0079] The electron transit layer 22 is in contact with the drift layer 12 at the bottom surface 20a and the side surface 20b of the vertical conducting opening 20. The electron transit layer 22 is in contact with the block layer 14 and the foundation layer 16 at the side surface 20b of the vertical conducting opening 20. Furthermore, the electron transit layer 22 is in contact with the top surface of the foundation layer 16.

[0080] The electron transit layer 22 has a channel region. Specifically, a two-dimensional electron gas 25, which serves as a channel, is generated near the interface between the electron transit layer 22 and the electron supply layer 24. In FIG. 1 , the two-dimensional electron gas 25 is schematically illustrated by a dashed line. The two-dimensional electron gas 25 bends along the interface between the electron transit layer 22 and the electron supply layer 24, i.e., along the inner surface of the vertical conduction opening 20.

[0081] 1 shows the nitride semiconductor device 1 in an off state, i.e., a state in which a gate voltage less than the threshold voltage is applied to the gate electrode 32. In this case, the figure shows a state in which the two-dimensional electron gas 25 disappears and becomes depleted directly below the gate electrode 32. When the nitride semiconductor device 1 is in an on state, i.e., a state in which a voltage equal to or greater than the threshold voltage is applied to the gate electrode 32, the potential decreases directly below the gate electrode 32, generating the two-dimensional electron gas 25. This establishes electrical conduction between the first source electrode 36 and the drain electrode 38.

[0082] Although not shown in Figure 1, an AlN layer with a thickness of about 1 nm is provided as a second regrown layer between the electron transit layer 22 and the electron supply layer 24. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. However, the AlN layer is not necessarily required.

[0083] The electron supply layer 24 is an example of a third regrown layer provided to cover the upper surface of the base layer 16 and the side surface 20b and bottom surface 20a of the vertical conductive opening 20. The electron transit layer 22 and the electron supply layer 24 are provided in this order from the substrate 10 side. The electron supply layer 24 is, for example, a 20 nm-thick film made of undoped AlGaN.

[0084] The electron supply layer 24 is formed with a substantially uniform thickness in a shape that conforms to the upper surface of the electron transit layer 22. As shown in Fig. 1, the upper surface of the electron supply layer 24 includes a flat portion 24a, an inclined portion 24b, and an outer edge portion 24c.

[0085] The flat portion 24a is a portion along the bottom surface 20a of the vertical conductive opening 20. The flat portion 24a is, for example, a plane parallel to the bottom surface 20a. The flat portion 24a is the lowest portion of the upper surface of the electron supply layer 24.

[0086] The inclined portion 24b is a portion along the side surface 20b of the vertical conductive opening 20. The inclined portion 24b is, for example, an inclined surface parallel to the side surface 20b of the vertical conductive opening 20. The inclined portions 24b are provided on both sides of the flat portion 24a.

[0087] The outer edge 24c is a portion extending from the upper end of the inclined portion 24b in a direction away from the flat portion 24a. Here, the "direction away from the flat portion 24a" refers to a direction from the bottom surface 20a of the vertical conductive opening 20 toward the first source electrode 36 in a plan view of the substrate 10. The "direction away from the flat portion 24a" corresponds to a direction toward the outside of the vertical conductive opening 20 in a plane parallel to the main surface of the substrate 10. The outer edge 24c is a plane parallel to the main surface of the substrate 10. The outer edge 24c is the uppermost portion of the top surface of the electron supply layer 24.

[0088] The flat portion 24a, the inclined portion 24b, and the outer edge portion 24c may each be a curved surface. The flat portion 24a and the inclined portion 24b may be connected by a smooth curve. The outer edge portion 24c and the inclined portion 24b may be connected by a smooth curve.

[0089] The electron supply layer 24 has a larger band gap than the electron transit layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 24 and the electron transit layer 22. The electron supply layer 24 supplies electrons to a channel region (two-dimensional electron gas 25) formed in the electron transit layer 22.

[0090] The p-type semiconductor layer 26 is an example of a second p-type nitride semiconductor layer and is provided above the electron supply layer 24 at a position overlapping the bottom surface 20a and the side surface 20b of the vertical conductive opening 20 in a plan view of the substrate 10. A portion of the lower surface of the p-type semiconductor layer 26 is located above the opening surface of the vertical conductive opening 20. Specifically, the lower surface of the p-type semiconductor layer 26 continuously covers at least a portion of the flat portion 24a, the inclined portion 24b, and a portion of the outer edge portion 24c of the upper surface of the electron supply layer 24. More specifically, in the cross section shown in FIG. 1 , the lower surface of the p-type semiconductor layer 26 is provided so as to contact and cover the entire left-side inclined portion 24b, the flat portion 24a, and the right-side inclined portion 24b from one (e.g., left) outer edge portion 24c to the other (e.g., right) outer edge portion 24c.

[0091] The p-type semiconductor layer 26 has a thickness of 200 nm and a carrier concentration of 1×10 17 cm -3 p-type Al x Ga 1-x The film is made of N (0≦x≦1). Note that the thickness and carrier concentration are merely examples and can be changed as appropriate.

[0092] The p-type semiconductor layer 26 is provided at a position separated from the gate electrode 32. Specifically, the p-type semiconductor layer 26 is electrically isolated from the gate electrode 32. In this embodiment, the p-type semiconductor layer 26 overlaps the block layer 14 in a planar view of the substrate 10. Specifically, an end of the p-type semiconductor layer 26 on the gate electrode 32 side (hereinafter referred to as the gate-side end) overlaps the block layer 14 in a planar view. The gate-side end of the p-type semiconductor layer 26 may overlap the upper surface of the block layer 14 in a planar view. Alternatively, the gate-side end of the p-type semiconductor layer 26 may overlap the inclined side surface of the block layer 14 (i.e., the side surface 20b of the vertical conductive opening 20) in a planar view. Furthermore, the gate-side end of the p-type semiconductor layer 26 may overlap the upper surface of the base layer 16 in a planar view. That is, the gate side end of the p-type semiconductor layer 26 may be located in a position closer to the gate electrode 32 and the first source electrode 36 in plan view than the upper end of the side surface 20b of the vertical conductive opening 20. Simply put, the gate side end of the p-type semiconductor layer 26 may be located outside the vertical conductive opening 20 in plan view. The closer the gate side end of the p-type semiconductor layer 26 is to the gate electrode 32, that is, the larger the p-type semiconductor layer 26 is, the more effective it is at shielding electric field lines, which will be described later, and which can contribute to reducing the parasitic capacitance Cgd.

[0093] Instead of the p-type semiconductor layer 26, an insulating layer having a single layer structure or a multi-layer structure including a film selected from the group consisting of SiN, SiO2, HfO2, Al2O3, ZrO2, AlN, HfON, and ZrON may be provided.

[0094] The electron transit layer 22, the electron supply layer 24, and the p-type semiconductor layer 26 are formed by forming the vertical conduction opening 20, followed by sequentially depositing nitride semiconductor films using a crystal regrowth process and patterning them into a predetermined shape. Specifically, an undoped GaN film forming the electron transit layer 22, an undoped AlGaN film forming the electron supply layer 24, and a p-type AlGaN film forming the p-type semiconductor layer 26 are sequentially deposited by MOVPE, HVPE, or the like. After deposition, portions of the p-type AlGaN film are etched away until the undoped AlGaN film is exposed, thereby forming the p-type semiconductor layer 26. Furthermore, portions of the undoped AlGaN film and the undoped GaN film, as well as portions of the underlayer 16, are sequentially etched away until the block layer 14 is exposed. This forms a source opening 30 reaching the block layer 14, resulting in the electron supply layer 24 and the electron transit layer 22 patterned into a predetermined shape.

[0095] The source opening 30 is an example of a second opening that penetrates the electron supply layer 24 and the electron transit layer 22 at a position away from the gate electrode 32 in a plan view of the substrate 10, and reaches the block layer 14. In the present embodiment, the source opening 30 is provided at a position away from both the vertical conduction opening 20 and the gate electrode 32 in a plan view of the substrate 10.

[0096] The bottom surface 30a of the source opening 30 is part of the upper surface of the block layer 14. In the example shown in FIG. 1, the bottom surface 30a is flush with the lower surface of the underlayer 16, but this is not limiting. The bottom surface 30a may be located lower than the lower surface of the underlayer 16. The lower surface of the underlayer 16 corresponds to the interface between the underlayer 16 and the block layer 14. The bottom surface 30a is parallel to the main surface of the substrate 10, for example.

[0097] 1, the source opening 30 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the side surface 30b of the source opening 30 is perpendicular to the bottom surface 30a. In other words, the cross-sectional shape of the source opening 30 is rectangular.

[0098] Alternatively, the source opening 30 may be formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 30b of the source opening 30 may be inclined obliquely. For example, the cross-sectional shape of the source opening 30 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side surface 30b relative to the bottom surface 30a may be, for example, in the range of 30° to 60°. The oblique inclination of the side surface 30b increases the contact area between the first source electrode 36 and the electron transit layer 22 (two-dimensional electron gas 25), making it easier to achieve ohmic contact. The two-dimensional electron gas 25 is exposed at the side surface 30b of the source opening 30 and is connected to the first source electrode 36 at the exposed portion.

[0099] The provision of the source opening 30 reduces the ohmic contact resistance between the two-dimensional electron gas 25 functioning as a channel and the first source electrode 36. Furthermore, the blocking layer 14 and the first source electrode 36 can be electrically connected, which stabilizes the potential of the blocking layer 14 and provides the effect of improving the breakdown voltage.

[0100] The gate electrode 32 is provided above the electron supply layer 24 at a position overlapping the base layer 16 in a plan view of the substrate 10. Specifically, the gate electrode 32 is provided in contact with the upper surface of the electron supply layer 24. More specifically, the gate electrode 32 is provided in contact with the outer edge portion 24c of the upper surface of the electron supply layer 24.

[0101] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 can be made of a material that forms a Schottky contact with the n-type GaN layer. For example, palladium (Pd), nickel (Ni)-based materials, tungsten silicide (WSi), gold (Au), etc. can be used. The gate electrode 32 is formed by forming a conductive film by sputtering, vapor deposition, etc., after the source opening 30 is formed, or after the first source electrode 36 and the second source electrode 34 are formed, and then patterning the formed conductive film.

[0102] The second source electrode 34 is provided above the p-type semiconductor layer 26 so as to cover the vertical conductive opening 20 in plan view. Specifically, the second source electrode 34 is provided in contact with the upper surface of the p-type semiconductor layer 26.

[0103] Similar to the p-type semiconductor layer 26, the second source electrode 34 is provided above the electron supply layer 24 at a position overlapping the bottom surface 20a and the side surface 20b of the vertical conductive opening 20 in a plan view of the substrate 10. A portion of the lower surface of the second source electrode 34 is located above the opening surface of the vertical conductive opening 20. In a plan view of the substrate 10, the second source electrode 34 overlaps the flat portion 24a, the inclined portion 24b, and the outer edge portion 24c of the upper surface of the electron supply layer 24. In other words, the gate-side end of the second source electrode 34 overlaps the outer edge portion 24c of the upper surface of the electron supply layer 24 in a plan view.

[0104] In addition, in a plan view, the gate side end of the second source electrode 34 may overlap the block layer 14. In a plan view, the gate side end of the second source electrode 34 may overlap the upper surface of the block layer 14. Alternatively, in a plan view, the gate side end of the p-type semiconductor layer 26 may overlap the inclined side surface of the block layer 14 (i.e., the side surface 20b of the vertical conductive opening 20). In addition, the gate side end of the second source electrode 34 may overlap the upper surface of the base layer 16 in a plan view. In other words, in a plan view, the gate side end of the second source electrode 34 may be located closer to the gate electrode 32 and the first source electrode 36 than the upper end of the side surface 20b of the vertical conductive opening 20. Simply put, in a plan view, the gate side end of the second source electrode 34 may be located outside the vertical conductive opening 20. The closer the gate side end of the second source electrode 34 is to the gate electrode 32, that is, the larger the second source electrode 34 is, the greater the shielding effect of the electric field lines described below, which can contribute to reducing the parasitic capacitance Cgd.

[0105] The second source electrode 34 is electrically connected to the first source electrode 36. That is, the second source electrode 34 is an electrode to which the same source potential as that of the first source electrode 36 is supplied. The second source electrode 34 is not directly connected to the two-dimensional electron gas 25. A drain current from the drain electrode 38 flows to the first source electrode 36 via the two-dimensional electron gas 25. The second source electrode 34 is electrically connected to the p-type semiconductor layer 26. Therefore, a source potential is applied to the p-type semiconductor layer 26, similar to the block layer 14.

[0106] The second source electrode 34 is formed using a conductive material such as a metal. The second source electrode 34 can be formed using the same material as the gate electrode 32. Therefore, for example, the second source electrode 34 and the gate electrode 32 can be formed in the same process. The second source electrode 34 is formed by, for example, forming a conductive film by sputtering or vapor deposition, and patterning the formed conductive film.

[0107] The first source electrode 36 is provided to cover the source opening 30. Specifically, the first source electrode 36 is provided in contact with the bottom surface 30a and the side surface 30b of the source opening 30 so as to fill the source opening 30. The first source electrode 36 is electrically connected to the block layer 14 exposed at the bottom surface 30a of the source opening 30.

[0108] The first source electrode 36 may also be in contact with an outer edge 24c of the upper surface of the electron supply layer 24, which corresponds to the edge of the source opening 30. The first source electrode 36 is in direct contact with the two-dimensional electron gas 25 at the side surface 30b of the source opening 30. This makes it possible to reduce the contact resistance between the first source electrode 36 and the two-dimensional electron gas 25.

[0109] The first source electrode 36 is formed using a conductive material such as a metal. For example, a material that can be ohmically connected to the n-type GaN layer by heat treatment, such as Ti / Al (a laminated structure of a Ti layer and an Al layer), can be used as the material for the first source electrode 36. The first source electrode 36 is formed by patterning a conductive film formed by, for example, sputtering or vapor deposition.

[0110] The drain electrode 38 is provided below the substrate 10. Specifically, the drain electrode 38 is provided in contact with the lower surface of the substrate 10.

[0111] The drain electrode 38 is formed using a conductive material such as a metal. As with the material of the first source electrode 36, the material of the drain electrode 38 may be a material that forms an ohmic contact with n-type GaN, such as Ti / Al. The drain electrode 38 is formed by forming a conductive film by, for example, sputtering or vapor deposition, and then patterning the formed conductive film.

[0112] [Characteristic composition] Next, the main characteristic configuration of the nitride semiconductor device 1 according to this embodiment will be described.

[0113] As described above, in the nitride semiconductor device 1 according to the present embodiment, the p-type semiconductor layer 26 and the second source electrode 34 are provided so as to cover from a position above the opening surface of the vertical conducting opening 20 to the side surface 20b and bottom surface 20a of the vertical conducting opening 20. Moreover, above the electron supply layer 24, the gate electrode 32 is disposed at a position electrically independent from both the first source electrode 36 and the second source electrode 34. Specifically, the gate electrode 32 is disposed away from all of the first source electrode 36, the second source electrode 34, and the p-type semiconductor layer 26.

[0114] 2A and 2B are cross-sectional views illustrating the gate-drain parasitic capacitance Cgd of the nitride semiconductor device according to the comparative example and the present embodiment, respectively.

[0115] 2A shows the vicinity of the gate opening 20x in the cross-sectional configuration of the nitride semiconductor device 1x according to the comparative example. The nitride semiconductor device 1x according to the comparative example differs from the nitride semiconductor device 1 in that it includes a gate opening 20x, a gate electrode 32x, and a threshold adjustment layer 28x instead of the vertical conduction opening 20, the p-type semiconductor layer 26, the gate electrode 32, and the second source electrode 34.

[0116] The gate opening 20x is substantially the same as the vertical conduction opening 20. The gate electrode 32x and the threshold adjustment layer 28x are provided along the bottom surface 20a and side surface 20b of the gate opening 20x. Specifically, the threshold adjustment layer 28x is provided so as to cover the flat portion 24a, the inclined portion 24b, and the outer edge portion 24c of the upper surface of the electron supply layer 24. The gate electrode 32x is provided in contact with the upper surface of the threshold adjustment layer 28x. Specifically, the gate electrode 32x is provided at a position overlapping the bottom surface 20a of the gate opening 20x in a plan view.

[0117] This configuration increases the area where the gate electrode 32x and the threshold adjustment layer 28x face the drain electrode 38. This increases the parallel plate capacitance between the gate and the drain, and almost all of the electric field lines from the drain to the gate that contribute to the parasitic capacitance Cgd between the gate and the drain are terminated at the gate. This makes it difficult to reduce the parasitic capacitance Cgd.

[0118] 2B, in the configuration according to the present embodiment, the second source electrode 34 and the p-type semiconductor layer 26 are provided near the bottom surface 20a of the vertical conductive opening 20. Therefore, some of the electric field lines directed from the drain to the gate can be terminated at the second source electrode 34 and the p-type semiconductor layer 26. As a result, it is possible to reduce the parasitic capacitance Cgd between the gate and the drain.

[0119] 2B, the block layer 14 is also disposed between the gate electrode 32 and the drain electrode 38. This allows the block layer 14 to also shield the electric field lines directed toward the gate electrode 32. This further reduces the gate-drain parasitic capacitance Cgd, enabling the transistor to operate at high speed.

[0120] In addition, the second source electrode 34 is in contact with the p-type semiconductor layer 26, and a pn diode is formed by the p-type semiconductor layer 26 and the two-dimensional electron gas 25. This makes it possible to reduce the reverse leakage current and improve the breakdown voltage compared to a Schottky diode, thereby realizing a highly reliable transistor.

[0121] [Variations] Next, a modification of the first embodiment will be described.

[0122] The main difference between the modified example of the first embodiment and the first embodiment is that an opening is provided in the p-type nitride semiconductor layer provided above the electron supply layer, and the second source electrode is connected to the electron supply layer through the opening. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0123] 3 is a cross-sectional view of a nitride semiconductor device 2 according to Modification 1 of Embodiment 1. As shown in Fig. 3, compared to nitride semiconductor device 1, nitride semiconductor device 2 includes a p-type semiconductor layer 126 and a second source electrode 134 instead of p-type semiconductor layer 26 and second source electrode 34.

[0124] The p-type semiconductor layer 126 corresponds to the p-type semiconductor layer 26, and differs in that an opening 127 is provided therein. The opening 127 is an example of a third opening, and penetrates the p-type semiconductor layer 126 to reach the electron supply layer 24. In a plan view of the substrate 10, the opening 127 is provided at a position overlapping with the flat portion 24a of the upper surface of the electron supply layer 24.

[0125] The second source electrode 134 is disposed so as to cover the opening 127. Specifically, the second source electrode 134 corresponds to the second source electrode 34, and differs from the second source electrode 34 in that the second source electrode 134 is in contact with the electron supply layer 24 at the bottom surface of the opening 127. Note that the size, shape, and number of the openings 127 are not particularly limited as long as the second source electrode 134 can be in contact with the electron supply layer 24.

[0126] The second source electrode 134 is made of an electrode material that forms a Schottky contact with n-type GaN. Furthermore, since the two-dimensional electron gas 25 generated near the heterojunction interface between the electron supply layer 24 and the electron transit layer 22 can be considered to be n-type GaN, the second source electrode 134 in the opening 127 forms a Schottky contact with the electron supply layer 24. Therefore, a JBS (Junction Barrier Schottky) structure is formed near the vertical conduction opening 20, which combines a pn diode formed by the p-type semiconductor layer 126 and the two-dimensional electron gas 25 and a Schottky diode formed by the second source electrode 134 and the electron supply layer 24. The JBS structure has a lower threshold voltage than a pn diode.

[0127] When the nitride semiconductor device 2 operates in reverse conduction mode, current flows through the JBS structure near the vertical conduction opening 20. At this time, the threshold voltage is lowered, which reduces the driving voltage and reduces the conduction loss in the reverse conduction mode.

[0128] Furthermore, the opening 127 provided in the p-type semiconductor layer 126 is provided at a position overlapping the bottom surface 20a of the vertical conductive opening 20 in a plan view of the substrate 10, but is not limited to this. The opening 127 may overlap the side surface 20b of the vertical conductive opening 20 in a plan view of the substrate 10, or may be located at a position not overlapping the vertical conductive opening 20. In other words, the inclined portion 24b or the outer edge portion 24c of the upper surface of the electron supply layer 24 may be exposed at the bottom surface of the opening 127.

[0129] (Embodiment 2) Next, a second embodiment will be described.

[0130] The main difference between the second embodiment and the first embodiment is that a threshold adjustment layer is provided between the gate electrode and the electron supply layer. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0131] Fig. 4 is a cross-sectional view of a nitride semiconductor device 3 according to embodiment 2. As shown in Fig. 4, the nitride semiconductor device 3 differs from the nitride semiconductor device 1 shown in Fig. 1 in that a threshold adjustment layer 228 is provided.

[0132] The threshold adjustment layer 228 is an example of a third p-type nitride semiconductor layer, and is provided between the gate electrode 32 and the electron supply layer 24, spaced apart from the p-type semiconductor layer 26. Specifically, the threshold adjustment layer 228 is disposed so as to be in direct contact with the upper surface of the electron supply layer 24 at a position overlapping with the base layer 16 in a plan view. The gate electrode 32 is disposed above the threshold adjustment layer 228. The gate electrode 32 is in contact with the upper surface of the threshold adjustment layer 228. The threshold adjustment layer 228 and the p-type semiconductor layer 26 are disposed apart from each other and are electrically isolated from each other. The threshold adjustment layer 228 and the first source electrode 36 are disposed apart from each other and are electrically isolated from each other.

[0133] The threshold adjustment layer 228 has a thickness of 200 nm and a carrier concentration of 1×10 17 cm -3p-type Al x Ga 1-x N (0≦x≦1). The threshold adjustment layer 228 has, for example, the same composition, thickness, carrier concentration, etc. as the p-type semiconductor layer 26. Note that the thickness and carrier concentration are merely examples and can be changed as appropriate.

[0134] According to this configuration, the carrier concentration directly below the gate electrode 32 can be reduced, and the threshold voltage of the transistor can be shifted to the positive side. Therefore, the nitride semiconductor device 3 according to this embodiment can be easily realized as a normally-off type FET.

[0135] The threshold adjustment layer 228 can be formed simultaneously with the p-type semiconductor layer 26 below the second source electrode 34. Specifically, the electron transit layer 22, the electron supply layer 24, the p-type semiconductor layer 26, and the threshold adjustment layer 228 are formed by forming the vertical conductive opening 20, followed by successively depositing nitride semiconductor films using a crystal regrowth process and patterning them into a predetermined shape. Specifically, an undoped GaN film serving as the base of the electron transit layer 22, an undoped AlGaN film serving as the base of the electron supply layer 24, and a p-type AlGaN film serving as the base of the p-type semiconductor layer 26 and the threshold adjustment layer 228 are successively deposited by MOVPE, HVPE, or the like. After deposition, a portion of the p-type AlGaN film is etched away until the undoped AlGaN film is exposed, thereby forming the p-type semiconductor layer 26 and the threshold adjustment layer 228. The threshold adjustment layer 228 may be formed in a process different from that for the p-type semiconductor layer 26. The composition, thickness, carrier concentration, etc. of the threshold adjustment layer 228 can be made different from those of the p-type semiconductor layer 26, so that the threshold voltage can be adjusted to a desired value.

[0136] In this embodiment, the gate electrode 32 can be made of a material that makes ohmic contact with the p-type GaN layer. For example, palladium (Pd), nickel (Ni)-based materials, tungsten silicide (WSi), gold (Au), etc. can be used. The gate electrode 32 is formed by forming a conductive film by sputtering, vapor deposition, or the like after the source opening 30 is formed or after the first source electrode 36 and the second source electrode 34 are formed, and then patterning the formed conductive film.

[0137] In the present embodiment, similarly to the modified example of the first embodiment, an opening 127 may be provided in the p-type semiconductor layer 26, and the second source electrode 34 may be connected to the electron supply layer 24 via the opening 127.

[0138] (Embodiment 3) Next, a third embodiment will be described.

[0139] The main difference between the third embodiment and the first embodiment is that an insulating film is provided between the gate electrode and the electron supply layer. The following description will focus on the differences from the first embodiment, and the description of the commonalities between the first embodiment and the third embodiment will be omitted or simplified.

[0140] Fig. 5 is a cross-sectional view of a nitride semiconductor device 4 according to embodiment 3. As shown in Fig. 5, the nitride semiconductor device 4 differs from the nitride semiconductor device 1 shown in Fig. 1 in that an insulating film 328 is provided.

[0141] The insulating film 328 is provided between the gate electrode 32 and the electron supply layer 24. Specifically, the insulating film 328 is arranged so as to be in direct contact with the upper surface of the electron supply layer 24 at a position overlapping with the base layer 16 in a plan view. The gate electrode 32 is arranged above the insulating film 328. The gate electrode 32 is in contact with the upper surface of the insulating film 328. The gate electrode 32 and the p-type semiconductor layer 26 below the second source electrode 34 are arranged at a distance from each other and are electrically isolated from each other. The insulating film 328 may be in contact with the p-type semiconductor layer 26 and the first source electrode 36.

[0142] The insulating film 328 has a single-layer structure or a multi-layer structure including a film selected from the group consisting of SiN, SiO2, HfO2, Al2O3, ZrO2, AlN, HfON, and ZrON. The insulating film 328 is formed by, for example, a sputtering method, an atomic layer deposition (ALD) method, or a plasma CVD (chemical vapor deposition) method after the source opening 30 is formed. When an insulating film is provided below the second source electrode 34 instead of the p-type semiconductor layer 26, the insulating film and the insulating film 328 may be formed simultaneously.

[0143] According to this configuration, the gate of the nitride semiconductor device 4 has a Metal-Insulator-Semiconductor (MIS) structure. This allows the nitride semiconductor device 4 to suppress reverse leakage current at the gate and become a voltage-driven device. This makes it possible to realize a nitride semiconductor device 4 that is easy to drive and achieves both high-speed operation and high reliability.

[0144] In the present embodiment, similarly to the modification of the first embodiment, an opening 127 may be provided in the p-type semiconductor layer 26, and the second source electrode 34 may be connected to the electron supply layer 24 via the opening 127. Furthermore, the threshold adjustment layer 228 and the insulating film 328 according to the second embodiment may be stacked. In this case, the threshold voltage can be shifted further to the positive side, thereby suppressing false turning-on and improving the reliability of the nitride semiconductor device 4.

[0145] (Fourth embodiment) Next, a fourth embodiment will be described.

[0146] The fourth embodiment differs from the first embodiment in that an impurity region is provided in a part of the electron supply layer directly below the gate electrode. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0147] Fig. 6 is a cross-sectional view of a nitride semiconductor device 5 according to embodiment 4. As shown in Fig. 6, the nitride semiconductor device 5 differs from the nitride semiconductor device 1 shown in Fig. 1 in that an impurity region 424 is provided.

[0148] The impurity region 424 is an impurity region provided in a region overlapping the gate electrode 32 in a plan view of the substrate 10. Specifically, the impurity region 424 is a region in which a portion of the electron supply layer 24 is doped with Fe, B, or the like by ion implantation at a position overlapping the gate electrode 32 in a plan view, causing defects that act as electron traps and resulting in high resistance. Alternatively, the impurity region 424 may be a region doped with, for example, Mg, which acts as an acceptor in GaN. The impurity region 424 can also be called an ion-implanted region.

[0149] In this embodiment, the impurity region 424 is provided in an area narrower than the gate electrode 32 in plan view. Specifically, the entire impurity region 424 is covered by the gate electrode 32, and the gate electrode 32 is in contact with the region of the electron supply layer 24 other than the impurity region 424. The impurity region 424 may be formed larger than the gate electrode 32 in plan view. A part of the impurity region 424 may not be covered by the gate electrode 32.

[0150] According to this configuration, the carrier concentration directly below the gate electrode 32 can be reduced, and the threshold voltage of the transistor can be shifted to the positive side. Therefore, the nitride semiconductor device 5 according to this embodiment can be easily realized as a normally-off type FET.

[0151] In the present embodiment, similarly to the modification of the first embodiment, the p-type semiconductor layer 26 may be provided with an opening 127, and the second source electrode 34 may be connected to the electron supply layer 24 via the opening 127. Furthermore, at least one of the threshold adjustment layer 228 according to the second embodiment and the insulating film 328 according to the third embodiment may be provided between the impurity region 424 and the gate electrode 32. In this case, the threshold voltage can be shifted more positively, thereby suppressing false turning-on and improving the reliability of the nitride semiconductor device 5.

[0152] (Embodiment 5) Next, a fifth embodiment will be described.

[0153] The fifth embodiment differs from the first embodiment in that a recess is provided in a part of the electron supply layer directly below the gate electrode. The recess is also called a recess portion. The nitride semiconductor device according to the fifth embodiment has a gate recess structure. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0154] Fig. 7 is a cross-sectional view of a nitride semiconductor device 6 according to the fifth embodiment. As shown in Fig. 7, the nitride semiconductor device 6 differs from the nitride semiconductor device 1 shown in Fig. 1 in that a gate recess structure is provided. Specifically, the nitride semiconductor device 6 includes a threshold adjustment layer 528. In addition, a recess 524 is provided in the electron supply layer 24.

[0155] The recess 524 is provided at a position overlapping the gate electrode 32 in a plan view of the substrate 10. The recess 524 is formed, for example, by removing a part of the electron supply layer 24 by dry etching or the like.

[0156] The threshold adjustment layer 528 corresponds to the threshold adjustment layer 228 according to the second embodiment, and differs in that it is provided so as to cover the recess 524. The threshold adjustment layer 528 contacts and covers the bottom and side surfaces of the recess 524. Note that the threshold adjustment layer 528 may not be provided, and the gate electrode 32 may be in contact with the bottom and side surfaces of the recess 524. Alternatively, an insulating film similar to the insulating film 328 may be provided instead of the threshold adjustment layer 528.

[0157] In this embodiment, the recess 524 is provided in an area narrower than the threshold adjustment layer 528 in a plan view. Specifically, the entire recess 524 is covered by the threshold adjustment layer 528, and the threshold adjustment layer 528 is in contact with the region of the electron supply layer 24 outside the recess 524. The recess 524 may be formed smaller than the threshold adjustment layer 528 and the gate electrode 32 in a plan view. For example, the threshold adjustment layer 528 and the gate electrode 32 may cover the bottom surface of the recess 524 but not the side surface of the recess 524.

[0158] According to this configuration, the carrier concentration directly below the gate electrode 32 can be reduced, and the threshold voltage of the transistor can be further shifted to the positive side. Therefore, the nitride semiconductor device 6 according to this embodiment can be most easily realized as a normally-off type FET.

[0159] Alternatively, instead of providing the recess 524, the electron supply layer 24 may be thickened in a portion other than the portion directly below the threshold adjustment layer 528 and the gate electrode 32. Alternatively, the Al composition of the electron supply layer 24 may be increased. This makes it possible to reduce the on-resistance while achieving a threshold voltage equivalent to that of the nitride semiconductor device 1.

[0160] The recess 524 is formed by successively depositing nitride semiconductor films for the electron transit layer 22 and the electron supply layer 24 through a crystal regrowth process, followed by patterning into a predetermined shape. Specifically, an undoped GaN film, which serves as the base of the electron transit layer 22, and an undoped AlGaN film, which serves as the base of the electron supply layer 24, are successively deposited by MOVPE, HVPE, or the like. After deposition, a portion of the undoped AlGaN film is removed by etching to form the recess 524. Thereafter, a p-type AlGaN layer, which serves as the base of the threshold adjustment layer 528 and the p-type semiconductor layer 26, is deposited by MOVPE, HVPE, or the like. After deposition, a portion of the p-type AlGaN film is removed by etching, thereby separating the threshold adjustment layer 528 and the p-type semiconductor layer 26. In other words, the nitride semiconductor device 6 can be fabricated by adding one additional regrowth process compared to conventional methods.

[0161] The bottom of the recess 524 is provided above the upper surface of the electron transit layer 22, but may penetrate the electron supply layer 24 and reach the electron transit layer 22. In this case, an undoped AlGaN film and a p-type AlGaN film are formed again in the subsequent crystal growth step, thereby forming a structure similar to that described above.

[0162] In the present embodiment, similarly to the modification of the first embodiment, the p-type semiconductor layer 26 may be provided with an opening 127, and the second source electrode 34 may be connected to the electron supply layer 24 via the opening 127. Furthermore, the insulating film 328 according to the third embodiment may be stacked on the threshold adjustment layer 528. Furthermore, the impurity region 424 according to the fourth embodiment may be provided in the electron supply layer 24 in a region including the bottom surface of the recess 524. In these cases, the threshold voltage can be shifted more positively, thereby suppressing false firing and improving the reliability of the nitride semiconductor device 5.

[0163] (Embodiment 6) Next, a sixth embodiment will be described.

[0164] The sixth embodiment differs from the fifth embodiment in that the distance between the lower surface of the p-type semiconductor layer and the substrate is shorter than the distance between the lower surface of the block layer and the substrate. The following description will focus on the differences from the fifth embodiment, and the description of the commonalities will be omitted or simplified.

[0165] FIG. 8 is a cross-sectional view of a nitride semiconductor device 7 according to the sixth embodiment. As shown in FIG. 8, the nitride semiconductor device 7 differs from the nitride semiconductor device 6 according to the fifth embodiment in that the vertical conduction opening 20 is formed so as to remove a greater depth from the drift layer 12. As a result, the lower surface of the p-type semiconductor layer 26 is located lower than the lower surface of the block layer 14. Specifically, the distance A between the p-type semiconductor layer 26 and the drain electrode 38 is shorter than the distance B between the block layer 14 and the drain electrode 38. The distance A is the shortest distance between the p-type semiconductor layer 26 and the drain electrode 38. The distance A corresponds to the distance between the flat portion 24a on the upper surface of the electron supply layer 24 and the upper surface of the drain electrode 38.

[0166] According to this configuration, the vertical conductive opening 20 is formed by dry etching, and therefore the side surface of the block layer 14 corresponding to the side surface 20b of the vertical conductive opening 20 contains damage caused by the dry etching. Furthermore, because the side surface of the block layer 14 is inclined, the portion near the side surface of the block layer 14 is not only thin but also has a sharp angle. This results in a structure in which an electric field is likely to concentrate and dielectric breakdown is likely to occur.

[0167] In contrast, in the nitride semiconductor device 7, when a high voltage is applied to the drain electrode 38 in the off state, a high electric field is applied to the bottom of the p-type semiconductor layer 26, which is closer to the drain electrode 38 than the block layer 14. In other words, the electric field applied to the side surface of the block layer 14 can be alleviated. Therefore, the nitride semiconductor device 7 according to this embodiment can be realized as an FET with a high breakdown voltage.

[0168] The relationship between distance A and distance B according to this embodiment is also applicable to nitride semiconductor devices 1, 2, 3, 4, 5 and 6 according to the first to sixth embodiments and their respective modifications.

[0169] (Other embodiments) While nitride semiconductor devices according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0170] For example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) gradually decreases from the substrate 10 side to the block layer 14 side. The donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si. Alternatively, the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations. Specifically, the drift layer may be two-layered, with a layer with a low donor concentration disposed below the block layer and a layer with a high donor concentration disposed on the substrate side. By providing a vertical conductive opening 20 that penetrates the layer with a low donor concentration, current flows through the layer with a high donor concentration through the vertical conductive opening 20 when the transistor is on, thereby reducing the on-resistance. Conversely, when the transistor is off, a high electric field is maintained by the layer with a low donor concentration, thereby achieving both low on-resistance and high breakdown voltage.

[0171] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents. [Industrial Applicability]

[0172] The nitride semiconductor device of the present disclosure is useful, for example, as a power transistor used in power supply circuits, inverter circuits, and the like of equipment. [Explanation of symbols]

[0173] 1, 2, 3, 4, 5, 6, 7 Nitride Semiconductor Devices 10 Substrate 12 Drift Layer 14 Block Layer 16 Base layer 20 Vertical Conduction Opening 20a, 30a bottom 20b, 30b side 22 Electron transit layer 24 Electron supply layer 24a Flat area 24b Slope 24c outer edge 25 Two-dimensional electron gas 26, 126 p-type semiconductor layer 30 Source opening 32 gate electrode 34, 134 second source electrode 36 first source electrode 38 Drain electrode 127 Opening 228, 528 Threshold adjustment layer 328 Insulating Film 424 Impurity region 524 recess

Claims

1. A substrate; a first nitride semiconductor layer provided above the substrate; a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer; a second nitride semiconductor layer provided above the first p-type nitride semiconductor layer; an electron transit layer and an electron supply layer provided in this order from below so as to cover a side surface and a bottom surface of a first opening that penetrates the second nitride semiconductor layer and the first p-type nitride semiconductor layer to reach the first nitride semiconductor layer, and an upper surface of the second nitride semiconductor layer; a second p-type nitride semiconductor layer provided above the electron supply layer at a position overlapping a bottom surface and a side surface of the first opening in a plan view of the substrate; a gate electrode provided above the electron supply layer at a position overlapping the second nitride semiconductor layer in a plan view of the substrate; a first source electrode provided at a position away from the gate electrode in a plan view of the substrate, the first source electrode penetrating the electron supply layer and the electron transit layer and covering a second opening reaching the first p-type nitride semiconductor layer, the first source electrode being electrically connected to the first p-type nitride semiconductor layer; a drain electrode provided below the substrate; a second source electrode provided above the second p-type nitride semiconductor layer and electrically connected to the second p-type nitride semiconductor layer and the first source electrode; a part of a lower surface of the second p-type nitride semiconductor layer is located above an opening surface of the first opening; Nitride semiconductor devices.

2. a side surface of the first opening is inclined with respect to a bottom surface of the first opening, The upper surface of the electron supply layer is a flat portion along the bottom surface of the first opening; a sloped portion along the side of the first opening; an outer edge portion extending from an upper end of the inclined portion in a direction away from the flat portion, the lower surface of the second p-type nitride semiconductor layer continuously covers at least a portion of the flat portion, the inclined portion, and a portion of the outer edge portion; The nitride semiconductor device of claim 1 .

3. In a plan view of the substrate, the second p-type nitride semiconductor layer overlaps the first p-type nitride semiconductor layer. The nitride semiconductor device of claim 1 .

4. a third p-type nitride semiconductor layer provided between the gate electrode and the electron supply layer and spaced apart from the second p-type nitride semiconductor layer; The nitride semiconductor device according to claim 1 .

5. an insulating film provided between the gate electrode and the electron supply layer; The nitride semiconductor device according to claim 1 .

6. the electron supply layer has an impurity region provided at a position overlapping the gate electrode in a plan view of the substrate; The nitride semiconductor device according to claim 1 .

7. a recess is provided in the electron supply layer at a position overlapping the gate electrode in a plan view of the substrate; The nitride semiconductor device according to claim 1 .

8. a distance between the second p-type nitride semiconductor layer and the drain electrode is shorter than a distance between the first p-type nitride semiconductor layer and the drain electrode; The nitride semiconductor device according to claim 1 .

9. a third opening is provided in the second p-type nitride semiconductor layer, the third opening penetrating the second p-type nitride semiconductor layer and reaching the electron supply layer; the second source electrode is in contact with the electron supply layer at a bottom surface of the third opening. The nitride semiconductor device according to claim 1 .

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