Structure and method for manufacturing structure

Abstract

To provide a structure excellent in quality.SOLUTION: A structure includes: a substrate; a plurality of semiconductor films arranged directly or through another layer on the substrate, adjacent to each other and including crystalline oxide; and an edge cut part for separating the plurality of semiconductor films from each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to structures and methods for manufacturing structures. [Background technology]

[0002] Patent Document 1 discloses a crystalline body in which a crystalline stress relaxation layer, a semiconductor layer, a cap layer, and an insulating film are formed on a base substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5397794 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned crystals, warping, distortion, cracks, etc. may occur, which may result in a deterioration in quality.

[0005] An object of the present disclosure is to provide a high-quality structure. [Means for solving the problem]

[0006] A structure according to one aspect of the present disclosure includes a substrate, a plurality of semiconductor films each having a crystalline oxide, the semiconductor films being disposed adjacent to each other on the substrate directly or via another layer, and an edge separation portion separating the plurality of semiconductor films from each other.

[0007] A structure according to one aspect of the present disclosure includes a plurality of semiconductor films adjacent to each other and each having a crystalline oxide, and an edge separation portion separating the plurality of semiconductor films from each other.

[0008] A method for manufacturing a structure according to one aspect of the present disclosure includes roughening a portion of a surface of a substrate to form a rough surface, forming an edge cutting portion on the rough surface, and forming a plurality of semiconductor films having crystalline oxides, the semiconductor films being separated by the edge cutting portion, on portions of the surface of the substrate other than the rough surface.

[0009] A method for manufacturing a structure according to one aspect of the present disclosure includes forming a groove on a surface of a substrate, forming an edge cutting portion in the groove, and forming a plurality of semiconductor films having a crystalline oxide, the semiconductor films being separated by the edge cutting portion, on a portion of the surface of the substrate other than the groove.

[0010] A method for manufacturing a structure according to one aspect of the present disclosure includes forming an edge cutting portion on a portion of a surface of a substrate, and forming a plurality of semiconductor films, each having a crystalline oxide, separated by the edge cutting portion on a portion of the surface of the substrate other than the edge cutting portion. [Effects of the Invention]

[0011] According to the present disclosure, a high-quality structure can be provided. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a plan view schematically showing a structure according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 3 is a flowchart showing a method for manufacturing the structure. [Figure 4] FIG. 4 is a cross-sectional view schematically showing the substrate. [Figure 5] FIG. 5 is a cross-sectional view schematically showing a substrate on which a second region is formed. [Figure 6] FIG. 6 is a schematic diagram showing an example of a film forming apparatus. [Figure 7] FIG. 7 is a schematic diagram showing another example of a film forming apparatus. [Figure 8] FIG. 8 is a schematic diagram showing a film forming apparatus according to still another example. [Figure 9] FIG. 9 is a cross-sectional view schematically showing a structure according to the second embodiment. [Figure 10] FIG. 10 is a flowchart showing a method for manufacturing the structure of the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view schematically showing a substrate on which grooves are formed. [Figure 12] FIG. 12 is a cross-sectional view that schematically shows a cross section of the structure of the third embodiment. [Figure 13] FIG. 13 is an enlarged view of part B in FIG. [Figure 14] FIG. 14 is a flowchart showing a method for manufacturing the structure of the third embodiment. [Figure 15] FIG. 15 is an explanatory diagram that schematically shows a cross section of a substrate on which an edge cutting portion is formed. [Figure 16] FIG. 16 is a cross-sectional view that schematically shows a cross section of a structure of another example of the third embodiment. [Figure 17] FIG. 17 is a cross-sectional view that schematically shows a cross section of a structure of yet another example of the third embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing a schematic example of a semiconductor device. [Figure 19] FIG. 19 is a cross-sectional view schematically showing another example of a semiconductor device. [Figure 20] FIG. 20 is a cross-sectional view schematically showing a semiconductor device according to still another example. [Figure 21] FIG. 21 is a cross-sectional view schematically showing a semiconductor device according to still another example. [Figure 22] FIG. 22 is a cross-sectional view schematically showing a semiconductor device according to still another example. [Figure 23] FIG. 23 is a cross-sectional view schematically showing a semiconductor device according to still another example. [Figure 24] FIG. 24 is a cross-sectional view schematically showing a semiconductor device according to still another example. [Figure 25] FIG. 25 is a cross-sectional view schematically showing a semiconductor device according to still another example. [Figure 26]FIG. 26 is a block diagram of an example power supply system. [Figure 27] FIG. 27 is a block diagram of an example system device. [Figure 28] FIG. 28 is a circuit diagram showing a power supply circuit of an example power supply device. [Figure 29] FIG. 29 is a magnified photograph of the surface of the substrate taken using an optical microscope. [Figure 30] FIG. 30 is a photograph of a cross section of the groove portion of the structure taken using an SEM. [Figure 31] FIG. 31 is an enlarged photograph of the surface of the structure of the example taken using an optical microscope. [Figure 32] FIG. 32 is an enlarged photograph of the surface of the structure of the comparative example taken using an optical microscope. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, the invention according to the claims is not limited to the embodiments shown below. Furthermore, not all of the combinations of the configurations described in the following embodiments are necessarily required to solve the problems. Furthermore, each configuration of the present disclosure is described to the extent that it does not interfere with the solution of the problems of the present disclosure. Note that the same components are designated by the same reference numerals to avoid redundant description.

[0014] Additionally, as will be apparent to those skilled in the art, features shown in the drawings are not necessarily drawn to scale, even if not otherwise stated herein. It should also be noted that one feature in one embodiment may be used in another embodiment. Descriptions of well-known elements and processing techniques may be omitted so as not to unnecessarily obscure the embodiments of the present disclosure. The examples used herein are merely intended to aid in the understanding of the present disclosure and further enable those skilled in the art to practice the embodiments of the present disclosure. Therefore, the embodiments and examples herein should not be construed as limiting the scope of the present disclosure, which is defined solely by the claims and applicable law.

[0015] Terms such as "first," "second," and the like are used to describe various elements used herein, but the elements are not limited by these terms. Terms such as "first," "second," and the like are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and a second element could be referred to as the first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any or all combinations of one or more of the listed items.

[0016] When an element, such as a layer, region, or substrate, is referred to as being "on" another element, it is understood that it can be directly on the other element, or intervening elements may be present. When an element is referred to as being "connected" or "coupled" to another element, it is understood that it can be directly connected or coupled to the other element, or intervening elements may be present.

[0017] The terms used in this specification are intended to describe particular embodiments only and are not intended to limit the disclosure. As used in this specification, the words "comprise," "have," and "include" refer to the presence of stated elements and do not exclude the presence of one or more other elements.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning that is consistent with the meaning in the context of this specification and the related art. Furthermore, unless defined herein, it should be understood that terms used herein should not be interpreted in an idealized or overly formal sense.

[0019] (First embodiment) First, a first embodiment will be described. FIG. 1 is a plan view showing a portion of a structure 1A of this embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. The structure 1A is, for example, a wafer from which a plurality of semiconductor chips can be cut out. The structure 1A includes a substrate 20, a plurality of adjacent semiconductor films 2 disposed on the substrate 20 directly or via other layers, and an edge separation portion 3 separating the plurality of semiconductor films 2 from one another. In other words, the structure 1A is a stacked structure. The plurality of semiconductor films 2 may also be referred to as adjacent semiconductor films 2. The structure 1A may further include a layer formed on the plurality of semiconductor films 2 and / or the edge separation portion 3. The layer formed on the plurality of semiconductor films 2 and / or the edge separation portion 3 is, for example, another semiconductor layer such as an n+ layer or a p layer.

[0020] In the present disclosure, the thickness direction of the substrate 20 is referred to as the "vertical direction." Within the vertical direction, the direction from the substrate 20 toward the plurality of semiconductor films 2 is referred to as the "upward direction," and the direction from the plurality of semiconductor films 2 toward the substrate 20 is referred to as the "downward direction." In this specification, a planar view means a view from above. Note that the "vertical direction," "upward," and "downward" do not limit the direction of gravity or the mounting direction of the semiconductor device on a circuit board or the like when mounted. The structure 1A may not include the substrate 20. For example, if the substrate 20 is removed during the manufacturing process of the semiconductor chip, the structure 1A may not include the substrate 20. All or a part of the structure 1A may be included in a semiconductor device. The semiconductor device is, for example, a diode or a transistor.

[0021] The substrate 20 serves as a base for the multiple semiconductor films 2. The substrate 20 supports the multiple semiconductor films 2. The substrate 20 may be an insulating substrate, a semiconductor substrate, or a conductive substrate. The substrate 20 may be a single-crystal substrate or a polycrystalline substrate. The substrate 20 may be, for example, a sapphire substrate, a gallium substrate, or a mixed crystal substrate containing Ga2O3 and Al2O3. The crystal structure of the substrate 20 may be, for example, a corundum structure, a β-gallium structure, a hexagonal crystal structure (e.g., an ε-type structure), an orthorhombic crystal structure (e.g., a κ-type structure), a cubic crystal structure, or a tetragonal crystal structure. The substrate 20 preferably has the same crystal structure as the multiple semiconductor films 2. It is more preferable that the substrate 20 contains, as a main component, a crystalline material having the same crystal structure as the multiple semiconductor films 2. In this disclosure, the term "main component" means that the substrate contains 50% or more of the total amount of the crystalline material. The crystal structure of the substrate 20 is preferably a corundum structure, and more preferably, the substrate 20 contains a crystalline material having a corundum structure as a main component. Substrates having a corundum structure include, for example, sapphire substrates such as c-plane sapphire substrates, m-plane sapphire substrates, a-plane sapphire substrates, and r-plane sapphire substrates; α-type gallium oxide substrates; and α-type mixed crystal substrates containing Ga2O3 and Al2O3. An α-type mixed crystal substrate is, for example, a substrate containing more than 0 wt% and not more than 60 wt% Al2O3.

[0022] Substrate 20 may have an off-angle. The off-angle is, for example, preferably 0.01° or more, and more preferably 0.2° or more. The off-angle is more preferably 0.2° or more and 12° or less. The value of the off-angle of substrate 20 is not particularly limited. Substrate 20 does not need to have an off-angle. The thickness of substrate 20 is not particularly limited, but is preferably 10 μm or more and 20 mm or less, and more preferably 10 μm or more and 1000 μm or less.

[0023] In this embodiment, the upper surface of the substrate 20 includes a plurality of first regions 21 adjacent to each other and a second region 22 disposed between the plurality of first regions 21. The first region 21 is a smooth surface compared to the second region 22 and is a growth region where epitaxial growth is likely to occur. The second region 22 is a rough surface with a large surface roughness compared to the first region 21 and has fine irregularities. The second region 22 is a non-growth region where epitaxial growth is less likely to occur compared to the first region 21. The second region 22 is an example of a region on the surface of the substrate 20 where crystal growth is less likely to occur than in other parts. The second region 22 may include, for example, as part of the irregularities, a convex portion protruding above the first region 21 or a concave portion recessed below the first region 21, or both of these convex portions and concave portions.

[0024] When the structure 1A is separated into a plurality of semiconductor chips, the second region 22 may be a region located between adjacent semiconductor chips. In other words, the second region 22 may be a region where the structure 1A is cut during dicing. The shape of the second region 22 in a plan view is, for example, a rectangular lattice shape. The first region 21 is the entire region of the upper surface of the substrate 20 except for the second region 22. The multiple first regions 21 are partitioned by the second regions 22. The multiple first regions 21 include first regions 21 surrounded by second regions 22. The shape of the first region 21 in a plan view is, for example, a rectangle.

[0025] The plurality of semiconductor films 2 are disposed above the substrate 20. The plurality of semiconductor films 2 may be formed directly on the substrate 20, or may be formed on the substrate 20 via another layer such as a buffer layer. In this example, the plurality of semiconductor films 2 are formed directly on the substrate 20.

[0026] The multiple semiconductor films 2 have thicknesses. The thickness of the multiple semiconductor films 2 is, for example, the maximum thickness of the multiple semiconductor films 2. The thickness of the multiple semiconductor films 2 may be the minimum or average thickness of the multiple semiconductor films 2, or the thickness of a portion of one semiconductor film 2 included in the multiple semiconductor films 2. The multiple semiconductor films 2 are formed in multiple first regions 21, respectively. The multiple semiconductor films 2 are aligned along the top surface of the substrate 20. More specifically, the multiple semiconductor films 2 are aligned along an imaginary plane that is substantially perpendicular to the thickness direction of the substrate 20. In the present disclosure, the direction perpendicular to the imaginary plane may be defined as the "vertical direction."

[0027] Each of the multiple semiconductor films 2 has a shape that conforms to the upper surface of the substrate 20. The thickness direction of each semiconductor film 2 substantially coincides with the thickness direction of the substrate 20. The thickness direction of the semiconductor film 2 may be defined as the "vertical direction." The shape of the semiconductor film 2 in a planar view and the shape of the corresponding first region 21 in a planar view may substantially coincide with or be substantially similar to each other. The shape of the semiconductor film 2 in a planar view is, for example, rectangular. The shapes of the semiconductor film 2 and the first region 21 are not limited. The shapes of the semiconductor film 2 and the first region 21 in a planar view may be, for example, a square, a parallelogram, a rhombus, a triangle, a polygon such as a pentagon or a hexagon, or a circle, an ellipse, or the like.

[0028] The semiconductor film 2 may be an n-type semiconductor or a p-type semiconductor. In this disclosure, "n-type semiconductor" includes semiconductors used as n-type semiconductors and semiconductors used as n+-type semiconductors in semiconductor devices. In this disclosure, "p-type semiconductor" includes semiconductors used as p-type semiconductors and semiconductors used as p+-type semiconductors in semiconductor devices. That is, the semiconductor film 2 may be an n-type semiconductor, an n+-type semiconductor, a p-type semiconductor, or a p+-type semiconductor.

[0029] The semiconductor film 2 may contain a crystalline oxide as a main component. The semiconductor film 2 may contain 70% or more, or 90% or more, of a crystalline oxide in terms of atomic ratio. The semiconductor film 2 may be a crystalline oxide. That is, the semiconductor film 2 may contain 100% of a crystalline oxide in terms of atomic ratio. The crystalline oxide is preferably a metal oxide. The semiconductor film 2 preferably has a wide bandgap semiconductor.

[0030] It is more preferable that the crystalline oxide contains gallium. Gallium may be the main component of all metal elements contained in the crystalline oxide. That is, the atomic ratio of gallium to all metal elements contained in the crystalline oxide may be 50% or more. The atomic ratio of gallium to all metal elements contained in the crystalline oxide may be 70% or more, or may be 90% or more. The crystalline oxide may contain gallium oxide. In addition to gallium, the crystalline oxide may contain one or more metals selected from iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr). The crystalline oxide preferably contains, in addition to gallium, at least one metal selected from aluminum and indium. The components contained in the crystalline oxide are not limited. The crystalline oxide may also contain, for example, germanium oxide.

[0031] The crystalline oxide contained in the semiconductor film 2 may be single crystal or polycrystalline. Preferably, the crystalline oxide is single crystal. Examples of the crystalline structure of the crystalline oxide include a corundum structure, a β-gallium structure, a hexagonal structure (e.g., an ε-type structure), an orthorhombic structure (e.g., a κ-type structure), a cubic structure, and a tetragonal structure. Preferably, the crystalline oxide has the same crystalline structure as the substrate 20. More preferably, the crystalline oxide contains, as a main component, a crystalline substance having the same crystalline structure as the crystalline substance contained as a main component of the substrate 20. Preferably, the crystalline structure of the crystalline oxide is a corundum structure. The crystalline oxide may be a mixed crystal containing two or more metal oxides. More preferably, the crystalline oxide is α-Ga2O3 or a mixed crystal thereof.

[0032] The semiconductor film 2 is, for example, a film epitaxially grown on the first region 21, i.e., an epitaxially grown film. The semiconductor film 2 may be a film heteroepitaxially grown on the first region 21, or a film homoepitaxially grown on the first region 21.

[0033] The semiconductor film 2 may further contain a dopant. The dopant may be a known dopant. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, and niobium, and p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, and P. The dopant content in the composition of the semiconductor film 2 is preferably 0.00001 atomic % or more. The dopant content in the composition of the semiconductor film 2 is more preferably 0.00001 atomic % or more and 20 atomic % or less, and even more preferably 0.00001 atomic % or more and 10 atomic % or less. For example, the carrier concentration may be 1×10 16 / cm 3 More than 1×10 22 / cm 3 The carrier concentration is 1×10 16 / cm 3 May be less than 1 x 10 22 / cm 3 The carrier concentration can exceed 1×10 17 / cm 3 The semiconductor film 2 may not contain a dopant.

[0034] The edge cutting portion 3 is disposed above the substrate 20. The edge cutting portion 3 may be formed directly on the substrate 20, or may be formed on the substrate 20 via another layer such as a buffer layer. In this example, the edge cutting portion 3 is formed directly in the second region 22. The edge cutting portion 3 is located between a plurality of semiconductor films 2. Stress may occur in the semiconductor film 2 due to, for example, the difference in lattice constant between the substrate 20 and the semiconductor film 2. The edge cutting portion 3 relieves the stress occurring in the semiconductor film 2.

[0035] The edge cutting portion 3 extends along the adjacent semiconductor film 2. The edge cutting portion 3 has a thickness. The thickness direction of the edge cutting portion 3 substantially coincides with the thickness direction of the substrate 20. In this example, the thickness of the edge cutting portion 3 is greater than the thicknesses of the multiple semiconductor films 2, and the upper end of the edge cutting portion 3 is located above the multiple semiconductor films 2. The thickness of the edge cutting portion 3 may be the same as the thicknesses of the multiple semiconductor films 2, or may be smaller than the thicknesses of the multiple semiconductor films 2. The upper end of the edge cutting portion 3 may be flush with the upper surfaces of the multiple semiconductor films 2, or may be located below the upper surfaces of the multiple semiconductor films 2.

[0036] The edge cutting portion 3 has a width. The width of the edge cutting portion 3 is the dimension in a direction perpendicular to both the thickness direction and the length direction of the edge cutting portion 3, i.e., the dimension in the direction in which the multiple semiconductor films 2 are arranged. The width of the edge cutting portion 3 substantially matches the spacing between the multiple semiconductor films 2. The width of the edge cutting portion 3 is preferably larger than the thickness of the edge cutting portion 3. The width of the edge cutting portion 3 is preferably larger than the thickness of the multiple semiconductor films 2. The width of the edge cutting portion 3 is more preferably at least twice the thickness of the multiple semiconductor films 2, and even more preferably at least three times the thickness of the multiple semiconductor films 2. The width of the edge cutting portion 3 is not limited. The width of the edge cutting portion 3 may be, for example, a dimension equal to or smaller than the thickness of the edge cutting portion 3. The difference between the thickness of the multiple semiconductor films 2 and the thickness of the edge cutting portion 3 is preferably smaller than the width of the edge cutting portion 3, and more preferably smaller than the thickness of the multiple semiconductor films 2. The difference between the thickness of the multiple semiconductor films 2 and the thickness of the edge cutting portion 3 may be equal to or larger than the width of the edge cutting portion 3.

[0037] The edge cutting portion 3 contacts the plurality of semiconductor films 2. Note that in Figures 1 and 2, the boundary between the edge cutting portion 3 and the plurality of semiconductor films 2 is shown by a solid line for ease of understanding, but the boundary between the edge cutting portion 3 and the plurality of semiconductor films 2 does not need to be clearly visible in appearance. The same applies to Figure 9 and the like described below. The edge cutting portion 3 completely separates the plurality of semiconductor films 2 so that the plurality of semiconductor films 2 do not come into contact with each other. Note that the edge cutting portion 3 does not need to completely separate the plurality of semiconductor films 2. For example, the edge cutting portion 3 may separate the plurality of semiconductor films 2 in a state where the lower ends, upper ends, or vertical middle portions of the plurality of semiconductor films 2 are connected to each other.

[0038] The edge cutting portion 3 may be amorphous, single crystalline, or polycrystalline. It is preferable that the edge cutting portion 3 has an amorphous structure or a crystalline structure different from the crystalline structure of the plurality of semiconductor films 2. The edge cutting portion 3 may contain an oxide. The edge cutting portion 3 may contain an oxide semiconductor as a main component. The edge cutting portion 3 may contain an oxide semiconductor in an atomic ratio of 70% or more, or 90% or more. The edge cutting portion 3 may be an oxide semiconductor.

[0039] The oxide semiconductor of the edge cutting portion 3 preferably contains the same elements as the crystalline oxide of the semiconductor film 2. For example, if the crystalline oxide of the semiconductor film 2 contains gallium, the oxide semiconductor of the edge cutting portion 3 preferably contains gallium. Gallium may be the main component of all metal elements contained in the oxide semiconductor of the edge cutting portion 3. That is, the atomic ratio of gallium to all metal elements contained in the oxide semiconductor of the edge cutting portion 3 may be 50% or more. The atomic ratio of gallium to all metal elements contained in the oxide semiconductor of the edge cutting portion 3 may be 70% or more, or may be 90% or more. The oxide semiconductor of the edge cutting portion 3 may contain, in addition to gallium, one or more metals selected from iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr). The oxide semiconductor of the edge cutting portion 3 preferably contains, in addition to gallium, at least one metal selected from aluminum and indium. The main component of the edge cutting portion 3 is preferably the same as the main component of the semiconductor film 2. It is more preferable that the edge cutting portion 3 is formed from substantially the same material as the material of the semiconductor film 2. The components contained in the edge cutting portion 3 are not limited. The elastic modulus of the edge cutting portion 3 may be lower than the elastic modulus of the multiple semiconductor films 2. The elastic modulus of the edge cutting portion 3 may be higher than the elastic modulus of the multiple semiconductor films 2.

[0040] Next, an example of a method for manufacturing the structure 1A will be described. FIG. 3 is a flowchart showing a method for manufacturing the structure 1A. FIGS. 4 and 5 are cross-sectional views sequentially illustrating the method for manufacturing the structure 1A. The method for manufacturing the structure 1A includes forming an edge cutting portion 3 on the surface of the substrate 20 (hereinafter, this step will be simply referred to as the "edge cutting portion forming step") and forming a plurality of semiconductor films 2 on the surface of the substrate 20 (hereinafter, this step will be simply referred to as the "semiconductor film forming step"). In this example, the edge cutting portion forming step and the semiconductor film forming step are performed substantially simultaneously. Hereinafter, a step that serves as both the edge cutting portion forming step and the semiconductor film forming step will be referred to as a shaping step. In other words, performing the shaping step means that the edge cutting portion forming step and the semiconductor film forming step are performed. Note that the plurality of semiconductor films 2 and the edge cutting portion 3 do not have to be formed simultaneously. For example, the semiconductor film forming step may be performed after the edge cutting portion forming step is performed. The manufacturing method of the structure 1A may further include preparing a substrate 20 (hereinafter, this process will be simply referred to as the "substrate preparation process") and forming a second region 22 on the substrate 20 (hereinafter, this process will be simply referred to as the "second region formation process").

[0041] In the substrate preparation step, for example, a substrate 20 as shown in Fig. 4 is prepared. The upper surface of this substrate 20 is a smooth plane over its entire surface.

[0042] The second region forming step is performed after the substrate preparation step. In the second region forming step, for example, as shown in FIG. 5, a second region 22 is formed on a portion of the upper surface of the substrate 20 prepared in the substrate preparation step. In the second region forming step, for example, a laser is irradiated onto only a portion of the upper surface of the substrate 20. As a result, the portion of the upper surface of the substrate 20 irradiated with the laser is roughened to become the second region 22. The portion of the upper surface of the substrate 20 not irradiated with the laser forms the first region 21. In other words, the first region 21 is a portion that is not roughened by the laser irradiation.

[0043] The shaping process is performed after the second region forming process. That is, the edge cutting portion forming process and the semiconductor film forming process are performed after the second region forming process. In the shaping process, for example, material for the semiconductor film 2 and the edge cutting portion 3 is supplied onto the substrate 20. This material reacts or the like to form multiple semiconductor films 2 and edge cutting portions 3 on the substrate 20. When the material is supplied onto the substrate 20, epitaxial growth occurs in the first region 21, and the semiconductor film 2 is formed from the material. On the other hand, the second region 22 has a larger surface roughness than the first region 21, making epitaxial growth more difficult. Therefore, in the second region 22, crystals having an amorphous structure or a crystal structure different from the crystal structure of the semiconductor film 2 are formed from the material. The amorphous structure or crystals having a crystal structure different from the crystal structure of the semiconductor film 2 formed in the second region 22 in this way become the edge cutting portion 3.

[0044] In the molding process, the semiconductor films 2 and the edge cutting portion 3 are formed by, for example, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), metal organic vapor-phase epitaxy (MOVPE), mist CVD, mist epitaxy, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or pulse growth. In the molding process, the semiconductor films 2 and the edge cutting portion 3 are preferably formed by mist CVD, mist epitaxy, or HVPE.

[0045] When forming a plurality of semiconductor films 2 and edge cutting portions 3 by mist CVD or mist epitaxy, the forming step may include atomizing a raw material solution containing metal to generate mist or atomized droplets (hereinafter, this step will be referred to as the "atomization step"), and transporting the obtained atomized droplets to the vicinity of the substrate 20 by a carrier gas, thereby causing the atomized droplets to react and form a plurality of semiconductor films 2 and edge cutting portions 3 (film formation step). Hereinafter, when there is no need to distinguish between the semiconductor films 2 and the edge cutting portions 3, each of the semiconductor films 2 and the edge cutting portions 3 will be referred to as the "formed film."

[0046] The raw material solution used in the atomization step contains the metal contained in the film to be formed, and may contain either an inorganic material or an organic material.

[0047] The source solution can be prepared by dissolving or dispersing the metal contained in the film in the form of a complex or salt in an organic solvent or water. Examples of the complex include an acetylacetonate complex, a carbonyl complex, an ammine complex, and a hydride complex. Examples of the salt include an organic metal salt (e.g., a metal acetate, a metal oxalate, a metal citrate, etc.), a metal sulfide salt, a metal nitrate salt, a metal phosphate salt, or a metal halide salt (e.g., a metal chloride salt, a metal bromide salt, a metal iodide salt, etc.).

[0048] The solvent for the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. The solvent preferably contains water.

[0049] The source solution may contain additives such as hydrohalic acid or an oxidizing agent. Examples of hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Examples of oxidizing agents include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, peracetic acid, nitrobenzene, and organic peroxides. The source solution may also contain the dopant described above.

[0050] In the atomization process, a raw material solution containing a metal is prepared, and the prepared raw material solution is atomized. This causes atomized droplets to float. The atomization means is not particularly limited and may be a known atomization means. The atomization means is preferably a means for atomizing the raw material solution using ultrasonic vibrations. The atomized droplets generated in the atomization process float in the air, and are preferably droplets that float in space with an initial velocity of zero and can be transported as a gas, rather than being sprayed like a spray, for example. The size of the atomized droplets is preferably 50 μm or less, and more preferably 1 μm or more and 10 μm or less. The size of the atomized droplets is not particularly limited and may be, for example, about several mm.

[0051] In the film formation process, atomized droplets are transported to the substrate 20 by a carrier gas. The type of carrier gas is not particularly limited. The carrier gas may be, for example, oxygen, ozone, an inert gas (such as nitrogen or argon), or a reducing gas (such as hydrogen gas or forming gas). There may be one type of carrier gas, or two or more types. A diluted gas with a different carrier gas concentration (such as a 10-fold diluted gas) may also be used as a second carrier gas. The number of carrier gas supply locations may be two or more, rather than just one. The flow rate of the carrier gas is not particularly limited, but is preferably 1.0 LPM or less, and more preferably 0.1 LPM to 1.0 LPM.

[0052] The atomized droplets transported to the substrate 20 react to form a film on the substrate 20. The reaction is not particularly limited as long as it forms a film from the atomized droplets, but a thermal reaction is preferred. The thermal reaction is not particularly limited as long as the atomized droplets react due to heat, and the reaction conditions are not particularly limited. The thermal reaction is typically carried out at a temperature equal to or higher than the evaporation temperature of the solvent in the raw material solution. The thermal reaction is preferably carried out at a relatively low temperature, specifically, at a temperature of 650°C or lower. The thermal reaction may be carried out under any of the following conditions: vacuum, oxygen-free atmosphere, reducing gas atmosphere, and oxygen atmosphere. It may also be carried out under atmospheric pressure, pressurized atmosphere, or reduced pressure. The thermal reaction is preferably carried out under atmospheric pressure, as this simplifies the calculation of the evaporation temperature and simplifies the equipment. The thickness of the film formed in the film formation process can be set by adjusting the film formation time.

[0053] A preferred film formation apparatus for use in the forming process will be described below. The film formation apparatus 30 shown in Fig. 6 includes a carrier gas source 32a for supplying a carrier gas, a flow rate control valve 33a for adjusting the flow rate of the carrier gas delivered from the carrier gas source 32a, a carrier gas source 32b for supplying a carrier gas (diluted), i.e., a diluted carrier gas, a flow rate control valve 33b for adjusting the flow rate of the carrier gas (diluted) delivered from the carrier gas source 32b, an atomized droplet generating source 34 for storing a raw material solution 34a, a container 35 for containing water 35a, an ultrasonic vibrator 36 attached to the bottom of the container 35, a film formation chamber 37, a supply pipe 38 connecting the atomized droplet generating source 34 and the film formation chamber 37, and a hot plate (heater) 39 installed within the film formation chamber 37. The film formation chamber 37 is provided with an exhaust port 37a for discharging the atomized droplets and exhaust gas after the reaction.

[0054] The substrate 20 is placed on the hot plate 39. The raw material solution 34a is contained in the atomized droplet generating source 34. In this state, the hot plate 39 is operated, and the temperature inside the film formation chamber 37 is increased by the hot plate 39. Next, the flow rate control valves 33a, 33b are opened, and the carrier gas and the carrier gas (diluted) are supplied into the film formation chamber 37 from the carrier gas sources 32a, 32b. After the atmosphere in the film formation chamber 37 is sufficiently replaced with the carrier gas and the carrier gas (diluted), the flow rates of the carrier gas and the carrier gas (diluted) are adjusted, respectively. Next, the ultrasonic vibrator 36 vibrates. The vibration of the ultrasonic vibrator 36 propagates to the raw material solution 34a through the water 35a. As a result, the raw material solution 34a is atomized to generate atomized droplets 34b. The atomized droplets 34b are introduced into the film formation chamber 37 by the carrier gas and the carrier gas (diluted), and then transported to the vicinity of the substrate 20. Then, the atomized droplets 34b undergo a thermal reaction in the film-forming chamber 37 under atmospheric pressure, and a film is formed on the substrate 20.

[0055] Similar to the film formation apparatus 30, the film formation apparatus 40 shown in FIG. 7 includes a carrier gas source 32a, a flow rate control valve 33a, a carrier gas source 32b, a flow rate control valve 33b, an atomized droplet generating source 34, a container 35, and an ultrasonic vibrator 36. Additionally, the film formation apparatus 40 includes a supply pipe 42 to which atomized droplets are supplied from the atomized droplet generating source 34, a susceptor 41 disposed within the supply pipe 42, and a heater 43 disposed around the supply pipe 42. The supply pipe 42 essentially forms a film formation chamber. The supply pipe 42 is provided with an exhaust port 42a for discharging atomized droplets and exhaust gas after reaction. The susceptor 41 has a mounting surface on which the substrate 20 is placed. The mounting surface is inclined relative to the horizontal plane in the longitudinal direction of the supply pipe 42 so that the mounting surface is positioned higher as it approaches the exhaust port 42a. The film formation apparatus 40 can be operated in the same manner as the film formation apparatus 30 described above.

[0056] When the semiconductor film 2 is formed by the HVPE method, the forming step includes, for example, gasifying a metal source containing metal to generate a metal-containing source gas (hereinafter, this step is referred to as the "gasification step"), and supplying the metal-containing source gas and the oxygen-containing source gas to a crystalline substrate 20 placed in a reaction chamber, and forming the semiconductor film 2 on the substrate 20 by epitaxial growth of crystals (hereinafter, this step is referred to as the "film formation step"). In the film formation step, a reactive gas may be supplied to the substrate 20 in addition to the metal-containing source gas and the oxygen-containing source gas.

[0057] 8 shows a suitable film formation apparatus (HVPE apparatus) 50 used when forming a semiconductor film 2 by the HVPE method. The film formation apparatus 50 includes a reaction chamber 51, heaters 52a and 52b, a metal-containing source gas supply pipe 53b, and an oxygen-containing source gas supply pipe 55b. The film formation apparatus 50 may further include a reactive gas supply pipe 54b.

[0058] A metal source 57 and a substrate 20 are placed in the reaction chamber 51. The substrate 20 is held by, for example, a holder 56 provided inside the reaction chamber 51. A protective sheet 58 that prevents the reaction product from being deposited may be provided on the inner wall of the reaction chamber 51. A heater 52a heats the metal source 57. A heater 52b heats the substrate 20.

[0059] The metal-containing source gas supply pipe 53b and the oxygen-containing source gas supply pipe 55b are provided in the reaction chamber 51. The metal-containing source gas supply pipe 53b is provided in the reactive gas supply pipe 54b. The reactive gas supply pipe 54b and the metal-containing source gas supply pipe 53b form a double-pipe structure. The metal-containing source gas supply pipe 53b is connected to a halogen-containing source gas supply source 53a. A metal source 57 is provided in the metal-containing source gas supply pipe 53b. The halogen-containing source gas from the halogen-containing source gas supply source 53a is supplied to the metal-containing source gas supply pipe 53b. The halogen-containing source gas is supplied to the metal source 57 and becomes a metal-containing source gas. The metal-containing source gas is supplied to the substrate 20 via the metal-containing source gas supply pipe 53b. The oxygen-containing source gas supply pipe 55b is connected to the oxygen-containing source gas supply source 55a. The oxygen-containing source gas from the oxygen-containing source gas supply source 55a is supplied to the substrate 20 via an oxygen-containing source gas supply pipe 55b.

[0060] The metal source 57 is not particularly limited as long as it can be gasified, and may be a metal element or a metal compound. The metal source 57 contains the metal contained in the semiconductor film 2. The metal source 57 may be gallium element. The metal source 57 may be a gas, liquid, or solid. The metal source 57 is preferably a liquid.

[0061] The means for gasifying the metal source 57 is not particularly limited and may be a known means. The gasification of the metal source 57 is preferably carried out, for example, by halogenating the metal source 57. The halogenating agent used for the halogenation is, for example, contained in the halogen-containing source gas supplied from the halogen-containing source gas supply source 53a to the metal-containing source gas supply pipe 53b. The halogenating agent is not particularly limited and may be a known halogenating agent. Examples of the halogenating agent include halogen and hydrogen halide. Examples of halogen include fluorine, chlorine, bromine, and iodine. Examples of hydrogen halides include hydrogen fluoride, hydrogen chloride, hydrogen bromide, and hydrogen iodide. For halogenation, hydrogen halide is preferably used, and hydrogen chloride is more preferably used. The gasification of the metal source 57 is preferably carried out by supplying a halogen or hydrogen halide as a halogenating agent to the metal source 57 and reacting the metal source 57 with the halogen or hydrogen halide at a temperature equal to or higher than the vaporization temperature of the metal halide to form a metal halide. The halogenation reaction temperature is not particularly limited. For example, when the metal source 57 is gallium and the halogenating agent is HCl, the halogenation reaction temperature is preferably 900°C or less. The halogenation reaction temperature is more preferably 700°C or less, and even more preferably 400°C or more and 700°C or less. The metal-containing source gas is not particularly limited as long as it is a gas containing the metal of the metal source 57. Examples of the metal-containing source gas include metal halides (fluorides, chlorides, bromides, iodides, etc.).

[0062] The oxygen-containing source gas is, for example, O gas, CO gas, NO gas, NO gas, N2O gas, H2O gas, or O3 gas. The oxygen-containing source gas is preferably one or more gases selected from the group consisting of O2, H2O, and N2O, and more preferably contains O2. The oxygen-containing source gas may also contain CO2.

[0063] The reactive gas supply pipe 54b is provided inside the reaction chamber 51. The reactive gas supply pipe 54b is connected to the reactive gas supply source 54a. The reactive gas from the reactive gas supply source 54a is supplied to the substrate 20 through the reactive gas supply pipe 54b. The reaction chamber 51 is provided with a gas exhaust unit 59 that exhausts used gas.

[0064] The reactive gas is typically a gas with a different reactivity from the metal-containing source gas and the oxygen-containing source gas, and does not include an inert gas. The reactive gas is not particularly limited, but may be, for example, an etching gas. The etching gas is not particularly limited and may be a known etching gas. The reactive gas is preferably a halogen gas (e.g., fluorine gas, chlorine gas, bromine gas, or iodine gas), a hydrogen halide gas (e.g., hydrofluoric acid gas, hydrochloric acid gas, hydrogen bromide gas, hydrogen iodide gas), hydrogen gas, or a mixed gas of two or more of these, more preferably a hydrogen halide gas, and even more preferably hydrogen chloride. The metal-containing source gas, oxygen-containing source gas, or reactive gas may contain a carrier gas. The carrier gas is, for example, an inert gas such as nitrogen or argon. The partial pressure of the metal-containing source gas is not particularly limited, but is preferably 0.5 Pa to 1 kPa, more preferably 5 Pa to 0.5 kPa. The partial pressure of the oxygen-containing source gas is not particularly limited, but is preferably 0.5 to 100 times the partial pressure of the metal-containing source gas, and more preferably 1 to 20. The partial pressure of the reactive gas is also not particularly limited, but is preferably 0.1 to 5 times the partial pressure of the metal-containing source gas, and more preferably 0.2 to 3 times.

[0065] A dopant-containing gas may also be supplied to the substrate 20. The dopant-containing gas is not particularly limited as long as it contains the dopant contained in the semiconductor film 2. By using the dopant-containing gas, the conductivity of the resulting semiconductor film 2 can be easily controlled. The dopant-containing gas preferably contains the dopant in the form of a compound (e.g., halide, oxide, etc.), more preferably in the form of a halide. The partial pressure of the dopant-containing source gas is not particularly limited, but is preferably 1×10 of the partial pressure of the metal-containing source gas. -7 It is preferable that the ratio is 2.5×10 to 0.1 times. -6 7.5×10 times more -2 Preferably, the dopant-containing gas is supplied onto the substrate 20 together with the reactive gas.

[0066] By using the above-described film formation apparatuses 30, 40, and 50, a film can be easily formed on the substrate 20. The semiconductor film 2 is formed by epitaxial crystal growth.

[0067] In the structure 1A of the first embodiment described above, the edge separation portions 3 separating the multiple semiconductor films 2 can alleviate stress generated in the semiconductor films 2. The edge separation portions 3 also suppress the transmission of stress in the semiconductor films 2 between the multiple semiconductor films 2. This suppresses the occurrence of distortion or cracks in the semiconductor films 2 and warpage in the structure 1A, improving the handleability of the structure 1A and enabling a thicker film. Furthermore, by disposing the edge separation portions 3 between the multiple semiconductor films 2, even if a crack occurs in one of the adjacent semiconductor films 2, the crack is less likely to propagate to the other semiconductor film 2. This improves the yield of the structure 1A. Furthermore, when another layer, such as a semiconductor layer, is formed on each semiconductor film 2, the transmission of stress between the other layers can also be suppressed, making it less likely that cracks will occur in the other layers.

[0068] (Second embodiment) Next, a second embodiment will be described. Fig. 9 is a cross-sectional view showing a structure 1B of the second embodiment. Fig. 9 corresponds to Fig. 2 and is a cross-sectional view taken along line AA in Fig. 1. Note that structure 1B has elements in common with structure 1A of the first embodiment. Therefore, elements of structure 1B of the second embodiment that correspond to elements of structure 1A of the first embodiment are given the same reference numerals, and descriptions of matters in common with the first embodiment will be omitted.

[0069] In this embodiment, a groove is formed on the upper surface of the substrate 20 as the second region 22. The portion of the upper surface of the substrate 20 other than the groove is the first region 21. The cross-sectional shape of the groove as the second region 22 is, for example, a square-shaped, U-shaped, V-shaped, or arc-shaped.

[0070] In a cross section perpendicular to the longitudinal direction of the groove, which is the second region 22, the orientation of the inner surface of the groove changes stepwise or continuously. For example, in the case of a groove having a U-shaped cross section as shown in FIG. 9, the orientation of one side surface of the groove, the orientation of the bottom surface of the groove, and the orientation of the other side surface of the groove change stepwise. Also, in the case of a groove having a U-shaped or arc-shaped cross section, the orientation of the inner surface of the groove changes continuously from one side surface to the bottom surface and then to the other side surface. Because the orientation of the inner surface of the groove changes in this way, it is more difficult for crystals to grow epitaxially in the portion of the top surface of the substrate 20 corresponding to the groove than in the first region 21.

[0071] The grooves that are the second regions 22 have depths. The depth direction of the grooves substantially coincides with the thickness direction of the substrate 20. The depth of the grooves is preferably greater than the thickness of the plurality of semiconductor films 2. However, the depth of the grooves may be less than the thickness of the plurality of semiconductor films 2.

[0072] The grooves that are the second regions 22 have a width. The width of the groove is the dimension in a direction perpendicular to both the length direction and depth direction of the groove, i.e., the dimension in the direction in which the multiple semiconductor films 2 are arranged. The width of the groove is preferably wider than the thickness of the semiconductor film 2. The width of the groove is more preferably at least twice the thickness of the semiconductor film 2, and even more preferably at least three times the thickness of the semiconductor film 2. The width of the groove may be equal to or smaller than the thickness of the semiconductor film 2.

[0073] The groove edge 24, which is the second region 22, specifically the boundary between the upper surface of the substrate 20 and the side surface of the groove, may be located above the upper surface of the substrate 20. In this embodiment, the edges 24 on both sides in the width direction of the groove protrude above the upper surface of the substrate 20 (specifically, the portion of the upper surface of the substrate 20 excluding the edges 24). Such edges 24 can be formed, for example, by setting the laser wavelength, processing speed, number of repetitions, etc. to specific values ​​when irradiating the upper surface of the substrate 20 with a laser to form a groove. Note that the groove edge 24 may be flush with the upper surface of the substrate 20.

[0074] The edge cutting portion 3 is preferably formed on the groove, which is the second region 22 of the upper surface of the substrate 20. In this embodiment, the lower part of the edge cutting portion 3 is embedded in the groove, and the upper part of the edge cutting portion 3 protrudes from the groove above the upper surface of the substrate 20.

[0075] It is preferable that at least a part of the upper surface of the edge cutting portion 3 is located lower than the upper surfaces of the plurality of semiconductor films 2. In this embodiment, a recess is formed in the upper surface of the edge cutting portion 3, and a part of the recess is located lower than the upper surfaces of the plurality of semiconductor films 2. The entire upper surface of the edge cutting portion 3 may be located lower than the upper surfaces of the semiconductor films 2. Also, a part or the entire upper surface of the edge cutting portion 3 may be located higher than the upper surfaces of the plurality of semiconductor films 2. Also, the upper surface of the edge cutting portion 3 and the upper surfaces of the plurality of semiconductor films 2 may be flush with each other.

[0076] Next, an example of a method for manufacturing structure 1B will be described. Fig. 10 is a flowchart showing a method for manufacturing structure 1B. The method for manufacturing structure 1B may further include cleaning substrate 20 (hereinafter, this step will be simply referred to as the "cleaning step") in addition to the steps of the method for manufacturing structure 1A of the first embodiment.

[0077] In the second region forming step of this embodiment, instead of forming a rough surface on the upper surface of the substrate 20, grooves that become the second regions 22 are formed on the upper surface of the substrate 20. FIG. 11 is a cross-sectional view that schematically shows the substrate 20 on which grooves have been formed. The grooves are formed, for example, by irradiating only a portion of the upper surface of the substrate 20 with a laser. It is preferable that edges 24 on both sides of the groove protrude above the upper surface of the substrate 20.

[0078] The cleaning step is performed after the second region forming step. In the cleaning step, the upper surface of the substrate 20 is cleaned, including the grooves that form the second regions 22. In the cleaning step, cleaning is performed using, for example, a chemical solution such as a cleaning solution containing hydrofluoric acid or water.

[0079] The forming process is performed after the cleaning process. In the forming process, for example, as in the first embodiment, a material such as atomized droplets is supplied to a plurality of first regions 21 and second regions 22. As a result, epitaxial growth occurs in the first region 21 to form the semiconductor film 2. Meanwhile, in the grooves of the second region 22, crystals having an amorphous structure or a crystal structure different from that of the semiconductor film 2 are formed. The amorphous structure or the crystals having a crystal structure different from that of the semiconductor film 2 formed in the grooves of the second region 22 in this way become the edge cutting portion 12. In the portion of the upper surface of the edge cutting portion 12 formed in this way that corresponds to the groove, a recess is formed, for example, as shown in FIG. 9. Furthermore, in the portion of the upper surface of the edge cutting portion 12 that corresponds to the edge 24 of the groove, a protrusion that protrudes above the upper surface of the semiconductor film 2 is formed.

[0080] In the structure 1B of the second embodiment, the edge cutting portion 3 also reduces stress generated in the semiconductor film 2. Additionally, a recess is formed in the upper surface of the edge cutting portion 3 in a portion corresponding to the groove. This recess is located between adjacent semiconductor films 2 and contributes to reducing stress in the semiconductor film 2. Furthermore, because the groove edge 24 is located higher than other portions of the upper surface of the substrate 20, stress in the semiconductor film 2 is less likely to be transmitted to the edge cutting portion 12, further reducing the transmission of stress in the semiconductor film 2 between multiple semiconductor films 2. Furthermore, by performing a cleaning process after the second region formation process as in this embodiment, even if debris or the like is generated on the substrate 20 during the second region formation process, this debris or the like can be removed. This further improves the quality of the structure 1B.

[0081] (Third embodiment) Next, a third embodiment will be described. Note that the structure 1C of the third embodiment has elements in common with the structure 1A of the first embodiment. Therefore, among the elements of the structure 1C of the third embodiment, elements corresponding to the elements of the structure 1A of the first embodiment are assigned the same reference numerals, and descriptions of matters in the third embodiment that are common to the first embodiment will be omitted.

[0082] FIG. 12 shows a structure 1C of a third embodiment. FIG. 12 corresponds to FIG. 2 and is a cross-sectional view taken along line AA in FIG. 1. In this embodiment, the edge cutting portion 3 contains a compound different from the compound contained in the crystalline oxide. Note that, in this embodiment as well, the structure 1C may further include a layer formed on the plurality of semiconductor films 2 and / or the edge cutting portion 3. The layer formed on the plurality of semiconductor films 2 and / or the edge cutting portion 3 is, for example, another semiconductor layer such as an n+ layer or a p layer.

[0083] The upper surface of the substrate 20 in this embodiment does not include the second region 22. A plurality of semiconductor films 2 and an edge termination portion 3 are formed on the upper surface of the substrate 20. The edge termination portion 3 covers a portion of the upper surface of the substrate 20. That is, the edge termination portion 3 functions as a mask. The edge termination portion 3 may be formed from an insulating material, a conductive material, or a semiconductor material. The material of the edge termination portion 3 may be amorphous, single crystal, or polycrystalline. The material of the edge termination portion 3 is, for example, an oxide, nitride, carbide, carbon, diamond, or metal such as Si, Ge, Ti, Zr, Hf, Ta, or Sn, or a mixture thereof. The material of the edge termination portion 3 is preferably a Si-containing compound containing SiO2, SiN, or polycrystalline silicon as a main component, or a metal having a melting point higher than the crystal growth temperature of the crystalline oxide (e.g., a noble metal such as platinum, gold, silver, palladium, rhodium, iridium, or ruthenium). These materials are preferably the main components of the entire edge cutting portion 3. That is, these materials preferably account for 50% or more of the entire edge cutting portion 3 in terms of composition ratio. These materials preferably account for 70% or more of the entire edge cutting portion 3 in terms of composition ratio, and more preferably 90% or more.

[0084] The edge cutting portion 3 is formed directly on the substrate 20 and is in contact with the plurality of semiconductor films 2. The portion of the upper surface of the substrate 20 where the edge cutting portion 3 is formed may be smooth like the other portions.

[0085] Fig. 13 is an enlarged view of part B in Fig. 12. In order to make it even more difficult for the semiconductor films 2 to come into contact with each other, it is preferable that the thickness T1 of the edge cutting portion 3 is smaller than the thickness T2 of the semiconductor films 2. In other words, it is preferable that the upper end of the edge cutting portion 3 is located lower than the upper surfaces of the semiconductor films 2. Furthermore, it is preferable that the difference between the thickness T2 of the semiconductor films 2 and the thickness T1 of the edge cutting portion 3 is smaller than the width W of the edge cutting portion 3.

[0086] Furthermore, the width W of the edge cutting portion 3 is W / 2>t·(V L It is preferable that the relationship of V / V is satisfied. Lis the crystal growth rate of the semiconductor film 2 in the width direction of the edge cutoff portion 3, and V v is the crystal growth rate of the semiconductor film 2 in the vertical direction, and t is the difference between the thickness T2 of the multiple semiconductor films 2 and the thickness T1 of the edge cutting portion 3, more specifically, the thickness of the semiconductor film 2 at one end of the edge cutting portion 3 in the width direction.

[0087] [Table 1] Table 1 shows the ratio of the growth rate of laterally grown films to that of vertically grown films for combinations of the a-plane, c-plane, and m-plane growth planes. Table 1 also shows the test results for epitaxially growing α-Ga2O3 semiconductor films using the mist CVD method. In Test Examples 1 to 6, the film formation temperature was 550°C. In Test Examples 7 to 12, the film formation temperature was 450°C.

[0088] For example, when the surface of the substrate 20 is an m-plane and the width direction of the edge cutting portion 3 is the c-axis direction, L / Vv" can be 1.964, which is the ratio of growth rates in Test Example 2. In this case, the width W of the edge cutting portion 3 satisfies the relationship W / 2>1.964t, so that the plurality of semiconductor films 2 are less likely to come into contact with each other. Note that the thickness T1 of the edge cutting portion 3 and the thickness T2 of the semiconductor film 2 are not limited in the present disclosure. For example, the width W of the edge cutting portion 3 can be set to W / 2≦t·(V L / Vv) The difference t between the thickness T2 of the plurality of semiconductor films 2 and the thickness T1 of the edge cutting portion 3 may be equal to or greater than the width W of the edge cutting portion 3.

[0089] Next, an example of a method for manufacturing structure 1C will be described. Fig. 14 is a flowchart showing a method for manufacturing structure 1C. Fig. 15 is a cross-sectional view showing substrate 20 on which edge cutting portion 3 is formed in this embodiment. The method for manufacturing structure 1C in this embodiment does not include a second region forming step.

[0090] The edge cutting portion forming step is performed after the substrate preparation step. In the edge cutting portion forming step, an edge cutting portion 3 is formed on the substrate 20 prepared in the substrate preparation step, i.e., the substrate 20 having a smooth upper surface as shown in FIG. 4. In the edge cutting portion forming step, the edge cutting portion 3 is formed only on a part of the upper surface of the substrate 20 as shown in FIG. 15. The means for forming the edge cutting portion 3 may be a known means, and examples thereof include known patterning processing means such as photolithography, electron beam lithography, laser patterning, and subsequent etching (e.g., dry etching or wet etching). On the upper surface of the substrate 20, the portion where the edge cutting portion 3 is formed becomes a portion where it is difficult for crystals to grow epitaxially.

[0091] The semiconductor film forming process is performed after the edge cutting portion forming process. In the semiconductor film forming process, atomized droplets are supplied onto the substrate 20 on which the edge cutting portion 3 is formed. As a result, crystals made of atomized droplets grow epitaxially on the portion of the upper surface of the substrate 20 where the edge cutting portion 3 is not formed, forming a semiconductor film 2. On the other hand, epitaxial growth of crystals is difficult on the portion of the upper surface of the substrate 20 covered by the edge cutting portion 3. Therefore, for example, as shown in FIG. 12, the semiconductor film 2 is not formed on at least a portion of the edge cutting portion 3, and gaps are formed between the multiple semiconductor films 2. In other words, the multiple semiconductor films 2 are separated by the edge cutting portion 3 and the gaps above the edge cutting portion 3. Note that a portion of the semiconductor film 2 may or may not be formed on the edge cutting portion 3. Furthermore, crystals having an amorphous structure or a crystal structure different from the crystal structure of the semiconductor film 2 may be formed on the edge cutting portion 3.

[0092] Fig. 16 shows a structure 1D according to a modified example of this embodiment. Fig. 16 corresponds to Fig. 12 and is a cross-sectional view taken along line AA in Fig. 1. In this example, the thickness of the edge cutting portion 3 is greater than the thickness of the semiconductor films 2, and the upper end of the edge cutting portion 3 is located above the upper surfaces of the semiconductor films 2. Although not shown, the thickness of the edge cutting portion 3 may be the same as the thickness of the semiconductor films 2, and the upper end of the edge cutting portion 3 may be flush with the upper surfaces of the semiconductor films 2.

[0093] FIG. 17 shows a structure 1E according to another modification of this embodiment. FIG. 17 corresponds to FIG. 12 and is a cross-sectional view taken along line AA in FIG. 1. In this example, the multiple semiconductor films 2 and the edge cutting portion 3 are formed on a substrate 20 via another layer 4. The other layer 4 is, for example, a semiconductor film. The other layer 4 preferably contains the same components as the multiple semiconductor films 2. The other layer 4 preferably has the same crystalline structure as the multiple semiconductor films 2. It is more preferable that the main component of the other layer 4 is the same as the main component of the multiple semiconductor films 2, and that the crystalline structure of the other layer 4 is the same as the crystalline structure of the multiple semiconductor films 2. The other layer 4 may contain a different component from the components of the multiple semiconductor films 2, or may have a different crystalline structure from the crystalline structure of the multiple semiconductor films 2. The other layer 4 may also be a layer other than a semiconductor film. The other layer 4 may be formed, for example, by the same means as the multiple semiconductor films 2 of the first embodiment. In this example, the upper end of the edge cutting portion 3 is located below the upper surfaces of the plurality of semiconductor films 2, but it may be located above the upper surfaces of the plurality of semiconductor films 2, as in the modified example shown in FIG.

[0094] In the structure 1C, 1D, or 1E of the third embodiment, the edge cutting portion 3 can also reduce stress generated in the semiconductor film 2. In addition, a void is formed on the edge cutting portion 3. This void is disposed between adjacent semiconductor films 2, and further contributes to reducing stress in the semiconductor film 2.

[0095] (Semiconductor Devices) The structures 1A to 1E are useful for semiconductor devices, particularly power devices. The semiconductor devices including the structures 1A to 1E may be vertical or horizontal devices. A vertical device is a device in which electrodes are arranged on both sides of the structures 1A to 1E in the thickness direction. A horizontal device is a device in which electrodes are arranged on only one side of the structures 1A to 1E in the thickness direction. The structures 1A to 1E may be used as a semiconductor layer of a semiconductor device, for example, after being peeled off from the substrate 20. The structures 1A to 1E may be used by being arranged on another substrate having higher thermal conductivity than the substrate 20, for example. Suitable examples of semiconductor devices include transistors such as MESFETs (metal semiconductor field effect transistors), MOSFETs (metal oxide semiconductor field effect transistors), MISFETs (metal insulating film semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), HEMTs (high electron mobility transistors), JFETs (junction field effect transistors), and SITs (static induction transistors), TFTs, SBDs (Schottky barrier diodes) and JBSs (junction barrier Schottky diodes) that utilize semiconductor-metal junctions, PN or PIN diodes combined with other P layers, LEDs (light emitting diodes), and light emitting and receiving elements.

[0096] Hereinafter, preferred examples of semiconductor devices incorporating all or part of structures 1A, 1B, 1C, 1D, or 1E will be described. The semiconductor film 2 included in structures 1A to 1E may be an n-type semiconductor or a p-type semiconductor in the semiconductor device. Furthermore, when the semiconductor device includes multiple semiconductor layers, all of the multiple semiconductors may be semiconductor film 2, or only some of the multiple semiconductor layers may be semiconductor film 2. When the semiconductor device includes an n-type semiconductor layer and a p-type semiconductor layer, each of the n-type semiconductor layer and the p-type semiconductor layer may be semiconductor film 2.

[0097] FIG. 18 is a cross-sectional view schematically illustrating an example semiconductor device 100. The semiconductor device 100 is an SBD. The semiconductor device 100 includes a semiconductor layer 101, a first electrode 104, and a second electrode 105. The semiconductor layer 101 includes an n+ type semiconductor layer 102 and an n- type semiconductor layer 103. The n+ type semiconductor layer 102 and the n- type semiconductor layer 103 are aligned in the thickness direction of the semiconductor layer 101. The surface of the n- type semiconductor layer 103 opposite to the n+ type semiconductor layer 102 forms a first surface 101a, which is one surface of the semiconductor layer 101 in the thickness direction. The surface of the n+ type semiconductor layer 102 opposite to the n- type semiconductor layer 103 forms a second surface 101b, which is the surface of the semiconductor layer 101 opposite to the first surface 101a. The first electrode 104 is disposed on the first surface 101a. The first electrode 104 is a Schottky electrode. The second electrode 105 is disposed on the second surface 101b. The second electrode 105 is an ohmic electrode.

[0098] The material of each of the first electrode 104 and the second electrode 105 may be a known electrode material. Examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof, conductive metal oxide films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures and laminates thereof.

[0099] The method for forming the first electrode 104 and the second electrode 105 is not particularly limited. The method for forming the first electrode 104 and the second electrode 105 can be appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into account their suitability for the materials. The first electrode 104 and the second electrode 105 may each be formed using two types of metal, a first metal and a second metal. In this case, the first electrode 104 or the second electrode 105 may be formed by stacking a layer made of the first metal and a layer made of the second metal, and then patterning the layer made of the first metal and the layer made of the second metal using a photolithography technique.

[0100] When a forward voltage is applied to the semiconductor device 100, electrons flow from the second electrode 105 to the first electrode 104. When a reverse voltage is applied to the semiconductor device 100, the depletion layer expands into the n-type semiconductor layer 103, resulting in a high-voltage SBD.

[0101] FIG. 19 is a cross-sectional view schematically illustrating another example of a semiconductor device 200. The semiconductor device 200 is a JBS. The semiconductor device 200 includes a semiconductor layer 201, a barrier height adjusting region 202, a first electrode 203, and a second electrode 204. The semiconductor layer 201 may be a single layer or may include multiple semiconductor layers. The semiconductor layer 201 has a first surface 201a, which is one surface of the semiconductor layer 201 in the thickness direction, and a second surface 201b, which is the surface opposite to the first surface 201a. The barrier height adjusting region 202 is formed on the first surface 201a. The first electrode 203 is formed on the first surface 201a so as to be in contact with both the semiconductor layer 201 and the barrier height adjusting region 202. The first electrode 203 is a barrier electrode that forms a Schottky barrier between the first electrode 203 and the semiconductor layer 201. The second electrode 204 is formed on the second surface 201b. The second electrode 204 is an ohmic electrode.

[0102] The barrier height adjustment region 202 is formed between the semiconductor layer 201 and the first electrode 203. The barrier height adjustment region 202 forms a Schottky barrier between the semiconductor layer 201 and the first electrode 203, the barrier height adjustment region 202 having a barrier height greater than that of the Schottky barrier of the first electrode 203. In this example, a plurality of trenches 201c are formed in the first surface 201a of the semiconductor layer 201. The barrier height adjustment region 202 is embedded in each trench 201c. The barrier height adjustment region 202 is preferably provided at regular intervals. The barrier height adjustment region 202 is preferably provided at least between both ends of the first electrode 203 and the semiconductor layer 201.

[0103] The material of each of the first electrode 203 and the second electrode 204 may be a known electrode material. The electrode material may be the same as the material of each of the first electrode 104 and the second electrode 105 of the semiconductor device 100. Each of the first electrode 203 and the second electrode 204 may be formed by a known method, such as a vacuum deposition method or a sputtering method. Each of the first electrode 203 and the second electrode 204 may be formed in the same manner as each of the first electrode 104 and the second electrode 105 of the semiconductor device 100. The same applies to the material and formation of each of the electrodes of the semiconductor devices 300, 400, 500, 600, 700, and 800 described below.

[0104] FIG. 20 is a cross-sectional view schematically illustrating a semiconductor device 300 according to another embodiment. The semiconductor device 300 is a JBS. Like the semiconductor device 200, the semiconductor device 300 includes a semiconductor layer 201, a barrier height adjusting region 202, a first electrode 203, and a second electrode 204. In addition, the semiconductor device 300 further includes a guard ring 305 formed on the semiconductor layer 201. In this embodiment, the semiconductor device 300 includes a plurality of guard rings 305. The guard rings 305 are positioned around the first electrode 203. At least a portion of the guard rings 305 is embedded in the semiconductor layer 201. By providing the guard rings 305, the breakdown voltage of the semiconductor device 300 can be improved, resulting in a semiconductor device with better semiconductor characteristics.

[0105] The guard ring 305 is typically made of a material with a high barrier height. Examples of materials used for the guard ring 305 include conductive materials with a barrier height of 1 eV or greater. The material for the guard ring 305 may be the same material as the electrode material. The material for the guard ring 305 may be any of the metals exemplified as the materials for the first electrode 104 and the second electrode 105 of the semiconductor device 100. In this case, the design freedom for the voltage-resistant structure is high, allowing for the provision of multiple guard rings 305, thereby flexibly improving the voltage resistance. The shape of the guard ring 305 is not particularly limited. Examples of the shape of the guard ring 305 include a square shape, a circular shape, a U-shape, an L-shape, and a strip shape. The number of guard rings 305 included in the semiconductor device 300 is also not particularly limited. The semiconductor device 300 preferably includes three or more guard rings 305, and more preferably six or more guard rings 305.

[0106] FIG. 21 is a cross-sectional view schematically illustrating a semiconductor device 400 according to another embodiment. The semiconductor device 400 is an LED. The semiconductor device 400 includes an n-type semiconductor layer 401, a light-emitting layer 402, a p-type semiconductor layer 403, a translucent electrode 404, a first electrode 405, and a second electrode 406. The light-emitting layer 402 is formed on the n-type semiconductor layer 401. The light-emitting layer 402 emits light. The p-type semiconductor layer 403 is formed on the light-emitting layer 402. The translucent electrode 404 is formed on the p-type semiconductor layer 403. The translucent electrode 404 is translucent. Therefore, light generated in the light-emitting layer 402 passes through the translucent electrode 404. The first electrode 405 is formed on the translucent electrode 404. The first electrode 405 is an anode electrode. The second electrode 406 is formed on the surface of the n-type semiconductor layer 401 opposite to the light emitting layer 402. The second electrode 406 is a cathode electrode. The semiconductor device 400 may be covered with a protective layer except for the electrode portion.

[0107] 22 is a cross-sectional view schematically showing yet another example of a semiconductor device 500. The semiconductor device 500 is a MOSFET, more specifically, a trench MOSFET. The semiconductor device 500 includes a first n+ type semiconductor layer 501, an n- type semiconductor layer 502, a p-type semiconductor layer 503, a second n+ type semiconductor layer 504, an insulating film 505, a first electrode 506, a second electrode 507, and a third electrode 508.

[0108] The n-type semiconductor layer 502 is formed on the first n+ type semiconductor layer 501. The p-type semiconductor layer 503 is formed on the n- type semiconductor layer 502. The second n+ type semiconductor layer 504 is formed on the p-type semiconductor layer 503. The first electrode 506 is formed on the second n+ type semiconductor layer 504. The first electrode 506 is a source electrode. The second electrode 507 is formed on the surface of the first n+ type semiconductor layer 501 opposite to the n- type semiconductor layer 502. The second electrode 507 is a drain electrode. A plurality of trenches 509 are formed on the surface of the semiconductor layer formed from the n- type semiconductor layer 502, the p-type semiconductor layer 503, and the second n+ type semiconductor layer 504 on the first electrode 506 side. Each of the plurality of trenches 509 penetrates the second n+ type semiconductor layer 504 and the p-type semiconductor layer 503 to reach the n- type semiconductor layer 502. A third electrode 508 is buried in each trench 509 via an insulating film 505. The third electrode 508 is a gate electrode.

[0109] 23 is a cross-sectional view schematically showing another example of a semiconductor device 600. The semiconductor device 600 is an IGBT. The semiconductor device 600 includes a p-type semiconductor layer 601, an n-type semiconductor layer 602, an n-type semiconductor layer 603, a p-type semiconductor region 604, an n+ type semiconductor region 605, an insulating film 606, and a plurality of first electrodes 607, second electrodes 608, and third electrodes 609.

[0110] The n-type semiconductor layer 602 is formed on the p-type semiconductor layer 601. The n-type semiconductor layer 603 is formed on the n-type semiconductor layer 602. A plurality of trenches 603a are formed on the surface of the n-type semiconductor layer 603 opposite to the n-type semiconductor layer 602. A p-type semiconductor region 604 is formed inside each of the plurality of trenches 603a. An n+ type semiconductor region 605 is formed inside each of the p-type semiconductor regions 604. An insulating film 606 is formed on the n-type semiconductor layer 603 so as to be in contact with the n-type semiconductor layer 603, the p-type semiconductor region 604, and the n+ type semiconductor region 605. Each of the plurality of first electrodes 607 is formed on the p-type semiconductor region 604 so as to be in contact with the p-type semiconductor region 604 and the n+ type semiconductor region 605. Each of the first electrodes 607 is an emitter electrode. The second electrode 608 is formed on the surface of the p-type semiconductor layer 601 opposite to the n-type semiconductor layer 602. The second electrode 608 is a collector electrode. The third electrode 609 is formed on the insulating film 606. The third electrode 609 is a gate electrode.

[0111] FIG. 24 is a cross-sectional view schematically illustrating a semiconductor device 700 according to another example. The semiconductor device 700 is a HEMT. The semiconductor device 700 includes a semi-insulating layer 701, a buffer layer 702, a first n-type semiconductor layer 703, a second n-type semiconductor layer 704, a plurality of n+ type semiconductor layers 705, a first electrode 706, a second electrode 707, and a third electrode 708. The buffer layer 702 is formed on the semi-insulating layer 701. The first n-type semiconductor layer 703 is formed on the buffer layer 702. The second n-type semiconductor layer 704 is formed on the first n-type semiconductor layer 703. The band gap of the second n-type semiconductor layer 704 is wider than the band gap of the first n-type semiconductor layer 703. The plurality of n+ type semiconductor layers 705 are embedded in the first n-type semiconductor layer 703 and the second n-type semiconductor layer 704. The n+ type semiconductor layer 705 is in contact with the first n-type semiconductor layer 703 and the second n-type semiconductor layer 704. A first electrode 706 and a second electrode 707 are formed on each of the n+ type semiconductor layers 705. The first electrode 706 is a source electrode. The second electrode 707 is a drain electrode. A third electrode 708 is formed on the second n-type semiconductor layer 704. The third electrode 708 is a gate electrode.

[0112] 25 is a cross-sectional view schematically showing a semiconductor device 800 according to another example. The semiconductor device 800 is a JFET. The semiconductor device 800 includes a first n+ type semiconductor layer 801, an n- type semiconductor layer 802, a second n+ type semiconductor layer 803, a first electrode 804, a second electrode 805, and a third electrode 806. The n- type semiconductor layer 802 is formed on the first n+ type semiconductor layer 801. The second n+ type semiconductor layer 803 is formed on the n- type semiconductor layer 802. The first electrode 804 is formed on the second n+ type semiconductor layer 803. The first electrode 804 is a source electrode. In the layer formed by the n-type semiconductor layer 802, the second n+ type semiconductor layer 803, and the first electrode 804, a plurality of trenches 807 are formed, which extend from the surface of the first electrode 804 opposite the n+ type semiconductor layer 803, through the first electrode 804 and the second n+ type semiconductor layer 803, and reach the n- type semiconductor layer 802. The second electrode 805 is formed on the surface of the first n+ type semiconductor layer 801 opposite the n- type semiconductor layer 802. The third electrode 806 is formed at the bottom of each trench 807. The third electrode 806 is in contact with the n- type semiconductor layer 802. The third electrode 806 is a gate electrode.

[0113] In addition to the above, semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800 can be suitably used as power modules, inverters, or converters using known methods, and can also be suitably used in semiconductor systems using power supply devices, etc. The power supply device can be fabricated using known methods by connecting semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800 to a wiring pattern, etc.

[0114] Fig. 26 is a block diagram of an example power supply system 900. The power supply system 900 includes a plurality of power supply devices 901 and 902 and a control circuit 903. Fig. 27 is a block diagram of an example system device 910. The system device 910 includes the power supply system 900 and an electronic circuit 911.

[0115] Figure 28 is a circuit diagram showing the power supply circuit of an example power supply device. This power supply circuit includes a power circuit and a control circuit. This power supply circuit uses inverter 921 (comprised of MOSFETs A to D) to switch DC voltage at high frequency to convert it to AC, then transforms and insulates the voltage using transformer 922, rectifies the voltage using rectifier MOSFET 923, and smooths it using DCL 924 (smoothing coils L1 and L2) and a capacitor to output a DC voltage. At this time, voltage comparator 925 compares the output voltage with a reference voltage, and PWM control circuit 926 controls inverter 921 and rectifier MOSFET 923 to achieve the desired output voltage.

[0116] (Example) Examples of the present disclosure will be described below, but the present disclosure is not limited to these.

[0117] Example 1 1.Film forming equipment To fabricate the structure, a film formation apparatus 40 shown in Fig. 7 was prepared. A quartz tube with an inner diameter of 40 mm was used as the supply pipe 42. A susceptor 41 made of quartz was used. The reason that both the supply pipe 42 and the susceptor 41 were made of quartz was to prevent impurities from the apparatus from being mixed into the semiconductor film.

[0118] 2. Preparation of the Stock Solution Gallium bromide was mixed with ultrapure water to a concentration of 0.1 mol / L, and hydrobromic acid was added at a volume ratio of 10%. This was used as raw material solution 34a.

[0119] 3. Substrate Preparation A sapphire substrate was prepared as substrate 20, and a short wavelength laser (pulsed solid state laser, laser wavelength 532 nm, processing speed 200 mm / s, repetition rate 1 time) was irradiated onto a portion of the upper surface of this substrate 20, thereby forming a second region with large surface roughness on the upper surface of substrate 20 as shown in Fig. 29. Thereafter, the upper surface of substrate 20 was cleaned with hydrofluoric acid.

[0120] 4. Film preparation preparation The raw material solution 34a obtained in 2 above was placed in the atomized droplet generating source 34. Next, the substrate 20 prepared in 3 was placed on the susceptor 41, and the temperature of the heater 43 was raised to 500°C. Next, the flow rate control valves 33a and 33b were opened, and carrier gas was supplied from the carrier gas sources 32a and 32b into the supply pipe 42, and the atmosphere in the supply pipe 42 was thoroughly replaced with the carrier gas. Thereafter, the flow rate of the carrier gas from the carrier gas source 32a was adjusted to 5.0 L / min, and the flow rate of the carrier gas (diluted) from the carrier gas source 32b was adjusted to 0.5 L / min. Note that oxygen was used as the carrier gas.

[0121] 5. Film formation After step 4, ultrasonic vibrator 36 was vibrated, and the vibrations were propagated to raw material solution 34a through water 35a, thereby atomizing raw material solution 34a and generating atomized droplets. These atomized droplets were transported to supply pipe 42 by carrier gas, and under atmospheric pressure at 500°C, the atomized droplets thermally reacted near the surface of substrate 20 to form structure 1A on substrate 20, including a plurality of semiconductor films 2 and edge cutting portions 3.

[0122] Example 2 A structure was fabricated in the same manner as in Example 1. However, a groove was formed as the second region on the upper surface of substrate 20 by irradiating it with a long wavelength laser (SHG laser, laser wavelength 655 nm, processing speed 200 mm / s, repetition number 4). Figure 30 is a photograph of the cross section of the obtained structure taken with an SEM.

[0123] Example 3 A structure was fabricated in the same manner as in Example 1. However, instead of forming the second region by irradiating the upper surface of the substrate 20 with a laser, a cutting portion 3 made of SiO2 was formed by photolithography.

[0124] (Comparative Example) A structure was produced in the same manner as in Example 1. However, on the upper surface of the substrate 20, none of the portions with high surface roughness in Example 1, the grooves in Example 2, and the edge cutting portion 3 in Example 3 were formed.

[0125] (evaluation) The surfaces of the structures of Examples 1 to 3 and the Comparative Example were observed using an optical microscope. Fig. 31 is a photograph of the surface of the structure obtained in Example 3 taken with an optical microscope. Fig. 32 is a photograph of the surface of the structure obtained in the Comparative Example taken with an optical microscope. In any of the structures of Examples 1 to 3, no cracks were observed on the surface of the semiconductor film, as shown in Fig. 31. Cracks were observed on the surface of the semiconductor film in the structure of the Comparative Example, as shown in Fig. 32.

[0126] The following additional notes are provided regarding this disclosure.

[0127] (Appendix 1) A structure comprising a substrate, a plurality of semiconductor films each having a crystalline oxide, the semiconductor films being disposed adjacent to each other on the substrate directly or via another layer, and an edge separation portion separating the plurality of semiconductor films from each other.

[0128] (Appendix 2) 2. The structure according to claim 1, wherein the edge cutting portion has an amorphous structure or a crystalline structure different from the crystalline structure of the plurality of semiconductor films.

[0129] (Appendix 3) 3. The structure of claim 2, wherein the crystalline oxide and the edge portion each contain gallium.

[0130] (Appendix 4) 4. The structure according to any one of claims 1 to 3, wherein the upper end of the edge cutting portion is located above the plurality of semiconductor films.

[0131] (Appendix 5) 5. The structure according to any one of claims 1 to 4, wherein the width of the edge cutoff portion is three times or more the thickness of the plurality of semiconductor films.

[0132] (Appendix 6) 6. The structure according to any one of claims 1 to 5, wherein a groove deeper than the thickness of the semiconductors is formed on the surface of the substrate, and the edge cutting portion is located on the groove.

[0133] (Appendix 7) 7. The structure of claim 6, wherein the edge of the groove is located above the surface of the substrate.

[0134] (Appendix 8) a region in which crystal growth is less likely to occur than in other regions is formed in a portion of the surface of the substrate; 6. The structure according to any one of claims 1 to 5, wherein the edge cutting portion is formed in the region.

[0135] (Appendix 9) 6. The structure according to any one of claims 1 to 5, wherein the edge cutting portion contains a compound different from the compound contained in the crystalline oxide.

[0136] (Appendix 10) 10. The structure according to claim 9, wherein a difference between the thickness of the semiconductor films and the thickness of the edge cutting portion is smaller than a width of the edge cutting portion.

[0137] (Appendix 11) 11. The structure according to any one of claims 1 to 10, wherein the crystalline oxide has a corundum structure.

[0138] (Appendix 12) A structure comprising a plurality of semiconductor films adjacent to each other and each having a crystalline oxide, and an edge separation portion separating the plurality of semiconductor films from each other.

[0139] (Appendix 13) A method for manufacturing a structure, comprising: roughening a portion of a surface of a substrate to form a rough surface; forming an edge cutting portion on the rough surface; and forming a plurality of semiconductor films, each having a crystalline oxide, separated by the edge cutting portion on a portion of the surface of the substrate other than the rough surface.

[0140] (Appendix 14) A method for manufacturing a structure, comprising: forming a groove on a surface of a substrate; forming an edge cutting portion in the groove; and forming a plurality of semiconductor films, each having a crystalline oxide, separated by the edge cutting portion on a portion of the surface of the substrate other than the groove.

[0141] (Appendix 15) A method for manufacturing a structure, comprising: forming an edge cutting portion on a portion of a surface of a substrate; and forming a plurality of semiconductor films, each having a crystalline oxide, separated by the edge cutting portion on a portion of the surface of the substrate other than the edge cutting portion. [Industrial Applicability]

[0142] The structure of the present disclosure can be used in a wide range of fields, including semiconductor devices (e.g., compound semiconductor electronic devices), electronic components and electrical equipment parts, optical and electrophotographic related devices, and industrial materials, but is particularly useful in semiconductor devices and the like. [Explanation of symbols]

[0143] L1 Smoothing coil L2 Smoothing coil 1A Structure 1B structure 1C structure 1D Structure 1E structure 2. Semiconductor film 3 Edge incision 4 layers 12 Edge incision 20 PCB 21 First area 22 Second area (area) 24 Groove Edge 30 Film deposition equipment 32a Carrier gas source 32b Carrier gas (dilution) source 33a Flow control valve 33b Flow control valve 34 Atomized droplet source 34a Raw material solution 34b Atomized droplets 35 Container 35a water 36 Ultrasonic transducer 37 Deposition chamber 37a Exhaust port 38 Supply pipe 39 Hot Plate 40 Film deposition equipment 41 Susceptor 42 Supply pipe 42a Exhaust port 43 Heater 44 Exhaust port 50 Film deposition equipment 51 Reaction chamber 52a Heater 52b Heater 53a Halogen-containing source gas supply pipe 53b Metal-containing raw material gas supply pipe 54a Reactive gas supply reduction 54b Reactive gas supply pipe 55a Oxygen-containing raw gas supply pipe 55b Oxygen-containing raw gas supply pipe 56 Holder 57 Metal sources 58 Protective Sheet 59 Gas exhaust section 100 Semiconductor device 101 n-type semiconductor layer 101a 1st page 101b 2nd page 102 n+ type semiconductor layer 103 n-type semiconductor layer 104 First electrode 105 Second electrode 200 Semiconductor device 201 Semiconductor layer 201a 1st page 201b 2nd page 201c Trench 202 Barrier Height Adjustment Area 203 First electrode 204 Second electrode 300 Semiconductor device 305 Guard Ring 400 Semiconductor Devices 401 n-type semiconductor layer 402 Light-emitting layer 403 p-type semiconductor layer 404 Translucent electrode 405 First electrode 406 Second electrode 500 Semiconductor devices 501 First n+ type semiconductor layer 502 n-type semiconductor layer 503 p-type semiconductor layer 504 Second n+ type semiconductor layer 505 insulating film 506 First electrode 507 Second electrode 508 Third Electrode 509 Trench 600 Semiconductor devices 601 p-type semiconductor layer 602 n-type semiconductor layer 603 n-type semiconductor layer 603a Trench 604 p-type semiconductor region 605 n-type semiconductor region 606 Insulating film 607 First electrode 608 Second electrode 609 Third Electrode 700 Semiconductor devices 701 Semi-insulating layer 702 Buffer layer 703 First n-type semiconductor layer 704 Second n-type semiconductor layer 705 n+ type semiconductor layer 706 First electrode 707 Second electrode 708 Third Electrode 800 Semiconductor devices 801 First n+ type semiconductor layer 802 n-type semiconductor layer 803 Second n+ type semiconductor layer 804 First electrode 805 Second electrode 806 Third Electrode 807 Trench 900 Power System 901 Power Supply 902 Power Supply 903 Control circuit 910 System Unit 911 Electronic circuit 921 Inverter 922 Trans 923 Rectifier MOSFET 924 DCL 925 Voltage Comparator 926 PWM control circuit

Claims

1. A substrate; a plurality of semiconductor films each having a crystalline oxide, which are disposed adjacent to each other on the substrate directly or through another layer; and a separation portion separating the plurality of semiconductor films from each other.

2. The structure according to claim 1 , wherein the edge cutting portion has an amorphous structure or a crystal structure different from the crystal structure of the plurality of semiconductor films.

3. 3. The structure of claim 2, wherein the crystalline oxide and the edge each comprise gallium.

4. 4. The structure according to claim 1, wherein the upper end of the edge cutting portion is located above the plurality of semiconductor films.

5. 4. The structure according to claim 1, wherein the width of the edge cutting portion is at least three times the thickness of the plurality of semiconductor films.

6. a groove formed on the surface of the substrate that is deeper than the thickness of the plurality of semiconductor films; 4. The structure according to claim 1, wherein the edge cutting portion is located on the groove.

7. The structure of claim 6 , wherein the edges of the grooves are positioned above the surface of the substrate.

8. a region in which crystal growth is less likely to occur than in other regions is formed in a portion of the surface of the substrate; The structure according to claim 1 , wherein the edge cutting portion is formed in the region.

9. The structure according to claim 1 , wherein the edge portion contains a compound different from the compound contained in the crystalline oxide.

10. The structure according to claim 9 , wherein a difference between the thickness of the semiconductor films and the thickness of the edge cutting portion is smaller than a width of the edge cutting portion.

11. 4. The structure according to claim 1, wherein the crystalline oxide has a corundum structure.

12. a plurality of semiconductor films adjacent to each other and having a crystalline oxide; and a separation portion separating the plurality of semiconductor films from each other.

13. Roughening a portion of the surface of the substrate to form a rough surface; forming an edge cutting portion on the rough surface; forming a plurality of semiconductor films, each having a crystalline oxide, separated by the edge separation portion on a portion of the surface of the substrate other than the rough surface.

14. forming a groove in a surface of a substrate; forming an edge cut portion in the groove; forming a plurality of semiconductor films, each having a crystalline oxide, separated by the edge separation portion on a portion of the surface of the substrate other than the groove.

15. forming a cutting edge on a portion of a surface of the substrate; and forming a plurality of semiconductor films, each having a crystalline oxide, separated by the edge separation portion on a portion of the surface of the substrate other than the edge separation portion.

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