Semiconductor device and manufacturing method for the same

Abstract

To provide a semiconductor device with high reliability that can apply polysilicon to a fuse, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device according to an embodiment includes a fuse 1 and a transistor provided on a semiconductor substrate 10. The fuse 1 includes the semiconductor substrate 10, a separation region 12 provided in the semiconductor substrate 10, a polysilicon layer 14B provided on the separation region 12 and having impurities added to a dummy polysilicon layer 14, and electrode layers (26, 28, 30) provided on the separation region 12, substituted by the dummy polysilicon layer 14, and electrically connected to the polysilicon layer 14B. The transistor includes an active region electrically separated by the separation region 12, and a metal gate provided over the active region and including a multilayer structure of the electrode layers (26, 28, 30).SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Electrically programmable fuses (e-fuses) allow for easy programming to electrically break fuse regions and reduce the chip footprint, leading to their use in large-scale integrated circuits (LSIs) such as central processing units (CPUs), various memory devices, and application-specific integrated circuits (ASICs). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2008 / 0067629 [Patent Document 2] US Patent Application Publication No. 2015 / 0179632 [Patent Document 3] US Patent Application Publication No. 2015 / 0179753 Summary of the Invention [Problem to be solved by the invention]

[0004] When replacement metal gate (RMG) technology is applied, the polysilicon that served as both the polysilicon gate electrode and the fuse is replaced with a metal gate material, so that the polysilicon can no longer be used as a fuse.

[0005] The problem to be solved by the embodiments is to provide a highly reliable semiconductor device in which polysilicon can be applied to fuses, and a method for manufacturing the same. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes a fuse and a transistor provided on a semiconductor substrate. The fuse is provided on an isolation region of the semiconductor substrate and includes a polysilicon layer formed by doping an impurity into a dummy polysilicon layer, and an electrode layer provided on the isolation region, replacing the dummy polysilicon layer and electrically connected to the polysilicon layer. The transistor is provided on an active region electrically isolated by the isolation region and includes a metal gate including a stacked structure of the electrode layer. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 2 is a plan view of a fuse of the semiconductor device according to the embodiment. [Figure 1B] FIG. 1B is a cross-sectional view taken along line II in FIG. 1A. [Figure 2A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 2B] FIG. 2B is a cross-sectional view taken along line II-II in FIG. 2A. [Figure 3A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 3B] FIG. 3B is a cross-sectional view taken along line III-III in FIG. 3A. [Figure 4A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 4B] FIG. 4B is a cross-sectional view taken along line IV-IV in FIG. 4A. [Figure 5A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 5B] FIG. 5B is a cross-sectional view taken along line VV in FIG. 5A. [Figure 6A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 6B] FIG. 6B is a cross-sectional view taken along line VI-VI in FIG. 6A. [Figure 7A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 7B] FIG. 7B is a cross-sectional view taken along line VII-VII in FIG. 7A. [Figure 8A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 8B] FIG. 8B is a cross-sectional view taken along line VIII-VIII in FIG. 8A. [Figure 9A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 9B] 9B is a cross-sectional view taken along line IX-IX in FIG. 9A. [Figure 10A] 1A and 1B are plan views of a first method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 10B] 10B is a cross-sectional view taken along line XX in FIG. 10A. [Figure 11A] FIG. 10 is a plan view of a second method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 11B] 11B is a cross-sectional view taken along line XI-XI in FIG. 11A. [Figure 12A] FIG. 10 is a plan view of a second method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 12B] 12B is a cross-sectional view taken along line XII-XII in FIG. 12A. [Figure 13A] FIG. 10 is a plan view of a second method for manufacturing a fuse of a semiconductor device according to an embodiment. [Figure 13B] 13B is a cross-sectional view taken along line XIII-XIII in FIG. 13A. [Figure 14A] Example 1 of contact and polysilicon layer pattern placement. [Figure 14B] Example 2 of contact and polysilicon layer pattern placement. [Figure 14C] Example 3 of contact and polysilicon layer pattern placement. [Figure 14D] Example 4: Contact and polysilicon layer pattern placement. [Figure 14E] Example 5: Contact and polysilicon layer pattern placement. [Figure 15A]FIG. 10 is a cross-sectional view of a fuse of a semiconductor device according to a first modified example of the embodiment. [Figure 15B] FIG. 10 is a cross-sectional view of a fuse of a semiconductor device according to a second modification of the embodiment. [Figure 15C] FIG. 11 is a cross-sectional view of a fuse of a semiconductor device according to a third modification of the embodiment. [Figure 15D] FIG. 10 is a cross-sectional view of a fuse of a semiconductor device according to a fourth modification of the embodiment. [Figure 16A] FIG. 13 is a plan view of a fuse of a semiconductor device according to a fifth modification of the embodiment. [Figure 16B] 16B is a cross-sectional view taken along line XVI-XVI in FIG. 16A. [Figure 17A] FIG. 2 is a plan view of an NMOS transistor in the semiconductor device according to the embodiment. [Figure 17B] 17B is a cross-sectional view taken along line XVII-XVII in FIG. 17A. [Figure 18A] FIG. 2 is a plan view of a PMOS transistor in the semiconductor device according to the embodiment. [Figure 18B] 18B is a cross-sectional view taken along line XVIII-XVIII in FIG. 18A. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same or similar components will be assigned the same reference numerals, and components that have already been described will not be described again. In the following description, the direction perpendicular to the semiconductor substrate extending in the XY plane will be referred to as the Z direction, the direction perpendicular to the Z direction and extending in the polysilicon layer that becomes the fuse will be referred to as the X direction, and the direction perpendicular to the Z direction and the X direction will be referred to as the Y direction.

[0009] (Configuration of semiconductor device) Fig. 1A is a plan view of a fuse 1 of a semiconductor device according to an embodiment, and Fig. 1B is a cross-sectional view taken along line II in Fig. 1A.

[0010] The semiconductor device according to the embodiment includes a fuse 1 and a transistor provided on a semiconductor substrate 10. The semiconductor device according to the embodiment realizes a polysilicon fuse structure by a complementary metal oxide semiconductor (CMOS) device technology that combines a high-k (HK) / metal gate (MG) HKMG technology and a RMG technology.

[0011] As shown in FIGS. 1A and 1B , fuse 1 of the semiconductor device according to the embodiment includes an isolation region 12 provided on a semiconductor substrate 10 such as a semiconductor wafer, a polysilicon layer 14B provided on isolation region 12 and formed by doping impurities into dummy polysilicon layer 14, and electrode layers (26, 28, 30) provided on isolation region 12, replacing dummy polysilicon layer 14, and electrically connected to polysilicon layer 14B. Also included are a first electrode 321 and a second electrode 322 electrically connected to electrode layers (26, 28, 30). The first electrode 321 and the second electrode 322 constitute electrode terminals of fuse 1. The first electrode 321 is connected to metal electrode layer 30 via contact CS1. The second electrode 322 is connected to metal electrode layer 30 via contact CS2. An example of the pattern arrangement of contacts and polysilicon layers will be described later in the description of FIGS. 14A to 14E. The electrode layers (26, 28, 30) are provided on both ends of the polysilicon layer 14B extending in the X direction on the isolation region 12. The isolation region 12 is an insulating layer called shallow trench isolation (STI).

[0012] The transistor comprises a metal gate including a stack of electrode layers (26, 28, 30) disposed on an active region electrically isolated by isolation regions 12. The transistor is described below in the description of Figures 17A, 17B and 17A, 17B.

[0013] 1A and 1B, the fuse 1 of the semiconductor device according to the embodiment has a stacked structure including a high-dielectric-constant dielectric layer 24, a metal-containing layer 26 provided on the high-dielectric-constant dielectric layer 24, a work function metal (WF) layer 28 provided on the metal-containing layer 26, and a metal electrode layer 30 provided on the work function metal layer 28. Although not shown in FIGS. 1A and 1B, an oxide film (IL: Inter Layer; SiO2) is provided between the high-dielectric-constant dielectric layer 24 and the isolation region 12.

[0014] The high-dielectric-constant dielectric layer 24 has a relative dielectric constant k of, for example, 10 or more, and may be made of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), zirconium oxide (ZrO2), or the like.

[0015] The metal-containing layer 26 can be made of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), tungsten (W), or the like. For example, in the case of TiN, the interface with the polysilicon layer 14B is silicided with TiN. This reduces the resistance of the connection between the polysilicon layer 14B and the electrode layers (26, 28, 30). In the case of TaN, Ta, or W, the interface with the polysilicon layer 14B is silicided with TaN, Ta, or W silicide, reducing the resistance of the connection.

[0016] In HKMG technology, a thin work function metal layer 28 is inserted between the high-k dielectric layer 24 and the metal electrode layer 30. The threshold voltage can be adjusted by varying the thickness of the work function metal layer 28. The work function metal layer 28 may include metals such as aluminum (Al) or lanthanum (La).

[0017] The metal electrode layer 30 may be made of, for example, W or Al.

[0018] The fuse 1 of the semiconductor device according to the embodiment can be electrically programmed by applying a voltage between the first electrode 321 and the second electrode 322 to break the polysilicon layer 14B.

[0019] In the fuse 1 of the semiconductor device according to the embodiment, for example, boron (B) ions are implanted as an impurity into the dummy polysilicon layer 14, so that the B-doped polysilicon layer 14B can be selectively left at any desired location even after the RMG process and can be used as a polysilicon fuse. A heat treatment process may be added after the B ion implantation process.

[0020] In the fuse 1 of the semiconductor device according to the embodiment, the polysilicon layer 14B can be left in any desired location by simply adding an impurity ion implantation process, even in an RMG process that does not leave behind the dummy polysilicon layer 14, thereby realizing a polysilicon fuse. The junction surface between the polysilicon layer 14B and the electrode layer (26, 28, 30) can be controlled to any shape by adjusting the implantation impurity profile of the polysilicon layer 14B.

[0021] In the fuse 1 of the semiconductor device according to the embodiment, there is no need to place materials with different resistivities in the material of the fuse formation layer, which eliminates the need for a layout in which the line width is narrowed to concentrate power at the breaking point and break the fuse, thereby reducing the area occupied by the fuse.

[0022] In the fuse 1 of the semiconductor device according to the embodiment, a polysilicon layer can be applied to the fuse, allowing for a finer layout design than metal fuses using metal wiring layers, and the fuse area can be reduced. In metal fuses using metal wiring layers, the ruptured portion recombines over the long term due to electromigration (EM) or stress migration (SM), resulting in reliability problems such as loss of fuse information. In the fuse 1 of the semiconductor device according to the embodiment, a polysilicon layer can be applied to the fuse, preventing the ruptured portion from recombining due to EM or SM phenomena, and realizing a fuse structure with higher reliability in data retention than metal fuses.

[0023] In the fuse 1 of the semiconductor device according to the embodiment, by selectively implanting an impurity (B) into the dummy polysilicon layer 14 to be replaced in the RMG process, the etching rate of the polysilicon can be reduced, and the polysilicon layer 14B that functions as a fuse can remain even after the RMG process. Therefore, a polysilicon fuse structure can be easily realized even in a device to which the RMG process is applied.

[0024] In the fuse 1 of the semiconductor device according to the embodiment, the shape of the connection portion with the electrode layer (26, 28, 30) can be controlled to any shape by controlling the profile of the impurity injection into the polysilicon layer 14B that remains as the fuse, and the contact area between the polysilicon layer 14B and the electrode layer (26, 28, 30) can be adjusted, thereby reducing the contact resistance.

[0025] For example, in memory devices, W wiring is generally used for lower-layer wiring, but W has a high melting point of 3407°C and is therefore unsuitable for a metal fuse structure. In this case, fuses are formed using upper-layer wiring such as Cu (melting point 1084.5°C) or Al (melting point 660°C), but the design rules for upper-layer wiring are relatively strict, which increases the fuse layout area. In fuse 1 of the semiconductor device according to the embodiment, polysilicon (melting point 1410°C) is used to reduce the area occupied by the fuse, enabling a highly reliable fuse structure to be achieved.

[0026] If the direction in which the polysilicon layer 14B extends is the X direction and the direction perpendicular to the semiconductor substrate 10 is the Z direction, in the cross-sectional structure along the XZ plane of the polysilicon layer 14B, the first bonding surface between the polysilicon layer 14B and the electrode layer (26, 28, 30) connected to the first electrode 321 and the second bonding surface between the polysilicon layer 14B and the electrode layer (26, 28, 30) connected to the second electrode 322 can be formed to have various arbitrary shapes.

[0027] 1B, the fuse 1 of the semiconductor device according to the embodiment has a cross-sectional structure along the XZ plane of the polysilicon layer 14B that is reverse tapered in the Z direction. This junction shape allows for a larger area than when the junction surface is formed vertically, thereby reducing the contact resistance of the junction surface.

[0028] (impurity ion implantation) By implanting an impurity (B) into the dummy polysilicon layer 14, the etching rate can be controlled so that the boron-doped polysilicon layer 14B is not removed even in the RMG process. The timing of implanting impurity ions into the dummy polysilicon layer 14 may be any step before the dummy polysilicon layer 14 is peeled off by the RMG process. As will be explained in the manufacturing method of a semiconductor device according to an embodiment described later, this can be realized either before or after processing the fuse structure.

[0029] Furthermore, by controlling the impurity profile of the polysilicon layer 14B that will become the fuse, the shape of the end of the polysilicon layer 14B during etching of the dummy polysilicon layer 14 can be controlled. The impurity profile of the polysilicon layer 14B can be controlled so that the end shape of the polysilicon layer 14B becomes, for example, an inverse tapered, forward tapered, parallelogram, barrel-shaped, or hourglass-shaped. In the ion implantation, oblique ion implantation may be performed, or ion implantation may be performed in multiple stages to adjust the shape. The dose and acceleration energy during ion implantation may also be changed. Furthermore, a heat treatment process may be added as appropriate.

[0030] The boron impurity concentration is 1x10 20 cm -3 In this case, the etching selectivity is about 15, and the boron impurity concentration is 1x10 21 cm -3 In this case, the etching selectivity is approximately 100 or more. 19 cm -3 Therefore, the boron impurity concentration should be at least about 1×10 19 cm -3 It is desirable that this is the case.

[0031] By increasing the junction area between the polysilicon layer 14B and the electrode layers (26, 28, 30), it is possible to limit the rupture area by moving the fuse rupture location to the inside of the polysilicon layer 14B, which has a higher resistance than the electrode layers (26, 28, 30). Also, by increasing the junction area between the polysilicon layer 14B and the electrode layers (26, 28, 30), it is possible to reduce the area of ​​the contacts CS between the first electrode 321 and the second electrode 322 and the metal electrode layer 30.

[0032] (Method of manufacturing a semiconductor device according to an embodiment) In the method for manufacturing a semiconductor device according to the embodiment, an electrically programmable fuse 1 is formed on an isolation region 12 of a semiconductor substrate 10, and a transistor is formed on an active region of the semiconductor substrate 10.

[0033] In the fuse 1, a dummy polysilicon layer 14 is formed on an isolation region 12, a polysilicon layer 14B is formed by adding impurities to the dummy polysilicon layer 14, the dummy polysilicon layer 14 is removed by etching to leave the polysilicon layer 14B on the isolation region 12, and electrode layers (26, 28, 30) are formed electrically connected to the polysilicon layer 14B in place of the dummy polysilicon layer 14.

[0034] The transistor is formed by forming a dummy polysilicon layer above an active region, then removing the dummy polysilicon layer by etching, and forming a metal gate in place of the dummy polysilicon layer.

[0035] -First manufacturing method- In a first manufacturing method of fuse 1 of a semiconductor device according to an embodiment, an isolation region 12 is formed on a semiconductor substrate 10, an undoped dummy polysilicon layer 14 is formed on the isolation region 12, a polysilicon layer 14B is formed by adding impurities to the dummy polysilicon layer 14 by lithography and ion implantation technology, an insulating layer 18 is formed on the entire surface, and then the dummy polysilicon layer 14 is processed to expose the surface of the isolation region 12, an interlayer insulating film 22 is formed on the entire surface, planarization is performed to expose the surface of the polysilicon layer 14B, etching is performed to remove the dummy polysilicon layer 14 while leaving the polysilicon layer 14B, and the surface of the isolation region 12 is exposed, electrode layers (26, 28, 30) are formed on the entire surface, planarization is performed to expose the surfaces of the electrode layers (26, 28, 30) and the polysilicon layer 14B so that they are flush with each other, an interlayer insulating film 34 is formed on the entire surface, and a first electrode 321 and a second electrode 322 are formed on the electrode layer 30 by patterning.

[0036] In the first manufacturing method of the fuse 1 of the semiconductor device according to the embodiment, impurity ions are implanted into the dummy polysilicon layer 14 before processing the dummy polysilicon layer 14. Therefore, dimensional controllability in the process is relatively low, and manufacturing is easy.

[0037] (A) Fig. 2A is a plan view of a first manufacturing method, and Fig. 2B is a cross-sectional view taken along line II-II in Fig. 2A. First, as shown in Figs. 2A and 2B, a dummy polysilicon layer 14 is formed on a semiconductor substrate 10. The dummy polysilicon layer 14 is formed on an isolation region 12 formed on the semiconductor substrate 10. This dummy polysilicon layer 14 will become a polysilicon layer 14B for a fuse after doping, but since the electrode portion is replaced with a metal electrode by the RMG process, it is called a dummy polysilicon layer.

[0038] (B) FIG. 3A is a plan view of the first manufacturing method, and FIG. 3B is a cross-sectional view taken along line III-III in FIG. 3A. Next, as shown in FIGS. 3A and 3B, a resist layer 16 is applied to the dummy polysilicon layer 14, and then a window is opened in the dummy polysilicon layer 14 by a lithography process, followed by ion implantation of impurity ions. Here, boron (B), for example, can be used as the impurity. The depth and impurity concentration distribution of boron ions implanted into the dummy polysilicon layer 14 can be controlled by the acceleration energy and dose. An annealing process may also be performed after the boron ion implantation. The boron ion implantation may be performed in multiple stages. An oblique ion implantation technique may also be used. Here, the polysilicon layer 14B into which boron ions have been implanted is the region that will become the polysilicon fuse.

[0039] (C) Fig. 4A is a plan view of the first manufacturing method, and Fig. 4B is a cross-sectional view taken along line IV-IV in Fig. 4A. Next, as shown in Figs. 4A and 4B, after the resist layer 16 is removed, an insulating layer (Cap film) 18 is formed on the polysilicon layer 14B and the dummy polysilicon layer 14. Here, for example, a silicon nitride film (SiN) can be used as the insulating layer 18. The insulating layer 18 can be used as a hard mask.

[0040] (D) Fig. 5A is a plan view of the first manufacturing method, and Fig. 5B is a cross-sectional view taken along line VV in Fig. 5A. Next, as shown in Figs. 5A and 5B, the dummy polysilicon layer 14 is removed by an etching technique such as reactive ion etching (RIE) using the insulating layer 18 as a hard mask, thereby exposing the surface of the isolation region 12. As a result, the dummy polysilicon layer 14 and polysilicon layer 14B are formed on the isolation region 12.

[0041] (E) Fig. 6A is a plan view of the first manufacturing method, and Fig. 6B is a cross-sectional view taken along line VI-VI in Fig. 6A. Next, as shown in Figs. 6A and 6B, an insulating layer 18 and an oxide film 20 are formed on the sidewalls of the dummy polysilicon layer 14. After a planarization process, the surface of the insulating layer 18 is exposed, and an interlayer insulating film 22 is formed on the entire surface including the isolation region 12. As a result, the dummy polysilicon layer 14 and the polysilicon layer 14B are formed on the isolation region 12, embedded in the interlayer insulating film 22.

[0042] (F) Fig. 7A is a plan view of the first manufacturing method, and Fig. 7B is a cross-sectional view taken along line VII-VII in Fig. 7A. Next, as shown in Fig. 7A and Fig. 7B, the entire surface of the device is etched back using chemical mechanical polishing (CMP) to expose the surfaces of the dummy polysilicon layer 14 and polysilicon layer 14B. An insulating layer 18, an oxide film 20, and an interlayer insulating film 22 are sequentially stacked on the sidewall surface of the dummy polysilicon layer 14.

[0043] (G) Figure 8A is a plan view of the first manufacturing method, and Figure 8B is a cross-sectional view taken along line VIII-VIII in Figure 8A. Next, as shown in Figures 8A and 8B, the dummy polysilicon layer 14 is peeled off and removed by wet etching. Here, the boron-doped polysilicon layer 14B remains due to the difference in etching rate. The surface of the isolation region 12 is exposed at the bottom of the recess regions 151 and 152 from which the dummy polysilicon layer 14 has been removed, and the insulating layer 18 is exposed on the sidewall surfaces.

[0044] 9A is a plan view of the first manufacturing method, and FIG. 9B is a cross-sectional view taken along line IX-IX in FIG. 9A. Next, as shown in FIGS. 9A and 9B, in order to form electrodes in the recess regions 151 and 152 where the dummy polysilicon layer 14 has been removed, a high-dielectric-constant dielectric layer 24, a metal-containing layer 26, a work-function metal layer 28, and a metal electrode layer 30 are sequentially stacked over the entire surface of the device. An oxide film (IL) is formed under the high-dielectric-constant dielectric layer 24, but is not shown in the figure.

[0045] (I) Figure 10A is a plan view of the first manufacturing method, and Figure 10B is a cross-sectional view taken along line XX in Figure 10A. Next, as shown in Figures 10A and 10B, the entire device surface is planarized by CMP to expose the surface of the polysilicon layer 14B. Recess regions 151 and 152 are filled with a high-k dielectric layer 24, a metal-containing layer 26, a work function metal layer 28, and an electrode portion of a metal electrode layer 30.

[0046] (J) Next, as shown in Figures 1A and 1B, after forming an interlayer insulating film 34 over the entire surface of the device, a window is opened in the interlayer insulating film 34 by a lithography process, and a first electrode 321 connected to the metal electrode layer 30 via a contact CS1 and a second electrode 322 connected to the metal electrode layer 30 via a contact CS2 are formed.

[0047] -Second manufacturing method- The second method of manufacturing fuse 1 of the semiconductor device according to the embodiment includes forming isolation region 12 on semiconductor substrate 10, forming non-doped dummy polysilicon layer 14 on isolation region 12, forming insulating layer 18 on dummy polysilicon layer 14, processing dummy polysilicon layer 14 to expose the surface of isolation region 12, forming polysilicon layer 14B by adding impurities to dummy polysilicon layer 14 by lithography and ion implantation technology, forming interlayer insulating film 22 on the entire surface, and flattening. The surface is planarized by chemical treatment to expose the surface of the polysilicon layer 14B, the dummy polysilicon layer 14 is removed by etching while leaving the polysilicon layer 14B to expose the surface of the isolation region 12, electrode layers (26, 28, 30) are formed on the entire surface, the surfaces of the electrode layers (26, 28, 30) and the polysilicon layer 14B are exposed flush by chemical treatment, an interlayer insulating film 34 is formed on the entire surface, and a first electrode 321 and a second electrode 322 are formed on the metal electrode layer 30 by patterning.

[0048] In the second manufacturing method of the fuse 1 of the semiconductor device according to the embodiment, in terms of the process flow, ion implantation is performed to form the polysilicon layer 14B after processing the dummy polysilicon layer 14. Since ion implantation is performed on the dummy polysilicon layer 14 after processing the dummy polysilicon layer 14, higher dimensional controllability is required in terms of the process compared to the first manufacturing method.

[0049] (K) Fig. 11A is a plan view of the second manufacturing method, and Fig. 11B is a cross-sectional view taken along line XI-XI in Fig. 11A. First, after the steps shown in Fig. 1A and Fig. 1B are performed, an insulating layer 18 is formed on the dummy polysilicon layer 14, as shown in Fig. 11A and Fig. 11B. Here, as in the first manufacturing method, for example, a silicon nitride film (SiN) is used as the insulating layer 18.

[0050] (L) Fig. 12A is a plan view of the second manufacturing method, and Fig. 12B is a cross-sectional view taken along line XII-XII in Fig. 12A. Next, as shown in Figs. 12A and 12B, the dummy polysilicon layer 14 is removed by an etching technique such as RIE using the insulating layer 18 as a hard mask, exposing the surface of the isolation region 12. As a result, the dummy polysilicon layer 14 is gate-processed on the isolation region 12.

[0051] (M) Figure 13A is a plan view of the second manufacturing method, and Figure 13B is a cross-sectional view taken along line XIII-XIII in Figure 13A. Next, as shown in Figures 13A and 13B, a resist layer 17 is applied to the entire surface of the device, and then windows are opened in the insulating layer 18 and the dummy polysilicon layer 14 by a lithography process. Furthermore, impurity ions are implanted through the insulating layer 18. Here, boron (B), for example, can be used as the impurity.

[0052] (N) Next, the resist layer 17 is stripped off to obtain the structure shown in FIGS. 5A and 5B after the same steps as in the first manufacturing method.

[0053] Thereafter, the same steps as in the first manufacturing method (FIGS. 6A and 6B to 11A and 11B) are carried out to obtain the structure shown in FIGS. 1A and 1B.

[0054] (contact and polysilicon layer patterns) -Layout example 1- FIG. 14A shows a first pattern layout example of the contacts and polysilicon layers of fuse 1 of the semiconductor device according to the embodiment. One contact CS1 and one contact CS2 are arranged on metal electrode layer 30, and polysilicon layer 14B is linearly arranged in the X direction. FIG. 14A shows the simplest pattern layout example. As shown in FIG. 14A, pattern layout example 1 shows polysilicon layer 14B extending in the X direction, metal electrode layer 30 connected to the ends of polysilicon layer 14B in the positive and negative X directions, and contacts CS1 and CS2 arranged on metal electrode layer 30. Contact CS1 is connected to a first electrode 321, and contact CS2 is connected to a second electrode 322.

[0055] -Layout example 2- FIG. 14B shows a second pattern layout example of the contacts and polysilicon layer of fuse 1 of the semiconductor device according to the embodiment. In pattern layout example 2, as shown in FIG. 14B, a polysilicon layer 14B extending in the X direction, a metal electrode layer 30 connected to the ends of the polysilicon layer 14B in the positive and negative X directions, and contacts CS11, CS12, and contacts CS21, CS22 arranged on the metal electrode layer 30 are shown. Contacts CS11 and CS12 are connected to a first electrode 321, and contacts CS21 and CS22 are connected to a second electrode 322. Arranging two contacts for each of the first electrode 321 and the second electrode 322 can improve the contact connection yield. Arranging multiple contacts for the first electrode 321 and the second electrode 322 reduces the connection resistance to the first electrode 321 and the second electrode 322, and can limit the fuse blowout location to the polysilicon layer 14B. The number of contacts is not limited to two and may be three or more.

[0056] -Layout example 3- FIG. 14C illustrates a third pattern layout example of the contacts and polysilicon layers of fuse 1 of the semiconductor device according to the embodiment. In this third pattern layout example, as shown in FIG. 14C, polysilicon layers 14B1, 14B2, and 14B3 are divided into multiple parts in the X direction. A metal electrode layer 30 is connected to polysilicon layer 14B1. Another metal electrode layer 30 is connected to polysilicon layer 14B3. Contacts CS11, CS12, and contacts CS21 and CS22 are arranged on metal electrode layer 30. Contacts CS11 and CS12 are connected to a first electrode 321, and contacts CS21 and CS22 are connected to a second electrode 322. Providing multiple polysilicon layers in the fuse region can prevent the area that is physically destroyed when the fuse is blown from expanding. In FIG. 14C, the central polysilicon layer 14B2, which is long in the X direction, is a high-resistance region where the fuse will blow. The short polysilicon layers 14B1 and 14B3 at both ends in the X direction are regions that function as physical barriers that limit the fuse blow. 14C, a plurality of contacts are provided for the first electrode 321 and the second electrode 322 of the polysilicon layer, thereby improving the contact connection yield. Furthermore, by providing a plurality of contacts for the first electrode 321 and the second electrode 322, the connection resistance for the first electrode 321 and the second electrode 322 is reduced, and the fuse rupture location can be limited to the polysilicon layer 14B2. Note that the metal layer 15 connecting between the polysilicon layer 14B1 and the polysilicon layer 14B2 and between the polysilicon layer 14B2 and the polysilicon layer 14B3 has a stacked structure similar to that of the electrode layers (26, 28, 30).

[0057] -Layout example 4- FIG. 14D shows a fourth pattern layout example of contacts and polysilicon layers of fuse 1 of a semiconductor device according to an embodiment. This fourth pattern layout example shows a polysilicon layer 14B, a metal electrode layer 30 connected to the ends of the polysilicon layer 14B in the positive and negative X directions, and contacts CS11, CS12, and contacts CS21, CS22 arranged on the metal electrode layer 30. Contacts CS11 and CS12 are connected to a first electrode 321, and contacts CS21 and CS22 are connected to a second electrode 322. Arranging two contacts for each of the first electrode 321 and the second electrode 322 can improve the contact connection yield. In the example of FIG. 14D, by forming the interface between the polysilicon layer 14B and the metal electrode layer 30 in a zigzag shape rather than a linear shape in a plan view, the cross-sectional shape and the layout pattern can reduce the resistance at the interface between the polysilicon layer 14B and the metal electrode layer 30. Furthermore, by arranging a plurality of contacts for the first electrode 321 and the second electrode 322, the connection resistance for the first electrode 321 and the second electrode 322 can be reduced, and the fuse breakage location can be limited to the polysilicon layer 14B.

[0058] -Layout example 5- FIG. 14E shows a fifth pattern layout example of the contacts and polysilicon layer of fuse 1 in the semiconductor device according to the embodiment. In pattern layout example 5, the fuse rupture location is narrowed by the layout pattern, limiting the destruction location at the time of fuse rupture to the polysilicon layer 14B. In the example of FIG. 14E, multiple contacts for the first electrode 321 and the second electrode 322 of the polysilicon layer are arranged, which can improve the contact connection yield. Furthermore, by arranging multiple contacts for the first electrode 321 and the second electrode 322, the connection resistance to the first electrode 321 and the second electrode 322 is reduced, and the fuse rupture location can be limited to the narrow portion of the polysilicon layer 14B by the layout pattern.

[0059] (Variation 1) FIG. 15A is a cross-sectional view of a fuse 1A of a semiconductor device according to a first modification of the embodiment. As shown in FIG. 15A, in the cross-sectional structure of the fuse 1A taken along the XZ plane of the polysilicon layer 14B, a first junction surface between the polysilicon layer 14B and the electrode layer (26, 28, 30) connected to the first electrode 321 and a second junction surface between the polysilicon layer 14B and the electrode layer (26, 28, 30) connected to the second electrode 322 have asymmetric shapes in the X direction. The first junction surface and the second junction surface form parallel surfaces extending in the Y direction. An angled implantation of impurities during the ion implantation process can provide an asymmetric structure at both ends of the polysilicon layer 14B. This junction shape allows for a larger area than a perpendicularly formed junction surface, thereby reducing the contact resistance of the junction surface.

[0060] (Variation 2) 15B is a cross-sectional view of fuse 1B of a semiconductor device according to a second modification of the embodiment. As shown in FIG. 15B, in the cross-sectional structure of fuse 1B along the XZ plane of polysilicon layer 14B, the first and second bonding surfaces have a right-and-left hourglass shape (tapered in the middle) in the X direction. This shape of the bonding portion allows for a larger area than when the bonding surfaces are formed vertically, thereby reducing the contact resistance of the bonding surfaces.

[0061] (Variation 3) 15C is a cross-sectional view of fuse 1C of a semiconductor device according to Modification 3 of the embodiment. As shown in FIG. 15C, in fuse 1C, in a cross-sectional structure along the XZ plane of polysilicon layer 14B, the first and second bonding surfaces have a forward tapered shape in the Z direction. This shape of the bonding portion allows the area to be wider than when the bonding surfaces are formed vertically, and therefore the contact resistance of the bonding surfaces can be reduced.

[0062] (Variation 4) 15D is a cross-sectional view of a fuse 1D of a semiconductor device according to a fourth modification of the embodiment. As shown in FIG. 15D, in the cross-sectional structure of the fuse 1D along the XZ plane of the polysilicon layer 14B, the first and second bonding surfaces have a barrel-like (bowing and center-wide) shape in the X direction. This shape of the bonding portion allows for a larger area than when the bonding surfaces are formed vertically, thereby reducing the contact resistance of the bonding surfaces.

[0063] (Variation 5) FIG. 16A is a plan view of fuse 1E of a semiconductor device according to a fifth variation of the embodiment. FIG. 16B is a cross-sectional view taken along line XVI-XVI in FIG. 16A. Fuse 1E includes polysilicon layers 14B1, 14B2, and 14B3 divided into multiple parts. Providing multiple divided polysilicon layers 14B1, 14B2, and 14B3 prevents the area of ​​physical destruction from expanding when the fuse ruptures. In FIGS. 16A and 16B, the central, long polysilicon layer 14B2 in the X direction is a high-resistance region where the fuse ruptures, and the short polysilicon layers 14B1 and 14B3 at both ends function as physical barriers limiting the fuse rupture. Metal layers 15 are formed between polysilicon layers 14B1 and 14B2, and between polysilicon layers 14B2 and 14B3. The metal layer 15 has the same structure as the electrode layers (26, 28, 30).

[0064] (Transistor structure) Fig. 17A is a plan view of an NMOS transistor 2N constituting a CMOS in a semiconductor device according to an embodiment, Fig. 17B is a cross-sectional view taken along line XVII-XVII in Fig. 17A, Fig. 18A is a plan view of a PMOS transistor 2P constituting a CMOS in a semiconductor device according to an embodiment, and Fig. 18B is a cross-sectional view taken along line XVIII-XVIII in Fig. 18A.

[0065] In the semiconductor device according to the embodiment, the metal gate GN of the NMOS transistor 2N and the metal gate GP of the PMOS transistor 2P constituting the CMOS can be formed by a CMOS device technology that combines the HKMG technology and the RMG technology.

[0066] 17A and 17B, the NMOS transistor 2N is provided on an active region 10A electrically isolated by an isolation region 12, and includes a metal gate GN including a stacked structure of electrode layers (26, 28, 30) shown in FIGS. 1A and 1B. Here, the active region 10A can be formed of a P-type semiconductor substrate 10 or a P-well region.

[0067] 18A and 18B, the PMOS transistor 2P is provided on an active region 10B electrically isolated by an isolation region 12, and includes a metal gate GP including a stacked structure of electrode layers (26, 28, 30) shown in FIGS. 1A and 1B. Here, the active region 10B can be formed of an N-type semiconductor substrate 10 or an N-well region.

[0068] 17A and 17B, the metal gate GN includes an oxide film (IL) 23 provided on the active region 10A, a high-k dielectric layer 24 provided on the oxide film 23, a metal-containing layer 261 provided on the high-k dielectric layer 24, a work function metal layer 28 provided on the metal-containing layer 261, and a metal electrode layer 30 provided above the work function metal layer 28. In the NMOS, a work function metal layer 29 and a metal-containing layer 262 are provided between the work function metal layer 28 and the metal electrode layer 30. The metal gate GN is buried in an interlayer insulating film 36, as shown in FIGS.

[0069] 18A and 18B, the metal gate GP includes an oxide film 23 provided on the active region 10B, a high-dielectric-constant dielectric layer 24 provided on the oxide film 23, a metal-containing layer 261 provided on the high-dielectric-constant dielectric layer 24, a work function metal layer 28 provided on the metal-containing layer 261, and a metal electrode layer 30 provided above the work function metal layer 28. In the PMOS, a metal-containing layer 263, a work function metal layer 29, and a metal-containing layer 262 are provided between the work function metal layer 28 and the metal electrode layer 30. The metal gate GN is buried in an interlayer insulating film 36, as shown in FIGS.

[0070] Metal-containing layers 261, 262, and 263 may be made of TiN, TaN, Ta, or W, similar to metal-containing layer 26 used in fuse 1. The threshold voltage of the PMOS can be adjusted by changing the thickness of work function metal layer 29. Work function metal layer 29 may contain metals such as aluminum (Al) and lanthanum (La).

[0071] The thicknesses of the components constituting the semiconductor device in this specification, the distances between the components, and so on can be easily measured by physical analysis using, for example, a secondary electron microscope (SEM). The position of the fuse portion can be identified by planar SEM observation, and unruptured fuses can be easily observed by cross-sectional SEM observation.

[0072] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0073] 1, 1A, 1B, 1C, 1D, 1E...Fuse 2N...NMOS transistor 2P...PMOS transistor 10...Semiconductor substrate 10A, 10B...active area 12...Separation area 14...Dummy polysilicon layer 14B...Polysilicon layer 15...Metal layer 16, 17...resist layer 18...Insulating layer 20. Oxide film 22, 34, 36...Interlayer insulating film 23...Oxide film (IL) 24...High-permittivity dielectric layer 26, 261, 262,263…metal-containing layer 28, 29...Work function metal layer 30…Metal electrode layer 151, 152...Recess area 321...1st electrode 322…Second electrode CS1, CS11, CS12, CS2, CS21, CS22...Contact

Claims

1. a semiconductor substrate; an isolation region provided in the semiconductor substrate; a polysilicon layer formed on the isolation region and having an impurity added to a dummy polysilicon layer; a fuse provided on the isolation region, the fuse including a first electrode layer and a second electrode layer that replace the dummy polysilicon layer and are electrically connected to the polysilicon layer; an active region provided in the semiconductor substrate and electrically isolated by the isolation region; a transistor comprising a metal gate disposed over the active region and including a stack of the first electrode layer and the second electrode layer; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said fuse is electrically programmable by fracturing said polysilicon layer by applying a voltage between said first electrode layer and said second electrode layer.

3. 2. The semiconductor device of claim 1, wherein the first electrode layer and the second electrode layer are provided on both ends of the polysilicon layer above the isolation region, and comprise a first high-k dielectric layer, a first metal-containing layer provided on the first high-k dielectric layer, a first work function metal layer provided on the first metal-containing layer, and a first metal electrode layer provided on the first work function metal layer.

4. The first high-k dielectric layer is made of hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), tantalum oxide (Ta 2 O 5 ), strontium titanium oxide (SrTiO 3 ), or zirconium oxide (ZrO 2 4. The semiconductor device according to claim 3, comprising:

5. 4. The semiconductor device of claim 3, wherein the first metal-containing layer comprises any of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), or tungsten (W).

6. The semiconductor device of claim 3 , wherein the first work function metal layer comprises aluminum (Al) or lanthanum (La).

7. The semiconductor device of claim 3 , wherein the first metal electrode layer comprises tungsten (W) or aluminum (Al).

8. 4. The semiconductor device of claim 3, wherein the metal gate comprises: a second high-k dielectric layer disposed above the active region; a second metal-containing layer disposed on the second high-k dielectric layer; a second work function metal layer disposed on the second metal-containing layer; and a second metal electrode layer disposed on the second work function metal layer.

9. 2. The semiconductor device according to claim 1, wherein the concentration distribution of the impurity added to the polysilicon layer is adjusted, and the shape of the junction surfaces between the polysilicon layer and the first and second electrode layers is controllable.

10. 10. The semiconductor device according to claim 9, wherein, when an extension direction of the polysilicon layer is defined as an X direction and a direction perpendicular to the semiconductor substrate is defined as a Z direction, in a cross-sectional structure of the polysilicon layer along an XZ plane, a first bonding surface between the polysilicon layer and the first electrode layer and a second bonding surface between the polysilicon layer and the second electrode layer have arbitrary shapes.

11. 11. The semiconductor device according to claim 10, wherein the first bonding surface and the second bonding surface have any one of a left-right asymmetric shape in the X direction, a reverse tapered shape in the Z direction, a forward tapered shape in the Z direction, a left-right barrel shape in the X direction, and a left-right hourglass shape in the X direction.

12. The impurity added to the polysilicon layer is boron (B), and the concentration of the impurity is 1×10 19 atoms / cm 3 2. The semiconductor device according to claim 1, wherein:

13. 1. A method for manufacturing a semiconductor device, comprising forming an electrically programmable fuse on an isolation region of a semiconductor substrate and forming a transistor on an active region of the semiconductor substrate, the method comprising: The fuse is forming a first dummy polysilicon layer on the isolation region, forming a polysilicon layer by adding an impurity to the first dummy polysilicon layer, removing the first dummy polysilicon layer by etching to leave the polysilicon layer on the isolation region, and forming a first electrode layer and a second electrode layer electrically connected to the polysilicon layer in place of the first dummy polysilicon layer; The transistor is a second dummy polysilicon layer formed above the active region, the second dummy polysilicon layer being removed by etching, and a metal gate being formed in place of the second dummy polysilicon layer;

14. forming an isolation region on a semiconductor substrate; forming a non-doped dummy polysilicon layer on the isolation region; forming a polysilicon layer by adding impurities to the dummy polysilicon layer using lithography and ion implantation techniques; forming an insulating layer on the entire surface, processing the polysilicon layer to expose the surface of the isolation region, and forming a first interlayer insulating film on the entire surface; planarizing the surface of the polysilicon layer by a planarization process to expose the surface of the polysilicon layer; removing the dummy polysilicon layer by etching while leaving the polysilicon layer to expose the surface of the isolation region; An electrode layer is formed on the entire surface, a planarization process to expose the surfaces of the electrode layer and the polysilicon layer flush with each other; A method for manufacturing a semiconductor device, comprising forming a second interlayer insulating film on the entire surface, and forming a first electrode and a second electrode on the electrode layer by patterning.

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein after processing said dummy polysilicon layer, an impurity is added to said dummy polysilicon layer to form said polysilicon layer.

16. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the first electrode layer and the second electrode layer are provided on both ends of the polysilicon layer above the isolation region, and are formed by sequentially stacking a first high-dielectric-constant dielectric layer, a first metal-containing layer provided on the first high-dielectric-constant dielectric layer, a first work function metal layer provided on the first metal-containing layer, and a first metal electrode layer provided on the first work function metal layer.

17. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the metal gate is provided above the active region and comprises a second high-k dielectric layer, a second metal-containing layer provided on the second high-k dielectric layer, a second work function metal layer provided on the second metal-containing layer, and a second metal electrode layer provided on the second work function metal layer.

18. 14. The method for manufacturing a semiconductor device according to claim 13, wherein a concentration distribution of the impurity added to the polysilicon layer is adjusted, and a shape of a junction surface between the polysilicon layer and the first electrode layer and the second electrode layer can be controlled.

19. 14. The method for manufacturing a semiconductor device according to claim 13, wherein, when an extension direction of the polysilicon layer is defined as an X direction and a direction perpendicular to the semiconductor substrate is defined as a Z direction, in a cross-sectional structure of the polysilicon layer along an XZ plane, a first bonding surface between the polysilicon layer and the first electrode layer and a second bonding surface between the polysilicon layer and the second electrode layer can be formed into any shape.

20. The impurity added to the polysilicon layer is boron (B), and the concentration of the impurity is at least 1×10 19 cm -3 The method for manufacturing a semiconductor device according to claim 13, wherein the method is as described above.

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