Semiconductor wafer and semiconductor wafer inspection method

Abstract

To enable process monitoring for each semiconductor chip without increasing the area of the semiconductor chip.SOLUTION: A semiconductor wafer includes a plurality of semiconductor chips arranged with scribe lines sandwiched between them. Each of the semiconductor chips includes a guard ring having a ring-shaped conductive film provided along the outer edge of the semiconductor chip, and electrode pads connected to the guard ring are provided on the scribe lines.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The disclosed technology relates to a semiconductor wafer and a method for inspecting the semiconductor wafer. [Background technology]

[0002] The following technologies are known as technologies related to semiconductor wafers: Patent Document 1 describes a semiconductor wafer in which a plurality of chip regions on which semiconductor elements are formed are defined between adjacent chip regions via scribe regions, and the semiconductor wafer has a monitor element arranged in the scribe region, pads arranged in the chip region, wiring connecting the monitor element and the pad, and a guard ring arranged along the edge of the chip region and having a notch formed therein for passing the wiring.

[0003] Patent document 2 describes a semiconductor wafer on which a large number of semiconductor chips are arranged, each of the arranged semiconductor chips having a plurality of pads, and in which pads of adjacent semiconductor chips facing each other across a scribe area are individually electrically connected by a conductive layer formed in this scribe area, and in which test pads are formed in this scribe area, each of which is individually electrically connected to each of the conductive layers.

[0004] Patent document 3 describes a semiconductor device in which a plurality of semiconductor chips each having a bonding pad are arranged side by side on the main surface of a semiconductor wafer, and each semiconductor chip has the same configuration, and in which at least two conductivity detection pads, which are electrically connected to each other along the direction in which the semiconductor chips are arranged side by side and have an area smaller than the bonding pads, are provided in the scribe region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-87354 [Patent Document 2] Japanese Patent Application Publication No. 6-151535 [Patent Document 3] Japanese Patent Application Publication No. 6-45419 Summary of the Invention [Problem to be solved by the invention]

[0006] A TEG (Test Elementary Group) formed on a semiconductor wafer is a test pattern used, for example, to monitor the manufacturing process of a semiconductor device. TEGs are not involved in the essential functions of a semiconductor device and are generally provided in scribe lines to avoid increasing the area of ​​semiconductor chips. Therefore, the area available for providing TEGs is limited. Furthermore, only a small number of TEGs can be provided per exposure shot layout. Due to these circumstances, the placement positions and number of TEGs within a semiconductor wafer are limited. For semiconductor chips located in areas of the semiconductor wafer where TEGs are not provided, process monitoring using TEGs is not possible, making it difficult to detect specific process anomalies.

[0007] The disclosed technology has been made in view of the above points, and aims to enable process monitoring for each semiconductor chip without increasing the area of ​​the semiconductor chip. [Means for solving the problem]

[0008] The semiconductor wafer according to the disclosed technology is a semiconductor wafer having a plurality of semiconductor chips arranged with scribe lines sandwiched between them, each of the plurality of semiconductor chips having a guard ring with a ring-shaped conductive film provided along the outer edge of the semiconductor chip, and an electrode pad connected to the guard ring is provided on the scribe line.

[0009] The semiconductor wafer inspection method according to the disclosed technique is the above-described semiconductor wafer inspection method, in which the electrical characteristics of the structure that constitutes the guard ring are obtained via the electrode pad. [Effects of the Invention]

[0010] According to the disclosed technology, it is possible to perform process monitoring for each semiconductor chip without increasing the area of ​​the semiconductor chip. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing an example of a schematic configuration of a semiconductor wafer according to an embodiment of the disclosed technique; [Figure 2] 1 is a plan view showing an example of a schematic configuration of a semiconductor chip according to an embodiment of the disclosed technique; [Figure 3] 1 is an enlarged plan view showing the vicinity of an outer edge portion and a scribe line of a semiconductor chip according to an embodiment of the disclosed technique; [Figure 4A] FIG. 4 is a cross-sectional view taken along line 4A-4A in FIG. 3. [Figure 4B] FIG. 4 is a cross-sectional view taken along line 4B-4B in FIG. 3. [Figure 4C] FIG. 4 is a cross-sectional view taken along line 4C-4C in FIG. 3. [Figure 4D] FIG. 4 is a cross-sectional view taken along line 4D-4D in FIG. 3. [Figure 5] FIG. 10 is a plan view showing an example of a schematic configuration of a semiconductor wafer according to another embodiment of the disclosed technique. [Figure 6] 1 is a plan view showing an example of a schematic configuration of a semiconductor chip according to an embodiment of the disclosed technique; [Figure 7] 1 is a diagram showing an example of a cross section along a current path of a test current in a semiconductor chip according to an embodiment of the disclosed technique; [Figure 8] 1 is a diagram showing an example of a cross section along a current path of a test current in a semiconductor chip according to an embodiment of the disclosed technique; DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, the disclosed embodiments will be described with reference to the drawings, in which the same reference numerals are used to designate substantially the same or equivalent components or parts.

[0013] 1 is a plan view showing an example of a schematic configuration of a semiconductor wafer 10 according to an embodiment of the disclosed technique. The semiconductor wafer 10 is configured to include a semiconductor such as silicon. The semiconductor wafer 10 has a plurality of semiconductor chips 20 arranged with scribe lines 30 sandwiched therebetween. The semiconductor wafer 10 is cut along the scribe lines 30 to separate the plurality of semiconductor chips 20.

[0014] FIG. 2 is a plan view showing an example of a schematic configuration of a semiconductor chip 20. The semiconductor chip 20 has a square or rectangular outer shape. The semiconductor chip 20 has an annular guard ring 21 provided along the outer edge of the semiconductor chip 20. The area inside the guard ring 21 of the semiconductor chip 20 is a device area 22 in which devices that realize the original functions of the semiconductor chip 20 are formed. For example, a circuit composed of elements such as transistors, resistors, capacitors, and wiring is formed in the device area 22. In FIG. 2, the detailed configuration of the device area 22 is omitted. By surrounding the outer periphery of the device area 22 with the guard ring 21, it is possible to reduce the risk of cracks that may occur when cutting the semiconductor wafer 10 along the scribe lines 30 reaching the device area 22.

[0015] Fig. 3 is an enlarged plan view showing the vicinity of the outer edge of the semiconductor chip 20 and the scribe line 30. Fig. 4A is a cross-sectional view taken along line 4A-4A in Fig. 3, Fig. 4B is a cross-sectional view taken along line 4B-4B in Fig. 3, Fig. 4C is a cross-sectional view taken along line 4C-4C in Fig. 3, and Fig. 4D is a cross-sectional view taken along line 4D-4D in Fig. 3.

[0016] The semiconductor chip 20 has a semiconductor substrate 23 made of a semiconductor such as silicon, and a wiring layer 25 provided on the surface of the semiconductor substrate 23. The guard ring 21 is provided on the wiring layer 25. FIGS. 4A to 4D show an example of a wiring layer 25 having four layers. The guard ring 21 has a conductive film 26A provided on the wiring layer 25A, a conductive film 26B provided on the wiring layer 25B, a conductive film 26C provided on the wiring layer 25C, and a conductive film 26D provided on the wiring layer 25D. Each of the conductive films 26A to 26D has a ring shape that follows the outer edge of the semiconductor chip 20.

[0017] Conductive film 26A is connected to semiconductor substrate 23 through via 27A. Conductive film 26B is connected to conductive film 26A in the layer immediately below through via 27B. Conductive film 26C is connected to conductive film 26B in the layer immediately below through via 27C. Conductive film 26D is connected to conductive film 26C in the layer immediately below through via 27D. Conductive films 26A to 26D and vias 27A to 27D are embedded inside insulating film 24 made of an insulator such as SiO2.

[0018] Each of the conductive films 26A to 26D that make up the guard ring 21 is formed by the same process as the wiring (not shown) provided in the wiring layer 25 of the device region 22. Similarly, the vias 27A to 27D that make up the guard ring 21 are formed by the same process as the vias (not shown) provided in the wiring layer 25 of the device region 22.

[0019] 4A, a lead-out wiring 40A is connected to the conductive film 26A that constitutes the guard ring 21. The tip of the lead-out wiring 40A reaches the scribe line 30. The tip of the lead-out wiring 40A is connected to an electrode pad 42A through a via 41A. That is, the electrode pad 42A is electrically connected to the conductive film 26A. The electrode pad 42A is provided on the scribe line 30 on the surface of the semiconductor wafer 10.

[0020] Similarly, as shown in FIG. 4B, a lead-out wiring 40B is connected to the conductive film 26B that constitutes the guard ring 21. The tip of the lead-out wiring 40B reaches the scribe line 30. The tip of the lead-out wiring 40B is connected to an electrode pad 42B through a via 41B. That is, the electrode pad 42B is electrically connected to the conductive film 26B. The electrode pad 42B is provided on the scribe line 30 on the surface of the semiconductor wafer 10.

[0021] Similarly, as shown in FIG. 4C , a lead-out wiring 40C is connected to the conductive film 26C that constitutes the guard ring 21. The tip of the lead-out wiring 40C reaches the scribe line 30. The tip of the lead-out wiring 40C is connected to an electrode pad 42C through a via 41C. That is, the electrode pad 42C is electrically connected to the conductive film 26C. The electrode pad 42C is provided on the scribe line 30 on the surface of the semiconductor wafer 10.

[0022] Similarly, as shown in FIG. 4D, a lead-out wiring 40D is connected to the conductive film 26D that constitutes the guard ring 21. The tip of the lead-out wiring 40D reaches the scribe line 30. The tip of the lead-out wiring 40D is connected to an electrode pad 42D. In other words, the electrode pad 42D is electrically connected to the conductive film 26D. The electrode pad 42D is provided on the scribe line 30 on the surface of the semiconductor wafer 10.

[0023] As described above, the vias 27A to 27D that constitute the guard ring 21 are formed by the same process as the vias (not shown) that are provided in the wiring layer 25 of the device region 22. Therefore, the vias 27A to 27D that constitute the guard ring 21 are formed with substantially the same workmanship as the vias that are provided in the wiring layer 25 of the device region 22. Therefore, the guard ring 21 functions as a TEG for process monitoring. More specifically, the guard ring 21 functions as a TEG for process monitoring of the vias.

[0024] For example, it is possible to measure the electrical resistance of the via 27B by bringing an inspection probe (not shown) into contact with the electrode pad 42A and the electrode pad 42B and measuring the electrical resistance between these electrode pads. This allows process monitoring of a via (not shown) provided in the same layer as the via 27B in the device region 22.

[0025] Furthermore, for example, it is possible to measure the electrical resistance of the via 27C by bringing an inspection probe (not shown) into contact with the electrode pad 42B and the electrode pad 42C and measuring the electrical resistance between these electrode pads. This allows process monitoring of a via (not shown) provided in the same layer as the via 27C in the device region 22.

[0026] Furthermore, for example, it is possible to measure the electrical resistance of the via 27D by bringing an inspection probe (not shown) into contact with the electrode pad 42C and the electrode pad 42D and measuring the electrical resistance between these electrode pads. This allows process monitoring of a via (not shown) provided in the same layer as the via 27D in the device region 22.

[0027] Furthermore, for example, by bringing an inspection probe (not shown) into contact with electrode pad 42A and electrode pad 42D and measuring the electrical resistance between these electrode pads, it is possible to measure the combined resistance of vias 27B, 27C, and 27D. This allows process monitoring of each via (not shown) provided in the same layer as vias 27B, 27C, and 27D in device region 22.

[0028] The semiconductor wafer 10 according to this embodiment realizes an inspection method for determining the formation process of the corresponding via based on the measured value of the electrical resistance between the electrode pads. For example, if the measured value of the electrical resistance between the electrode pads 42A and 42B is greater than a threshold value, it can be determined that there is an abnormality in the formation process of the via provided in the same layer as the via 27B in the device region 22.

[0029] As described above, the semiconductor wafer 10 according to the embodiment of the disclosed technique has a plurality of semiconductor chips 20 arranged with scribe lines 30 sandwiched between them. Each of the plurality of semiconductor chips 20 has a guard ring 21 having annular conductive films 26A-26D provided along the outer edge of the semiconductor chip. Electrode pads 42A-42D connected to the guard ring 21 are provided on the scribe line 30. The guard ring 21 has a plurality of annular conductive films 26A-27D provided on each of the plurality of wiring layers 25A-25D and connected to each other through vias 27A-27D.

[0030] The inspection method according to the embodiment of the disclosed technique includes acquiring the electrical characteristics of the structure that constitutes the guard ring 21 via the electrode pads 42A to 42D, and making a judgment about the via formation process based on the acquired electrical characteristics.

[0031] TEGs are not involved in the essential functions of a semiconductor device and are generally provided in scribe lines on a semiconductor wafer to avoid increasing the area of ​​the semiconductor chip. Therefore, the area available for providing TEGs is limited. Furthermore, only a small number of TEGs can be provided per exposure shot layout. Due to these circumstances, the placement positions and number of TEGs on a semiconductor wafer are limited. For semiconductor chips located in areas of the semiconductor wafer where TEGs are not provided, process monitoring using TEGs cannot be performed, making it difficult to detect specific process anomalies.

[0032] According to the semiconductor wafer 10 of the first embodiment of the disclosed technology, the guard ring 21 formed on each semiconductor chip 20 functions as a TEG for process monitoring, making it possible to process monitor each semiconductor chip without increasing the area of ​​the semiconductor chip 20.

[0033] [Second embodiment] FIG. 5 is a plan view showing an example of a schematic configuration of a semiconductor wafer 10A according to the second embodiment of the disclosed technique.

[0034] As described above, the conductive films 26A to 26D that constitute the guard ring 21 are formed by the same process as the wiring (not shown) provided in the wiring layer 25 of the device region 22. Therefore, the conductive films 26A to 26D that constitute the guard ring 21 are formed with substantially the same quality as the wiring provided in the wiring layer 25 of the device region 22. Therefore, in the semiconductor wafer 10A according to this embodiment, the guard ring 21 functions as a TEG for process monitoring of the wiring provided in the wiring layer 25 of the device region 22.

[0035] 5, lead-out wirings 40D1 and 40D2 are connected to different locations on conductive film 26D that constitutes guard ring 21. The tips of lead-out wirings 40D1 and 40D2 reach scribe line 30. Lead-out wirings 40D1 and 40D2 are connected to electrode pads 42D1 and 42D2, respectively. That is, electrode pads 42D1 and 42D2 are electrically connected to conductive film 26D that constitutes guard ring 21. Electrode pads 42D1 and 42D2 are provided on scribe line 30 on the surface of semiconductor wafer 10A.

[0036] The electrical resistance of the conductive film 26D can be measured by bringing an inspection probe (not shown) into contact with the electrode pad 42D1 and the electrode pad 42D2 and measuring the electrical resistance between these electrode pads. This allows process monitoring of wiring (not shown) provided in the same layer as the conductive film 26D in the device region 22.

[0037] Similarly, by connecting lead wiring and electrode pads to the conductive films 26A to 26C that make up the guard ring 21, process monitoring of wiring (not shown) provided in the same layer as the conductive films 26A to 26C in the device region 22 is possible.

[0038] As described above, according to the semiconductor wafer 10A of the second embodiment of the disclosed technology, similar to the semiconductor wafer 10 of the first embodiment, the guard ring 21 formed on each semiconductor chip 20 functions as a TEG for process monitoring, making it possible to process monitor each semiconductor chip without increasing the area of ​​the semiconductor chip 20.

[0039] [Third embodiment] When the guard ring 21 is used as a TEG for process monitoring, it is preferable that as many vias as possible be arranged on the path of the test current among the vias constituting the guard ring 21. For example, as illustrated in Fig. 6, by forming a current path P1 of the test current that starts at electrode pad 42E, goes around the guard ring 21 almost once, and reaches electrode pad 42F, it is possible to arrange many vias constituting the guard ring 21 on the current path P1. The electrode pads 42E and 42F are arranged on the scribe lines and are connected to the conductive film constituting the guard ring 21 via lead wirings 40E and 40F, respectively.

[0040] 7 is a diagram showing an example of a cross section along a current path P1 of a test current in a semiconductor chip 20. As shown in Fig. 7, by making the current path P1 of the test current a path that repeatedly travels back and forth between the wiring layer 25A and the wiring layer 25D, it becomes possible to arrange all of the vias 27 arranged between the wiring layers 25A to 25D on the current path P1. In this embodiment, for example, process monitoring for the purpose of managing the quality of a product becomes possible.

[0041] FIG. 8 is a diagram showing another example of a cross section of a semiconductor chip along the current path P1 of the test current. As shown in FIG. 8, by making the current path P1 of the test current a path that repeatedly travels back and forth between specific wiring layers, it is possible to arrange only vias arranged in specific layers on the current path P1. FIG. 8 illustrates a configuration in which, of the multiple vias that make up the guard ring 21, only via 27 arranged between wiring layers 25B and 25C is arranged on the current path P1. This configuration realizes, for example, a process monitor aimed at identifying an abnormal process. Depending on the layout of the guard ring 21, it is also possible to arrange vias arranged in other layers on the current path P1.

[0042] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) A semiconductor wafer having a plurality of semiconductor chips arranged with scribe lines therebetween, each of the plurality of semiconductor chips has a guard ring having a ring-shaped conductive film provided along an outer edge of the semiconductor chip; The scribe line is provided with an electrode pad connected to the guard ring. Semiconductor wafer.

[0043] (Appendix 2) The guard ring is provided in each of a plurality of wiring layers and has a plurality of annular conductive films connected to each other through vias. 2. The semiconductor wafer of claim 1.

[0044] (Appendix 3) A semiconductor wafer inspection method according to claim 1 or 2, comprising: The electrical characteristics of the structure that constitutes the guard ring are acquired via the electrode pad. Testing method.

[0045] (Appendix 4) the guard ring includes a plurality of annular conductive films provided in each of a plurality of wiring layers and connected to each other through vias; A determination is made regarding a process for forming the via based on the electrical characteristics. Testing method described in Appendix 3. [Explanation of symbols]

[0046] 10, 10A semiconductor wafer 20 Semiconductor chips 21 Guard Ring 30 Scribe Line 42A, 42B, 42C, 42D electrode pads

Claims

1. A semiconductor wafer having a plurality of semiconductor chips arranged with scribe lines therebetween, each of the plurality of semiconductor chips has a guard ring having a ring-shaped conductive film provided along an outer edge of the semiconductor chip; The scribe line is provided with an electrode pad connected to the guard ring. Semiconductor wafer.

2. The guard ring is provided in each of a plurality of wiring layers and has a plurality of annular conductive films connected to each other through vias. The semiconductor wafer of claim 1 .

3. 2. The semiconductor wafer inspection method according to claim 1, The electrical characteristics of the structure that constitutes the guard ring are acquired via the electrode pad. Testing method.

4. the guard ring includes a plurality of annular conductive films provided in each of a plurality of wiring layers and connected to each other through vias; A determination is made regarding a process for forming the via based on the electrical characteristics. The inspection method according to claim 3.

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