Method of manufacturing semiconductor device and semiconductor device

Abstract

To provide a technique capable of securing a breakdown voltage of a super junction (SJ) structure.SOLUTION: Disclosed is a method of manufacturing a semiconductor device comprising a multilayer SJ structure. In a lower-side SJ layer, a lower-side first column of a first conductivity type and a lower-side second column of a second conductivity type are repeatedly disposed in a first direction. In an upper-side SJ layer, an upper-side first column of the first conductivity type and an upper-side second column of the second conductivity type are repeatedly disposed in a second direction. The manufacturing method includes the step of forming an upper-side semiconductor layer of the first conductivity type on a top face of the lower-side SJ layer. The manufacturing method includes the step of forming an upper-side mask layer comprising an opening corresponding to the upper-side second column on a top face of the upper-side semiconductor layer. The manufacturing method includes a first injection step of injecting a first impurity of the first conductivity type to the top face of the lower-side SJ layer via the upper-side mask layer. The manufacturing method includes a second injection step of performing multistep injection of a second impurity of the second conductivity type to the entire upper-side semiconductor layer in a depth direction via the upper-side mask layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device with a stacked superjunction structure in which an upper superjunction layer is stacked on a lower superjunction layer. In the lower superjunction layer, n-type columns and p-type columns are alternately and repeatedly arranged along a first direction. In the upper superjunction layer, n-type columns and p-type columns are alternately and repeatedly arranged along a second direction that is angled with the first direction.

[0003] The process for fabricating the upper superjunction layer begins with growing an n-type epitaxial layer on the lower superjunction layer. Next, a mask layer with openings corresponding to the p-type columns of the upper superjunction layer is formed on the surface of the epitaxial layer. P-type impurities are implanted in multiple stages through the mask layer throughout the entire depth of the epitaxial layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-89916 Summary of the Invention [Problem to be solved by the invention]

[0005] In the multistage implantation of the upper superjunction layer, ions are implanted so that the peak concentration of p-type impurities is constant from the top to the bottom of the p-type columns. Therefore, when ions are implanted into the bottom of the p-type columns of the upper superjunction layer, the peak concentration is located at the bottom. This inevitably results in p-type impurities being implanted into the top surface of the lower superjunction layer. This is because ion implantation has a Gaussian concentration distribution with tails on both sides of the concentration peak. When p-type impurities are implanted into the top surface of the p-type columns of the lower superjunction layer, the amount of p-type charge on this top surface increases. Furthermore, when p-type impurities are implanted into the top surface of the n-type columns of the lower superjunction layer, the amount of n-type charge on this top surface decreases. This disrupts the charge balance between the parallel p-type and n-type columns in the lower superjunction layer, which may result in a decrease in breakdown voltage. [Means for solving the problem]

[0006] One embodiment of a method for manufacturing a semiconductor device disclosed herein is a method for manufacturing a semiconductor device having a stacked superjunction structure including a lower superjunction layer and an upper superjunction layer disposed on an upper surface of the lower superjunction layer. The lower superjunction layer has lower first columns of a first conductivity type and lower second columns of a second conductivity type alternately arranged along a first direction. The upper superjunction layer has upper first columns of the first conductivity type and upper second columns of the second conductivity type alternately arranged along a second direction that is angled with the first direction. The manufacturing method includes a step of forming an upper semiconductor layer of a first conductivity type on an upper surface of the lower superjunction layer. The manufacturing method also includes a step of forming an upper mask layer on an upper surface of the upper semiconductor layer, the upper mask layer having openings corresponding to the upper second columns. The manufacturing method also includes a first implantation step of implanting a first impurity of a first conductivity type into the upper surface of the lower superjunction layer via the upper mask layer. The manufacturing method includes a second implantation step of implanting a second impurity of a second conductivity type in multiple stages into the entire upper semiconductor layer in the depth direction through the upper mask layer.

[0007] One embodiment of a method for manufacturing a semiconductor device disclosed herein is a method for manufacturing a semiconductor device having a stacked superjunction structure including a lower superjunction layer and an upper superjunction layer disposed on an upper surface of the lower superjunction layer. The lower superjunction layer has lower first columns of a first conductivity type and lower second columns of a second conductivity type alternately arranged along a first direction. The upper superjunction layer has upper first columns of the first conductivity type and upper second columns of the second conductivity type alternately arranged along a second direction that is angled with the first direction. The manufacturing method includes a step of forming a lower mask layer on an upper surface of the lower superjunction layer, the lower mask layer having openings corresponding to the upper second columns. The manufacturing method includes a first implantation step of implanting a first impurity of the first conductivity type into the upper surface of the lower superjunction layer through the lower mask layer. The manufacturing method includes a step of forming an upper semiconductor layer of the first conductivity type on the upper surface of the lower superjunction layer. The manufacturing method includes a step of forming an upper mask layer on an upper surface of the upper semiconductor layer, the upper mask layer having openings corresponding to the upper second columns. The manufacturing method includes a second implantation step of implanting a second impurity of a second conductivity type in multiple stages into the entire upper semiconductor layer in the depth direction through the upper mask layer.

[0008] A second conductivity type upper second column is formed in the upper superjunction layer by the second implantation step. At this time, a second conductivity type second impurity is implanted into a region of the upper surface of the lower superjunction layer corresponding to the upper second column. Therefore, the above method includes a first implantation step of implanting a first conductivity type first impurity into a region of the upper surface of the lower superjunction layer corresponding to the upper second column. This allows the first impurity implanted into the upper surface of the lower superjunction layer by the first implantation step to offset the effect of the second impurity implanted into the upper surface of the lower superjunction layer by the second implantation step. Since this suppresses deterioration of charge balance, it is possible to prevent events in which desired electrical characteristics, such as breakdown voltage, cannot be obtained.

[0009] One embodiment of a semiconductor device disclosed herein is a semiconductor device with a stacked superjunction structure including a lower superjunction layer and an upper superjunction layer disposed on an upper surface of the lower superjunction layer. The lower superjunction layer has lower first columns of a first conductivity type and lower second columns of a second conductivity type alternately arranged along a first direction. The upper superjunction layer has upper first columns of the first conductivity type and upper second columns of the second conductivity type alternately arranged along a second direction forming an angle with the first direction. When viewed from above, the lower superjunction layer has a first overlap region overlapping with the upper first columns and a second overlap region overlapping with the upper second columns. The concentration of a first impurity of the first conductivity type doped into the upper surface of the lower superjunction layer in the second overlap region is higher than the concentration of the first impurity doped into the upper surface of the lower superjunction layer in the first overlap region.

[0010] The concentration of the second impurity of the second conductivity type doped into the upper surface of the lower superjunction layer may be higher in the second overlap region than in the first overlap region. Therefore, in the above configuration, the concentration of the first impurity of the first conductivity type doped into the upper surface of the lower superjunction layer is made higher in the second overlap region than in the first overlap region. This allows the influence of the second impurity to be offset by the first impurity in the upper surface of the lower superjunction layer in the second overlap region. Since deterioration of charge balance can be suppressed, it is possible to prevent events in which desired electrical characteristics such as breakdown voltage cannot be obtained. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a perspective view of a semiconductor device disclosed in the present specification; [Figure 2] FIG. 1 is a flow chart showing a manufacturing method in Example 1. [Figure 3] FIG. 10 is a perspective view showing some steps of a manufacturing method. [Figure 4]FIG. 10 is a perspective view showing some steps of a manufacturing method. [Figure 5] FIG. 10 is a perspective view showing some steps of a manufacturing method. [Figure 6] FIG. 10 is a perspective view showing some steps of a manufacturing method. [Figure 7] FIG. 10 is a perspective view showing some steps of a manufacturing method. [Figure 8] FIG. 10 is a perspective view showing some steps of a manufacturing method. [Figure 9] FIG. 10 is a cross-sectional view showing a stacked SJ structure SS of a comparative example. [Figure 10] FIG. 1 is a cross-sectional view showing a stacked SJ structure SS in the technology of the present specification. [Figure 11] FIG. 1 is a cross-sectional view showing a stacked SJ structure SS in the technology of the present specification. [Figure 12] FIG. 1 is a flow chart showing a manufacturing method in Example 2. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0012] Hereinafter, the semiconductor device disclosed in this specification will be described with reference to the drawings. For the purpose of clarity in the drawings, when components are repeatedly arranged, only one of them may be designated by a reference numeral.

[0013] 1, the semiconductor device 1 is a type of power semiconductor device known as a MOSFET. The semiconductor device 1 includes a semiconductor substrate 10, a drain electrode 22 covering the lower surface of the semiconductor substrate 10, a source electrode 24 covering the upper surface of the semiconductor substrate 10, and a plurality of trench gates 30 provided in the upper layer of the semiconductor substrate 10.

[0014] The material of the semiconductor substrate 10 is not particularly limited. In this embodiment, silicon carbide is used. The n-type impurity is phosphorus, and the p-type impurity is aluminum. The semiconductor substrate 10 is made of n +The semiconductor device includes an n-type drain region 11, an n-type drift region 12, a lower superjunction layer 13, an upper superjunction layer 14, a body region 15, and a source region 16. In the following, the superjunction layer may be abbreviated as "SJ layer."

[0015] The drain region 11 is provided at a position exposed on the lower surface of the semiconductor substrate 10. The drain region 11 contains a high concentration of n-type impurities and is in ohmic contact with the drain electrode 22. The drift region 12 is provided between the drain region 11 and the lower SJ layer 13 and is in contact with both the drain region 11 and the lower SJ layer 13. The concentration of n-type impurities in the drift region 12 is lower than the concentration of n-type impurities in the drain region 11.

[0016] A stacked SJ structure SS is disposed on the upper surface of the drift region 12. The stacked SJ structure SS includes a lower SJ layer 13 and an upper SJ layer 14 disposed on the upper surface of the lower SJ layer.

[0017] The lower SJ layer 13 includes a plurality of n-type lower first columns 13n and a plurality of p-type lower second columns 13p. The lower first columns 13n and the lower second columns 13p are alternately arranged along a first direction. In this embodiment, the first direction is the y direction.

[0018] The lower SJ layer 13 is configured such that, in the repeating direction (y direction), the amount of positive charge when the lower first columns 13n are depleted and the amount of negative charge when the lower second columns 13p are depleted are balanced, thereby forming a so-called superjunction structure.

[0019] The upper SJ layer 14 includes a plurality of n-type upper first columns 14n and a plurality of p-type upper second columns 14p. The upper first columns 14n and the upper second columns 14p are alternately arranged along a second direction that is angled with the first direction. In this embodiment, the second direction is the x-direction. That is, in this embodiment, the first and second directions are orthogonal to each other. Similar to the lower SJ layer 13, a superjunction structure is also formed in the upper SJ layer 14.

[0020] The body region 15 is disposed on the upper SJ layer 14. The body region 15 is provided between the upper SJ layer 14 and the source region 16, contacts both the upper SJ layer 14 and the source region 16, and separates the upper SJ layer 14 from the source region 16. The body region 15 is electrically connected to the source electrode 24 via a p-type contact region (not shown). The concentration of p-type impurities in the body region 15 is adjusted according to the desired gate threshold voltage.

[0021] The source region 16 is provided on the body region 15, and is provided at a position exposed on the upper surface 10s of the semiconductor substrate 10. The source region 16 contacts the upper side surface of the trench gate 30. The source region 16 contains a high concentration of n-type impurities and is in ohmic contact with the source electrode 24.

[0022] A plurality of trenches TR extend from the surface of the source region 16 through the body region 15 to reach the upper first column 14n. A trench gate 30 is disposed inside each of the trenches TR. Each of the trench gates 30 includes a gate electrode 32 and a gate insulating film 34. The gate insulating film 34 is formed of silicon oxide and covers the inner wall of the trench. The gate electrode 32 is formed of polysilicon containing impurities and faces the semiconductor substrate 10 via the gate insulating film 34. Each of the trench gates 30 extends along the y direction in a cross section of the semiconductor substrate 10. The trench gates 30 are also disposed at intervals from one another along the direction (x direction) perpendicular to the longitudinal direction. That is, when the semiconductor substrate 10 is viewed in a plan view (when viewed from the z direction), the trench gates 30 are located within the region of the upper first column 14n.

[0023] (Method of manufacturing semiconductor device 1) Some steps in the method for manufacturing the semiconductor device 1 will be described with reference to the flow in Fig. 2 and Fig. 3 to Fig. 8. For the other steps for manufacturing the semiconductor device 1, known manufacturing techniques can be used.

[0024] In step S10, n + A silicon carbide substrate is prepared (see FIG. 3). In step S20, an n-type silicon carbide lower semiconductor layer 13b is formed on the surface of the drain region 11. The n-type lower semiconductor layer 13b can be formed, for example, by epitaxial growth so as to contain n-type impurities.

[0025] In step S30, a lower mask layer 41 is formed on the upper surface of the lower semiconductor layer 13b using known photolithography techniques (see FIG. 3). The lower mask layer 41 is a striped mask having openings corresponding to the lower second columns 13p. The lower mask layer 41 may be a resist mask made of resist, or may be a hard mask made of a silicon oxide film or the like.

[0026] In step S40, a lower ion implantation process is performed, as shown in FIG. 4. Specifically, p-type impurities are implanted in multiple stages into the entire lower semiconductor layer 13b in the depth direction via the lower mask layer 41. This allows a plurality of lower first columns 13n and a plurality of lower second columns 13p to be formed in the upper layer portion of the lower semiconductor layer 13b. A lower SJ layer 13 is formed in the upper layer portion of the lower semiconductor layer 13b, and the lower layer portion of the lower semiconductor layer 13b becomes the drift region 12 (see FIG. 4). In step S50, the lower mask layer 41 is removed.

[0027] In step S60, an upper semiconductor layer 14u of n-type silicon carbide is formed on the surface of the lower SJ layer 13 (see FIG. 5). The n-type upper semiconductor layer 14u can be formed, for example, by epitaxial growth so as to contain n-type impurities.

[0028] In step S70, an upper mask layer 42 is formed on the upper surface of the upper semiconductor layer 14u using known photolithography techniques (see FIG. 5). The upper mask layer 42 is a striped mask having openings corresponding to the upper second columns 14p. The upper mask layer 42 may be a resist mask made of resist, or may be a hard mask made of a silicon oxide film or the like.

[0029] When the upper semiconductor layer 14u is viewed vertically from above (in the +z direction), the lower SJ layer 13 includes a first overlapping region OA1 and a second overlapping region OA2. The first overlapping region OA1 is a region that overlaps with the upper mask layer 42 (i.e., a region that overlaps with the upper first column 14n). The second overlapping region OA2 is a region that does not overlap with the upper mask layer 42 (i.e., a region that overlaps with the upper second column 14p).

[0030] In step S80, a first implantation process is performed. Specifically, as shown in FIG. 6, n-type impurities are implanted into the upper surface of the lower SJ layer 13 through the upper mask layer 42. That is, high-energy implantation causes the n-type impurities to pass through the upper semiconductor layer 14u and reach the upper surface of the lower SJ layer 13. As a result, the n-type impurities are implanted into the upper surface of the lower SJ layer 13 in the second overlap region OA2 at a first concentration. The first concentration will be described later. In FIG. 6, the n-type impurities implanted into the upper surface of the lower SJ layer 13 in the first implantation process are schematically indicated by crosses. Impurities added to the lower SJ layer 13 in processes other than the first implantation process are not shown.

[0031] In the first implantation step, n-type impurities are selectively implanted only into the upper surface of the lower SJ layer 13 included in the second overlapping region OA2. Therefore, a characteristic concentration profile is formed in which the concentration of n-type impurities doped into the upper surface of the lower SJ layer 13 in the second overlapping region OA2 is higher than the concentration of n-type impurities doped into the upper surface of the lower SJ layer 13 in the first overlapping region OA1 (see the cross marks in FIG. 6).

[0032] In step S90, a second implantation process is performed. The second implantation process is performed by directly using the upper mask layer 42 used in the first implantation process. Specifically, as shown in FIG. 7, p-type impurities are implanted in multiple stages into the entire upper semiconductor layer 14u in the depth direction through the upper mask layer 42. This allows a plurality of upper first columns 14n and a plurality of upper second columns 14p to be formed in the upper semiconductor layer 14u. In other words, the upper semiconductor layer 14u can be converted into the upper SJ layer 14.

[0033] The multistage implantation of the upper semiconductor layer 14u is performed so that the concentration peak of the p-type impurity is constant from the top to the bottom of the upper second column 14p. Therefore, when ions are implanted into the bottom of the upper second column 14p, the concentration peak is located at the bottom. As a result, the p-type impurity is inevitably implanted into the top surface of the lower SJ layer 13 in the second overlap region OA2. This is because the ion implantation has a Gaussian concentration distribution with tails on both sides of the concentration peak. Note that in FIG. 7, the p-type impurity implanted into the top surface of the lower SJ layer 13 by the second implantation process is schematically indicated by a circle. Impurities added to the lower SJ layer 13 by processes other than the second implantation process are not shown.

[0034] In step S100, the upper mask layer 42 is removed. In step S110, the body region 15 and the source region 16 are formed on the upper SJ layer 14 (see FIG. 8). The body region 15 may be formed by epitaxial growth so as to contain p-type impurities. The source region 16 may be formed by ion implantation of n-type impurities into the upper surface of the body region 15.

[0035] In step S120, trenches TR are formed from the top surface of the source region 16, penetrating the source region 16 and the body region 15 to reach the upper first column 14n (see FIG. 8). The trenches TR can be formed using a known dry etching technique. In step S130, trench gates 30 are formed in the trenches TR, and the source electrode 24 and the drain electrode 22 are also formed. This completes the semiconductor device 1 shown in FIG.

[0036] (assignment) The problem will be explained using the stacked SJ structure SS of the comparative example in Figure 9. Figure 9 is a view of the semiconductor device 1 of Figure 1 as seen from the +x direction. In other words, Figure 9 is a cross-sectional view in the yz plane passing through the upper second column 14p (i.e., a cross-sectional view in the yz plane passing through the second overlap region OA2). Note that Figure 9 focuses on only the stacked SJ structure SS.

[0037] The upper second columns 14p of the upper SJ layer 14 are formed by multi-stage implantation of p-type impurities in the second implantation step (S90). As described above, in this second implantation step, the p-type impurities are inevitably implanted into the upper surface of the lower SJ layer 13 in the second overlap region OA2. In FIG. 9, the p-type impurities implanted into the upper surface of the lower SJ layer 13 in the second implantation step are schematically indicated by circles. When p-type impurities are additionally implanted into the upper surface of the p-type lower second columns 13p, the amount of p-type charge on this upper surface increases (see region Rp). Furthermore, when p-type impurities are counter-implanted into the upper surface of the n-type lower first columns 13n, the amount of n-type charge on this upper surface decreases (see region Rn). This disruption of the charge balance between the parallel lower second columns 13p and lower first columns 13n may result in failure to achieve desired electrical characteristics, such as breakdown voltage.

[0038] (Solution) A solution to the above problem will be described using the stacked SJ structure SS in the technology of this specification in Figures 10 and 11. The content of Figure 10 is similar to that of Figure 9 described above, so a description thereof will be omitted. Figure 11 is a cross-sectional view in the yz plane passing through the upper first column 14n (i.e., a cross-sectional view in the yz plane passing through the first overlap region OA1).

[0039] In the second implantation step (S90), as described above, p-type impurities are implanted into the upper surface of the lower SJ layer 13 in the second overlapping region OA2. In FIG. 10, the p-type impurities implanted into the upper surface of the lower SJ layer 13 in the second implantation step are schematically indicated by circles. The technology of this specification further includes a first implantation step (S80). In the first implantation step, n-type impurities are implanted at a first concentration into the upper surface of the lower SJ layer 13 in the second overlapping region OA2. In FIG. 10, the n-type impurities implanted into the upper surface of the lower SJ layer 13 in the first implantation step are schematically indicated by crosses.

[0040] As a result, in the second overlapping region OA2, the influence of p-type impurities unintentionally implanted into the upper surface of the lower SJ layer 13 can be mitigated by the counter-implanted n-type impurities (see regions Rp_C2 and Rn_C2). Since deterioration of the charge balance can be suppressed, it is possible to suppress the occurrence of an event in which the desired electrical characteristics, such as the breakdown voltage of the semiconductor device 1, cannot be obtained.

[0041] 11, in the first overlapping region OA1, p-type impurities are not implanted into the upper surface of the lower SJ layer 13 in the second implantation step (S90) and n-type impurities are not implanted into the upper surface of the lower SJ layer 13 (see regions Rp_C1 and Rn_C1). Therefore, in the first overlapping region OA1, deterioration of charge balance due to unintentionally implanted p-type impurities does not occur.

[0042] The first concentration of the n-type impurity implanted in the first implantation step is preferably a concentration that satisfies the following requirements: (1) The first concentration is a concentration that makes the amount of n-type charge on the upper surface of the n-type lower first column 13n approximately equal in the first overlap region OA1 (Rn_C1) and the second overlap region OA2 (Rn_C2) that are adjacent to each other. (2) The first concentration is a concentration that makes the amount of p-type charge on the upper surface of the p-type lower second column 13p approximately equal in the first overlap region OA1 (Rp_C1) and the second overlap region OA2 (Rp_C2) that are adjacent to each other. Using such a first concentration makes it possible to more appropriately maintain the charge balance between the lower first column 13n and the lower second column 13p.

[0043] In the technology of this specification, the lower first column 13n of the second overlap region OA2 has the following characteristics. In the lower first column 13n, the concentrations of n-type impurities and p-type impurities are higher in the second overlap region OA2 than in the first overlap region OA1, and the amount of n-type charge is approximately the same in the second overlap region OA2 and the first overlap region OA1. In the lower second column 13p, the concentrations of n-type impurities and p-type impurities are higher in the second overlap region OA2 than in the first overlap region OA1, and the amount of p-type charge is approximately the same in the second overlap region OA2 and the first overlap region OA1. The concentration of n-type impurities is higher on the top surface (region Rn_C) than in the interior (region Rn_I). Meanwhile, the amount of n-type charge is approximately the same on the top surface (region Rn_C) and the interior (region Rn_I). Similarly, the lower second column 13p of the second overlap region OA2 has the following characteristics. The concentration of n-type impurities is higher on the top surface (region Rp_C) than in the interior (region Rp_I). On the other hand, the amount of p-type charge is approximately the same on the top surface (region Rp_C) and in the interior (region Rp_I). The presence or absence of these characteristics can be easily identified by cross-sectional analysis and impurity concentration analysis.

[0044] (Other effects) In the technology of this embodiment, the n-type impurity is phosphorus and the p-type impurity is aluminum. Because these impurities have similar mass numbers, the depth control and scattering effects during ion implantation can be approximately matched. This allows the dose and depth profile of the p-type impurity (Al) implanted into the upper surface of the lower SJ layer 13 in the second implantation step (S90) to be approximately matched with the dose and depth profile of the n-type impurity (P) implanted into the upper surface of the lower SJ layer 13 in the first implantation step (S80). This makes it possible to more appropriately maintain charge balance on the upper surface of the lower SJ layer 13.

[0045] During the epitaxial growth (S60) of the upper semiconductor layer 14u, film thickness variations occur within the wafer surface. On the other hand, the ion implantation depth depends on the accelerating voltage of the equipment, and the depth is uniform within the wafer surface. Therefore, the depth profile of the p-type impurity implanted into the upper surface of the lower SJ layer 13 in the second implantation step (S90) reflects the in-plane variation of the upper semiconductor layer 14u, resulting in in-plane variation. Therefore, in the technology of this embodiment, the first implantation step (S80) is performed via the upper semiconductor layer 14u. This allows the in-plane variation of the upper semiconductor layer 14u to be reflected in the depth profile of the n-type impurity implanted into the upper surface of the lower SJ layer 13 in the first implantation step (S80). Since the in-plane variation of the depth profiles of the p-type impurity and the n-type impurity implanted into the upper surface of the lower SJ layer 13 can be matched, it is possible to suppress in-plane variation in charge balance. [Example]

[0046] In Example 2, an example in which the timing of performing the first injection step is changed will be described. Fig. 12 shows the manufacturing flow of Example 2. Note that, compared to the manufacturing flow of Example 1 (Fig. 2), only the differences will be described below.

[0047] In step S40, a lower ion implantation step is performed through the lower mask layer 41 (see FIG. 4). In step S42a, the lower mask layer 41 is removed. In step S44a, a specific mask layer 43 is formed on the upper surface of the lower SJ layer 13. The specific mask layer 43 is a striped mask having openings corresponding to the upper second columns 14p. The specific mask layer 43 may be formed by reusing the reticle for the upper mask layer 42. In step S46a, a first implantation step is performed. Specifically, n-type impurities are implanted into the upper surface of the lower SJ layer 13 through the specific mask layer 43. That is, the n-type impurities are implanted near the surface of the lower SJ layer 13 by low-energy implantation. In step S48a, the specific mask layer 43 is removed.

[0048] After the upper mask layer 42 is formed (S70), a second implantation step (S90) is performed. Since the first implantation step has already been performed in step S46a, the first implantation step using the upper mask layer 42 is not performed.

[0049] (effect) The first implantation step can be performed directly on the top surface of the lower SJ layer 13 without going through the upper SJ layer 14. This can prevent implantation damage to the upper SJ layer 14 during the first implantation step. It is possible to maintain high crystallinity of the upper SJ layer 14.

[0050] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility.

[0051] (Variation) The stacked SJ structure SS of this specification is not limited to MOSFETs and can be applied to various device structures such as diodes.

[0052] In Example 1 (FIG. 2), the order of the first injection step (S80) and the second injection step (S90) is not particularly limited. The first and second injection steps may be reversed or may be performed simultaneously.

[0053] The method for forming the n-type upper semiconductor layer 14u (S60) may be various. For example, after the upper semiconductor layer 14u is epitaxially grown, n-type impurities may be implanted into the entire surface in multiple stages.

[0054] The SJ structure in this specification is not limited to a stripe shape and may have various shapes. For example, the n-type columns and the p-type columns may be arranged in a lattice pattern when the semiconductor substrate 10 is viewed from above.

[0055] The material of the semiconductor substrate 10 is not limited to silicon carbide, and various materials can be used, such as silicon or various wide-gap semiconductors (such as gallium nitride and gallium oxide).

[0056] Aspects of the present technology are listed below. [Aspect 1] A method for manufacturing a semiconductor device (1) having a stacked superjunction structure (SS) including a lower superjunction layer (13) and an upper superjunction layer (14) disposed on an upper surface of the lower superjunction layer, comprising: In the lower superjunction layer, lower first columns (13n) of a first conductivity type and lower second columns (13p) of a second conductivity type are alternately and repeatedly arranged along a first direction (y direction), In the upper superjunction layer, upper first columns (14n) of a first conductivity type and upper second columns (14p) of a second conductivity type are alternately and repeatedly arranged along a second direction (x direction) that is angled with the first direction, A step (S60) of forming an upper semiconductor layer (14u) of a first conductivity type on an upper surface of the lower superjunction layer; a step (S70) of forming an upper mask layer (42) having openings corresponding to the upper second columns on the upper surface of the upper semiconductor layer; a first implantation step (S80) of implanting a first impurity (phosphorus) of a first conductivity type into the upper surface of the lower superjunction layer through the upper mask layer; a second implantation step (S90) of implanting a second impurity (aluminum) of a second conductivity type in multiple stages into the entire upper semiconductor layer in the depth direction through the upper mask layer; A method for manufacturing a semiconductor device, comprising: [Aspect 2] A method for manufacturing a semiconductor device having a stacked superjunction structure including a lower superjunction layer and an upper superjunction layer disposed on an upper surface of the lower superjunction layer, the method comprising: the lower superjunction layer has lower first columns of a first conductivity type and lower second columns of a second conductivity type alternately arranged along a first direction; the upper superjunction layer has upper first columns of a first conductivity type and upper second columns of a second conductivity type alternately arranged along a second direction that is angled with the first direction; a step (S44a) of forming a specific mask layer (43) having an opening corresponding to the upper second column on the upper surface of the lower superjunction layer; a first implantation step (S46a) of implanting a first impurity of a first conductivity type into the upper surface of the lower superjunction layer through the specific mask layer; A step (S60) of forming an upper semiconductor layer of a first conductivity type on an upper surface of the lower superjunction layer; a step (S70) of forming an upper mask layer (42) having openings corresponding to the upper second columns on the upper surface of the upper semiconductor layer; a second implantation step (S90) of implanting a second impurity of a second conductivity type in multiple stages into the entire upper semiconductor layer in a depth direction through the upper mask layer; A method for manufacturing a semiconductor device, comprising: [Aspect 3] When the upper superjunction layer is viewed vertically from above, the lower superjunction layer includes a first overlapping region (OA1) overlapping with the upper first column and a second overlapping region (OA2) overlapping with the upper second column; In the first implantation step, the first impurity is implanted into the upper surfaces of the lower first column and the lower second column at a first concentration; In the second implantation step, the second impurity is implanted into upper surfaces of the lower first column and the lower second column; The first concentration is The amount of charge of the first conductivity type on the upper surface of the lower first column is a concentration that is approximately the same in the first overlap region (Rn_C1) and the second overlap region (Rn_C2) adjacent to each other, and The method for manufacturing a semiconductor device according to aspect 1 or 2, wherein the amount of second conductivity type charge on the upper surface of the lower second column is at a concentration that is approximately the same in the first overlap region (Rp_C1) and the second overlap region (Rp_C2) adjacent to each other. [Aspect 4] the semiconductor material of the lower superjunction layer and the upper superjunction layer is silicon carbide; the first impurity is phosphorus; 4. The method for manufacturing a semiconductor device according to any one of aspects 1 to 3, wherein the second impurity is aluminum. [Aspect 5] A semiconductor device having a stacked superjunction structure including a lower superjunction layer and an upper superjunction layer disposed on an upper surface of the lower superjunction layer, the lower superjunction layer has lower first columns of a first conductivity type and lower second columns of a second conductivity type alternately arranged along a first direction; the upper superjunction layer has upper first columns of a first conductivity type and upper second columns of a second conductivity type alternately arranged along a second direction that is angled with the first direction; When the upper superjunction layer is viewed vertically from above, the lower superjunction layer includes a first overlapping region (OA1) overlapping with the upper first column and a second overlapping region (OA2) overlapping with the upper second column; a concentration of a first impurity of a first conductivity type doped into the upper surface of the lower superjunction layer in the second overlap region is higher than a concentration of the first impurity doped into the upper surface of the lower superjunction layer in the first overlap region; Semiconductor device. [Aspect 6] In the lower first column, the second overlapping region has a higher concentration of the first impurity and the second impurity of the second conductivity type than the first overlapping region, and the charge amount of the first conductivity type is substantially the same in the second overlapping region and the first overlapping region; A semiconductor device as described in aspect 5, wherein in the lower second column, the concentration of the first impurity and the second impurity is higher in the second overlap region than in the first overlap region, and the amount of charge of the second conductivity type is approximately the same in the second overlap region and the first overlap region. [Aspect 7] the semiconductor material of the lower superjunction layer and the upper superjunction layer is silicon carbide; the first impurity is phosphorus; 7. The semiconductor device of claim 5, wherein the second impurity of the second conductivity type is aluminum. [Explanation of symbols]

[0057] 1: semiconductor device 10: semiconductor substrate 13: lower superjunction layer 13n: lower first column 13p: lower second column 14: upper superjunction layer 14n: upper first column 14p: upper second column 14u: upper semiconductor layer 42: upper mask layer SS: stacked SJ structure

Claims

1. A method for manufacturing a semiconductor device (1) having a stacked superjunction structure (SS) including a lower superjunction layer (13) and an upper superjunction layer (14) disposed on an upper surface of the lower superjunction layer, comprising: In the lower superjunction layer, lower first columns (13n) of a first conductivity type and lower second columns (13p) of a second conductivity type are alternately and repeatedly arranged along a first direction (y direction), In the upper superjunction layer, upper first columns (14n) of a first conductivity type and upper second columns (14p) of a second conductivity type are alternately and repeatedly arranged along a second direction (x direction) that is angled with the first direction, A step (S60) of forming an upper semiconductor layer (14u) of a first conductivity type on an upper surface of the lower superjunction layer; a step (S70) of forming an upper mask layer (42) having openings corresponding to the upper second columns on the upper surface of the upper semiconductor layer; a first implantation step (S80) of implanting a first impurity (phosphorus) of a first conductivity type into the upper surface of the lower superjunction layer through the upper mask layer; a second implantation step (S90) of implanting a second impurity (aluminum) of a second conductivity type into the entire upper semiconductor layer in a depth direction through the upper mask layer in multiple stages; A method for manufacturing a semiconductor device, comprising:

2. A method for manufacturing a semiconductor device having a stacked superjunction structure including a lower superjunction layer and an upper superjunction layer disposed on an upper surface of the lower superjunction layer, the method comprising: the lower superjunction layer has lower first columns of a first conductivity type and lower second columns of a second conductivity type alternately arranged along a first direction; the upper superjunction layer has upper first columns of a first conductivity type and upper second columns of a second conductivity type alternately arranged along a second direction that is angled with the first direction, A step (S44a) of forming a specific mask layer (43) having an opening corresponding to the upper second column on the upper surface of the lower superjunction layer; a first implantation step (S46a) of implanting a first impurity of a first conductivity type into the upper surface of the lower superjunction layer through the specific mask layer; A step (S60) of forming an upper semiconductor layer of a first conductivity type on an upper surface of the lower superjunction layer; a step (S70) of forming an upper mask layer (42) having openings corresponding to the upper second columns on the upper surface of the upper semiconductor layer; a second implantation step (S90) of implanting a second impurity of a second conductivity type in multiple stages into the entire upper semiconductor layer in a depth direction through the upper mask layer; A method for manufacturing a semiconductor device, comprising:

3. When the upper superjunction layer is viewed from above vertically, the lower superjunction layer includes a first overlapping region (OA1) overlapping with the upper first column and a second overlapping region (OA2) overlapping with the upper second column; In the first implantation step, the first impurity is implanted into upper surfaces of the lower first column and the lower second column at a first concentration; In the second implantation step, the second impurity is implanted into upper surfaces of the lower first column and the lower second column; The first concentration is The amount of charge of the first conductivity type on the upper surface of the lower first column is at a concentration that is substantially the same in the first overlap region (Rn_C1) and the second overlap region (Rn_C2) adjacent to each other, and 3. The method for manufacturing a semiconductor device according to claim 1, wherein the amount of second conductivity type charge on the upper surface of the lower second column is at a concentration that is approximately the same in the first overlap region (Rp_C1) and the second overlap region (Rp_C2) adjacent to each other.

4. the semiconductor material of the lower superjunction layer and the upper superjunction layer is silicon carbide; the first impurity is phosphorus; 3. The method for manufacturing a semiconductor device according to claim 1, wherein said second impurity is aluminum.

5. A semiconductor device having a stacked superjunction structure including a lower superjunction layer and an upper superjunction layer disposed on an upper surface of the lower superjunction layer, the lower superjunction layer has lower first columns of a first conductivity type and lower second columns of a second conductivity type alternately arranged along a first direction; the upper superjunction layer has upper first columns of a first conductivity type and upper second columns of a second conductivity type alternately arranged along a second direction that is angled with the first direction, When the upper superjunction layer is viewed from above vertically, the lower superjunction layer includes a first overlapping region (OA1) overlapping with the upper first column and a second overlapping region (OA2) overlapping with the upper second column; a concentration of a first impurity of a first conductivity type doped into the upper surface of the lower superjunction layer in the second overlap region is higher than a concentration of the first impurity doped into the upper surface of the lower superjunction layer in the first overlap region; Semiconductor device.

6. In the lower first column, the second overlapping region has a higher concentration of the first impurity and the second impurity of the second conductivity type than the first overlapping region, and the amount of charge of the first conductivity type is substantially the same in the second overlapping region and the first overlapping region; 6. The semiconductor device according to claim 5, wherein in the lower second column, the concentrations of the first impurity and the second impurity are higher in the second overlap region than in the first overlap region, and the amount of charge of the second conductivity type is approximately the same in the second overlap region and the first overlap region.

7. the semiconductor material of the lower superjunction layer and the upper superjunction layer is silicon carbide; the first impurity is phosphorus; 6. The semiconductor device according to claim 5, wherein said second impurity of said second conductivity type is aluminum.

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