Storage system

Abstract

To treat a drive slot as a common slot for a drive and the other type of the device.SOLUTION: A storage system includes: a plurality of drive slots into which a drive storing data can be inserted; and one or more controllers including a processor. At least a part of the plurality of drive slots is a common slot into which a first device of a type different from the drive can be inserted, and a port of a controller to which the drive is connected from the common slot and a port of a controller to which the first device is connected from the common slot are different from each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a storage system including a plurality of drive slots. [Background technology]

[0002] A storage system has a processor, a primary storage medium (such as DRAM (Dynamic Random Access Memory)), and a secondary storage medium as its components, and data processing is performed by the processor. Traditionally, storage systems have stored data using HDDs (Hard Disk Drives) as secondary storage media. In such storage systems, the data read / write performance of the HDDs, which are secondary storage media, has been a bottleneck.

[0003] However, in recent years, storage systems that use solid-state drives (SSDs) as secondary storage media have become more common. SSDs have improved data read / write performance compared to HDDs, eliminating the performance bottleneck caused by secondary storage media mentioned above. However, while the data read / write performance of secondary storage media has improved, the performance improvement of processors that process data has slowed, and there have been an increasing number of cases where processors have become a bottleneck in the processing performance of storage systems. In what follows, the primary storage media in a storage system will be referred to as memory, and the secondary storage media will be referred to as drives.

[0004] In order to eliminate the bottleneck in data processing performance caused by this processor, storage systems have appeared that aim to offload part of the data processing to an accelerator and reduce the amount of data processing performed by the processor (for example, Patent Document 1).

[0005] In storage systems, examples of processes that are typically offloaded to accelerators include compression and encryption, and it is expected that the types and amounts of processes that can be offloaded will continue to increase in the future.

[0006] However, there may be a limit to the number of accelerators that a storage system can accommodate. For example, in a mid-range storage system with strict space and thermal design constraints, it is difficult to accommodate a sufficient number of accelerators to offload all of the processes that can be offloaded.

[0007] Furthermore, when an accelerator is installed in a storage system, a transmission path large enough to support the data processing throughput of the accelerator is required. PCI-Express (hereafter referred to as PCIe; both are registered trademarks) is known as the standard for communication networks connecting processors and accelerator cards. Accelerators installed in storage systems often require a connection with at least eight PCIe lanes.

[0008] Furthermore, a recent market trend is that SSD capacity is increasing at a faster rate than storage system capacity, which means that in the future there will likely be an increasing number of surplus internal drive slots in current storage systems.

[0009] In recent years, a new SSD form factor called EDSFF has emerged, and it is expected to become the mainstream SSD for future storage systems. One of the features of EDSFF is that it supports up to 16 PCIe lanes. This means that the new EDSFF standard will enable connections at a bandwidth that can support the accelerator's data processing throughput. This opens up the possibility of storage systems with an architecture that incorporates accelerators in drive slots.

[0010] As a conventional technique, Patent Document 2 discloses a technique for mounting an optional device other than a drive in a drive slot. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] International Publication No. 2017 / 119098 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-265010 Summary of the Invention [Problem to be solved by the invention]

[0012] When considering installing an accelerator in a drive slot, for example, the issue is that the requirements for connecting devices differ between drives and accelerators. To ensure system availability, drives are often connected to both storage controllers, but the data transfer bandwidth per transmission path only requires two lanes per controller, for a total of four lanes. In contrast, accelerators only need to be connected to one storage controller, but the transmission path must have enough bandwidth to support the amount of data processed by the accelerator, so a connection with at least eight lanes is often required. These differences in device connection requirements can also occur between accelerators and other devices and drives.

[0013] Storage systems have a wide range of requirements depending on the customer, and to accommodate these, it is desirable to be able to choose whether to install a drive or an accelerator in the slot where the device is installed. This also applies when installing a device other than an accelerator together with the drive.

[0014] Patent Document 2 discloses a technology for installing optional devices other than drives in drive slots. However, simply installing an accelerator in a drive slot using the technology disclosed in Patent Document 2 does not allow for switching the connection destination or bandwidth depending on the device installed, and does not satisfy the accelerator connection requirements. Therefore, the technology disclosed in Patent Document 2 has the problem that even if you try to select and install devices with different connection requirements in a drive slot, you can only configure it as a dedicated slot for one of the devices. [Means for solving the problem]

[0015] A storage system according to one embodiment of the present invention includes a plurality of drive slots into which drives for storing data can be inserted, and one or more controllers including a processor, wherein at least some of the plurality of drive slots are common slots into which a first device of a type different from the drive can be inserted, and the port of the controller to which the drive is connected from the common slot is different from the port of the controller to which the first device is connected from the common slot. [Effects of the Invention]

[0016] According to one aspect of the present invention, drive slots can be treated as common slots in which either drives or other types of devices can be selected and installed to meet the requirements of the storage system, thereby increasing the maximum number of devices other than drives that can be installed in the storage system and improving the performance of the storage system. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram illustrating an example of a storage system according to a first embodiment. [Figure 2] FIG. 2 is a front view showing an example of a midplane provided with a common slot according to the first embodiment. [Figure 3A]FIG. 2 is a diagram illustrating an example of the structure of a drive to be inserted into a common slot according to the first embodiment. [Figure 3B] FIG. 2 is a diagram illustrating an example of the structure of an accelerator inserted into a common slot according to the first embodiment. [Figure 4] FIG. 10 is a diagram illustrating a state in which a drive is inserted into a common slot according to the first embodiment. [Figure 5] 1 is a diagram illustrating a typical PCIe signal line used when the drive plug connector and the drive receptacle connector according to the first embodiment are connected to each other. [Figure 6] FIG. 10 is a diagram illustrating how an accelerator is inserted into a common slot according to the first embodiment. [Figure 7] 1 is a diagram illustrating typical PCIe signal lines used when the accelerator plug connector and accelerator receptacle connector according to the first embodiment are connected to each other. FIG. [Figure 8] FIG. 11 is a front view showing an example of a midplane provided with a common slot according to a second embodiment. [Figure 9] FIG. 10 is a diagram illustrating an example of an accelerator inserted into a common slot according to a second embodiment. [Figure 10] FIG. 10 is a diagram illustrating a state in which a drive is inserted into a common slot according to the second embodiment. [Figure 11] FIG. 10 is a diagram illustrating a typical signal line of PCIe used when a drive plug connector and a common receptacle connector according to a second embodiment are connected to each other. [Figure 12] FIG. 10 is a diagram illustrating how an accelerator is inserted into a common slot according to the second embodiment. [Figure 13] FIG. 10 is a diagram illustrating a typical signal line of PCIe used when an accelerator plug connector and a common receptacle connector according to a second embodiment are connected to each other. [Figure 14] FIG. 11 is a diagram illustrating an example of a midplane equipped with a common slot according to a third embodiment. [Figure 15] FIG. 11 illustrates an example of an accelerator inserted into a common slot according to a third embodiment. [Figure 16] FIG. 11 is a diagram illustrating a state in which a drive is inserted into a common slot according to a third embodiment. [Figure 17] FIG. 11 is a diagram illustrating a typical PCIe signal line used when a drive plug connector and a common receptacle connector according to a third embodiment are connected. [Figure 18] FIG. 11 is a diagram illustrating how an accelerator is inserted into a common slot according to a third embodiment. [Figure 19] FIG. 11 is a diagram illustrating a typical signal line of PCIe used when an accelerator plug connector and a common receptacle connector according to a third embodiment are connected to each other. [Figure 20] FIG. 11 is a diagram illustrating details of back-end wiring in a storage system according to a third embodiment. [Figure 21] 11 is a flowchart showing a process from when a device is inserted into a common slot until it becomes available for use according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] The following describes embodiments with reference to the drawings. Note that the embodiments are merely examples for realizing the present invention and do not limit the technical scope of the present invention. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] In the following explanation, various types of information may be described using the expression "xxx table," but the various types of information may be expressed using data structures other than tables. To indicate that it is not dependent on the data structure, the "xxx table" may be referred to as "xxx information." Also, in the following explanation, numbers are used as identification information for elements, but other types of identification information (for example, names, identifiers) may be used.

[0020] In addition, in the following description, when describing elements of the same type without distinguishing between them, common reference symbols (or reference signs) may be used, and when describing elements of the same type with distinction between them, reference symbols (or element IDs) may be used.

[0021] The program is executed by a processor (e.g., a CPU (Central Processing Unit)) included in the storage controller to perform the specified processing using storage resources (e.g., main memory) and / or a communication interface device as appropriate, so the subject of the processing may be the storage controller or the processor. The storage controller may also include hardware circuits that perform some or all of the processing. The computer program may be installed from a program source. The program source may be, for example, a program distribution server or a computer-readable storage medium.

[0022] A storage system according to an embodiment of this specification can install a device other than a drive by utilizing one or more of the slots that can accommodate a drive, without providing a dedicated slot or interface for installing the device. The drive is a secondary storage medium. In the following, an embodiment of a storage system equipped with an accelerator and a drive will be described in particular, but the storage system may also be equipped with a device other than the accelerator together with the drive. Furthermore, two or more types of devices other than the drive may also be installed together with the drive.

[0023] An accelerator is a dedicated hardware circuit that can execute some of the processes that can be executed by the processor of a storage controller. The accelerator may, for example, execute at least a part of the encoding process of data to be stored in a drive. The encoding process includes, for example, a compression process of data to be written to a drive, a decompression process of compressed data in a drive, an encryption process of data to be written to a drive, and a decryption process of encrypted data in a drive. The accelerator may execute some or all of these encoding processes. [Example]

[0024] The present embodiment will be described below with reference to the drawings.

[0025] FIG. 1 is a diagram showing an example of the configuration of a storage system in this embodiment. In the following, different elements of the same type are represented by the same prefix and different suffixes. Also, one or more elements of the same type may be represented by only a prefix. For example, storage controllers 111-1 and 111-2 represent different individual storage controllers of the same type, and storage controller 111 may represent either or both of storage controllers 111-1 and 111-2.

[0026] The hosts 102-1 and 102-2 are computer devices that send data read commands and write commands to the storage system 101 based on user operations or the operation of application software, etc. The hosts 102-1 and 102-2 may also be virtual computer devices such as virtual machines.

[0027] In FIG. 1, one host 102-1 or 102-2 is connected to one storage controller 111-1 or 111-2, but multiple hosts may be connected to one storage controller.

[0028] The storage system 101 has a dual-controller configuration equipped with two storage controllers 111-1 and 111-2, and also includes an external drive box 112, drive slots 113-1 to 113-3, and accelerator drive common slots (common slots) 114-1 and 114-2.

[0029] The storage controller 111-1 includes a front-end interface (FE IF) 121-1, a back-end interface (BE IF) 122-1, a memory 123-1, a processor (MP) 124-1, an inter-controller interface (inter-CTL IF) 125-1, and a PCIe switch (PCIe SW) 126-1.

[0030] The FE IF 121-1 connects the host 102-1 and the storage system 101. The FE IF 121-1 converts between the data transfer protocol between the host 102-1 and the storage controller 111-1 and the data transfer protocol within the storage controller 111-1.

[0031] The host 102-1 and the FE IF 121-1 are connected via a transmission line such as a Fibre Channel cable, an Ethernet cable, etc. The host 102-1 and the FE IF 121-1 may also be connected via a storage area network made up of multiple transmission lines and multiple switches.

[0032] The BE IF 122-1 connects the storage controller 111-1 and the drive box 112. The BE IF 122-1 converts between the data transfer protocol within the storage controller 111-1 and the data transfer protocol between the storage controller 111-1 and the drive box 112.

[0033] If the storage device housed in the drive box 112 is a PCIe-connected NVMe SSD, the BE IF 122-1 is a PCIe switch that does not perform protocol conversion.

[0034] The memory 123-1 is a main storage device used by the MP 124-1, and stores programs executed by the MP 124-1 (for example, storage control programs, etc.) and information such as management tables referenced by the MP 124-1.

[0035] The MP 124-1 controls data transfer between the host 102-1 connected via the FE IF 121-1 and the drive box 112 connected via the BE IF 122-1, and devices connected to the drive slots 113-1 to 113-3 and the common slots 114-1 and 114-2. Furthermore, the MP 124-1 controls data transfer between the storage controllers 111.

[0036] The inter-CTL IF 125-1 connects the MPs 124-1 and 124-2 included in the storage controllers 111-1 and 111-2.

[0037] The PCIe SW 126-1 is a component that relays a high-speed external IO bus, and connects the drives installed in the drive slots 113-1 to 113-3 or the common slots 114-1 and 114-2 to the MP 124-1.

[0038] The storage controller 111-2 includes an FE IF 121-2, a BE IF 122-2, a memory 123-2, an MP 124-2, an inter-CTL IF 125-2, and a PCIe SW 126-2. The same description as for the storage controller 111-1 above can be applied to the storage controller 111-2.

[0039] The drive slots 113-1 to 113-3 are slots into which drives built into the storage system 101 are inserted. To improve the availability of the storage system, each of the drive slots 113 to 113-3 is a dual port, connected to PCIe SW126-1 via signal line 115-1 and connected to PCIe SW126-2 via signal line 115-2.

[0040] Signal lines 115-1 and 115-2 indicate lanes that serve as PCIe data transmission paths. Each of signal lines 115-1 and 115-2 has a bandwidth of two lanes. Therefore, each drive is connected to the storage system 101 with a bandwidth of four lanes in total. As a result, even if an abnormality occurs in one of the storage controllers 111-1 and 111-2, any drive can be accessed from the other, maintaining availability.

[0041] The common slots 114-1 and 114-2 are slots that extend the functions of the drive slots 113-1 to 113-3 and can accommodate accelerators in addition to drives.

[0042] Each of the common slots 114-1 and 114-2 is wired to be connected to PCIe SW126-1 via signal line 116-1 and to PCIe SW126-2 via signal line 116-2. Furthermore, the common slot 114-1 is wired to be connected to MP124-1 of the storage controller 111-1 via signal line 117-1, and the common slot 114-2 is wired to be connected to MP124-2 of the storage controller 111-2 via signal line 117-2. The signal lines 116-1, 116-2, and 117-1 and 117-2 indicate lanes that serve as PCIe data transmission paths.

[0043] When a drive is inserted into the common slot 114-1 or 114-2, that common slot behaves in the same way as when a drive is inserted into any of the drive slots 113-1 to 113-3. In other words, when a drive is inserted into the common slot 114-1 or 114-2, the drive is dual-port connected to PCIe SW126-1 via signal line 116-1 and to PCIe SW126-2 via signal line 116-2.

[0044] The signal lines 116-1 and 116-2 each have a bandwidth of two lanes. Therefore, the drives are connected to the storage system 101 with a total bandwidth of four lanes. At this time, the signal lines 117-1 and 117-2 connected to the MPs 124-1 and 124-2 are not used. Note that the drives may include three or more drive ports, each connected to a different PCIe SW, or the number of drive ports may be one.

[0045] When an accelerator is installed in the common slot 114-1 or 114-2, it is connected to the MP 124-1 or 124-2 of one of the storage controllers 111-1 or 111-2 via the corresponding signal line 117-1 or 117-2. The signal lines 117-1 and 117-2 have an eight-lane bandwidth to support the processing speed of the accelerator. At this time, the signal lines 116-1 and 116-2 connected to the PCIe SW 126-1 and 126-2 are not used.

[0046] This allows the storage system 101 to select whether to install a drive or an accelerator in each of the common slots 114-1 and 114-2. When drives are installed in the common slots 114-1 and / or 114-2, the capacity of the storage system is expanded, and when accelerators are installed in the common slots 114-1 and / or 114-2, the processing performance of the storage system 101 is improved.

[0047] FIG. 2 is a front view of a midplane 201 in which the drive slots 113 and the common slots 114 are provided in the storage system 101 of FIG.

[0048] The midplane 201 includes at least one drive slot 113 and two common slots 114. In this embodiment, the case where there are two common slots 114 is described, but the present embodiment is not limited to this example. For example, the midplane 201 may be configured to be equipped with four common slots 114.

[0049] The drive slot 113 includes a drive receptacle connector 211-1 as a connector for connecting a drive. When a drive is installed in the drive slot 113, the drive receptacle connector 211-1 connects the drive to the drive slot 113. The drive receptacle connector 211-1 is connected to the PCIe SW 126 via a signal line 115.

[0050] The common slot 114 includes a drive receptacle connector 211-2 having the same configuration and function as the drive receptacle connector 211-1 included in the drive slot 113, and an accelerator receptacle connector 212 for mounting an accelerator.

[0051] In one embodiment of this specification, the wiring and position of drive receptacle connector 211 conform to standards, allowing the use of generic drives. Accelerator receptacle connector 212 is positioned in common slot 114 so as not to interfere with drive receptacle connector 211-2.

[0052] The drive receptacle connector 211-2 is connected to the PCIe SW 126 via a signal line 116. The accelerator receptacle connector 212 is connected to the MP 124 via a signal line 117.

[0053] 3A and 3B show examples of various devices connected to each slot of the midplane 201 shown in Fig. 2. Specifically, Fig. 3A shows an example of the structure of a drive 301, and Fig. 3B shows an example of the structure of an accelerator 303.

[0054] 3A, drive 301 represents a secondary storage medium such as an SSD (Solid State Drive). Drive 301 includes a drive plug connector 302 for insertion into drive slot 113 or common slot 114 and connection to a receptacle connector. Drive plug connector 302 is a four-lane connector size.

[0055] As shown in FIG. 3B, the accelerator 303 represents a data processing circuit configured, for example, by an FPGA (Field-Programmable Gate Array). The accelerator 303 is equipped with circuits for performing dedicated processing such as compression and encryption, and can improve the processing performance of the storage system 101 by offloading part of the processing performed by the MP 124. The accelerator 303 includes an accelerator plug connector 304 for connecting to the common slot 114. The accelerator plug connector 304 is an 8-lane connector size.

[0056] The accelerator 303 uses a uniquely designed board to connect to the accelerator receptacle connector 212, which is located in a special position that does not conform to the standard, and the accelerator plug connector 304 is located in a position that differs from the standard.

[0057] 4 shows how the drive 301 is inserted into the common slot 114 shown in FIG. 2. When the drive 301 is inserted into the common slot 114, of the two receptacle connectors of the common slot 114, the drive receptacle connector 211-2 and the drive plug connector 302 are connected. At this time, the accelerator receptacle connector 212 is not used. By connecting the drive plug connector 302 and the drive receptacle connector 211-2, the drive 301 is connected to the PCIe SW 126-1 via the signal line 116-1 and to the PCIe SW 126-2 via the signal line 116-2.

[0058] 5 shows typical PCIe signal lines used when the drive plug connector 302 and the drive receptacle connector 211-2 are connected. Signal lines 501 and 504 represent the reference clock signal (differential) of the PCIe link, called REFCLK. Signal line 501 represents REFCLK0#, and signal line 504 represents REFCLK1#. Signal lines 502 and 505 represent reset signals, called PERST, which indicate that the power supply and reference clock are stable. Signal line 502 represents PERST0#, and signal line 505 represents PERST1#.

[0059] Signal line 503 is a signal called PRSNT that is used to detect PCIe devices. Devices that support a 4-lane connector must implement PRSNT0#. Devices that support an 8-lane connector must implement PRSNT0# and PRSNT1#. Devices that support a 16-lane connector must implement PRSNT0#, PRSNT1#, and PRSNT2#. Since drive plug connector 302 is a 4-lane connector size, PRSNT0# is implemented on signal line 503.

[0060] Signal set 511 is a set that combines signal lines 501, 502, and 503. Signal set 511 is used in correspondence with signal line 116-1. Similarly, signal line set 512 is a set that combines signal lines 504, 505, and 503. Signal line set 512 is used in correspondence with signal line 116-2.

[0061] 6 shows how the accelerator 303 is inserted into the common slot 114 provided in the midplane 201 shown in FIG. 2. When the accelerator 303 is inserted into the common slot 114, of the two receptacle connectors that the common slot 114 has, the accelerator receptacle connector 212 and the accelerator plug connector 304 are connected. At this time, the drive receptacle connector 211 is not used. The accelerator 303 is connected to the MP 124 of one of the storage controllers 111 via the signal line 117 by connecting the accelerator plug connector 304 and the accelerator receptacle connector 212.

[0062] 7 shows typical PCIe signal lines used when the accelerator plug connector 304 and the accelerator receptacle connector 212 are connected. Signal line 701 indicates REFCLK0#. Signal line 702 indicates PERST0#. Signal line 703 indicates PRSNT0#. Signal line 704 indicates PRSNT1#.

[0063] Since the accelerator plug connector 304 is an 8-lane connector size, PRSNT0# is implemented on signal line 703, and PRSNT1# is implemented on signal line 704. Signal line set 711 is a set that combines signal line 701, signal line 702, signal line 703, and signal line 704. Signal line set 711 is used in correspondence with signal line 117.

[0064] As explained above, the maximum number of accelerators that can be installed in the storage system 101 of the first embodiment is increased, thereby improving the processing performance of the storage system 101.

[0065] There is no limit to the number of common slots that can be implemented, and it may be any value equal to or greater than 1. Also, all of the drive slots 113 may be common slots 114. By modifying some parts as necessary, the explanation of the first embodiment can be applied to a storage system that incorporates devices other than accelerators together with drives. This point is the same in the other embodiments. [Example]

[0066] In this embodiment, as a modification of the first embodiment, an example will be described in which the receptacle connectors of the common slot 114 are unified into one. The configuration of the storage system in this embodiment is the same as that of the first embodiment shown in FIG. 1, and therefore a description thereof will be omitted.

[0067] 8 is a front view of the midplane 201 in this embodiment included in the storage system 101. The common slot 114 has a common receptacle connector 801 in this embodiment.

[0068] The common receptacle connector 801 is a dual-purpose connector that can connect to both drives and accelerators. The common receptacle connector 801 is a 16-lane connector, of which signal pins of lanes 0 to 3 are assigned to signal lines 116-1 and 116-2 as drive-only lanes. In addition, in the common receptacle connector 801, signal pins of lanes 8 to 15 are assigned to signal line 117 as accelerator-only lanes.

[0069] 9 is a diagram showing the configuration of an accelerator 901 in this embodiment. The accelerator 901 has the same functions as the accelerator 303 shown in FIG. 3B, but differs from the accelerator 303 in that the accelerator plug connector 902 has a connector size of 16 lanes.

[0070] 10 shows how the drive 301 is inserted into the common slot 114 shown in FIG. 8. Because the drive 301 is a general-purpose product, the drive plug connector 302 is wired according to the standard. The drive plug connector 302, retaining its 4-lane connector size, is inserted into the common receptacle connector 801, which has a 16-lane size. The drive plug connector 302 connects to the signal pins of lanes 0 to 3 of the common receptacle connector 801, and is connected to PCIe SW126-1 via signal line 116-1 and to PCIe SW126-2 via signal line 116-2.

[0071] 11 shows typical PCIe signal lines used when the drive plug connector 302 and the common receptacle connector 801 are connected. Signal line 1101 indicates REFCLK0#. Signal line 1102 indicates PERST0#. Signal line 1103 indicates PRSNT0#. Signal line 1104 indicates REFCLK1#. Signal line 1105 indicates PERST1#.

[0072] The signal line set 1111 is a set that includes the signal lines 1101, 1102, and 1103. The signal line set 1111 is used in correspondence with the signal line 116-1. The signal line set 1112 is a set that includes the signal lines 1103, 1104, and 1105. The signal line set 1112 is used in correspondence with the signal line 116-2.

[0073] Fig. 12 shows how an accelerator 901 is inserted into the common slot 114 shown in Fig. 8. In this embodiment, a 16-lane size accelerator plug connector 902 is connected to a 16-lane size common receptacle connector 801.

[0074] 13 shows typical PCIe signal lines used when the accelerator plug connector 902 is connected to the common receptacle connector 801. Signal lines 1101, 1102, and 1103 are signal lines that are commonly used regardless of whether a drive or an accelerator is connected to the common receptacle connector 801.

[0075] Signal line 1301 indicates PRSNT1#. Signal line 1302 indicates PRSNT2#. Since the accelerator plug connector 902 is a 16-lane connector size, PRSNT0# is implemented on signal line 1103, PRSNT1# is implemented on signal line 1301, and PRSNT2# is implemented on signal line 1302. Signal line set 1311 is a set that brings together signal line 1101, signal line 1102, signal line 1103, signal line 1301, and signal line 1302. Signal line set 1311 is used in correspondence with signal line 117.

[0076] The accelerator 901 is a device card of a unique design that does not conform to standards, and has unique wiring applied to the accelerator plug connector 902. The accelerator plug connector 902 is wired only to the signal pins of lanes 8 to 15, and is essentially connected to the common receptacle connector 801 as an 8-lane plug connector. The accelerator plug connector 902 connects to the signal pins of lanes 8 to 15 of the common receptacle connector 801, and is connected to the MP 124 of one of the storage controllers 111 via a signal line 117. The mounting position of the connector 902 conforms to standards.

[0077] When connecting the accelerator 901 to the common receptacle connector 801, if it is desired to control PCIe sideband signals different from those of the drive, the unused signal pins of lanes 4 to 8 in the common receptacle connector 801 and the accelerator plug connector 902 may be assigned to wiring for sideband signals for the accelerator 901.

[0078] In this embodiment, the PCIe lane wiring (signal pins) used between the drive and the accelerator are separated, so that the connection destination automatically switches depending on the device installed. In another example, when the PRSNT signal is used to detect the insertion of a device into the common slot 114, the PRSNT signal is used as follows, for example. In a drive 301 that uses a 4-lane plug connector, PRSNT0# is connected to ground.

[0079] In the accelerator 303 that uses a 16-lane plug connector, PRSNT0# is not connected to ground, but PRSNT1# and PRNST2# are connected to ground. This makes it possible to detect that a drive 301 has been inserted when PRSNT0# is at a low level, and that an accelerator 303 has been inserted when PRSNT1# and PRSNT2# are at a low level when a device is inserted into the common slot 114.

[0080] According to the second embodiment, the receptacle connectors provided in the common slot 114 are unified into a 16-lane size connector, and the drives and accelerators can be connected to the common receptacle connector. The connectors of the first embodiment and the second embodiment may be implemented in one storage system. [Example]

[0081] In this embodiment, an example is shown in which the common slot 114 includes only one receptacle connector, and the connector size is implemented as 8 lanes. In the implementation of this embodiment, a selector is used for the back-end wiring, so that part of the back-end wiring is shared when connecting a drive and when connecting an accelerator.

[0082] The basic configuration of the storage system in this embodiment is the same as in embodiment 1, and therefore a description thereof will be omitted. However, in this embodiment, the back end of the storage system 101 will be described later with reference to FIG.

[0083] 14 is a front view of the midplane 201 in this embodiment that is included in the storage system 101. In this embodiment, the common slot 114 includes a common receptacle connector 1401. The common receptacle connector 1401 is an 8-lane receptacle connector that can be connected to either a drive or an accelerator.

[0084] FIG. 15 is a diagram showing the configuration of an accelerator 1501 in this embodiment. The accelerator 1501 has an accelerator plug connector 1502. The accelerator plug connector 1502 is an 8-lane plug connector. However, unlike the first embodiment, the accelerator plug connector 1502 is positioned in accordance with the EDSFF device standard. This is because in this embodiment, the drive and accelerator are connected to the same receptacle connector, and therefore there is no need to separately shift the position of the receptacle connector for connecting the accelerator as in the first embodiment.

[0085] Fig. 16 shows how the drive 301 is inserted into the common slot 114 shown in Fig. 14. The drive plug connector 302, while still in the 4-lane plug connector size, is inserted into the 8-lane common receptacle connector 1401.

[0086] 17 shows typical PCIe signal lines used when the drive plug connector 302 and the common receptacle connector 1401 are connected. Signal line 1701 indicates REFCLK0#. Signal line 1702 indicates PERST0#. Signal line 1703 indicates PRSNT0#. Signal line 1704 indicates REFCLK1#. Signal line 1705 indicates PERST1#.

[0087] Signal line set 1711 is a set that combines signal line 1701, signal line 1702, and signal line 1703. Signal line set 1711 is used in correspondence with signal line 116-1. Signal line set 1712 is a set that combines signal line 1703, signal line 1704, and signal line 1705. Signal line set 1712 is used in correspondence with signal line 116-2.

[0088] Figure 18 shows how an accelerator 1501 is inserted into the common slot 114 shown in Figure 14. In this embodiment, an 8-lane size accelerator plug connector 1502 is connected to an 8-lane size common receptacle connector 1401.

[0089] 19 shows typical PCIe signal lines used when the accelerator plug connector 1502 is connected to the common receptacle connector 1401. Signal lines 1701, 1702, and 1703 are signal lines that are commonly used regardless of whether a drive or an accelerator is connected to the common receptacle connector 1401. Signal line 1901 indicates PRSNT1#.

[0090] Since the accelerator plug connector 1502 is an 8-lane connector size, PRSNT0# is implemented on signal line 1703, and PRSNT1# is implemented on signal line 1901. Signal line set 1911 is a set that combines signal line 1701, signal line 1702, signal line 1703, and signal line 1901. Signal line set 1911 is used in correspondence with signal line 117.

[0091] Fig. 20 is a block diagram showing in detail the wiring connecting common receptacle connector 1401 to MP 124 and PCIe SW 126. The following description will be given assuming that a device is connected to common receptacle connector 1401-1. In the configuration example shown in Fig. 20, two common receptacle connectors 1401-1 and 1401-2 are implemented. Each common receptacle connector 1401 is wired with signal line 2011, signal line 2012, signal line 2013, signal line 1703, and signal line 1901.

[0092] When the accelerator 1501 is connected to the common receptacle connector 1401, the signal line 2011 is a transmission path for four lanes out of eight lanes that connect the accelerator 1501 to the MP 124. When the drive 301 is connected to the common receptacle connector 1401, the signal line 2011 is not used.

[0093] The signal lines 2012 and 2013 are signal lines that are used regardless of whether the drive 301 or the accelerator 1501 is connected to the common receptacle connector 1401. The signal lines 2012 and 2013 are each a two-lane transmission line.

[0094] When the drive 301 is mounted on the common receptacle connector 1401-1, the signal line 2012 is connected to the signal line 2016-1 by the selector 2001-1 and is connected to the PCIe SW 126-1. At this time, the signal line 2013 is connected to the signal line 2017-2 by the selector 2002-2 and is connected to the PCIe SW 126-2.

[0095] When accelerator 1501 is connected to common receptacle connector 1401-1, signal line 2012 is connected to signal line 2015-1 by selector 2001-1 and merges with junction 2004-1. At this time, signal line 2013 is connected to signal line 2018-2 by selector 2002-2 and merges with junction 2004-1. As a result, accelerator 1501 is connected to MP 124 with 8 lanes by signal line 2019.

[0096] The storage controller 111 includes, in addition to the MP 124 and PCIe SW 126, a selector 2001, a selector 2002, and a control microcomputer (MC) 2003. In the configuration example shown in Fig. 2, two MCs 2003-1 and 2003-2 are implemented.

[0097] When a device is connected to the common receptacle connector 1401, the MC2003 has a function of identifying the connected device from PRSNT0# transmitted via signal line 1703 and PRSNT1# transmitted via signal line 1901. The function of the MC2003 may be realized by incorporating the function into the PCIe SW126.

[0098] MCs 2003-1 and 2003-2 communicate with each other via signal line 2014 what the identified connected devices are for common receptacle connectors 1401-1 and 1401-2 to which they are connected.

[0099] MC2003-1 communicates the identification result of the device connected to common receptacle connector 1401-1 to selector 2001-1. Furthermore, MC2003-1 communicates the identification result of the device of common receptacle connector 1401-2 transmitted from MC2003-2 to selector 2002-1. MC2003-2 also operates in the same manner as MC2003-1, and communicates the identification result of the device connected to common receptacle connector 1401-2 to selector 2001-2. Furthermore, MC2003-2 communicates the identification result of the device of common receptacle connector 1401-1 transmitted from MC2003-1 to selector 2002-2.

[0100] Selector 2001 and selector 2002 have the function of recognizing the device inserted into common receptacle connector 1401 based on information transmitted from MC 2003, and switching the signal line to be used based on that information. The functions of selector 2001 and selector 2002 are realized by, for example, an analog switch having a demultiplexer function.

[0101] The selector 2001 has a function of switching the connection destination of the signal line 2012 extending from the common receptacle connector 1401 to either the signal line 2015 or the signal line 2016. For example, when the drive 301 is connected to the common receptacle connector 1401-1, the selector 2001-1 switches the wiring to the signal line 2016-1 and connects it to the PCIe SW 126-1. When the accelerator 1501 is connected to the common receptacle connector 1401-1, the selector 2001-1 switches the wiring to the signal line 2015-1 and connects it to the MP 124-1 via the junction 2004-1.

[0102] Similarly, when the drive 301 is connected to the common receptacle connector 1401-2, the selector 2001-2 switches the wiring to the signal line 2016-2 and connects it to the PCIe SW 126-2. When the accelerator 1501 is connected to the common receptacle connector 1401-2, the selector 2001-2 switches the wiring to the signal line 2015-2 and connects it to the MP 124-2 via the junction 2004-2.

[0103] The selector 2002 has a function of switching the connection destination of the signal line 2013 extending from the common receptacle connector between the signal line 2017 and the signal line 2018. For example, when the drive 301 is connected to the common receptacle connector 1401-1, the selector 2002-2 switches the wiring to the signal line 2017-2, which connects to the PCIe SW 126-2. When the accelerator 1501 is connected to the common receptacle connector 1401-1, the selector 2002-2 switches the wiring to the signal line 2018-2, which connects to the MP 124-1 via the junction 2004-1.

[0104] Similarly, when the drive 301 is connected to the common receptacle connector 1401-2, the selector 2002-1 switches the wiring to the signal line 2017-1 and connects it to the PCIe SW 126-1. When the accelerator 1501 is connected to the common receptacle connector 1401-2, the selector 2002-1 switches the wiring to the signal line 2018-1 and connects it to the MP 124-2 via the junction 2004-2.

[0105] Junction 2004 is a convenient point where three signal lines join together: signal line 2011 extending from common receptacle connector 1401, signal line 2015 extending from selector 2001, and signal line 2018 extending from selector 2002, and does not include any elements. By joining the signal lines at junction 2004, signal line 2019 between MP 124 and junction 2004 becomes eight lanes.

[0106] 20, the two-lane transmission path from signal line 2012 to signal line 2016 corresponds to signal line 116-1 in Fig. 1. When a drive 301 is installed in the common slot 114, these signal lines function as a data transmission path connecting the drive 301 and PCIe SW 126-1.

[0107] Similarly, in Fig. 20, a two-lane transmission path extending from signal line 2013 to signal line 2017 corresponds to signal line 116-2 in Fig. 1. These signal lines function as a data transmission path connecting drive 301 and PCIe SW 126-2 when drive 301 is installed in common slot 114.

[0108] 20, the eight-lane data transmission path consisting of the four-lane transmission path of signal line 2011, the two-lane transmission path from signal line 2012 to signal line 2015, the two-lane transmission path from signal line 2013 to signal line 2018, and signal line 2019 where these signal lines join together corresponds to signal line 117 in Fig. 1. When accelerator 1501 is connected to common receptacle connector 1401, these signal lines function as a data transmission path connecting accelerator 1501 and MP 124.

[0109] The MC2003 also has a function for performing heartbeats between the MC2003 of each storage controller 111. For example, if an abnormality occurs in the storage controller 111-2 and the partner MC2003-2 stops responding, the MC2003-1 will not know the connected device of the common receptacle connector 1401-2, for which the MC2003-2 is responsible for device identification, but in that case the selector 2002-1 will switch the wiring instruction to the drive connection side. As a result, if a drive 301 is connected to the common receptacle connector 1401-2, even if an abnormality occurs in the storage controller 111-2, the availability of access from the storage controller 111-1 to the drive 301 is maintained.

[0110] 21 is a flowchart showing an example of a process from when a device is inserted into the common slot 114 until the device starts to be used. Here, the description will be made assuming that, as an initial state, no device is inserted into the common slot 114, and the port of the PCIe SW 126 to which the drive 301 is connected and the root port of the MP 124 to which the accelerator 1501 is connected are both in a link-down state.

[0111] First, a maintenance person or the like inserts the drive 301 or accelerator 1501 into the shared slot 114 (step S2101).

[0112] The MC2003 detects the insertion of a device into the common slot 114 and identifies the device type by reading the PRSNT signal (step S2102). For example, if PRSNT#0 is low and PRSNT#1 is open, the MC2003 recognizes that a drive 301 has been inserted because the device is a four-lane connection. If both PRSNT#0 and PRSNT#1 are low, the MC2003 recognizes that an accelerator 1501 has been inserted because the device is an eight-lane connection.

[0113] The MC 2003 shares the information on the device type identified in step S2102 with the other MC 2003 (step S2103). For example, when a device is inserted into the common slot 114-1, the MC 2003-1 identifies the device type and shares this information with the MC 2003-2.

[0114] The MC 2003 issues a wiring switching instruction to the selector 2001 and the selector 2002 based on the information on the device type identified in step S2002 (step S2104).

[0115] For example, when a drive 301 is inserted into the shared slot 114-1, the MC 2003-1 identifies the device type as a drive, shares this information with the MC 2003-2, and instructs the selector 2001-1 to switch to the signal line 2016-1. The MC 2003-2 instructs the selector 2002-2 to switch to the signal line 2017-2 based on the device type information shared by the MC 2003-1.

[0116] When accelerator 1501 is inserted into common slot 114-1, MC 2003-1 identifies the device type as an accelerator, shares this information with MC 2003-2, and further instructs selector 2001-1 to switch to signal line 2015. MC 2003-2 instructs selector 2002-2 to switch to signal line 2018-2 based on the device type information shared by MC 2003-1.

[0117] When the MC 2003 confirms that the wiring of the selector 2001 and the selector 2002 has been switched, it notifies the MP 124 of this fact together with the device information (step S2105). An example of the notification method is as follows: The MC 2003 writes information that the wiring preparation of the selector 2001 and the selector 2002 has been completed and the device identification information to a predetermined address in the memory 123, and sends an interrupt to the MP 124.

[0118] Upon receiving the notification from the MC 2003, the MP 124 links up the specified port based on the installed device identification information and wiring switching information (step S2106).

[0119] An example of link-up processing by the MP 124 is as follows. If the notified device information is the drive 301, the MP 124 writes a link-up instruction to a predetermined register of the PCIe SW 126, and the PCIe SW 126 receives the instruction and performs link-up processing for the specified port. If the notified device information is the accelerator 1501, the MP 124 performs link-up processing for the port corresponding to the signal line 2019.

[0120] After the specified port is linked up, the MP 124 performs initial settings for the device (step S2107).

[0121] According to the third embodiment, the common slot 114 has one common receptacle connector of 8-lane size, and thus can accommodate both a drive and an accelerator.

[0122] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0123] Furthermore, the above-mentioned components, functions, processing units, etc. may be realized in part or in whole by hardware, for example, by designing them as integrated circuits. Furthermore, the above-mentioned components, functions, etc. may be realized in software by a processor interpreting and executing a program that realizes each function. Information such as the programs, tables, and files that realize each function can be stored in memory, a storage device such as a hard disk or SSD, or a storage medium such as an IC card or SD card.

[0124] In addition, the control lines and information lines shown are those that are considered necessary for the explanation, and do not necessarily show all the control lines and information lines in the product. In reality, it can be assumed that almost all components are interconnected. [Explanation of symbols]

[0125] 101 Storage System 111 Storage Controller 114 Common Slot 115, 116, 117, 501, 502, 503, 504, 505, 701, 702, 703, 704, 1101, 1102, 1103, 1104, 1105, 1301, 1302, 1701, 1702, 1703, 1704, 1705, 1901, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019 signal lines 123 memory 124 MP 126 PCIe SW 211 Drive Receptacle Connector 212 Accelerator Receptacle Connector 301 Drive 302 Drive Plug Connector 303, 901, 1501 Accelerators 304, 902, 1502 Accelerator Plug Connectors 511, 512, 711, 1111, 1112, 1311, 1711, 1712, 1911 signal line set 801, 1401 common receptacle connector 2001, 2002 Selector 2003 MC 2004 Confluence

Claims

1. 1. A storage system, comprising: a plurality of drive slots into which drives for storing data can be inserted; one or more controllers including a processor; At least some of the drive slots are common slots into which a first device of a type different from the drive can be inserted, A storage system in which the port of the controller to which the drive is connected from the common slot is different from the port of the controller to which the first device is connected from the common slot.

2. 2. The storage system according to claim 1, the first device is an accelerator that performs compression processing, decompression processing, encryption processing, and / or decryption processing; Storage system.

3. 2. The storage system according to claim 1, Contains multiple controllers, the drive includes two drive ports; When the drive is inserted into the common slot, the two drive ports are connected to different controllers; When the first device is inserted into the common slot, the first device is connected to one of the plurality of controllers. Storage system.

4. 2. The storage system according to claim 1, Each wiring between the common slot and the port of the controller is composed of a plurality of lanes; the number of lanes of wiring to be connected when the first device is inserted into the common slot is greater than the number of lanes of wiring to be connected when the drive is inserted into the common slot; Storage system.

5. 2. The storage system according to claim 1, the common slot includes a drive connection receptacle connector and a first device connection receptacle connector; When the drive is inserted into the common slot, a plug connector of the drive is connected to the drive connection receptacle connector; When the first device is inserted into the common slot, a plug connector of the first device is connected to the first device receptacle connector. Storage system.

6. 2. The storage system according to claim 1, the common slot includes a common receptacle connector for the drive connection and the first device connection; When the drive is inserted into the common slot, a plug connector of the drive is connected to a first data transfer signal pin of the common receptacle connector; When the first device is inserted into the common slot, a plug connector of the first device is connected to a second data transfer signal pin of the common receptacle connector that is different from the first data transfer signal pin. Storage system.

7. 2. The storage system according to claim 1, The storage system includes: a first controller and a second controller; a first common slot and a second common slot; the first common slot includes a first common receptacle connector, and the second common slot includes a second common receptacle connector; The first controller a first processor; A first switch; a first selector and a second selector; a first port and a second port; The second controller a second processor; and A second switch; a third selector and a fourth selector; a third port and a fourth port; the first port is connected to the first common receptacle connector, the first selector, and the third selector; the second port is connected to the first selector and the second selector via the first switch; the first selector is connected to the first common receptacle connector; the second selector is connected to the second common receptacle connector; the third port is connected to the second common receptacle connector, the second selector, and the fourth selector; the fourth port is connected to the third selector and the fourth selector via the second switch; the third selector is connected to the first common receptacle connector; the fourth selector connects to the second common receptacle connector; Storage system.

8. 8. The storage system according to claim 7, The process to be executed when a device is inserted into the first or second common slot is: Detecting a device inserted into the first or second common slot; Identifying a device type of the detected device; controlling connection destinations of the first, second, third, and fourth selectors based on the identified device type; Linking up the port to which the detected device is connected; Including, Storage system.

9. 8. The storage system according to claim 7, the first controller includes a first microcontroller; the first microcontroller is connected to the first and second selectors and the first common receptacle connector; the second controller includes a second microcontroller; the second microcontroller connects the third and fourth selectors and the second common receptacle connector; The first and second microcontrollers are interconnected, Detecting a device connected to the first or second common receptacle connector; Identifying a device type of the detected device based on information on the number of connection lanes of the detected device; Sharing information about the identified device type; controlling connection destinations of the first, second, third, and fourth selectors based on the device type information; Storage system.

10. 10. The storage system according to claim 9, When the drive is connected to the first common receptacle connector, The first microcontroller issuing a wiring instruction to the first selector so that the first common receptacle connector and the first switch are connected; The second microcontroller issuing a wiring instruction to the third selector so that the first common receptacle connector and the second switch are connected; When the first device is connected to the first common receptacle connector, The first microcontroller issuing a wiring instruction to the first and second selectors so that the first common receptacle connector and the first processor are connected; Storage system.

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