Circuit board and circuit module

Abstract

To suppress the destabilization of high-speed switching operation and local heat generation due to addition of functions of a Kelvin source terminal.SOLUTION: A circuit board 110 includes a wiring pattern 130 including a transistor mount pattern 140. The transistor mount pattern 140 includes a gate pad 141, a source pad 142, a drain pad 143 separated from the source pad 142 in a first direction Y, and a heat release pad 144 existing between the source pad 142 and the drain pad 143. The wiring pattern 130 includes a gate extension pattern 160 connected to the gate pad 141 and extending in a second direction X that intersects with the first direction Y, and a Kelvin source extension pattern 170 extending from the heat release pad 144 in the second direction X. The Kelvin source extension pattern 170 extends in the second direction X from a side edge 144E1 of the heat release pad 144 that intersects with the second direction X, the side edge 144E1 existing near the gate pad 141.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a circuit board and a circuit module. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices using HEMTs are recognized as devices that have lower on-resistance and are capable of high-speed, high-frequency operation compared to typical silicon (Si) power devices.

[0003] In a HEMT, a Kelvin source terminal (also called a driver source terminal) is used in addition to the source terminal to eliminate the influence of electromotive noise caused by parasitic inductance coupled to the source terminal. For example, Patent Document 1 discloses a semiconductor device equipped with a driver source lead. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-202310

[0005] [overview] For example, a Kelvin source terminal can be provided by allocating a portion of an existing source terminal (e.g., one of multiple source terminals) as the Kelvin source terminal. However, in this case, the number and arrangement of available source terminals are substantially limited due to the arrangement of the Kelvin source terminal, and therefore, variations in the wiring length (e.g., wire length) from the transistor chip to each source terminal may occur depending on, for example, the location of the source terminal. Such variations in wiring length cause deviations in parasitic inductance within the transistor chip, which can lead to instability in high-speed switching operation and localized heat generation.

[0006] A circuit board according to one embodiment of the present disclosure includes a wiring pattern including a transistor mounting pattern used to mount a surface-mount transistor. The surface-mount transistor includes a gate terminal, a source terminal, a drain terminal, and a heat dissipation terminal electrically connected to the source terminal. The transistor mounting pattern includes a gate pad used for electrical connection with the gate terminal, a source pad used for electrical connection with the source terminal, a drain pad used for electrical connection with the drain terminal and spaced apart from the source pad and the gate pad in a first direction, and heat dissipation pads used for electrical connection with the heat dissipation terminal and positioned between the source pad and the drain pad and between the gate pad and the drain pad in the first direction. The wiring pattern includes a gate extension pattern connected to the gate pad and extending in a second direction intersecting the first direction in a plan view, and a Kelvin source extension pattern extending from the heat dissipation pad in the second direction. The gate pad and the source pad are arranged side by side in the second direction. The heat dissipation pad includes a side edge that intersects with the second direction and is located closer to the gate pad than the source pad, and the Kelvin source extension pattern extends in the second direction from the side edge. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 is a schematic plan view of an exemplary circuit module according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view of an exemplary wiring pattern according to the first embodiment. [Figure 3] FIG. 3 is a schematic plan view of the surface-mounted transistor shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of an exemplary transistor structure for a surface mounted transistor. [Figure 5] FIG. 5 is a diagram showing a charge / discharge path between the gate and the Kelvin source in the circuit module of FIG. [Figure 6] FIG. 6 is a schematic circuit diagram of the circuit module of FIG. [Figure 7] FIG. 7 is a schematic plan view of an exemplary circuit module according to the second embodiment. [Figure 8] FIG. 8 is a schematic plan view of another exemplary wiring pattern. [Figure 9] FIG. 9 is a schematic plan view of yet another exemplary wiring pattern.

[0008] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] Terms such as "first," "second," and "third" used in this disclosure are used merely to distinguish between objects and do not rank the objects. Additionally, the expression "at least one" used in this disclosure means one or more of a desired number of options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] [First embodiment] A circuit module 100 according to a first embodiment will be described with reference to FIGS. 1 to 6. Note that in this disclosure, components may be described based on mutually orthogonal X, Y, and Z axes shown in the figures. The term "plan view" used in this disclosure refers to viewing the circuit module 100 in the Z-axis direction, unless explicitly stated otherwise. In the following description, for convenience, the +Z direction may be referred to as up, the -Z direction as down, the +X direction as right, and the -X direction as left in the circuit module 100 shown in FIG. 1. However, the up, down, left, and right directions of the circuit module 100 are not limited to these orientations.

[0012] [1-1. Schematic structure of the circuit module] 1 is a schematic plan view of a circuit module 100 according to a first embodiment. The circuit module 100 includes a circuit board 110 and a transistor 10 mounted on the circuit board 110. The transistor 10 is a surface-mount transistor, and may be, for example, but is not limited to, a nitride semiconductor device. An example of the transistor 10 is a HEMT using a nitride semiconductor.

[0013] The circuit module 100 further includes a gate driver 120 mounted on the circuit board 110 and driving the transistor 10. Note that in FIG. 1, for clarity, the circuit board 110 and the gate driver 120 are indicated by two-dot chain lines. The circuit module 100 may further include other circuits in addition to the transistor 10 and the gate driver 120.

[0014] The circuit board 110 includes a wiring pattern 130. The transistor 10 and the gate driver 120 are mounted on the wiring pattern 130. Therefore, the wiring pattern 130 electrically connects the transistor 10 and the gate driver 120.

[0015] [1-2. Wiring pattern] FIG. 2 is a diagram showing the wiring pattern 130 of the circuit board 110. As shown in FIG. The wiring pattern 130 includes a transistor mounting pattern 140 in the mounting area of ​​the transistor 10 (the area surrounded by a two-dot chain line in FIG. 1). The transistor mounting pattern 140 includes a gate pad 141, one or more (e.g., three in FIG. 1) source pads 142, one or more (e.g., four in FIG. 1) drain pads 143, and a heat dissipation pad 144. The gate pad 141, the source pad 142, the drain pad 143, and the heat dissipation pad 144 are areas that are soldered to the corresponding terminals of the transistor 10. The terminals of the transistor 10 will be described later with reference to FIG. 3.

[0016] The source pad 142, the heat dissipation pad 144, and the drain pad 143 are spaced apart and arranged side by side in one direction (the Y-axis direction in FIG. 1). For ease of explanation, hereinafter, the direction in which the source pad 142, the heat dissipation pad 144, and the drain pad 143 are arranged side by side in a plan view (the Y-axis direction in FIG. 1) will be referred to as a first direction Y, and the direction intersecting the first direction Y in a plan view (the X-axis direction orthogonal to the Y-axis direction in FIG. 1) will be referred to as a second direction X.

[0017] The heat dissipation pad 144 is located in the first direction Y between the source pad 142 and the drain pad 143 and between the gate pad 141 and the drain pad 143. In other words, the drain pad 143 is located apart from the source pad 142 and the gate pad 141 in the first direction Y with the heat dissipation pad 144 sandwiched therebetween.

[0018] The gate pad 141 is arranged next to the source pad 142 in the second direction X. Furthermore, the multiple (three in the example of FIG. 2) source pads 142 are also arranged next to each other in the second direction X. Therefore, the gate pad 141 and the three source pads 142 are aligned in a line in the second direction X. Similarly, the multiple (four in the example of FIG. 2) drain pads 143 are also aligned in a line in the second direction X.

[0019] The wiring pattern 130 includes a source connecting pattern 151 that connects the plurality of source pads 142 to each other. The same potential (e.g., ground voltage) is applied to the plurality of source pads 142 via the source connecting pattern 151. The wiring pattern 130 further includes a drain connecting pattern 152 that connects the plurality of drain pads 143 to each other. The same potential (e.g., power supply voltage) is applied to the plurality of drain pads 143 via the drain connecting pattern 152.

[0020] The gate pad 141, the source pad 142, the drain pad 143, and the heat dissipation pad 144 each have a rectangular shape in a plan view. Although not particularly limited, in the example of Fig. 2, the gate pad 141, the source pad 142, and the drain pad 143 each have a square shape, and the heat dissipation pad 144 has an elongated rectangular shape with the longitudinal direction aligned with the second direction X.

[0021] The thermal pad 144 includes four side edges, namely, a first side edge 144E1, a second side edge 144E2, a third side edge 144E3, and a fourth side edge 144E4, that define the outer shape of the thermal pad 144. The first and second side edges 144E1 and 144E2 are a pair of short sides extending parallel to each other along the first direction Y, and the third and fourth side edges 144E3 and 144E4 are a pair of long sides extending parallel to each other along the second direction X.

[0022] The gate pad 141 and the source pad 142 are disposed opposite the third side edge 144E3 of the heat dissipation pad 144. The gate pad 141 is located closer to the first side edge 144E1 of the heat dissipation pad 144. In the example of FIG. 2, the gate pad 141 is adjacent to the source pad 142 in the second direction X and faces the third side edge 144E3 at a position adjacent to the corner between the first side edge 144E1 and the third side edge 144E3.

[0023] The wiring pattern 130 further includes a gate extension pattern 160 extending from the gate pad 141 in the second direction X, and a Kelvin source extension pattern 170 extending from the heat dissipation pad 144 in the second direction X. In the first embodiment, the Kelvin source extension pattern 170 extends in the second direction X from a first side edge 144E1 of the heat dissipation pad 144 (i.e., a side edge that intersects with the second direction X and is located closer to the gate pad 141 than the source pad 142). The Kelvin source extension pattern 170 includes a driver connection pad 170P at an end opposite to the heat dissipation pad 144 in the second direction X.

[0024] 2, the Kelvin source extension pattern 170 extends in the second direction X from the first side edge 144E1 at a corner position between the first side edge 144E1 and the third side edge 144E3, i.e., at a corner position adjacent to the gate pad 141. Therefore, the Kelvin source extension pattern 170 extends in the second direction X adjacent to and substantially parallel to the gate extension pattern 160.

[0025] The gate extension pattern 160 may include a plurality of divided patterns spaced apart from each other. In the first embodiment, the gate extension pattern 160 includes a first divided pattern 161 and a second divided pattern 162 spaced apart from each other.

[0026] The first divided pattern 161 extends in the second direction X and includes the gate pad 141 at one end in the second direction X and the element connection pad 161P at the other end in the second direction X. The first divided pattern 161 extends in the second direction X from the gate pad 141 to the element connection pad 161P.

[0027] The second divided pattern 162 extends in the second direction X and includes an element connection pad 162PA at one end in the second direction X and a driver connection pad 162PB at the other end in the second direction X. The element connection pad 162PA faces and is spaced apart from the element connection pad 161P of the first divided pattern 161 in the second direction X. The second divided pattern 162 extends in the second direction X from the element connection pad 162PA to the driver connection pad 162PB.

[0028] The circuit module 100 includes a circuit element 180 mounted on an element connection pad 161P of the first divided pattern 161 and an element connection pad 161PA of the second divided pattern 162. The circuit element 180 is, for example, a resistive element. The resistive element (circuit element 180) is provided to adjust the rising slope and falling slope of the gate control voltage supplied from the gate driver 120 to the transistor 10, for example.

[0029] 1, the gate driver 120 is mounted on a driver connection pad 172PB of the gate extension pattern 160 (the second divided pattern 162 in the first embodiment) and on a driver connection pad 170P of the Kelvin source extension pattern 170. Therefore, the transistor 10 and the gate driver 120 are located on both sides of the Kelvin source extension pattern 170 in the second direction X. In addition, the transistor 10 and the gate driver 120 are located on both sides of the gate extension pattern 160 in the second direction X. The gate driver 120 is electrically connected to the transistor 10 by the gate extension pattern 160 and the Kelvin source extension pattern 170, and supplies a gate control voltage to the transistor 10 via the gate extension pattern 160.

[0030] [1-3. Schematic package structure of surface mount transistor] FIG. 3 is a schematic plan view of transistor 10 (surface-mounted transistor) mounted on circuit board 110 of FIG. 1, showing the package appearance of transistor 10. In FIG.

[0031] The transistor 10 includes a package surface 10S that is rectangular in plan view. The transistor 10 includes a gate terminal Tg, one or more (e.g., three) source terminals Ts, one or more (e.g., four) drain terminals Td, and a heat dissipation terminal Thd, each of which is exposed on the package surface 10S. The number of the source pads 142 and the number of the drain pads 143 described above correspond to the number of the source terminals Ts and the number of the drain terminals Td, respectively. Although not shown in the figure, the multiple source terminals Ts are connected to each other within the package (transistor 10). Similarly, the multiple drain terminals Td are also connected to each other within the package.

[0032] The package surface 10S includes four sides that define the package outline of the transistor 10: a first side edge 10E1, a second side edge 10E2, a third side edge 10E3, and a fourth side edge 10E4. When the transistor 10 is mounted on the transistor mounting pattern 140 (circuit board 110), the first and second side edges 10E1 and 10E2 extend parallel to each other along a first direction Y, and the third and fourth side edges 10E3 and 10E4 extend parallel to each other along a second direction X. The gate terminal Tg and the source terminal Ts are arranged along the third side edge 10E3, and the drain terminal Td is arranged along the fourth side edge 10E4 opposite the third side edge 10E3.

[0033] The transistor 10 is surface-mounted on the transistor mounting pattern 140 with the gate terminal Tg, source terminal Ts, drain terminal Td, and heat dissipation terminal Thd facing the gate pad 141, source pad 142, drain pad 143, and heat dissipation pad 144, respectively. Therefore, in the circuit module 100, the gate terminal Tg, source terminal Ts, drain terminal Td, and heat dissipation terminal Thd are electrically connected to the gate pad 141, source pad 142, drain pad 143, and heat dissipation pad 144, respectively.

[0034] Regarding the package size of the transistor 10, the length L1 of the third side edge 10E3 (i.e., the side edge on which the gate terminal Tg and the source terminal Ts are arranged) may be 6 mm or less. Note that the length L1 is the dimension in the second direction X. Alternatively, the length L1 of the third side edge 10E3 may be 4 mm or less. In one example, the length L1 of the third side edge 10E3 is 3.3 mm. The length of the fourth side edge 10E4 may be the same as the length L1 of the third side edge 10E3. The lengths of the first and second side edges 10E1 and 10E2 (dimensions in the first direction Y) may be equal to or less than the length L1 of the third side edge 10E3. For example, the planar size of the transistor 10 is 5.0 × 6.0 mm when L1 = 6 mm. 2 When L1=3.3 mm, the length is 3.3×3.3 mm. 2 It may be.

[0035] The transistor 10 includes a built-in transistor chip 10C mounted on a heat dissipation terminal Thd. The heat dissipation terminal Thd functions as a heat dissipation member for dissipating heat generated in the transistor chip 10C to the outside. The transistor chip 10C is electrically connected to the heat dissipation terminal Thd by a conductive bonding member such as solder (not shown in FIG. 3). Although not shown, the transistor chip 10C includes a gate electrode pad electrically connected to the gate terminal Tg, a source electrode pad electrically connected to the source terminal Ts, and a drain electrode pad electrically connected to the drain terminal Td. Electrical connection with these electrode pads is made using a connecting conductor such as a conductive wire or a conductive clip (a bridge-shaped conductor member). The heat dissipation terminal Thd is electrically connected to the source terminal Ts via an internal structure of the transistor chip 10C, which will be described later with reference to FIG. 4. Therefore, the same potential (e.g., ground voltage) as that of the source terminal Ts is applied to the heat dissipation terminal Thd.

[0036] [1-4. Transistor structure (HEMT structure)] FIG. 4 is a schematic cross-sectional view of an exemplary HEMT structure of transistor 10, showing the internal structure of transistor chip 10C.

[0037] The transistor 10 includes a semiconductor substrate 12 and a buffer layer 14 located on the semiconductor substrate 12. The transistor 10 further includes an electron transit layer 16 and an electron supply layer 18 located on the electron transit layer 16.

[0038] The semiconductor substrate 12 may be formed of Si, silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 is a conductive Si substrate. The semiconductor substrate 12 may have a thickness of, for example, 100 μm or more and 1500 μm or less. In one example, the thickness of the semiconductor substrate 12 is 250 μm.

[0039] The buffer layer 14 includes one or more nitride semiconductor layers. The electron transport layer 16 is located on the buffer layer 14. The buffer layer 14 may be made of any material that can facilitate epitaxial growth of the electron transport layer 16.

[0040] For example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different Al compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. To suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0041] The electron transit layer 16 may be, for example, a GaN layer. The electron transit layer 16 may have a thickness of, for example, 0.5 μm or more and 2 μm or less. To suppress leakage current in the electron transit layer 16, impurities may be introduced into a portion of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface region. In this case, the impurity may be, for example, C, and the impurity concentration in the electron transit layer 16 may be, for example, 4×10 16 cm -3 It can be more than that.

[0042] The electron supply layer 18 has a larger band gap than the electron transit layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. Since the band gap increases as the Al composition increases, the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. For example, the electron supply layer 18 is an Al GaN layer with an Al composition ratio X. X Ga (1-X)It is composed of N. The Al composition ratio X may be 0.1 < X < 0.4, preferably 0.1 < X < 0.3. The electron supply layer 18 may have a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the thickness of the electron supply layer 18 is 8 nm or more.

[0043] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants from each other. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, the 2DEG 20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0044] The transistor 10 further includes a gate layer 22 located on the electron supply layer 18 and a gate electrode 24 located on the gate layer 22. The gate layer 22 is partially provided on the electron supply layer 18.

[0045] The gate layer 22 is composed of a nitride semiconductor containing acceptor-type impurities. For example, the gate layer 22 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of acceptor-type impurities in the gate layer 22 is, for example, 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. In one example, the gate layer 22 is GaN containing at least one of Mg and Zn as an impurity.

[0046] The gate electrode 24 includes one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. In another example, the gate electrode 24 includes a first metal layer made of Ti and a second metal layer formed of TiN and located on the first metal layer. The gate electrode 24 forms a Schottky junction with the gate layer 22. The gate electrode 24 is partially disposed on the gate layer 22. The gate electrode 24 may have a thickness of, for example, 50 nm to 200 nm.

[0047] The transistor 10 further includes a passivation layer 26. The passivation layer 26 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 26 is formed of at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON), for example. In one example, the passivation layer 26 is formed of a material containing SiN. The passivation layer 26 may have a thickness of, for example, 80 nm to 150 nm.

[0048] The passivation layer 26 includes a source opening 26A and a drain opening 26B spaced apart from each other in the second direction X. The gate layer 22 is located between the source opening 26A and the drain opening 26B. The gate layer 22 is located closer to the source opening 26A than to the drain opening 26B.

[0049] The transistor 10 includes a source electrode 28 in contact with the electron supply layer 18 through a source opening 26A, and a drain electrode 30 in contact with the electron supply layer 18 through a drain opening 26B. The source electrode 28 and the drain electrode 30 may include one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be formed by combining two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, and the like. In one example, the source electrode 28 and the drain electrode 30 have a four-layer structure (Ti layer / AlCu layer / Ti layer / TiN layer) including, from the top surface side, a Ti layer, an AlCu layer, a Ti layer, and a TiN layer.

[0050] The source electrode 28 includes a source contact portion 28A filled in the source opening 26A and an extension portion 28B formed integrally with the source contact portion 28A and positioned on the passivation layer 26. The source contact portion 28A is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 via the source opening 26A. The extension portion 28B functions as a source field plate electrode.

[0051] 4, extension 28B (source field plate electrode) covers the entire gate electrode 24 and gate layer 22. Extension 28B includes end 28BE facing drain electrode 30 as a source field plate electrode end. Extension 28B (source field plate electrode) plays a role in alleviating electric field concentration near the end of gate layer 22 when a high voltage is applied between the source and drain in an off state in which 2DEG 20 in the region of electron transit layer 16 directly below gate layer 22 has disappeared.

[0052] The drain electrode 30 includes a drain contact portion 30A filled in the drain opening 26B. The drain contact portion 30A is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 via the drain opening 26B.

[0053] The transistor 10 further includes an interlayer insulating layer 32 covering the source electrode 28, the drain electrode 30, and the passivation layer 26, and a wiring layer 40 formed on the interlayer insulating layer 32. The interlayer insulating layer 32 is, for example, a SiO2 layer, but may be formed of other insulating materials. The wiring layer 40 is formed of a metal material such as gold (Au), Cu, or Al.

[0054] The wiring layer 40 includes a source wiring 42, a drain wiring 44, and a gate wiring (not shown). The source wiring 42 is connected to the source electrode 28 by a through conductor 46 that penetrates the interlayer insulating layer 32, and the drain wiring 44 is connected to the drain electrode 30 by a through conductor 48 that penetrates the interlayer insulating layer 32. Although not shown, the gate wiring is similarly connected to the gate electrode 24 by a through conductor that penetrates the interlayer insulating layer 32. Although not shown, the source wiring 42, the drain wiring 44, and the gate wiring are connected to a source electrode pad, a drain electrode pad, and a gate electrode pad, respectively, by individual through conductors that penetrate an interlayer insulating layer that further covers the wiring layer 40.

[0055] 4, the source wiring 42 is embedded in a first opening 52 that penetrates the interlayer insulating layer 32 and a second opening 54 that penetrates the nitride semiconductor layers (the electron supply layer 18, the electron transit layer 16, and the buffer layer 14 in the example of FIG. 4) on the semiconductor substrate 12 and reaches the semiconductor substrate 12, and is electrically connected to the semiconductor substrate 12. Therefore, the same potential as that applied to the source electrode 28 from the source terminal Ts via the source wiring 42 etc. is applied to the semiconductor substrate 12.

[0056] A back electrode 60 is provided on the back surface of the semiconductor substrate 12. The back electrode 60 may be formed of any conductive material including at least one of Ti, Ni, nickel-vanadium alloy (NiV), silver (Ag), and Au. The back electrode 60 is electrically connected to the heat dissipation terminal Thd by a conductive bonding member 70 such as solder. Therefore, the same potential as that of the semiconductor substrate 12, i.e., the same potential as that applied from the source terminal Ts to the source electrode 28 via the source wiring 42 or the like, is applied to the heat dissipation terminal Thd. In this way, the heat dissipation terminal Thd is electrically connected to the source terminal Ts through the internal structure of the transistor chip 10C (transistor 10).

[0057] In the transistor 10 configured as described above, the gate layer 22 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18. As a result, in the region immediately below the gate layer 22, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. As a result, when a gate control voltage that turns off the transistor 10 is applied to the gate electrode 24 (for example, when the gate-source voltage is 0 V or lower), a 2DEG 20 is not formed in the region of the electron transit layer 16 immediately below the gate layer 22. On the other hand, a 2DEG 20 is formed in the region of the electron transit layer 16 other than the region immediately below the gate layer 22.

[0058] In this way, the presence of the gate layer 22 doped with acceptor-type impurities causes the 2DEG 20 to disappear in the region of the electron transit layer 16 directly below the gate layer 22, thereby achieving normally-off operation of the transistor. When an appropriate gate control voltage (on voltage) is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the region of the electron transit layer 16 directly below the gate layer 22, establishing electrical conduction between the source and drain.

[0059] [1-5. Function of the circuit module] In the circuit module 100, the heat dissipation terminal Thd, to which the same potential as that of the source terminal Ts is applied, is used as the Kelvin source terminal Tks. That is, the heat dissipation terminal Thd also serves as the Kelvin source terminal Tks without using the source terminal Ts. FIG. 5 is a schematic diagram of the gate-Kelvin source charge / discharge path Pg for controlling the gate-source voltage of the transistor 10 in the circuit module 100. FIG. 6 is a schematic circuit diagram of the circuit module 100.

[0060] 5, the gate-Kelvin source charge / discharge path Pg includes, between the transistor 10 and the gate driver 120, the gate extension pattern 160, the gate pad 141, the gate terminal Tg (see FIG. 3), the heat dissipation terminal Thd, i.e., the Kelvin source terminal Tks (see FIG. 3), the heat dissipation pad 144, and the Kelvin source extension pattern 170. Therefore, the gate-Kelvin source charge / discharge path Pg is electrically isolated from the drain-source current path between the drain terminal Td and the source terminal Ts, through which the drain current flows.

[0061] 6, a parasitic inductance Ls resulting from, for example, the source-side wiring of the package (the source terminal Ts itself, and the connecting conductor connecting the source terminal Ts and the source electrode pad, etc.) is coupled to the source terminal Ts of the transistor 10. This parasitic inductance Ls generates electromotive noise due to changes in the drain current flowing in the drain-source current path when the transistor 10 is turned on.

[0062] In this regard, in the circuit module 100, the gate-Kelvin source charge / discharge path Pg is separated from the drain-source current path, so the gate-source voltage controlled based on the gate control voltage supplied from the gate driver 120 is not affected by the electromotive noise. This makes it possible to suppress switching losses caused by the electromotive noise and stabilize high-speed switching operations. Furthermore, because the gate-Kelvin source charge / discharge path Pg is not affected by electromotive noise, malfunctions such as self-turn-on can also be suppressed.

[0063] Additionally, in the circuit module 100, the heat dissipation terminal Thd doubles as the Kelvin source terminal Tks, even if the source terminal Ts is not used. This eliminates the need to limit the number and arrangement of the source terminals Ts, even if the function of the Kelvin source terminal Tks is added. This eliminates variations in the wiring length (e.g., wire length) from the transistor chip 10C to each source terminal Ts. This prevents instability in high-speed switching operation and localized heat generation due to uneven parasitic inductance within the transistor 10.

[0064] [1-6. Advantages of Circuit Boards and Circuit Modules] The circuit board 110 and the circuit module 100 of the first embodiment have the following advantages. (1-1) The wiring pattern 130 includes a transistor mounting pattern 140 used to mount a surface-mounted transistor 10. The wiring pattern 130 includes a gate extension pattern 160 connected to the gate pad 141 and extending in the second direction X, and a Kelvin source extension pattern 170 extending from the heat dissipation pad 144 in the second direction X. The gate pad 141 and the source pad 142 are arranged side by side in the second direction X, and the Kelvin source extension pattern 170 extends in the second direction X from a first side edge 144E1 of the heat dissipation pad 144 that is located closer to the gate pad 141 than the source pad 142.

[0065] This wiring pattern 130 allows the heat dissipation terminal Thd, which is electrically connected to the source terminal Ts in the transistor 10, to be used as the Kelvin source terminal Tks. This makes it possible to control the gate-source voltage through the gate-Kelvin source charge / discharge path Pg, which is not affected by electromotive noise generated in the drain-source current path, and realizes high-speed switching operation.

[0066] In particular, in this configuration, since the gate extension pattern 160 and the Kelvin source extension pattern 170 both extend in the same direction (the second direction X), the length of the gate-Kelvin source charge / discharge path Pg between the transistor 10 and the gate driver 120 can be minimized, thereby achieving stable high-speed switching operation.

[0067] In addition, adding the function of the Kelvin source terminal Tks does not limit the number and arrangement of the source terminals Ts, so it is possible to suppress instability of high-speed switching operation and localized heat generation caused by imbalances in the parasitic inductance within the transistor 10.

[0068] (1-2) The gate extension pattern 160 includes a first divided pattern 161 and a second divided pattern 162 that are spaced apart from each other. With this configuration, the gate control voltage can be adjusted by connecting a circuit element 180 between the first divided pattern 161 and the second divided pattern 162. For example, by using a resistive element as the circuit element 180, the rising slope and falling slope of the gate control voltage can be adjusted.

[0069] (1-3) The gate pad 141 is disposed adjacent to the corner between the first side edge 144E1 and the third side edge 144E3 of the heat dissipation pad 144, facing the third side edge 144E3, and the gate extension pattern 160 extends from this gate pad 141 in the second direction X. With this configuration, the length of the gate extension pattern 160, and therefore the length of the gate-Kelvin source charge / discharge path Pg, can be minimized, thereby achieving stable high-speed switching operation.

[0070] (1-4) The wiring pattern 130 includes a source connecting pattern 151 that connects the multiple source pads 142 to each other. This configuration simplifies the shape of the wiring pattern 130 and allows the same potential to be applied to each source pad 142 through the source connecting pattern 151. This is an advantage obtained by enabling the heat dissipation terminal Thd to be used as the Kelvin source terminal Tks.

[0071] (1-5) In the circuit module 100, the transistor 10 and the gate driver 120 are arranged on both sides of the Kelvin source extension pattern 170 in the second direction X. This arrangement makes it possible to minimize the length of the gate-Kelvin source charge / discharge path Pg, which includes the Kelvin source extension pattern 170 and the gate extension pattern 160.

[0072] (1-6) Because the heat dissipation terminal Thd also serves as the Kelvin source terminal Tks, there is no need to provide a new terminal to add the function of the Kelvin source terminal Tks. Therefore, only the gate terminal Tg and the source terminal Ts are arranged on the third side edge 10E3 (see FIG. 3) of the transistor 10. This contributes to a reduction in package size, and is advantageous in achieving, for example, a size in which the length L1 of the third side edge 10E3 is 6 mm or less (even 4 mm or less).

[0073] (1-7) The semiconductor substrate 12 of the transistor 10 is electrically connected to the heat dissipation terminal Thd, and is also electrically connected to the source electrode 28 by the source wiring 42. This makes it possible to apply the same potential to the source terminal Ts and the heat dissipation terminal Thd, and use the heat dissipation terminal Thd as the Kelvin source terminal Tks.

[0074] (1-8) The transistor 10 is configured as a HEMT using GaN. This allows the circuit module 100, which has the advantages of (1-1) to (1-7) above, to be used as a power device using a GaN-HEMT.

[0075] [Second embodiment] Next, a circuit module 200 and a circuit board 210 according to a second embodiment will be described with reference to FIG. 7. The second embodiment differs from the first embodiment in that the wiring pattern 130 is replaced with a wiring pattern 230, and the gate driver 120 is replaced with a gate driver 220. The other configurations are the same as those of the first embodiment. Below, a description of the same components as those in the first embodiment will be omitted, and only components different from those in the first embodiment will be described.

[0076] The circuit module 200 of the second embodiment is embodied as a half-bridge module including a half-bridge circuit formed by two transistors 10 and a gate driver 220 that controls the driving of the half-bridge circuit. The half-bridge circuit is formed by connecting two transistors 10 in series. In the half-bridge circuit, one of the two transistors 10 functions as a high-side transistor (control transistor) of the half-bridge circuit, and the other functions as a low-side transistor (synchronous rectification transistor) of the half-bridge circuit.

[0077] 7, the wiring pattern 230 includes first and second transistor mounting patterns 140A and 140B used to mount a half-bridge circuit (two transistors 10). The first transistor mounting pattern 140A is provided for mounting the transistor 10 (upper side in FIG. 7) that functions as a high-side transistor. The second transistor mounting pattern 140B is provided for mounting the transistor 10 (lower side in FIG. 7) that functions as a low-side transistor.

[0078] The first and second transistor mounting patterns 140A and 140B each have the same configuration as the transistor mounting pattern 140 described in the first embodiment with reference to Fig. 3. Therefore, detailed description thereof will be omitted.

[0079] The wiring pattern 230 of the second embodiment includes a source-drain connecting pattern 153 that connects the source pad 142 of the first transistor mounting pattern 140A and the drain pad 143 of the second transistor mounting pattern 140B to each other. As a result, the two transistors 10 mounted on the first and second transistor mounting patterns 140A and 140B are connected in series by the source-drain connecting pattern 153.

[0080] The wiring pattern 230 includes a gate extension pattern 160A extending in the second direction X from the gate pad 141 of the first transistor mounting pattern 140A, and a Kelvin source extension pattern 170A extending in the second direction X from the heat dissipation pad 144 (first side edge 144E1) of the first transistor mounting pattern 140A. The gate extension pattern 160A and the Kelvin source extension pattern 170A have the same configurations as the gate extension pattern 160 and the Kelvin source extension pattern 170 described in the first embodiment with reference to FIG. 3, respectively. Therefore, detailed description thereof will be omitted.

[0081] The wiring pattern 230 also includes a gate extension pattern 160B extending in the second direction X from the gate pad 141 of the second transistor mounting pattern 140B, and a Kelvin source extension pattern 170B extending in the second direction X from the heat dissipation pad 144 (first side edge 144E1) of the second transistor mounting pattern 140B.

[0082] The gate extension pattern 160B differs from the gate extension pattern 160A in that the first division pattern 161 and the second division pattern 162 are arranged so as to be spaced apart from each other in the first direction Y, specifically, the element connection pad 161P and the element connection pad 162PA are arranged side by side in the first direction Y.

[0083] The Kelvin source extension pattern 170B differs from the Kelvin source extension pattern 170A in that it extends in the second direction X from the first side edge 144E1 at the corner position of the heat dissipation pad 144 closer to the drain pad 143.

[0084] The circuit board 210 and the circuit module 200 of the second embodiment described above have the following advantages in addition to the advantages (1-1) to (1-8) described in the first embodiment. (2-1) The wiring pattern 230 of the second embodiment corresponds to a configuration in which two wiring patterns 130 of the first embodiment are connected by a source-drain coupling pattern 153. This allows the wiring pattern 230 to be used for a half-bridge circuit (half-bridge module).

[0085] [Example of change] The above-described embodiments can be modified, for example, as follows: The above-described embodiments and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above-described embodiments will be assigned the same reference numerals as in the above-described embodiments, and their description will be omitted.

[0086] FIG. 8 is a schematic plan view of another exemplary wiring pattern 130A. This wiring pattern 130A differs from the wiring pattern 130 of the first embodiment in that the Kelvin source extension pattern 170 extends in the second direction X from the first side edge 144E1 of the heat dissipation pad 144 at the corner between the first side edge 144E1 and the fourth side edge 144E4. In this manner, the Kelvin source extension pattern 170 may extend from any position on the first side edge 144E1 of the heat dissipation pad 144. This wiring pattern 130A also has advantages similar to those of the wiring pattern 130 of the first embodiment. For example, using the wiring pattern 130A provides the advantage of providing a larger space for arranging the circuit element 180.

[0087] FIG. 9 is a schematic plan view of yet another exemplary wiring pattern 130B. This wiring pattern 130B differs from the wiring pattern 130 of the first embodiment in that the first divided pattern 161 of the gate extension pattern 160 is bent into an L-shape in plan view. In the modification of FIG. 9 , the first divided pattern 161 extends slightly in the first direction Y from the gate pad 141 and then bends in the second direction X to extend in the second direction X. The second divided pattern 162 extends entirely in the second direction X. As described above, the gate extension pattern 160 needs only to extend entirely in the second direction X, and a portion of the gate extension pattern 160 may extend in the first direction Y. This wiring pattern 130B also has substantially the same advantages as the wiring pattern 130 of the first embodiment. Similar to the case of using the wiring pattern 130A, the use of the wiring pattern 130B provides an advantage, for example, of providing a larger space for arranging the circuit element 180.

[0088] Each of the gate extension patterns 160, 160A, and 160B does not have to be divided into a plurality of parts, and may be provided as a single gate extension pattern. Furthermore, the number of divisions of each of the gate extension patterns 160, 160A, and 160B is not necessarily limited to two, and each of the gate extension patterns 160, 160A, and 160B may be divided into three or more.

[0089] The source connection pattern 151 may be omitted, i.e., the plurality of source pads 142 may be separated from one another. Similarly, the drain connection pattern 152 may be omitted, i.e., the plurality of drain pads 143 may be separated from one another.

[0090] The gate pad 141 does not necessarily have to be located adjacent to the corner of the heat dissipation pad 144, but may be located slightly closer to the center of the third side edge 144E3 of the heat dissipation pad 144, for example.

[0091] The number of source pads 142 is not limited to three and may be one or a number other than three. Similarly, the number of drain pads 143 is not limited to four and may be one or a number other than four.

[0092] Furthermore, the shape and layout of each of the gate extension patterns 160, 160A, 160B are merely examples, and each of the gate extension patterns 160, 160A, 160B may have a different shape and layout as long as it extends in the second direction X.

[0093] Similarly, the shape and layout of each of the Kelvin source extension patterns 170, 170A, and 170B are merely examples. As long as each of the Kelvin source extension patterns 170, 170A, and 170B extends in the second direction X from the first side edge 144E1 of the heat dissipation pad 144, a portion of each of the Kelvin source extension patterns 170, 170A, and 170B may be bent (for example, as shown in FIG. 1).

[0094] The transistor 10 is not limited to a nitride semiconductor transistor and may be, for example, a silicon MOS transistor. Also, the transistor 10 is not limited to a GaN-based HEMT and may be another nitride semiconductor transistor.

[0095] The transistor 10 is not limited to the structure shown in Figure 4. For example, the gate layer 22 is not limited to the rectangular cross-sectional shape shown in Figure 4. For example, the gate layer 22 may be formed to have a convex cross-sectional shape that includes a main body portion (e.g., a ridge-shaped main body portion) in which the gate electrode 24 is located and two extension portions that extend from the main body portion toward the source contact portion 28A and the drain contact portion 30A.

[0096] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0097] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X axis direction may be the vertical direction, or the Y axis direction may be the vertical direction.

[0098] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0099] [Appendix 1] a wiring pattern (130; 130A; 130B; 230) including a transistor mounting pattern (140; 140A; 140B) used to mount a surface-mounted transistor (10) including a gate terminal (Tg), a source terminal (Ts), a drain terminal (Td), and a heat dissipation terminal (Thd) electrically connected to the source terminal (Ts); The transistor mounting pattern (140; 140A; 140B) a gate pad (141) used for electrical connection with the gate terminal (Tg); a source pad (142) used for electrical connection with the source terminal (Ts); a drain pad (143) used for electrical connection with the drain terminal (Td) and disposed spaced apart from the source pad (142) and the gate pad (141) in a first direction (Y); a heat dissipation pad (144) used for electrical connection with the heat dissipation terminal (Thd) and located between the source pad (142) and the drain pad (143) and between the gate pad (141) and the drain pad (143) in the first direction (Y); The wiring pattern (130; 130A; 130B; 230) a gate extension pattern (160; 160A; 160B) connected to the gate pad (141) and extending in a second direction (X) intersecting the first direction (Y) in a plan view; and a Kelvin source extension pattern (170; 170A; 170B) extending from the heat dissipation pad (144) in the second direction (X), The gate pad 141 and the source pad 142 are arranged side by side in the second direction (X), The heat dissipation pad (144) includes a side edge (144E1) that intersects with the second direction (X), the side edge (144E1) being located closer to the gate pad (141) than the source pad (142), The Kelvin source extension pattern (170; 170A; 170B) extends from the side edge (144E1) in the second direction (X), the circuit board (110; 210).

[0100] [Appendix 2] 2. The circuit board (110; 210) according to claim 1, wherein the gate extension pattern (160; 160A; 160B) includes a plurality of divided patterns (161, 162) spaced apart from each other.

[0101] [Appendix 3] The heat dissipation pad (144) has a rectangular shape in a plan view, including a first side edge (144E1), a second side edge (144E2), a third side edge (144E3), and a fourth side edge (144E4) that define the outer shape of the heat dissipation pad (144), The first side edge (144E1) and the second side edge (144E2) extend along the first direction (Y), The third side edge (144E3) and the fourth side edge (144E4) extend along the second direction (X), The side edge (144E1) of the heat dissipation pad (144) is the first side edge (144E1), The source pad (142) is disposed opposite the third side edge (144E3), The circuit board (110; 210) described in Appendix 1 or 2, wherein the gate pad (141) is adjacent to the source pad (142) in the second direction (X) and is positioned facing the third side edge (144E3) at a position adjacent to a corner between the first side edge (144E1) and the third side edge (144E3).

[0102] [Appendix 4] The source pad (142) is one of a plurality of source pads (142) arranged in the second direction (X), The circuit board (110; 210) according to any one of appendices 1 to 3, wherein the wiring pattern (130; 130A; 130B; 230) further includes a source connecting pattern (151) that connects the plurality of source pads (142) to each other.

[0103] [Appendix 5] The wiring pattern (230) includes a plurality of transistor mounting patterns (140A; 140B) used to mount a plurality of surface-mounted transistors (10), the transistor mounting pattern (140) is one of the plurality of transistor mounting patterns (140A, 140B), A circuit board (110; 210) according to any one of appendices 1 to 4, wherein the Kelvin source extension pattern (170; 170A; 170B) of each of the plurality of transistor mounting patterns (140A, 140B) extends in the second direction (X).

[0104] [Appendix 6] the plurality of transistor mounting patterns (140A, 140B) include a first transistor mounting pattern (140A) and a second transistor mounting pattern (140B) adjacent to each other in the first direction (Y), The circuit board (110; 210) described in Appendix 5, wherein the wiring pattern (230) further includes a source-drain connecting pattern (153) that connects the source pad (142) of the first transistor mounting pattern (140A) and the drain pad (143) of the second transistor mounting pattern (140B) to each other.

[0105] [Appendix 7] A circuit module (100; 200) comprising: A circuit board (110; 210) according to any one of appendices 1 to 6; The surface mount transistor (10) mounted on the transistor mounting pattern (140; 140A; 140B); A circuit module (100; 200) comprising:

[0106] [Appendix 8] 8. The circuit module (100; 200) according to claim 7, wherein the surface-mount transistor (10) is a nitride semiconductor transistor.

[0107] [Appendix 9] The device further includes a gate driver (120; 220) mounted on the wiring pattern (130; 130A; 130B; 230) and electrically connected to the gate extension pattern (160; 160A; 160B) and the Kelvin source extension pattern (170; 170A; 170B), A circuit module (100; 200) according to appendix 7 or 8, wherein the surface-mounted transistor (10) and the gate driver (120; 220) are located on both sides of the Kelvin source extension pattern (170; 170A; 170B) in the second direction (X).

[0108] [Appendix 10] The surface-mount transistor (10) includes a package surface (10S) that is rectangular in plan view, the gate terminal (Tg), the source terminal (Ts), the drain terminal (Td), and the heat dissipation terminal (Thd) are exposed from the package surface (10S); The gate terminal (Tg) and the source terminal (Ts) are arranged along one side edge (10E3) of four side edges (10E1, 10E2, 10E3, 10E4) that define the outline of the package surface (10S), A circuit module (100; 200) described in any one of Appendices 7 to 9, wherein the length (L1) of the side edge (10E3) of the package surface (10S) on which the gate terminal (Tg) and the source terminal (Ts) are arranged is 6 mm or less.

[0109] [Appendix 11] The surface mount transistor (10) a conductive semiconductor substrate (12) electrically connected to the heat dissipation terminal (Thd); a gate electrode (24) electrically connected to the gate terminal (Tg); a source electrode (28) electrically connected to the source terminal (Ts); a drain electrode (30) electrically connected to the drain terminal (Td), A circuit module (100; 200) according to any one of appendices 7 to 10, wherein the conductive semiconductor substrate (12) and the source electrode (28) are electrically connected by a source wiring (42).

[0110] [Appendix 12] The nitride semiconductor transistor (10) a conductive semiconductor substrate (12) electrically connected to the heat dissipation terminal (Thd); an electron transit layer (16); an electron supply layer (18) located on the electron transit layer (16) and having a band gap larger than that of the electron transit layer (16); a gate layer (22) located on the electron supply layer (18) and containing acceptor-type impurities; a gate electrode (24) located on the gate layer (22); a source electrode (28) and a drain electrode (30) located in contact with the electron supply layer (18); The circuit module (100; 200) according to any one of appendices 8 to 10, wherein the conductive semiconductor substrate (12) and the source electrode (28) are electrically connected by a source wiring (42). [Explanation of symbols]

[0111] 10...Transistor (surface-mounted transistor) 10E1…First side edge 10E2…Second side edge 10E3…Third side edge 10E4...Fourth side edge 10S...Package surface 12...Semiconductor substrate 14...Buffer layer 16...Electron transit layer 18...electron supply layer 20...2DEG 22...Gate layer 24...Gate electrode 26...passivation layer 28...Source electrode 28A...Source contact part 30...Drain electrode 30A...Drain contact 32...Interlayer insulating layer 40...Wiring layer 42...Source wiring 44...Drain wiring 46, 48...Through conductor 52...First opening 54...Second opening 60...Back electrode 70...Conductive joining material 100, 200... Circuit module 110, 210...Circuit board 120,220...Gate driver 130, 130A, 130B, 230...wiring pattern 140, 140A, 140B...Transistor mounting pattern 141...Gate Pad 142...Sauce Pad 143...Drain pad 144...Heat dissipation pad 144E1…First side edge 144E2…Second side edge 144E3…Third side edge 144E4…4th side edge 151...Source connection pattern 152...Drain connection pattern 153...Source-drain connection pattern 160, 160A, 160B...Gate extension pattern 161...First division pattern (division pattern) 161P: Element connection pad 162...Second division pattern (division pattern) 162PA...Element connection pad 162PB...Driver connection pad 170, 170A, 170B... Extension pattern for Kelvin source 170P...Driver connection pad 180...Circuit element Tg: Gate terminal Ts: Source terminal Td: Drain terminal Thd...heat dissipation terminal Tks: Kelvin source terminal Y...first direction X…Second direction L1...length

Claims

1. a wiring pattern including a transistor mounting pattern used for mounting a surface-mounted transistor including a gate terminal, a source terminal, a drain terminal, and a heat dissipation terminal electrically connected to the source terminal; The transistor mounting pattern is a gate pad used for electrical connection with the gate terminal; a source pad used for electrical connection with the source terminal; a drain pad used for electrical connection with the drain terminal and spaced apart from the source pad and the gate pad in a first direction; a heat dissipation pad used for electrical connection with the heat dissipation terminal and located between the source pad and the drain pad and between the gate pad and the drain pad in the first direction; The wiring pattern is a gate extension pattern connected to the gate pad and extending in a second direction intersecting the first direction in a plan view; an extension pattern for a Kelvin source extending from the heat dissipation pad in the second direction; the gate pad and the source pad are arranged side by side in the second direction, the thermal pad includes a side edge intersecting the second direction and positioned closer to the gate pad than the source pad; The Kelvin source extension pattern extends from the side edge in the second direction.

2. The circuit board according to claim 1 , wherein the gate extension pattern includes a plurality of divided patterns spaced apart from each other.

3. the thermal pad has a rectangular shape in a plan view, the rectangular shape including a first side edge, a second side edge, a third side edge, and a fourth side edge that define an outer shape of the thermal pad; the first side edge and the second side edge extend along the first direction, the third side edge and the fourth side edge extend along the second direction, the side edge of the thermal pad is the first side edge, the source pad is disposed opposite the third side edge, 2. The circuit board according to claim 1, wherein the gate pad is adjacent to the source pad in the second direction and is positioned facing the third side edge at a position adjacent to a corner between the first side edge and the third side edge.

4. the source pad is one of a plurality of source pads arranged side by side in the second direction, The circuit board of claim 1 , wherein the wiring pattern further comprises a source connecting pattern connecting the plurality of source pads to each other.

5. the wiring pattern includes a plurality of transistor mounting patterns used for mounting a plurality of surface-mounted transistors; the transistor mounting pattern is one of the plurality of transistor mounting patterns, The circuit board according to claim 1 , wherein the Kelvin source extension pattern of each of the plurality of transistor mounting patterns extends in the second direction.

6. the plurality of transistor mounting patterns include a first transistor mounting pattern and a second transistor mounting pattern adjacent to each other in the first direction, The circuit board of claim 5 , wherein the wiring pattern further includes a source-drain connecting pattern that connects the source pad of the first transistor mounting pattern and the drain pad of the second transistor mounting pattern to each other.

7. A circuit module comprising: The circuit board according to any one of claims 1 to 6, the surface mount transistor mounted on the transistor mounting pattern; A circuit module comprising:

8. The circuit module of claim 7 , wherein the surface-mount transistor is a nitride semiconductor transistor.

9. a gate driver mounted on the wiring pattern and electrically connected to the gate extension pattern and the Kelvin source extension pattern; The circuit module according to claim 7 , wherein the surface-mounted transistor and the gate driver are located on both sides of the Kelvin source extension pattern in the second direction.

10. the surface mount transistor includes a package surface that is rectangular in plan view, the gate terminal, the source terminal, the drain terminal, and the heat dissipation terminal are exposed from a surface of the package; the gate terminal and the source terminal are arranged along one of four side edges that define the outline of the package surface; 8. The circuit module according to claim 7, wherein the side edge of the package surface on which the gate terminals and the source terminals are arranged has a length of 6 mm or less.

11. The surface mount transistor is a conductive semiconductor substrate electrically connected to the heat dissipation terminal; a gate electrode electrically connected to the gate terminal; a source electrode electrically connected to the source terminal; a drain electrode electrically connected to the drain terminal; The circuit module according to claim 7 , wherein the conductive semiconductor substrate and the source electrode are electrically connected by a source wiring.

12. The nitride semiconductor transistor is a conductive semiconductor substrate electrically connected to the heat dissipation terminal; an electron transit layer; an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; a gate layer located on the electron supply layer and containing an acceptor-type impurity; a gate electrode located on the gate layer; a source electrode and a drain electrode located in contact with the electron supply layer, The circuit module according to claim 8 , wherein the conductive semiconductor substrate and the source electrode are electrically connected by a source wiring.

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