Electro-optical device and electronic apparatus

Abstract

To provide an electro-optical device capable of reducing light leakage current.SOLUTION: An electro-optical device includes: a pixel electrode; a wiring line separated from the pixel electrode and having a first layer, a second layer, and a third layer; a transistor that corresponds to the pixel electrode and at least partially overlaps the wiring line in plan view; a data line which is provided in a layer between the transistor and the wiring line, is electrically connected to the transistor, and at least partially overlaps the wiring line in plan view. The second layer is provided between the first layer and the third layer, and has light reflectance smaller than that of the first layer. The third layer is provided closer to the transistor than the first and second layers, has light reflectance smaller than that of the first layer, and is made of a material different from the second layer.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] 2. Description of the Related Art One known electro-optical device is an active drive type liquid crystal device, in which each pixel has a transistor that controls switching of a pixel electrode.

[0003] For example, Patent Document 1 describes an electro-optical device including a pixel electrode, a transistor, and a shield layer formed by laminating a low-reflection film made of TiN and a light-shielding screen containing Al. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-65034 Summary of the Invention [Problem to be solved by the invention]

[0005] Since liquid crystal devices are photosensitive, they use lighting devices to make the display easier to see. When light from the lighting device enters a transistor, the semiconductor layer of the transistor is excited by the incident light, causing a photo-leakage current. [Means for solving the problem]

[0006] One aspect of the electro-optical device according to the present invention is A pixel electrode; a wiring spaced apart from the pixel electrode and having a first layer, a second layer, and a third layer; a transistor corresponding to the pixel electrode and at least a portion of which overlaps with the wiring in a plan view; a data line provided in a layer between the transistor and the wiring, electrically connected to the transistor, and at least a portion of which overlaps with the wiring in a plan view; and the second layer is provided between the first layer and the third layer and has a light reflectance lower than that of the first layer; The third layer is provided closer to the transistor than the first layer and the second layer, has a lower optical reflectance than the first layer, and is made of a different material than the second layer.

[0007] One aspect of the electronic device according to the present invention is This is one aspect of the electro-optical device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 2] FIG. 1 is a cross-sectional view schematically showing an electro-optical device according to an embodiment. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the electro-optical device according to the embodiment. [Figure 4] FIG. 2 is a plan view illustrating the arrangement of pixels in the electro-optical device according to the embodiment. [Figure 5] FIG. 1 is a cross-sectional view schematically showing an electro-optical device according to an embodiment. [Figure 6] FIG. 1 is a cross-sectional view schematically showing an electro-optical device according to an embodiment. [Figure 7] FIG. 1 is a cross-sectional view schematically showing an electro-optical device according to an embodiment. [Figure 8] 1A and 1B are diagrams for explaining an electronic device according to an embodiment of the present invention. [Figure 9] FIG. 10 is a diagram for explaining a model used in a simulation. [Figure 10] 1 is a table showing the composition of the target demographic used in the simulation and the results of the simulation. [Figure 11] Graph showing the results of a simulation. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. Electro-optical devices 1.1. Overall structure First, a liquid crystal device 100 as an electro-optical device according to this embodiment will be described with reference to the drawings. Fig. 1 is a plan view schematically showing the liquid crystal device 100 according to this embodiment. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1, schematically showing the liquid crystal device 100 according to this embodiment. Note that Figs. 1 and 2 illustrate an X-axis, a Y-axis, and a Z-axis as three mutually orthogonal axes.

[0011] The liquid crystal device 100 is an active-drive liquid crystal device having a thin film transistor (TFT) as a transistor for each pixel. As shown in Figures 1 and 2, the liquid crystal device 100 includes, for example, an element substrate 10, a sealant 20, a liquid crystal layer 30, and an opposing substrate 40.

[0012] 1, the element substrate 10 is larger than the opposing substrate 40 in a plan view. In the illustrated example, the shape of the element substrate 10 is rectangular. In the illustrated example, "plan view" refers to the case when viewed from the Z-axis direction.

[0013] The sealant 20 bonds the element substrate 10 and the counter substrate 40 together. The sealant 20 is provided along the outer edge of the counter substrate 40. The sealant 20 is, for example, an adhesive such as a thermosetting, photosetting, or electron beam curing epoxy resin. A display region E including a plurality of pixels P arranged in a matrix is ​​provided inside the sealant 20. The peripheral region F is located outside the display region E. In the peripheral region F, a parting portion 42 is provided between the sealant 20 and the display region E, surrounding the display region E. For example, a light-blocking metal or metal oxide is used for the parting portion 42.

[0014] The element substrate 10 has a terminal section in which a plurality of external connection terminals 101 are arranged. A data line driving circuit 102 is provided between a first side along the terminal section and the sealing material 20. A test circuit 103 is provided between the sealing material 20 and the display region E along a second side opposite the first side. A scanning line driving circuit 104 is provided between the sealing material 20 and the display region E along third and fourth sides perpendicular to the first side and facing each other. A plurality of wirings 105 connecting the two scanning line driving circuits 104 are provided between the sealing material 20 and the test circuit 103 along the second side. The wirings 105 connected to the data line driving circuit 102 and the scanning line driving circuit 104 are electrically connected to the plurality of external connection terminals 101 arranged along the first side. Although not shown, the test circuit 103 may be arranged between the sealing material 20 and the display region E along the data line driving circuit 102.

[0015] As shown in FIG. 2, the element substrate 10 includes, for example, a first substrate 11, pixel electrodes 12, TFTs 50, a first alignment layer 13, and wiring 105.

[0016] The first substrate 11 is, for example, a glass substrate or a quartz substrate.

[0017] The pixel electrode 12 and the TFT 50 are provided on the liquid crystal layer 30 side of the first substrate 11. The pixel electrode 12 and the TFT 50 are provided for each pixel P. The pixel electrode 12 and the TFT 50 constitute a pixel P. The TFT 50 is provided corresponding to the pixel electrode 12. The pixel electrode 12 is a transparent electrode made of, for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0018] The first alignment layer 13 covers the first substrate 11, the pixel electrodes 12, the TFTs 50, and the wiring 105. The first alignment layer 13 is, for example, an inorganic alignment layer such as a silicon oxide layer, or an organic alignment layer such as a polyimide layer.

[0019] The liquid crystal layer 30 is provided between the element substrate 10 and the counter substrate 40. The liquid crystal layer 30 is formed by sealing liquid crystal having positive or negative dielectric anisotropy in the gap between the element substrate 10 and the counter substrate 40.

[0020] The counter substrate 40 is provided on the opposite side of the liquid crystal layer 30 from the element substrate 10 side. Light L is incident on the counter substrate 40. The light L is incident on the liquid crystal device 100 from the counter substrate 40 side. The light L is emitted, for example, from a laser light source (not shown). The direction of incidence of the light L on the liquid crystal device 100 is not limited to the counter substrate 40 side, but may be from the element substrate 10 side. Although not shown, the liquid crystal device 100 may have a focusing means such as a microlens that focuses the incident light L for each pixel P.

[0021] The counter substrate 40 includes, for example, a second substrate 41, a parting portion 42, an insulating layer 43, a counter electrode 44, and a second alignment layer 45.

[0022] The second substrate 41 is disposed opposite to the first substrate 11. The second substrate 41 is, for example, a glass substrate, a quartz substrate, etc. The second substrate 41 transmits light L therethrough.

[0023] The parting portion 42 is provided on the element substrate 10 side of the second substrate 41. As shown in FIG. 1, the parting portion 42 overlaps with the scanning line driving circuit 104 and the inspection circuit 103 in a plan view. The parting portion 42 functions as a light-shielding portion. Specifically, the parting portion 42 blocks light L incident from the counter substrate 40 side from entering peripheral circuits such as the scanning line driving circuit 104. The parting portion 42 has the function of preventing malfunction of the peripheral circuits. Furthermore, the parting portion 42 prevents unnecessary stray light from entering the display region E. This makes it possible to prevent a decrease in the contrast of the liquid crystal device 100.

[0024] 2, the insulating layer 43 covers the parting portion 42. The surface of the insulating layer 43 facing the liquid crystal layer 30 is, for example, a flat surface. The insulating layer 43 is, for example, a light-transmitting silicon oxide layer.

[0025] The counter electrode 44 covers the insulating layer 43. The counter electrode 44 is electrically connected to conductive portions 46 shown in FIG. 1 provided at the four corners of the counter substrate 40. The conductive portions 46 are electrically connected to common wiring 16, which will be described later. The counter electrode 44 is a transparent electrode made of, for example, ITO or IZO.

[0026] 2, the second alignment layer 45 covers the counter electrode 44. The liquid crystal layer 30 is provided between the first alignment layer 13 and the second alignment layer 45. The second alignment layer 45 is, for example, an inorganic alignment layer such as a silicon oxide layer, or an organic alignment layer such as a polyimide layer.

[0027] The liquid crystal device 100 employs optical designs for a normally white mode or a normally black mode. In the normally white mode, the transmittance of the pixel P when no voltage is applied is greater than the transmittance when a voltage is applied. In the normally black mode, the transmittance of the pixel P when no voltage is applied is less than the transmittance when a voltage is applied. Although not shown, the liquid crystal device 100 may have polarizing elements disposed on both the incident side and the exit side of the light L according to the optical design.

[0028] In the following, an example will be described in which the above-mentioned inorganic alignment layers are used as the alignment layers 13 and 45, and the liquid crystal layer 30 is made of liquid crystal having negative dielectric anisotropy, and an optical design of a normally black mode is adopted.

[0029] 1.2. Equivalent Circuit FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device 100. As shown in FIG.

[0030] 3, the liquid crystal device 100 includes, for example, scanning lines 14, data lines 15, and common wiring 16. The scanning lines 14, the data lines 15, and the common wiring 16 are provided above the first substrate 11 of the element substrate 10.

[0031] The scanning lines 14 extend along the X-axis. The data lines 15 and the common wiring 16 extend along the Y-axis. Although not shown, the common wiring 16 does not necessarily have to extend along the Y-axis.

[0032] The area defined by the scanning lines 14 and the data lines 15 is a pixel P. The pixel P includes a pixel electrode 12, a TFT 50, a first capacitance element 60, and a second capacitance element 70. The first capacitance element 60 and the second capacitance element 70 are provided corresponding to the pixel electrode 12.

[0033] The scanning lines 14 are electrically connected to the gates of the TFTs 50. The data lines 15 are electrically connected to the sources of the TFTs 50. The scanning lines 14 simultaneously control the on / off of the TFTs 50 in the same row. The pixel electrodes 12 are electrically connected to the drains of the TFTs 50.

[0034] The data lines 15 are electrically connected to the data line driving circuit 102. The data lines 15 supply image signals D1, D2, ..., Dn supplied from the data line driving circuit 102 to the pixels P. The scanning lines 14 are electrically connected to the scanning line driving circuit 104. The scanning lines 14 supply scanning signals SC1, SC2, ..., SCm supplied from the scanning line driving circuit 104 to the pixels P.

[0035] The image signals D1, D2, ..., Dn supplied from the data line driving circuit 102 to the data lines 15 may be supplied line-sequentially in this order, or may be supplied in groups to adjacent data lines 15. The scanning line driving circuit 104 may supply scanning signals SC1, SC2, ..., SCm to the scanning lines 14 in pulsed line-sequential manner at predetermined timing.

[0036] When a scanning signal SC1 is input to the TFT 50, the TFT 50 is turned on for a certain period of time. As a result, an image signal D1 supplied from the data line 15 is written to the pixel electrode 12 at a predetermined timing. The image signal D1 of a predetermined level written to the liquid crystal layer 30 via the pixel electrode 12 is then held for a certain period of time between the pixel electrode 12 and the counter electrode 44 disposed opposite the pixel electrode 12 with the liquid crystal layer 30 interposed therebetween.

[0037] In order to prevent leakage of the stored image signal D1, a first capacitive element 60 and a second capacitive element 70 are electrically connected in parallel to a liquid crystal capacitance provided between the pixel electrode 12 and the counter electrode 44. One end of the first capacitive element 60 is electrically connected to the drain of the TFT 50 and the pixel electrode 12. The other end of the first capacitive element 60 is electrically connected to a common wiring 16 to which a constant potential is applied. Similarly, one end of the second capacitive element 70 is electrically connected to the drain of the TFT 50 and the pixel electrode 12. The other end of the second capacitive element 70 is electrically connected to the common wiring 16.

[0038] Although not shown, an inspection circuit 103 is connected to the data lines 15. This makes it possible to detect the image signals D1, D2, ..., Dn during the manufacturing process of the liquid crystal device 100 and check for operational defects of the liquid crystal device 100.

[0039] 1.3. Pixel Arrangement 4 is a plan view illustrating the arrangement of pixels P of the liquid crystal device 100. Note that in FIG. 4, an area E1, which is a part of the display area E shown in FIG.

[0040] 4, the shape of the pixel electrode 12 is approximately square in plan view. A plurality of pixel electrodes 12 are provided in a matrix corresponding to the arrangement of the pixels P. The scanning lines 14 are provided between the pixel electrodes 12 adjacent to each other in the Y-axis direction. The data lines 15 and the common wiring 16 are provided between the pixel electrodes 12 adjacent to each other in the X-axis direction.

[0041] The display region E is provided with a light-shielding region SD that partitions a plurality of pixels P in a plane. The light-shielding region SD has a linear portion including the scanning lines 14 and a linear portion including the data lines 15 and common wiring 16. The light-shielding region SD has a lattice shape. In FIG. 4, the light-shielding region SD is indicated by a dashed line. Because a light-shielding conductive material is applied to functional layers and wiring such as the scanning lines 14 and data lines 15, the light-shielding region SD becomes a non-opening region. In other words, the region of the display region E other than the light-shielding region SD becomes an opening region.

[0042] A tenth contact hole 120 is formed corresponding to the pixel electrode 12. The pixel electrode 12 is electrically connected to a fifth relay electrode 95 (described later) via the tenth contact hole 120. In the liquid crystal device 100, the tenth contact hole 120 is formed in the light-shielding region SD, and the scanning lines 14, common wiring 16, and the like are not recessed in a planar manner. This allows the scanning lines 14 and common wiring 16 to be made thinner, making it easy to improve the aperture ratio.

[0043] 1.4. Element substrate configuration Fig. 5 is a cross-sectional view taken along line VV in Fig. 4, which schematically shows the element substrate 10 of the liquid crystal device 100. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 4, which schematically shows the element substrate 10. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 4, which schematically shows the element substrate 10.

[0044] The element substrate 10 of the liquid crystal device 100 includes, for example, a first capacitive element 60, a second capacitive element 70, interlayer insulating layers 81, 82, 83, 84, 85, and 86, and relay electrodes 91, 92, 93, 94, and 95, as shown in FIGS.

[0045] As shown in FIGS. 5 and 6, the second capacitive element 70 is provided on the first substrate 11. In the illustrated example, a recess 11a is formed in the first substrate 11. The second capacitive element 70 is provided in the recess 11a. The second capacitive element 70 is provided between the first substrate 11 and the scanning line 14. The second capacitive element 70 has a first capacitive electrode 72, a first dielectric layer 74, and a second capacitive electrode 76.

[0046] The first capacitor electrode 72 is provided on the first substrate 11. The first dielectric layer 74 is provided on the first capacitor electrode 72. The first dielectric layer 74 is provided between the first capacitor electrode 72 and the second capacitor electrode 76. The second capacitor electrode 76 is provided on the first dielectric layer 74. The first capacitor electrode 72 and the second capacitor electrode 76 are made of, for example, conductive polysilicon. The first dielectric layer 74 is made of, for example, silicon nitride, silicon oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

[0047] The first interlayer insulating layer 81 is provided on the first substrate 11. The first interlayer insulating layer 81 is provided between the first substrate 11 and the second interlayer insulating layer 82. The first interlayer insulating layer 81 covers the second capacitive element 70. The material of the first interlayer insulating layer 81 and interlayer insulating layers 82 to 86 described below is, for example, silicon oxide or silicon nitride.

[0048] The scanning lines 14 are provided on the first interlayer insulating layer 81. The scanning lines 14 are provided between the second capacitive elements 70 and the TFTs 50. In a plan view, at least a portion of the TFTs 50 overlaps with the scanning lines 14. The scanning lines 14 are made of, for example, tungsten silicide. The scanning lines 14 block light incident on the semiconductor layers 52 of the TFTs 50 from the first substrate 11 side.

[0049] The second interlayer insulating layer 82 is provided on the first interlayer insulating layer 81. The second interlayer insulating layer 82 is provided between the first interlayer insulating layer 81 and the third interlayer insulating layer 83. The second interlayer insulating layer 82 covers the scanning lines 14.

[0050] The TFT 50 is provided on the second interlayer insulating layer 82. The TFT 50 is provided between the first substrate 11 and the common wiring 16. The TFT 50 has a semiconductor layer 52, a gate insulating layer 54, and a gate electrode 56. The TFT 50 has, for example, an LDD (Lightly Doped Drain) structure.

[0051] The semiconductor layer 52 is provided on the second interlayer insulating layer 82. In the example shown in Fig. 5, the semiconductor layer 52 extends along the Y-axis. The semiconductor layer 52 constitutes the source region, drain region, and channel formation region of the TFT 50. The material of the semiconductor layer 52 is, for example, conductive polysilicon.

[0052] The gate insulating layer 54 is provided on the semiconductor layer 52. The gate insulating layer 54 is provided between the semiconductor layer 52 and the gate electrode 56. The material of the gate insulating layer 54 is, for example, silicon oxide.

[0053] The gate electrode 56 is provided on the gate insulating layer 54. The material of the gate electrode 56 is, for example, conductive polysilicon. As shown in FIG. 6, the gate electrode 56 is electrically connected to the scanning line 14. A first contact hole 111 is formed in the second interlayer insulating layer 82. The first contact hole 111 exposes the scanning line 14. The gate electrode 56 is provided in the first contact hole 111 and is electrically connected to the scanning line 14.

[0054] As shown in FIG. 5 , the first relay electrode 91 is provided on the semiconductor layer 52. The first relay electrode 91 and the relay electrodes 91 to 95 described later are made of a material such as copper or aluminum. A second contact hole 112 is formed in the interlayer insulating layers 81 and 82. The second contact hole 112 exposes the first capacitance electrode 72 of the second capacitance element 70. The first relay electrode 91 is provided in the second contact hole 112. The semiconductor layer 52 is electrically connected to the first capacitance electrode 72 via the first relay electrode 91.

[0055] As shown in FIGS. 6 and 7, the second relay electrode 92 is provided on the semiconductor layer 52. As shown in FIG. 7, a third contact hole 113 is formed in the interlayer insulating layers 81 and 82. The third contact hole 113 exposes the second capacitance electrode 76 of the second capacitance element 70. The second relay electrode 92 is provided in the third contact hole 113. The semiconductor layer 52 is electrically connected to the second capacitance electrode 76 via the second relay electrode 92.

[0056] The third interlayer insulating layer 83 covers the TFT 50 and the relay electrodes 91 and 92. The third interlayer insulating layer 83 is provided between the second interlayer insulating layer 82 and the fourth interlayer insulating layer 84.

[0057] 5 and 6, the first capacitive element 60 is provided on the third interlayer insulating layer 83. The first capacitive element 60 is provided between the TFT 50 and the data line 15. The first capacitive element 60 has a third capacitive electrode 62, a second dielectric layer 64, and a fourth capacitive electrode 66.

[0058] The third capacitance electrode 62 is provided on the third interlayer insulating layer 83. The third capacitance electrode 62 is electrically connected to the first relay electrode 91. As shown in FIG. 5 , a fourth contact hole 114 is formed in the second interlayer insulating layer 82. The fourth contact hole 114 exposes the first relay electrode 91. The third capacitance electrode 62 is provided in the fourth contact hole 114 and is electrically connected to the first relay electrode 91. The third capacitance electrode 62 is electrically connected to the first capacitance electrode 72 via the first relay electrode 91.

[0059] The second dielectric layer 64 is provided on the third capacitor electrode 62. The second dielectric layer 64 is provided between the third capacitor electrode 62 and the fourth capacitor electrode 66. The fourth capacitor electrode 66 is provided on the second dielectric layer 64. The third capacitor electrode 62 and the fourth capacitor electrode 66 are made of a material such as conductive polysilicon. The second dielectric layer 64 is made of a material such as silicon nitride, silicon oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

[0060] The fourth interlayer insulating layer 84 covers the first capacitive element 60. The fourth interlayer insulating layer 84 is provided between the third interlayer insulating layer 83 and the fifth interlayer insulating layer 85.

[0061] The data line 15 is provided on the fourth interlayer insulating layer 84. The data line 15 is separated from the first substrate 11. The data line 15 is provided in the fourth interlayer insulating layer 84 between the TFT 50 and the common wiring 16. In the example shown in the figure, the data line 15 is provided in the fourth interlayer insulating layer 84 between the first capacitive element 60 and the common wiring 16. In the example shown in FIG. 5, the data line 15 extends along the Y-axis. The material of the data line 15 is, for example, a metal such as aluminum or titanium, or a metal compound thereof.

[0062] The data line 15 is electrically connected to the TFT 50. A fifth contact hole 115 is formed in the interlayer insulating layers 83 and 84. The fifth contact hole 115 exposes the semiconductor layer 52 of the TFT 50. The data line 15 is provided in the fifth contact hole 115 and is electrically connected to the semiconductor layer 52.

[0063] As shown in FIG. 6 , the third relay electrode 93 is provided on the fourth interlayer insulating layer 84. The third relay electrode 93 is separated from the data line 15. A sixth contact hole 116 is formed in the interlayer insulating layers 83 and 84. The sixth contact hole 116 exposes the second relay electrode 92 and the fourth capacitance electrode 66 of the first capacitance element 60. The third relay electrode 93 is provided in the sixth contact hole 116. The third relay electrode 93 is electrically connected to the second relay electrode 92 and the fourth capacitance electrode 66.

[0064] The fourth relay electrode 94 is provided on the fourth interlayer insulating layer 84. The fourth relay electrode 94 is separated from the data line 15 and the third relay electrode 93. A seventh contact hole 117 is formed in the fourth interlayer insulating layer 84. The seventh contact hole 117 exposes the third capacitor electrode 62 of the first capacitor element 60. The fourth relay electrode 94 is provided in the seventh contact hole 117. The fourth relay electrode 94 is electrically connected to the third capacitor electrode 62.

[0065] The fifth interlayer insulating layer 85 is provided on the fourth interlayer insulating layer 84. The fifth interlayer insulating layer 85 is provided between the fourth interlayer insulating layer 84 and the sixth interlayer insulating layer 86. The fifth interlayer insulating layer 85 covers the data lines 15 and the relay electrodes 93 and 94.

[0066] The common wiring 16 is provided on a fifth interlayer insulating layer 85. The common wiring 16 is separated from the first substrate 11 and the pixel electrode 12. At least a portion of the TFT 50 and at least a portion of the data line 15 overlap with the common wiring 16 in a planar view. Furthermore, at least a portion of the first capacitor element 60 and at least a portion of the second capacitor element 70 overlap with the common wiring 16 in a planar view. An eighth contact hole 118 is formed in the fifth interlayer insulating layer 85. The eighth contact hole 118 exposes the third relay electrode 93. The common wiring 16 is provided in the eighth contact hole 118 and electrically connected to the first relay electrode 91. The common wiring 16 is electrically connected to the fourth capacitor electrode 66 via the third relay electrode 93. Furthermore, the common wiring 16 is electrically connected to the second capacitor electrode 76 via the third relay electrode 93 and the second relay electrode 92.

[0067] For example, a constant potential is applied to the common wiring 16. The common wiring 16 is electrically connected to, for example, the counter electrode 44. This allows the common wiring 16 to be applied with a constant potential.

[0068] The common wiring 16 has, for example, a first layer 161, a second layer 162, a third layer 163, and a fourth layer 164. In the illustrated example, the common wiring 16 is composed of the first layer 161, the second layer 162, the third layer 163, and the fourth layer 164. In other words, in the common wiring 16, the first layer 161, the second layer 162, the third layer 163, and the fourth layer 164 are stacked.

[0069] The first layer 161 is disposed on the second layer 162. The first layer 161 is disposed between the second layer 162 and the fourth layer 164. The electrical conductivity of the first layer 161 is greater than the electrical conductivity of the second layer 162, the electrical conductivity of the third layer 163, and the electrical conductivity of the fourth layer 164. The thickness T1 of the first layer 161 is greater than the thickness T2 of the second layer 162, the thickness T3 of the third layer 163, and the thickness T4 of the fourth layer 164. This increases the electrical conductivity of the common wiring 16. The thickness of the first layer 161 is, for example, 100 nm to 1000 nm, preferably 200 nm to 500 nm, and more preferably 300 nm to 400 nm. The thickness of each layer is measured, for example, by a scanning electron microscope (SEM). The first layer 161 is, for example, an aluminum (Al) layer.

[0070] The second layer 162 is provided on the third layer 163. The second layer 162 is provided between the third layer 163 and the first layer 161. The thickness T2 of the second layer 162 is greater than the thickness T3 of the third layer 163, for example. The thickness T2 may be the same as or greater than the thickness T3. The thickness T2 of the second layer 162 is, for example, 5 nm or more and 200 nm or less, and preferably 10 nm or more and 150 nm or less.

[0071] The reflectance of the second layer 162 to the light L is smaller than the reflectance of the first layer 161 to the light L. The reflectance is measured using a spectrophotometer or the like. The second layer 162 is, for example, a titanium nitride (TiN) layer or a titanium (Ti) layer.

[0072] The third layer 163 is provided, for example, on the fifth interlayer insulating layer 85. The third layer 163 is provided between the fifth interlayer insulating layer 85 and the second layer 162. The third layer 163 is provided closer to the TFT 50 than the first layer 161 and the second layer 162. The thickness T3 of the third layer 163 is, for example, not less than 5 nm and not more than 200 nm, and preferably not less than 10 nm and not more than 150 nm.

[0073] The reflectance of the third layer 163 for light L is lower than the reflectance of the first layer 161 for light L. The second layer 162 and the third layer 163 are made of different materials. The third layer 163 is, for example, a TiN layer or a Ti layer. When the second layer 162 is a TiN layer and the third layer 163 is a Ti layer, the reflectance of the second layer 162 for light L is lower than the reflectance of the third layer 163 for light L. When the second layer 162 is a Ti layer and the third layer 163 is a TiN layer, the reflectance of the third layer 163 for light L is lower than the reflectance of the second layer 162 for light L.

[0074] The fourth layer 164 is provided on the first layer 161. The fourth layer 164 is provided between the first layer 161 and the sixth interlayer insulating layer 86. The thickness T4 of the fourth layer 164 is, for example, 5 nm or more and 200 nm or less, and preferably 10 nm or more and 150 nm or less. The reflectance of the fourth layer 164 to light L is lower than the reflectance of the first layer 161 to light L. The fourth layer 164 is, for example, a TiN layer. In the example shown in FIG. 6 , the fourth layer 164 is not provided in the eighth contact hole 118. The first layer 161, the second layer 162, and the third layer 163 are provided in the eighth contact hole 118.

[0075] The fourth layer 164 may be provided on the entire top surface of the first layer 161, or may be provided on a portion of the top surface of the first layer 161. If the fourth layer 164 is provided on only a portion of the top surface of the first layer 161, the light L can be more reflected on the top surface of the first layer 161 where the fourth layer 164 is not provided. Therefore, it is possible to suppress the light L from being absorbed in the common wiring 16 and generating heat.

[0076] It is preferable that a fourth layer 164 be provided in a region overlapping with the eighth contact hole 118 in plan view. This allows the fourth layer 164 to protect the first layer 161 in the manufacturing process of patterning the common wiring 16. Therefore, etching of the first layer 161 is suppressed, and the reliability of the electrical connection can be improved.

[0077] As shown in FIG. 6 , the fifth relay electrode 95 is provided on the fifth interlayer insulating layer 85. The fifth relay electrode 95 is separated from the common wiring 16. A ninth contact hole 119 is formed in the fifth interlayer insulating layer 85. The ninth contact hole 119 exposes the fourth relay electrode 94. The fifth relay electrode 95 is provided in the ninth contact hole 119. The fifth relay electrode 95 is electrically connected to the fourth relay electrode 94.

[0078] The fifth relay electrode 95 has, for example, a fifth layer 955, a sixth layer 956, a seventh layer 957, and an eighth layer 958. In the example shown in the figure, the fifth relay electrode 95 is composed of the fifth layer 955, the sixth layer 956, the seventh layer 957, and the eighth layer 958.

[0079] The fifth layer 955 is provided on the sixth layer 956. The fifth layer 955 is provided between the sixth layer 956 and the eighth layer 958. The fifth layer 955 is formed in the same process as the first layer 161. The thickness of the fifth layer 955 is the same as the thickness of the first layer 161. The material of the fifth layer 955 is the same as the material of the first layer 161.

[0080] The sixth layer 956 is provided on the seventh layer 957. The sixth layer 956 is provided between the seventh layer 957 and the fifth layer 955. The sixth layer 956 is formed in the same process as the second layer 162. The thickness of the sixth layer 956 is the same as the thickness of the second layer 162. The material of the sixth layer 956 is the same as the material of the second layer 162.

[0081] The seventh layer 957 is provided on the fifth interlayer insulating layer 85. The seventh layer 957 is provided between the fifth interlayer insulating layer 85 and the sixth layer 956. The seventh layer 957 is formed in the same process as the third layer 163. The thickness of the seventh layer 957 is the same as the thickness of the third layer 163. The material of the seventh layer 957 is the same as the material of the third layer 163.

[0082] The eighth layer 958 is provided on the fifth layer 955. The eighth layer 958 is provided between the fifth layer 955 and the sixth interlayer insulating layer 86. The eighth layer 958 is formed in the same process as the fourth layer 164. The thickness of the eighth layer 958 is the same as the thickness of the fourth layer 164. The material of the eighth layer 958 is the same as the material of the fourth layer 164.

[0083] The sixth interlayer insulating layer 86 is provided on the fifth interlayer insulating layer 85. The sixth interlayer insulating layer 86 covers the common wiring 16 and the fifth relay electrode 95.

[0084] As shown in FIG. 7 , the pixel electrode 12 is provided on the sixth interlayer insulating layer 86. The pixel electrode 12 is separated from the first substrate 11. A tenth contact hole 120 is formed in the sixth interlayer insulating layer 86. The tenth contact hole 120 exposes the fifth relay electrode 95. A contact 2 is provided in the tenth contact hole 120. The element substrate 10 has the contact 2. The contact 2 penetrates the sixth interlayer insulating layer 86. The fifth relay electrode 95 is connected to the pixel electrode 12 by the contact 2. The contact 2 is made of a material such as tungsten or titanium.

[0085] The element substrate 10 is manufactured using known methods that are applied to known semiconductor processes, such as low-pressure CVD (Chemical Vapor Deposition), atmospheric CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization).

[0086] 1.5. Effects The liquid crystal device 100 includes a pixel electrode 12, a common wiring 16 spaced apart from the pixel electrode 12 and including a first layer 161, a second layer 162, and a third layer 163, a TFT 50 corresponding to the pixel electrode 12 and at least a portion of which overlaps with the common wiring 16 in a planar view, and a data line 15 provided on a fourth insulating layer 84 between the TFT 50 and the common wiring 16, electrically connected to the TFT 50, and at least a portion of which overlaps with the common wiring 16 in a planar view. The second layer 162 is provided between the first layer 161 and the third layer 163 and has a lower light reflectance than the first layer 161. The third layer 163 is provided closer to the TFT 50 than the first layer 161 and the second layer 162, has a lower reflectance than the first layer 161, and is made of a different material from the second layer 162.

[0087] Therefore, in the liquid crystal device 100, even if light L is reflected by an external member such as a polarizing plate (not shown) and enters the liquid crystal device 100 as stray light from the TFT 50 side, the second layer 162 and the third layer 163 can reduce the reflection of the stray light from the common wiring 16 toward the TFT 50 side. This can prevent the semiconductor layer 52 of the TFT 50 from being excited by the stray light. This can reduce the optical leakage current. As a result, flicker can be suppressed.

[0088] In the liquid crystal device 100, for example, a constant potential is applied to the common line 16. Therefore, in the liquid crystal device 100, electromagnetic wave noise incident on the TFT 50 can be reduced.

[0089] In the liquid crystal device 100, for example, the reflectance of the second layer 162 is smaller than the reflectance of the third layer 163. Therefore, in the liquid crystal device 100, the second layer 162 can absorb more light.

[0090] In the liquid crystal device 100, for example, the reflectance of the third layer 163 is smaller than the reflectance of the second layer 162. Therefore, in the liquid crystal device 100, the third layer 163 can absorb more light.

[0091] In the liquid crystal device 100, for example, the thickness T2 of the second layer 162 is greater than the thickness T3 of the third layer 163. Therefore, in the liquid crystal device 100, the second layer 162 can absorb more light.

[0092] The liquid crystal device 100 includes, for example, a fifth interlayer insulating layer 85 as a first insulating layer covering the data line 15, a fifth relay electrode 95 provided on the fifth interlayer insulating layer 85, and a sixth interlayer insulating layer 86 as a second insulating layer provided on the fifth interlayer insulating layer 85 and covering the fifth relay electrode 95. The common line 16 is provided on the fifth interlayer insulating layer 85 and spaced apart from the fifth relay electrode 95, and the sixth interlayer insulating layer 86 covers the common line 16. The pixel electrode 12 is provided on the sixth interlayer insulating layer 86, and the fifth relay electrode 95 is connected to the pixel electrode 12 by a contact 2 that penetrates the sixth interlayer insulating layer 86. Therefore, in the liquid crystal device 100, the common line 16 can be arranged closer to the pixel electrode 12 than the TFT 50 and the data line 15.

[0093] In the liquid crystal device 100, for example, the first layer 161 is an Al layer, the second layer 162 is a TiN layer, and the third layer 163 is a Ti layer. Therefore, in the liquid crystal device 100, reflection of light from the common line 16 toward the TFT 50 can be reduced.

[0094] In the liquid crystal device 100, for example, the first layer 161 is an Al layer, the second layer 162 is a Ti layer, and the third layer 163 is a TiN layer. Therefore, in the liquid crystal device 100, reflection of light from the common line 16 toward the TFT 50 can be reduced.

[0095] 2. Electronic equipment Next, a projector 200 as an electronic device according to this embodiment will be described with reference to the drawings. Fig. 8 is a diagram for explaining the projector 200 as an electronic device according to this embodiment.

[0096] The projector 200 includes, for example, a liquid crystal device 100. The projector 200 is a liquid crystal projector.

[0097] As shown in FIG. 8, the projector 200 includes, for example, a polarized lighting device 210 arranged along the system optical axis LS, two dichroic mirrors 220 and 222 as light separation elements, three reflecting mirrors 230, 232 and 234, five relay lenses 240, 242, 244, 246 and 248, three transmissive liquid crystal light valves 250, 252 and 254 as light modulation elements, a cross dichroic prism 260 as a light combining element, and a projection lens 270.

[0098] The polarized illumination device 210 has a lamp unit 212 as a light source, which is configured from a white light source such as an extra-high pressure mercury lamp or a halogen lamp, an integrator lens 214 , and a polarization conversion element 216 .

[0099] Dichroic mirror 220 reflects red light (R) and transmits green light (G) and blue light (B) out of the polarized light beam emitted from polarized illumination device 210. Dichroic mirror 222 reflects green light (G) that has transmitted through dichroic mirror 220 and transmits blue light (B).

[0100] Red light (R) reflected by dichroic mirror 220 is reflected by reflecting mirror 230 and then passes through relay lens 248 before entering liquid crystal light valve 250. Green light (G) reflected by dichroic mirror 222 passes through relay lens 246 and enters liquid crystal light valve 252. Blue light (B) transmitted through dichroic mirror 222 passes through a light guide system made up of three relay lenses 240, 242, and 244 and two reflecting mirrors 232 and 234 and enters liquid crystal light valve 254.

[0101] Liquid crystal light valves 250, 252, and 254 are disposed opposite the respective color light incident surfaces of cross dichroic prism 260. The color light incident on liquid crystal light valves 250, 252, and 254 is modulated based on video information (video signals) and emitted toward cross dichroic prism 260.

[0102] Cross dichroic prism 260 is made by bonding four right-angle prisms together, and on their inner surfaces, a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are arranged in a cross shape. These dielectric multilayer films combine the three colored lights to generate light that represents a color image. The combined light is projected onto screen 280 by projection lens 270, which is a projection optical system, and the image is enlarged and displayed.

[0103] For example, the above-described liquid crystal device 100 is applied to the liquid crystal light valve 250. The same applies to the liquid crystal light valves 252 and 254.

[0104] In addition to the projector 200, the liquid crystal device 100 may be installed in various electronic devices such as an EVF (Electrical View Finder), a mobile mini projector, a head-up display, a smartphone, a mobile phone, a mobile computer, a digital camera, a digital video camera, a display, an in-vehicle device, an audio device, an exposure device, and a lighting device.

[0105] 3. Experimental Example The reflectance of the common wiring was calculated by simulation. For the simulation, interference spectroscopy using Fresnel's formula was used. The specific simulation software used was "Thin Film Reflectance Simulation" by Filmetrics.

[0106] Figure 9 is a diagram illustrating model M used in the simulation. As shown in Figure 9, model M is composed of an Al layer with a thickness of 350 nm, a target layer provided on the Al layer, and an SiO2 layer provided on the target layer. Light with a wavelength of 550 nm was incident from the SiO2 layer side to calculate the reflectance of the target layer.

[0107] In the simulation, the target demographic composition was varied. Figure 10 is a table showing the target demographic composition.

[0108] In Experimental Example 1, as shown in FIG. 10, the target layer was a single TiN layer, and the thickness of the TiN layer was varied within the range of 10 nm to 250 nm.

[0109] In Example 2, the target layer was a single Ti layer, and the thickness of the Ti layer was varied within the range of 10 nm to 250 nm.

[0110] In Example 3, the target layer had a laminated structure of a TiN layer and a Ti layer from the Al layer side. That is, the TiN layer was provided between the Al layer and the Ti layer. In "3-1" of Example 3, the thickness of the TiN layer was 50 nm, and the thickness of the Ti layer was varied in the range of 10 nm to 150 nm. In "3-2", the thickness of the Ti layer was 50 nm, and the thickness of the TiN layer was varied in the range of 10 nm to 150 nm. In "3-3", the thickness of the TiN layer was 100 nm, and the thickness of the TiN layer was varied in the range of 10 nm to 150 nm.

[0111] In Example 4, the target layer had a laminated structure of a Ti layer and a TiN layer from the Al layer side. That is, the Ti layer was provided between the Al layer and the TiN layer. The thickness of the Ti layer was set to 50 nm, and the thickness of the TiN layer was varied in the range of 10 nm to 150 nm.

[0112] The simulation results are shown in Figure 10. Figure 11 is a graph plotting the simulation results of Figure 10. In Figure 11, the horizontal axis represents the thickness of the layer whose thickness was changed among the target layers, and the vertical axis represents the reflectance of the target layer.

[0113] As shown in Figures 10 and 11, in the stacked structure of Example 3, it was found that the reflectivity of the target layer can be reduced by setting the thickness of the TiN layer to 50 nm or more and 100 nm or less and the thickness of the Ti layer to less than 50 nm, preferably 10 nm or less.

[0114] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0115] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0116] The following can be derived from the above-described embodiment and modifications.

[0117] One aspect of the electro-optical device is A pixel electrode; a wiring spaced apart from the pixel electrode and having a first layer, a second layer, and a third layer; a transistor corresponding to the pixel electrode and at least a portion of which overlaps with the wiring in a plan view; a data line provided in a layer between the transistor and the wiring, electrically connected to the transistor, and at least a portion of which overlaps with the wiring in a plan view; and the second layer is provided between the first layer and the third layer and has a light reflectance lower than that of the first layer; The third layer is provided closer to the transistor than the first layer and the second layer, has a lower optical reflectance than the first layer, and is made of a different material than the second layer.

[0118] This electro-optical device can reduce the optical leakage current.

[0119] In one aspect of the electro-optical device, A constant potential may be applied to the wiring.

[0120] This electro-optical device can reduce electromagnetic noise incident on the transistor.

[0121] In one aspect of the electro-optical device, The reflectance of the second layer may be less than the reflectance of the third layer.

[0122] According to this electro-optical device, the second layer can absorb more light.

[0123] In one aspect of the electro-optical device, The reflectance of the third layer may be less than the reflectance of the second layer.

[0124] According to this electro-optical device, the third layer can absorb more light.

[0125] In one aspect of the electro-optical device, The second layer may have a thickness greater than the thickness of the third layer.

[0126] According to this electro-optical device, the second layer can absorb more light.

[0127] In one aspect of the electro-optical device, a first insulating layer covering the data line; a relay electrode provided on the first insulating layer; a second insulating layer provided on the first insulating layer and covering the relay electrode; and the wiring is provided on the first insulating layer and spaced apart from the relay electrode; the second insulating layer covers the wiring; the pixel electrode is provided on the second insulating layer, The relay electrode may be connected to the pixel electrode by a contact that penetrates the second insulating layer.

[0128] According to this electro-optical device, the wiring can be arranged closer to the pixel electrode 12 than the transistors and data lines.

[0129] In one aspect of the electro-optical device, the first layer is an Al layer, the second layer is a TiN layer, The third layer may be a Ti layer.

[0130] According to this electro-optical device, it is possible to reduce the reflection of light from the wiring toward the transistor side.

[0131] In one aspect of the electro-optical device, the first layer is an Al layer, the second layer is a Ti layer, The third layer may be a TiN layer.

[0132] According to this electro-optical device, it is possible to reduce the reflection of light from the wiring toward the transistor side.

[0133] One aspect of the electronic device is This is one aspect of the electro-optical device. [Explanation of symbols]

[0134] 2...contact, 10...element substrate, 11...first substrate, 12...pixel electrode, 13...first alignment layer, 14...scanning line, 15...data line, 16...common wiring, 20...sealing material, 30...liquid crystal layer, 40...counter substrate, 41...second substrate, 42...partition portion, 43...insulating layer, 44...counter electrode, 45...second alignment layer, 50...TFT, 52...semiconductor layer, 54...gate insulating layer, 56...gate electrode, 60...first capacitance element, 62...third capacitance electrode, 64...second dielectric layer, 66...fourth capacitance electrode, 70...second capacitance element, 72...first capacitance electrode, 74...first dielectric layer, 76...second capacitance electrode, 81...first interlayer insulating layer, 82...second interlayer insulating layer, 83...third interlayer insulating layer, 84...fourth interlayer insulating layer, 85...fifth interlayer insulating layer, 86...sixth Interlayer insulating layer, 91...first relay electrode, 92...second relay electrode, 93...third relay electrode, 94...fourth relay electrode, 95...fifth relay electrode, 100...liquid crystal device, 101...external connection terminal, 102...data line driving circuit, 103...inspection circuit, 104...scanning line driving circuit, 105...wiring, 200...projector, 210...polarized lighting device, 212...lamp unit, 214...integrator lens, 216...polarization conversion element, 220, 222...dichroic mirror, 230, 232, 234...reflection mirror, 240, 242, 244, 246, 248...relay lens, 250, 252, 254...liquid crystal light valve, 260...cross dichroic prism, 270...projection lens, 280...screen

Claims

1. A pixel electrode; a wiring spaced apart from the pixel electrode and having a first layer, a second layer, and a third layer; a transistor corresponding to the pixel electrode and at least a portion of which overlaps with the wiring in a plan view; a data line provided in a layer between the transistor and the wiring, electrically connected to the transistor, and at least a portion of which overlaps with the wiring in a plan view; and the second layer is provided between the first layer and the third layer and has a light reflectance lower than that of the first layer; The third layer is provided closer to the transistor than the first layer and the second layer, has a lower optical reflectivity than the first layer, and is made of a different material than the second layer.

2. In claim 1, A constant potential is applied to the wiring.

3. In claim 1, The reflectance of the second layer is lower than the reflectance of the third layer.

4. In claim 1, The reflectance of the third layer is lower than the reflectance of the second layer.

5. In claim 3, The electro-optical device, wherein the second layer has a thickness greater than the thickness of the third layer.

6. In claim 1, a first insulating layer covering the data line; a relay electrode provided on the first insulating layer; a second insulating layer provided on the first insulating layer and covering the relay electrode; and the wiring is provided on the first insulating layer and spaced apart from the relay electrode; the second insulating layer covers the wiring; the pixel electrode is provided on the second insulating layer, The relay electrode is connected to the pixel electrode by a contact that penetrates the second insulating layer.

7. In claim 3, the first layer is an Al layer, the second layer is a TiN layer, The electro-optical device, wherein the third layer is a Ti layer.

8. In claim 4, the first layer is an Al layer, the second layer is a Ti layer, The electro-optical device, wherein the third layer is a TiN layer.

9. An electronic device comprising the electro-optical device according to claim 1 .

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