Semiconductor device and method for manufacturing semiconductor device
By using substrate contacts and via holes to redirect plasma charges and forming diodes in the substrate layer, the issue of charge accumulation in semiconductor devices is addressed, ensuring reduced damage to insulator layers and improved device reliability.
Patent Information
- Application Number
- JP2024026730
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-02-26
- Publication Date
- 2025-09-05
AI Technical Summary
Charge accumulation in semiconductor layers and floating wirings of semiconductor devices using SOI substrates leads to potential differences and risk of damage to insulator layers due to plasma irradiation, particularly in stacked wirings and floating wirings.
Incorporating substrate contacts made of conductors that electrically connect semiconductor layers or floating wirings to the substrate layer, along with via holes to redirect plasma charges, and forming diodes in the substrate layer to block excessive current flow during plasma irradiation.
Suppresses charge accumulation in semiconductor layers and floating wirings, preventing excessive potential differences and reducing damage to insulator layers, thereby enhancing the reliability of semiconductor devices.
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Abstract
Description
[Technical Field]
[0001] The disclosed technology relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]
[0002] The following techniques are known as techniques relating to semiconductor devices. For example, Patent Document 1 discloses a method for manufacturing a semiconductor substrate including a substrate layer, a first insulator layer formed on the substrate layer, a semiconductor layer formed on the first insulator layer, and an element isolation region formed on the first insulator layer so as to electrically isolate the semiconductor layer into a plurality of element formation regions, a method for forming a second insulator layer on the semiconductor layer, a method for forming a first mask layer on the second insulator layer, and a method for forming at least one first contact hole and a second contact hole that penetrate the second insulating film, the element isolation region, and the first insulator layer and reach the substrate layer by dry etching via the first mask layer. The document describes a method for manufacturing a semiconductor device, including the steps of: forming at least one second contact hole penetrating the second insulator layer to reach the element formation region, and depositing a conductive product produced by dry etching on the inner wall surfaces of the first and second contact holes and on the surface of the first mask layer to electrically connect the element formation region and the substrate layer; and forming, after the formation of the first and second contact holes, at least one third contact hole penetrating the second insulator layer to reach the element formation region at a position different from the position where the second contact hole was formed, by dry etching. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-191676 Summary of the Invention [Problem to be solved by the invention]
[0004] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1X manufactured using an SOI (Silicon On Insulator) substrate. The semiconductor device 1X has a structure in which a substrate layer 11 and a semiconductor layer 13 (also called an SOI layer) formed thereon are insulated and separated by a BOX layer 12 (Buried Oxide) made of an insulator. This structure reduces leakage current to the substrate layer 11, making it possible to suppress power consumption.
[0005] A semiconductor element such as a MOSFET is formed on the semiconductor layer 13. The semiconductor element is connected to the wiring 30 via a device contact 40. The semiconductor device 1X has a floating wiring 31 that is not electrically connected to the semiconductor layer 13. The device contact 40, the wiring 30, and the floating wiring 31 are embedded inside an insulator layer 20 that covers the surface of the semiconductor layer 13. When multiple wirings are stacked, the wirings are connected between layers by vias.
[0006] The via hole 50 is formed by etching using a plasma device and a resist mask 90. Charges 91 in the plasma flow into the semiconductor layer 13 through the via hole 50 and the device contact 40 and accumulate there. The semiconductor layer 13 is insulated from the substrate layer 11, and because there is no escape route for the charges, charge accumulation is likely to occur. As a result, the potential difference between the semiconductor layer 13 and the substrate layer 11 increases, and there is a risk of damage to the BOX layer 12 present between these layers. Like the semiconductor layer 13, the floating wiring 31 is also prone to charge accumulation due to plasma irradiation. If the area difference between the floating wiring 31 and an adjacent wiring is large, the potential difference between the two increases, and there is a risk of damage to the insulator layer 20.
[0007] The disclosed technology has been made in view of the above points, and aims to suppress the accumulation of charges in a semiconductor layer or floating wiring in a semiconductor device using an SOI substrate. [Means for solving the problem]
[0008] The semiconductor device according to the disclosed technology includes a substrate layer, a first insulator layer provided on the surface of the substrate layer, a semiconductor layer provided on the surface of the first insulator layer, a second insulator layer provided on the surface of the semiconductor layer, a plurality of wirings provided inside the second insulator layer, and a substrate contact made of a conductor that electrically connects one of the plurality of wirings to the semiconductor layer.
[0009] Another semiconductor device relating to the disclosed technology has a substrate layer, a first insulator layer provided on the surface of the substrate layer, a semiconductor layer provided on the surface of the first insulator layer, a second insulator layer provided on the surface of the semiconductor layer, a plurality of wirings provided inside the second insulator layer, and, among the plurality of wirings, floating wirings that are not electrically connected to the semiconductor layer or wirings that are electrically connected to the floating wirings, and a substrate contact made of a conductor that electrically connects the substrate layer.
[0010] A method for manufacturing a semiconductor device according to the disclosed technology includes the steps of: preparing an SOI substrate having a substrate layer, a first insulator layer provided on a surface of the substrate layer, and a semiconductor layer provided on the surface of the first insulator layer; forming a field oxide film in a partial region of the semiconductor layer; etching the field oxide film and a partial region of the first insulator layer to expose the surface of the substrate layer; implanting impurity ions into the exposed portion of the substrate layer to form a diffusion region of a conductivity type opposite to that of the substrate layer; forming a second insulator layer on the surface of the SOI substrate to cover the exposed portion of the substrate layer; forming a contact hole that penetrates the second insulator layer and reaches the diffusion region; forming a substrate contact by embedding a conductor in the contact hole; and forming wiring connected to the substrate contact on the surface of the second insulator layer. [Effects of the Invention]
[0011] According to the disclosed technique, in a semiconductor device using an SOI substrate, it is possible to suppress accumulation of charges in a semiconductor layer or floating wiring. [Brief explanation of the drawings]
[0012] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device manufactured using an SOI substrate. [Figure 2] 1 is a cross-sectional view showing an example of a configuration of a semiconductor device according to an embodiment of the disclosed technique; [Figure 3A] 10A to 10C are cross-sectional views illustrating an example of a process for forming a substrate contact and a device contact according to an embodiment of the disclosed technique. [Figure 3B] 10A to 10C are cross-sectional views illustrating an example of a process for forming a substrate contact and a device contact according to an embodiment of the disclosed technique. [Figure 4] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to another embodiment of the disclosed technology. [Figure 5] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to another embodiment of the disclosed technology. [Figure 6] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to another embodiment of the disclosed technology. [Figure 7A] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 7B] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 7C] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 7D] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 7E] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 7F] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 7G]10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 7H] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 8A] 1 is a plan view showing an example of a configuration of a semiconductor wafer including a plurality of semiconductor devices according to an embodiment of the disclosed technique; [Figure 8B] FIG. 8B is an enlarged view of the boxed area in FIG. 8A. [Figure 8C] 10 is a plan view showing an example of an arrangement of a plurality of substrate contacts included in a substrate contact block according to an embodiment of the disclosed technique. FIG. DETAILED DESCRIPTION OF THE INVENTION
[0013] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.
[0014] [First embodiment] FIG. 2 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a first embodiment of the disclosed technology. The semiconductor device 1 is manufactured using an SOI substrate 10. The SOI substrate 10 is configured by stacking a substrate layer 11, a BOX layer 12, and a semiconductor layer 13. The substrate layer 11 and the semiconductor layer 13 are each made of a semiconductor material such as silicon. The SOI substrate 10 may be manufactured by any method, such as a bonding method or a SIMOX (Silicon Implanted Oxide) method. The BOX layer 12 is an example of a "first insulator layer" in the disclosed technology.
[0015] A semiconductor element such as a MOSFET is formed on the semiconductor layer 13. A field oxide film 14 made of an insulator such as SiO2 is formed on the semiconductor layer 13. The field oxide film 14 functions as an inter-element isolation film for insulating and isolating a plurality of semiconductor elements that may be formed on the semiconductor layer 13 from one another.
[0016] The entire surface of the semiconductor layer 13 is covered with an insulator layer 20 made of an insulator such as SiO2. The insulator layer 20 is an example of a "second insulator layer" in the disclosed technology. A plurality of wirings 30 made of a conductor such as Al are provided inside the insulator layer 20. While FIG. 2 shows the wirings 30 provided in the lowest wiring layer, the semiconductor device 1 may have a plurality of wirings stacked within the insulator layer 20.
[0017] The semiconductor device 1 has a device contact 40 made of a conductor that electrically connects any one of the multiple wirings 30 to the semiconductor layer 13 (semiconductor element). The device contact 40 is made of a conductor such as tungsten, and one end is connected to the semiconductor layer 13 (semiconductor element) and the other end is connected to the wiring 30.
[0018] The semiconductor device 1 has a substrate contact 41 made of a conductor that electrically connects the wiring 30 electrically connected to the semiconductor layer 13 and the substrate layer 11. The substrate contact 41 is made of a conductor such as tungsten, and has one end connected to the wiring 30 electrically connected to the semiconductor layer 13 and the other end connected to the substrate layer 11. The wiring 30 electrically connected to the semiconductor layer 13 extends above the field oxide film 14, and the substrate contact 41 is connected to the portion of the wiring 30 that extends above the field oxide film 14. The substrate contact 41 penetrates the field oxide film 14 and the BOX layer 12 and reaches the substrate layer 11. The semiconductor device 1 may have a substrate contact block 42 in which a plurality of substrate contacts 41 are densely packed.
[0019] A via hole 50 is formed in a portion of the insulator layer 20 that covers the surface of the wiring 30. The via hole 50 is formed by plasma etching using a patterned resist mask 90. Charges (holes or electrons) 91 in the plasma flow into the substrate layer 11 via the wiring 30 electrically connected to the semiconductor layer 13 and the substrate contact 41. This suppresses the flow of the charges 91 into the semiconductor layer 13, and suppresses the accumulation of the charges 91 in the semiconductor layer 13. As a result, the potential difference between the semiconductor layer 13 and the substrate layer 11 is prevented from becoming excessive, thereby reducing the risk of the BOX layer 12 being destroyed.
[0020] 3A and 3B, the substrate contact 41 and the device contact 40 are formed through the steps of forming contact holes 61 and 60, respectively. Since the contact hole 61 for forming the substrate contact 41 is deeper than the contact hole 60 for forming the device contact 40, if the diameter D1 of the substrate contact 41 is equal to the diameter D2 of the device contact 40, the etching rate may decrease at the bottom of the contact hole 61, as shown in FIG. 3A, which may result in an opening defect in which the contact hole 61 does not reach the substrate layer 11.
[0021] Therefore, it is preferable that the diameter D1 of the substrate contact 41 be larger than the diameter D2 of the device contact 40. This reduces the risk of an opening defect, in which the contact hole 61 for forming the substrate contact 41 does not reach the substrate layer 11, as shown in FIG. 3B. It is preferable that the diameter D1 of the substrate contact 41 be 1.5 times or more the diameter D2 of the device contact 40. The diameter D2 of the device contact 40 may be, for example, 0.2 μm, and the diameter D1 of the substrate contact 41 may be, for example, 0.3 μm.
[0022] [Second embodiment] 4 is a cross-sectional view showing an example of the configuration of a semiconductor device 1A according to a second embodiment of the disclosed technology. The semiconductor device 1A has, in the lowest wiring layer, a floating wiring 31 that is not electrically connected to the semiconductor layer 13 (semiconductor element). The semiconductor device 1A has a substrate contact 41 made of a conductor that electrically connects the floating wiring 31 and the substrate layer 11. The substrate contact 41 is made of a conductor such as tungsten, and has one end connected to the floating wiring 31 and the other end connected to the substrate layer 11. The floating wiring 31 extends above the field oxide film 14, and the substrate contact 41 is connected to a portion of the floating wiring 31 that extends above the field oxide film 14. The substrate contact 41 penetrates the field oxide film 14 and the BOX layer 12 to reach the substrate layer 11.
[0023] A via hole 50 is formed in a portion of the insulator layer 20 that covers the surface of the floating wiring 31. The via hole 50 is formed by plasma etching using a patterned resist mask 90. Charges 91 in the plasma flow into the substrate layer 11 via the floating wiring 31 and the substrate contact 41. This suppresses the inflow of charges 91 into the floating wiring 31, and suppresses the accumulation of charges 91 in the floating wiring 31. As a result, the potential difference between the floating wiring 31 and other adjacent wirings is prevented from becoming excessive, thereby reducing the risk of damage to the insulator layer 20.
[0024] 5, when the floating wiring 31 is provided in a wiring layer other than the lowest layer, the floating wiring 31 is electrically connected to the wiring 30 in the lowest layer through a via 70. One end of the substrate contact 41 is connected to the wiring 30 in the lowest layer that is electrically connected to the floating wiring 31, and the other end is connected to the substrate layer 11. Charge 91 in the plasma flows into the substrate layer 11 via the floating wiring 31, the wiring 30 in the lowest layer, and the substrate contact 41.
[0025] In addition, the semiconductor device 1 may include both a substrate contact 41 that electrically connects the floating wiring 31 and the substrate layer 11, and a substrate contact 41 (see Figure 2) that electrically connects the wiring electrically connected to the semiconductor layer 13 and the substrate layer 11.
[0026] [Third embodiment] 6 is a cross-sectional view showing an example of the configuration of a semiconductor device 1B according to a third embodiment of the disclosed technology. In the semiconductor device 1, a region of the substrate layer 11 to which the substrate contact 41 is connected has a diffusion region 15 made of a semiconductor of the opposite conductivity type to the substrate layer 11 body. That is, when the substrate layer 11 body is of N-type conductivity, the diffusion region 15 has a P-type conductivity, and when the substrate layer 11 body is of P-type conductivity, the diffusion region 15 has an N-type conductivity. Since the substrate layer 11 has the diffusion region 15 of the opposite conductivity type to the substrate layer 11 body, a PN junction is formed in the substrate layer 11, thereby forming a diode in the substrate layer 11. That is, the substrate contact 41 is connected to the diode formed in the substrate layer 11.
[0027] This diode is formed in a direction that provides a reverse bias with respect to the voltage generated during plasma irradiation and the voltage applied to the wiring 30 to which the substrate contact 41 is connected. This makes it possible to block current flowing into the substrate layer 11 through the substrate contact 41 during plasma irradiation and when a voltage is applied to the wiring 30 to which the substrate contact 41 is connected. If the voltage generated during plasma irradiation becomes excessive and exceeds the withstand voltage of the diode, an overcurrent may occur, but most of this overcurrent will flow into the substrate layer 11, so the semiconductor element formed in the semiconductor layer 13 will be protected.
[0028] 7A to 7H are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1 B. First, an SOI substrate 10 is prepared, which is configured by laminating a substrate layer 11, a BOX layer 12, and a semiconductor layer 13 (FIG. 7A).
[0029] Next, a field oxide film 14 is formed in a partial region of the semiconductor layer 13 using a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a deep trench isolation (DTI) method (FIG. 7B).
[0030] Next, using a known etching technique, the portions of the field oxide film 14 and the BOX layer where the diffusion region 15 is to be formed are etched to expose the surface of the substrate layer 11 in those portions (FIG. 7C).
[0031] Next, impurity ions are implanted into the exposed portion of the substrate layer 11 to form a diffusion region 15 of a conductivity type opposite to that of the main body of the substrate layer 11. If the substrate layer 11 is N-type, a P-type diffusion region 15 is formed by using, for example, boron as the impurity ion. If the substrate layer 11 is P-type, an N-type diffusion region 15 is formed by using, for example, phosphorus or arsenic as the impurity ion (FIG. 7D).
[0032] Next, using a CVD (Chemical Vapor Deposition) method, an insulator layer 20 made of an insulator such as SiO 2 is formed on the entire surface of the SOI substrate 10 so as to cover the exposed portion of the substrate layer 11 (FIG. 7E).
[0033] Next, a plurality of contact holes 61 are formed through the insulating layer 20 and reach the diffusion regions 15 using a known etching technique (FIG. 7F).
[0034] Next, a conductive material such as tungsten is embedded in each of the contact holes 61 using evaporation, sputtering, or CVD to form a plurality of substrate contacts 41. A substrate contact block 42 including the plurality of substrate contacts 41 is formed (FIG. 7G).
[0035] Next, a conductive film connected to the substrate contact 41 is formed on the surface of the insulator layer 20 using evaporation, sputtering, or CVD, and then this conductive film is patterned using photolithography to form the wiring 30 (FIG. 7H). This wiring 30 is electrically connected to the diffusion region 15 via the substrate contact 41 and is also electrically connected to the semiconductor layer 13 via a device contact (not shown). Note that the wiring 30 may be a floating wiring that is not electrically connected to the semiconductor layer 13 or a wiring electrically connected to a floating wiring.
[0036] [Fourth embodiment] 8A is a plan view showing an example of the configuration of a semiconductor wafer 2 including a plurality of semiconductor devices 1, 1A, or 1B according to the first to third embodiments described above. Each of the plurality of semiconductor devices 1 is separated into individual pieces by cutting along scribe lines 3. FIG. 8B is an enlarged view of a region A enclosed by a square in FIG. 8A.
[0037] As shown in Fig. 8B, the substrate contact block 42 included in each of the plurality of semiconductor devices 1 in the semiconductor wafer 2 is provided on the scribe line 3. Fig. 8C is a plan view showing an example of an arrangement of the plurality of substrate contacts 41 included in the substrate contact block 42. Fig. 8C illustrates a substrate contact block 42 made up of 400 substrate contacts 41 arranged in a 20 row x 20 column grid pattern.
[0038] For example, if the number of semiconductor devices 1 (semiconductor chips) provided on one semiconductor wafer 2 is 50, the number of substrate contact blocks 42 provided on one semiconductor device 1 is 10, and the number of substrate contacts 41 included in one substrate contact block 42 is 400, the number of substrate contacts 41 provided on one semiconductor wafer 2 will be 200,000, which is sufficient to achieve the effect of flowing the charge in the plasma into the substrate layer 11.
[0039] If a large number of substrate contacts 41 are provided inside the semiconductor device 1 (semiconductor chip), the area of the semiconductor device 1 (semiconductor chip) increases, reducing the number of semiconductor devices 1 that can be formed on one semiconductor wafer 2 and resulting in increased costs. By providing the substrate contacts 41 on the scribe lines 3, it is possible to avoid an increase in the area of the semiconductor device 1 that would accompany the introduction of the substrate contacts 41. The substrate contacts 41 are cut when the semiconductor device 1 is separated into individual pieces, but this does not pose a problem as they do not contribute to the original function of the semiconductor device 1. It is also possible to provide the substrate contacts 41 inside the semiconductor device 1 (semiconductor chip).
[0040] The following additional notes are disclosed regarding the first to fourth embodiments described above. (Appendix 1) a substrate layer; a first insulating layer provided on a surface of the substrate layer; a semiconductor layer provided on a surface of the first insulator layer; a second insulator layer provided on the surface of the semiconductor layer; a plurality of wirings provided inside the second insulator layer; The semiconductor device has a wiring electrically connected to the semiconductor layer among the plurality of wirings, and a substrate contact made of a conductor electrically connecting the wiring to the substrate layer.
[0041] (Appendix 2) a substrate layer; a first insulating layer provided on a surface of the substrate layer; a semiconductor layer provided on a surface of the first insulator layer; a second insulator layer provided on the surface of the semiconductor layer; a plurality of wirings provided inside the second insulator layer; a substrate contact made of a conductor that electrically connects a floating wiring that is not electrically connected to the semiconductor layer or a wiring that is electrically connected to the floating wiring among the plurality of wirings to the substrate layer; A semiconductor device having:
[0042] (Appendix 3) a device contact made of a conductor that electrically connects any one of the plurality of wirings to the semiconductor layer; The diameter of the substrate contact is larger than the diameter of the device contact. 10. The semiconductor device according to claim 1 or 2.
[0043] (Appendix 4) A region of the substrate layer to which the substrate contact is connected is a semiconductor of a first conductivity type, and another region of the substrate layer is a semiconductor of a conductivity type opposite to the first conductivity type. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.
[0044] (Appendix 5) A plurality of the substrate contacts are provided along scribe lines on a semiconductor wafer including the semiconductor device. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film.
[0045] (Appendix 6) providing an SOI substrate having a substrate layer, a first insulator layer provided on a surface of the substrate layer, and a semiconductor layer provided on a surface of the first insulator layer; forming a field oxide film on a partial region of the semiconductor layer; etching the field oxide film and a portion of the first insulator layer to expose a surface of the substrate layer; implanting impurity ions into the exposed portion of the substrate layer to form a diffusion region of a conductivity type opposite to that of the substrate layer; forming a second insulator layer on the surface of the SOI substrate to cover the exposed portion of the substrate layer; forming a contact hole that penetrates the second insulating layer and reaches the diffusion region; forming a substrate contact by filling the contact hole with a conductor; forming wiring connected to the substrate contact on a surface of the second insulator layer; A method for manufacturing a semiconductor device comprising: [Explanation of symbols]
[0046] 1, 1A, 1B, 1X Semiconductor Devices 2. Semiconductor wafers 3 Scribe line 10 SOI substrate 11 Substrate Layer 12 BOX layers 13 Semiconductor layer 14 Field oxide 15 Diffusion Area 20 Insulator layer 30 Wiring 31 Floating wiring 40 Device Contacts 41 PCB Contact 42 PCB contact block
Claims
1. a substrate layer; a first insulating layer provided on a surface of the substrate layer; a semiconductor layer provided on a surface of the first insulator layer; a second insulator layer provided on a surface of the semiconductor layer; a plurality of wirings provided inside the second insulator layer; a substrate contact made of a conductor electrically connecting a wiring electrically connected to the semiconductor layer and the substrate layer among the plurality of wirings; A semiconductor device having:
2. a substrate layer; a first insulating layer provided on a surface of the substrate layer; a semiconductor layer provided on a surface of the first insulator layer; a second insulator layer provided on a surface of the semiconductor layer; a plurality of wirings provided inside the second insulator layer; a substrate contact made of a conductor that electrically connects a floating wiring that is not electrically connected to the semiconductor layer or a wiring that is electrically connected to the floating wiring among the plurality of wirings to the substrate layer; A semiconductor device having:
3. a device contact made of a conductor that electrically connects any one of the plurality of wirings to the semiconductor layer; The diameter of the substrate contact is larger than the diameter of the device contact.
3. The semiconductor device according to claim 1.
4. A region of the substrate layer to which the substrate contact is connected is a semiconductor of a first conductivity type, and another region of the substrate layer is a semiconductor of a conductivity type opposite to the first conductivity type.
3. The semiconductor device according to claim 1.
5. A plurality of the substrate contacts are provided along scribe lines on a semiconductor wafer including the semiconductor device.
3. The semiconductor device according to claim 1.
6. preparing an SOI substrate having a substrate layer, a first insulator layer provided on a surface of the substrate layer, and a semiconductor layer provided on a surface of the first insulator layer; forming a field oxide film on a partial region of the semiconductor layer; etching the field oxide film and a portion of the first insulator layer to expose a surface of the substrate layer; implanting impurity ions into the exposed portion of the substrate layer to form a diffusion region of a conductivity type opposite to that of the substrate layer; forming a second insulator layer on the surface of the SOI substrate so as to cover the exposed portion of the substrate layer; forming a contact hole that penetrates the second insulating layer and reaches the diffusion region; forming a substrate contact by filling the contact hole with a conductor; forming wiring connected to the substrate contact on a surface of the second insulator layer; A method for manufacturing a semiconductor device comprising:
Citation Information
Patent Citations
Method of manufacturing semiconductor device
JP2013191676A