Communication device, communication system, and communication method

Abstract

To make communication data flexible when communication speed in asynchronous serial communication is adjusted.SOLUTION: A communication device includes: a timing unit that measures a first time indicating the duration of a first signal level and a second time indicating the duration of a second signal level in communication data input from an opposing device; a counting unit that counts a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level; a selection unit that selects either the first time or the second time based on the first number and the second number; and an adjustment unit that adjusts communication speed in asynchronous serial communication with the opposing device based on either the first time or the second time in accordance with the selection result.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The disclosed technology relates to a communication device, a communication system, and a communication method. [Background technology]

[0002] Patent Document 1 states that "when a communication connection is established, the time of the low level section within one frame of the UART signal transmitted from the communication partner device 2 is measured, and the baud rate is calculated based on the measurement result." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-091742 Summary of the Invention [Problem to be solved by the invention]

[0004] Asynchronous serial communication (also known as start-stop synchronization) is known, which communicates with a counterpart device without using a clock signal. In such asynchronous serial communication, fluctuations in the baud rate can cause communication errors with the counterpart device. Patent Document 1 discloses a technique for measuring the time of a low-level interval and adjusting the communication speed based on the measurement results. However, the technique in Patent Document 1 is based on the premise of using a predefined bit pattern, such that the start bit interval is low, the stop bit interval is high, and the interval between the start bit and the stop bit is low, resulting in a problem of lack of flexibility.

[0005] Therefore, an object of the present disclosure is to provide a communication device, a communication system, and a communication method that can provide flexibility to communication data when adjusting the communication speed in asynchronous serial communication. [Means for solving the problem]

[0006] The communication device of the present disclosure includes a timing unit that measures a first time indicating the duration of a first signal level and a second time indicating the duration of a second signal level in communication data input from an opposing device; a counting unit that counts a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level; a selection unit that selects either the first time or the second time based on the first number and the second number; and an adjustment unit that adjusts the communication speed in asynchronous serial communication with the opposing device based on either the first time or the second time in accordance with the selection result.

[0007] The communication system of the present disclosure includes a communication device and an opposing device, the communication device including: a timing unit that measures a first time indicating the duration of a first signal level and a second time indicating the duration of a second signal level in communication data input from the opposing device; a counting unit that counts a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level; a selection unit that selects either the first time or the second time based on the first number and the second number; and an adjustment unit that adjusts a communication speed in asynchronous serial communication with the opposing device based on either the first time or the second time in accordance with the selection result; and the opposing device.

[0008] The communication method disclosed herein includes a computer measuring a first time indicating the duration of a first signal level and a second time indicating the duration of a second signal level in communication data input from an opposing device, counting a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level, selecting either the first time or the second time based on the first number and the second number, and adjusting the communication speed in asynchronous serial communication with the opposing device based on either the first time or the second time according to the selected result. [Effects of the Invention]

[0009] The present disclosure advantageously provides a communication device, a communication system, and a communication method that can provide flexibility to communication data when adjusting the communication speed in asynchronous serial communication. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating an example of a schematic configuration of a communication system 10 according to the present embodiment. [Figure 2] 1 is a diagram showing an example of a hardware configuration of a communication device 100′ according to a comparative example, together with an associated device 200. FIG. [Figure 3] 10 is a diagram showing a schematic diagram of a baud rate fluctuation accompanying fluctuations in a clock CLK. FIG. [Figure 4] 1 is a diagram illustrating an example of a functional configuration of a communication device 100 according to the present embodiment. [Figure 5] 1 is a diagram showing an example of a hardware configuration of a communication device 100 according to the present embodiment, together with an associated device 200. FIG. [Figure 6] 10A and 10B are diagrams illustrating examples of various waveforms and values ​​when the communication device 100 according to the present embodiment adjusts the communication speed. DETAILED DESCRIPTION OF THE INVENTION

[0011] An example of an embodiment of the technology of the present disclosure will be described below with reference to the drawings. Note that the same reference numerals are used to designate identical or equivalent components and parts in each drawing. Furthermore, the dimensional proportions of the drawings may be exaggerated for the sake of explanation and may differ from the actual proportions.

[0012] 1 is a diagram showing an example of a schematic configuration of a communication system 10 according to this embodiment. The communication system 10 includes a communication device 100 and an associated device 200.

[0013] The communication device 100 is a device that communicates with the other device 200. The communication device 100 may be, for example, a microcomputer. However, the communication device 100 is not limited to this. The communication device 100 may be any computer that can communicate with the other device 200.

[0014] The counterpart device 200 is a device that communicates with the communication device 100. As an example, the counterpart device 200 may be a microcomputer different from the communication device 100. However, the counterpart device 200 is not limited to this. The counterpart device 200 may be any peripheral device that can exist outside the communication device 100, such as an external sensor or an external memory.

[0015] In the communication system 10, the communication device 100 and the counterpart device 200 communicate via asynchronous serial communication. Hereinafter, a case where the asynchronous serial communication is UART (Universal Asynchronous Receiver Transmitter) will be described as an example. UART is preferable because it is one of the most convenient and easy-to-use communication methods. However, this is not limiting. The communication device 100 and the counterpart device 200 may communicate via any asynchronous serial communication method, such as LIN (Local Interconnect Network).

[0016] In asynchronous serial communication, the port that transmits data is called Tx, and the port that receives data is called Rx. Data is transmitted and received from the transmitter's Tx to the receiver's Rx. In this diagram, the UART on the communication device 100 side is called UART_A, and the UART on the other device 200 side is called UART_B, and communication data A is transmitted from the Tx of UART_A to the Rx of UART_B, and communication data B is transmitted from the Tx of UART_B to the Rx of UART_A.

[0017] The UART data format includes a start bit, data bits, a parity bit, and a stop bit. The start bit is a bit that signals the start of data and consists of one bit. The data bits indicate data and can be set to any number between five and eight bits. The parity bit is a bit that detects data errors and consists of one bit. By adding the parity bit, if any bit in the data changes during transfer, a discrepancy will occur between the number of "1" bits in the data and the value of the parity bit, allowing the receiving side to notice the data error. The stop bit is a bit that signals the end of data and consists of one or two bits.

[0018] In order for a transmitter and receiver to communicate, they must synchronize the timing of sending and receiving data. In synchronous systems, data is sent and received in synchronization with a clock signal, but in asynchronous systems, no clock signal is used; instead, the transmitter and receiver each generate a clock internally, and send and receive data in synchronization with the internal clocks they each generate.

[0019] Therefore, it is necessary to match the baud rates between the transmitter and receiver. However, the internal clocks used to set the baud rates are asynchronous between the transmitter and receiver. Therefore, if the frequency of the internal clock fluctuates, the baud rate will fluctuate, causing a mismatch in the baud rates between the transmitter and receiver, which may result in communication errors. The technology disclosed herein makes it possible to provide flexibility to communication data when adjusting the communication speed to accommodate such baud rate fluctuations.

[0020] 2 is a diagram showing an example of a hardware configuration of a communication device 100′ according to a comparative example, together with an associated device 200. The communication device 100′ according to the comparative example includes a clock generation circuit 110, a baud rate setting register 120, and a baud rate generation counter 130.

[0021] The clock generation circuit 110 is a circuit that generates a clock CLK. The baud rate setting register 120 is a register that registers a value for setting a baud rate. The baud rate generation counter 130 is a counter that counts a value for generating a baud rate.

[0022] Here, the baud rate setting register 120 may register the number of cycles of the clock CLK per bit. More specifically, the baud rate setting register 120 may register a value indicating how many cycles of the clock CLK generated by the clock generation circuit 110 are set to one bit. The baud rate generation counter 130 may read the register value of the baud rate setting register 120 and count the number of cycles of the clock CLK generated by the clock generation circuit 110. Then, when the count value of the baud rate generation counter 130 matches the register value of the baud rate setting register 120, the baud rate generation counter 130 may overflow. In this way, the time from when the baud rate generation counter 130 starts counting until it overflows is the time per bit (also referred to as "one bit time"). The baud rate can be expressed, for example, as the reciprocal of one bit time.

[0023] 3 is a diagram showing a typical variation in the baud rate in response to variations in the clock CLK. From the top to the bottom, the diagram shows (X) a case where the frequency of the clock CLK is normal, (Y) a case where the frequency of the clock CLK increases, and (Z) a case where the frequency of the clock CLK decreases. In all of the cases (X), (Y), and (Z), the register value of the baud rate setting register 120 is assumed to be constant (here, 3).

[0024] In this diagram, comparing (X) and (Y), we can see that in the case of (Y), where the clock CLK frequency is high, the 1-bit time is shorter than in the case of (X). Therefore, it can be said that the baud rate is higher in the case of (Y) than in the case of (X). Furthermore, comparing (X) and (Z), we can see that in the case of (Z), where the clock CLK frequency is low, the 1-bit time is longer than in the case of (X). Therefore, it can be said that the baud rate is lower in the case of (Z) than in the case of (X).

[0025] Here, if the baud rate is set to synchronize with the case (X) where the frequency of the clock CLK in the opposite device 200 is normal, when the frequency of the clock CLK in the communication device 100 fluctuates as in the cases (Y) and (Z), a mismatch in the baud rate occurs between the communication device 100′ and the opposite device 200. As a result, an abnormality may occur in communication between the communication device 100′ and the opposite device 200.

[0026] In the above description, it has been explained that a baud rate mismatch occurs when the frequency of the clock CLK is normal in the opposite device 200 but the frequency of the clock CLK fluctuates in the communication device 100'. However, a baud rate mismatch also occurs when the frequency of the clock CLK is normal in the communication device 100' but the frequency of the clock CLK fluctuates in the opposite device 200, or when the frequency of the clock CLK fluctuates in both the communication device 100' and the opposite device 200. The communication device 100 according to this embodiment makes it possible to provide flexibility to communication data when adjusting the communication speed to accommodate such baud rate fluctuations.

[0027] FIG. 4 is a diagram showing an example of the functional configuration of a communication device 100 according to this embodiment. This diagram is merely an example of the functional configuration, and the communication device 100 may not include all of the components shown in this diagram, or may include other components not shown in this diagram. Furthermore, the configuration in this diagram is a functionally separated functional block and may differ from the actual device or apparatus configuration. In other words, even if a single block is shown in this diagram, this block does not necessarily have to be composed of a single device or apparatus. Similarly, even if multiple blocks are shown in this diagram, these multiple blocks do not necessarily have to be composed of separate devices or apparatuses.

[0028] The communication device 100 according to this embodiment includes a timer 101, a counting unit 102, a determination unit 103, a selection unit 104, a calculation unit 105, and an adjustment unit 106. These functional components may be implemented by dedicated hardware. Alternatively, these functional components may be implemented by a computer in which a processor reads a communication program from a ROM or storage and executes the program using a RAM as a work area.

[0029] The timing unit 101 measures a first time indicating the duration of a first signal level and a second time indicating the duration of a second signal level in communication data B input from the opposite device 200. As an example, the first signal level may be a high level (hereinafter referred to as an "H level"), and the second signal level may be a low level (hereinafter referred to as an "L level").

[0030] The counter 102 counts a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level.

[0031] The determining unit 103 determines whether to enable the first signal level or the second signal level based on the first number and the second number.

[0032] The selection unit 104 selects either the first time or the second time based on the first number and the second number. More specifically, the selection unit 104 may select either the first time or the second time in accordance with the result determined by the determination unit 103.

[0033] The calculation unit 105 divides either the first time period or the second time period by a set value according to the result selected by the selection unit 104. The set value will be described later.

[0034] The adjustment unit 106 adjusts the communication speed in the asynchronous serial communication with the opposing device 200 based on either the first time or the second time, in accordance with the result selected by the selection unit 104. More specifically, the adjustment unit 106 may adjust the communication speed in accordance with the result of the division performed by the calculation unit 105.

[0035] 5 is a diagram showing an example of the hardware configuration of the communication device 100 according to this embodiment, together with the counterpart device 200. In this diagram, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. The communication device 100 according to this embodiment further includes a first clock counter 141, a second clock counter 142, a first counting counter 151, a second counting counter 152, a bit number setting register 160, a determination circuit 170, a selector 180, and a division circuit 190.

[0036] The first time counter 141 measures a first time indicating the duration of a first signal level in the communication data B input from the opposite device 200. For example, the first time counter 141 may be a counter having an enable terminal. The communication data B transmitted from Tx of the opposite device 200 and input to Rx of the communication device 100 may be branched and input to the enable terminal. The first time counter 141 may then count the number of cycles of the clock CLK during the period in which the signal level of the communication data B is H level.

[0037] The second time counter 141 measures a second time indicating the duration of a second signal level in the communication data B input from the opposite device 200. For example, the second time counter 142 may be a counter having an enable terminal, similar to the first time counter 141. The communication data B transmitted from Tx of the opposite device 200 and input to Rx of the communication device 100 may be branched and input to the enable terminal. The second time counter 142 may then count the number of cycles of the clock CLK during the period in which the signal level of the communication data B is at L level.

[0038] The count value counted by the first time counter 141 and the count value counted by the second time counter 142, i.e., the first time and the second time, may be supplied to the selector 180. When implemented by dedicated hardware, the time counter unit 101 may be configured by, for example, such a first time counter 141 and second time counter 142.

[0039] The first counting counter 151 counts the number of bits of a first signal level in the communication data B input from the opposite device 200. For example, the first counting counter 151 may increment the count value by one if the signal level of the communication data B is H level when the communication data B is received at a predetermined timing.

[0040] The second counting counter 152 counts the number of bits of the second signal level in the communication data B input from the opposite device 200. For example, the second counting counter 152 may increment the count value by one if the signal level of the communication data B is an L level when the communication data B is received at a predetermined timing.

[0041] The count value counted by the first counter 151 and the count value counted by the second counter 152, i.e., the first number and the second number, may be supplied to the determination circuit 170. When implemented by dedicated hardware, the counting unit 102 may be configured by, for example, such a first counter 151 and second counter 152.

[0042] The timing for capturing communication data B may be set, for example, to the center of one bit time. As an example, assume that the register value of the baud rate setting register 120 is set to 99. In this case, the number of clock CLK cycles per bit is 99. Therefore, communication data B may be captured at the timing when the number of clock CLK cycles reaches 50.

[0043] The bit count setting register 160 is a register that registers a setting value for setting the number of valid bits to adjust the communication speed. This setting value may be a value less than the number of bits contained in one frame of communication data B. As an example, assume that the asynchronous serial communication is UART and communication data B includes one start bit, eight data bits, one parity bit, and one stop bit. In this case, the setting value may be a value less than 11. In particular, if the baud rates are inconsistent, baud rate discrepancies may accumulate in the latter half of the frame, resulting in the capture of the bit just before or just after the intended bit. Therefore, the setting value should be less than half the number of bits contained in one frame so that determination can be made in the first half of the frame. Here, the setting value is assumed to be 3.

[0044] The determination circuit 170 reads the set value of the bit number setting register 160 and compares it with the count value counted by the first counter 151 and the count value counted by the second counter 152, i.e., the first number and the second number, respectively, and determines whether the first signal level or the second signal level is to be enabled based on the comparison result.

[0045] More specifically, the determination circuit 170 may determine that the first signal level is enabled if the first number reaches the set value before the second number, and may determine that the second signal level is enabled if the second number reaches the set value before the first number. The determination circuit 170 supplies the result of the determination, i.e., a signal indicating whether the first signal level or the second signal level is enabled, to the selector 180. When realized by dedicated hardware, the determination unit 103 may be configured by, for example, such a bit number setting register 160 and the determination circuit 170.

[0046] The selector 180 selects either the first time or the second time in response to a signal from the determination circuit 170. For example, when the signal from the determination circuit 170 indicates that the first signal level is to be enabled, the selector 180 may supply the count value of the first time counter 141, i.e., the first time, to the division circuit 190. On the other hand, when the signal from the determination circuit 170 indicates that the second signal level is to be enabled, the selector 180 may supply the count value of the second time counter 142, i.e., the second time, to the division circuit 190. When realized by dedicated hardware, the selection unit 104 may be configured by, for example, such a selector 180.

[0047] The division circuit 190 divides either the first time or the second time by a set value according to the result selected by the selector 180. For example, when the count value of the first time counter 141 is supplied from the selector 180, the division circuit 190 may divide the count value by the set value of the number-of-bits setting register 160. On the other hand, when the count value of the second time counter 142 is supplied from the selector 180, the division circuit 190 may divide the count value by the set value of the number-of-bits setting register 160. The division circuit 190 may then supply the result of the calculation, i.e., the quotient, to the baud rate setting register 120. When implemented by dedicated hardware, the calculation unit 105 may be configured by, for example, such a division circuit 190.

[0048] Then, the baud rate setting register 120 changes the register value to be registered based on the quotient obtained by the division by the division circuit 190. This changes the number of clock cycles per bit, thereby adjusting the baud rate. When implemented by dedicated hardware, the adjustment unit 106 may be, for example, such a baud rate setting register 120. For example, the adjustment unit 106 may adjust the communication speed by adjusting the number of clock CLK cycles per bit in asynchronous serial communication in accordance with the result of division by the calculation unit 105 in this way. Such communication speed adjustment will be described in detail using waveforms and values.

[0049] 6 is a diagram showing an example of various waveforms and values ​​when the communication device 100 according to this embodiment adjusts the communication speed. In this diagram, from the top, the count value of the baud rate generation counter 130, the count value of the first clock counter 141, the count value of the second clock counter 142, the count value of the first counter 151, the count value of the second counter 152, communication data B, the timing of capturing communication data B, the register initial value of the baud rate setting register 120, and the register value of the baud rate setting register 120 are shown, and the horizontal axis represents time.

[0050] In addition, in this figure, the setting value registered in the bit number setting register 160 is set to 3 as an example.

[0051] Also, in this figure, the baud rate of the opposite device 200 is about 5% faster than the baud rate of the communication device 100, so when 3 bits of L level are received, the register value of the baud rate setting register 120 is adjusted from the initial value of 99 to 94 as an example.

[0052] Also, in this figure, an example is shown in which communication data B has start bit=L level, data bit 1=L level, data bit 2=H level, data bit 3=L level, data bit 4=H level, data bit 5=H level, data bit 6=L level, data bit 7=H level, data bit 8=L level, parity bit=L level, and stop bit=H level.

[0053] Here, when the start bit goes low, the second time counter 142 starts counting the number of cycles of the clock CLK. Then, at the first capture timing, the second count counter 152 increments its count value to 1 because the signal level of the captured communication data B is low. At this point, the first number is 0 and the second number is 1, and neither number has reached the setting value of 3 in the bit number setting register 160, so the determination circuit 170 does not enable adjustment of the communication speed.

[0054] Next, at the second capture timing, the second counting counter 152 increments the count value to 2 because the signal level of the captured communication data B is L level. At this point in time, the first number is 0 and the second number is 2, and neither has reached the set value of 3, so the determination circuit 170 does not enable adjustment of the communication speed.

[0055] Next, when data bit 2 goes high, the second clock counter 142 stops counting the number of cycles of the clock CLK. Meanwhile, the first clock counter 141 starts counting the number of cycles of the clock CLK. Then, at the third capture timing, the first counter 151 increments its count value to 1 because the signal level of the captured communication data B is high. At this point in time, the first number is 1 and the second number is 2, and neither has reached the set value of 3, so the determination circuit 170 does not enable adjustment of the communication speed.

[0056] Next, when data bit 3 goes low, the first clock counter 141 stops counting the number of cycles of the clock CLK. Meanwhile, the second clock counter 142 resumes counting the number of cycles of the clock CLK. Then, at the fourth capture timing, the second counter 152 increments its count value to 3 because the signal level of the captured communication data B is low. At this point, the first number is 1, the second number is 3, and the second number has reached the set value of 3, so the determination circuit 170 enables adjustment of the communication speed.

[0057] In this case, since the second number reaches the set value before the first number, the determination circuit 170 determines that the second signal level, i.e., the L level, is to be enabled, and supplies a signal to the selector 180 to enable the second signal level. In response to this, the selector 180 supplies the count value of the second time counter 142, i.e., the second time, to the division circuit 190.

[0058] Then, before counting the number of cycles after data bit 4, the division circuit 190 divides the second time by a set value. Here, the count value of the second time counter 142 is 284, so the division circuit 190 divides 284 by 3 to calculate a quotient of 94. The division circuit 190 then supplies the quotient of 94 to the baud rate setting register 120.

[0059] Then, the baud rate setting register 120 adjusts the register value from the initial register value of 99 to 94. As a result, the baud rate generation counter 130 applies the register value of 94 to count data bits 4 to 8, the parity bit, and the stop bit, causing an overflow. In this way, for example, the communication device 100 adjusts the communication speed by adjusting the number of clock cycles per bit.

[0060] If such an adjustment were not made, the 10th bit would capture parity as a stop bit. However, as shown in the figure, when three L-level bits are received, the register value of the baud rate setting register 120 is adjusted from the initial value of 99 to 94, so that in this frame, the communications device 100 receives the communication data B while maintaining the offset in capture timing. Then, the communications device 100 communicates using the adjusted register value from the next start bit, and is therefore able to capture the communication data B at the center timing of one bit time.

[0061] In the above description, the communication data B, from the start bit to the stop bit, is in the order of L level → L level → H level → L level → H level → H level → L level → H level → L level → L level → H level, and since the L level reached 3 bits before the H level, the communication device 100 determined that the L level, i.e., the second signal level, was valid and adjusted the communication speed based on the second time.

[0062] However, for example, if data bit 3 in the above bit pattern is at H level, the H level reaches bit 3 before the L level, so communication device 100 determines that the H level, i.e., the first signal level, is valid and adjusts the communication speed based on the first time period.

[0063] While typical embodiments that can be implemented have been described above as examples, the above embodiments can be modified in various ways or applied to various uses. For example, the above description has been given as an example in which the setting value registered in the bit number setting register 160 is fixed at 3. However, the setting value may be variable.

[0064] For example, when adjusting the number of clock cycles per bit based on the quotient obtained by dividing the first time or the second time by a set value, it is preferable to set the set value to a large value from the viewpoint of adjustment error. However, as described above, since baud rate deviations accumulate in the latter half of the frame, it is preferable to set the set value to a small value from the viewpoint of deviation accumulation. Therefore, the set value may be variable.

[0065] For example, if the bit just before or just after the intended bit is captured in the latter half of the frame, a discrepancy will occur between the number of high-level bits in the data bits and the value of the parity bit, allowing the receiver to notice the error.

[0066] Therefore, for example, if the initial setting value is set to setting value = 3, and if the communication speed is adjusted at setting value = 3 and no error occurs in the parity check, the determination unit 103 may change the setting value to = 4. If the communication speed is adjusted at setting value = 4 and no error occurs in the parity check, the determination unit 103 may change the setting value to = 5. If the communication speed is adjusted at setting value = 5 and an error occurs in the parity check, the determination unit 103 may return the setting value to = 4, and set the final setting value to = 4.

[0067] Alternatively, for example, if the initial setting value is set to setting value = 5, and an error occurs in the parity check when the communication speed is adjusted at setting value = 5, the determination unit 103 may change the setting value to setting value = 4. If no error occurs in the parity check when the communication speed is adjusted at setting value = 4, the determination unit 103 may set the final setting value to setting value = 4. In this way, for example, the determination unit 103 may change the setting value registered in the bit number setting register 160 based on the communication quality of the communication data B.

[0068] In the past, to accommodate fluctuations in the baud rate, the duration of the L level was measured and the communication speed was adjusted based on the measurement results. However, this conventional technology was based on the premise of using a predefined bit pattern, where the start bit is L level, the stop bit is H level, and the interval between the start bit and the stop bit is L level, which resulted in a lack of flexibility.

[0069] In contrast, the communication device 100 of this embodiment measures both a first time indicating the duration of a first signal level and a second time indicating the duration of a second signal level in communication data B input from the opposite device 200, and selects either the first time or the second time based on the first number indicating the number of bits of the first signal level and the second number indicating the number of bits of the second signal level to adjust the communication speed.

[0070] In this way, the communication device 100 according to this embodiment selects any of the times and adjusts the communication speed regardless of the bit pattern of the communication data B, so there is no need to predefine the bit pattern of the communication data B between the communication device 100 according to this embodiment and the other device 200. Therefore, the communication device 100 according to this embodiment can provide flexibility to the communication data B when adjusting the communication speed.

[0071] Also, for example, suppose the communication device 100 is a microcontroller equipped with a mechanism for suppressing frequency error to 1% or less in order to achieve UART communication using an oscillator circuit with large frequency fluctuations over a wide temperature range, such as an RC oscillator circuit, without incorporating a crystal oscillator circuit. Even in such a case, if the frequency error of the other device 200 is large, the communication device 100 must incorporate a crystal oscillator circuit, resulting in problems such as an increase in the number of components and increased costs. However, the communication device 100 according to this embodiment can adjust the communication speed to accommodate frequency errors in the other device 200 without incorporating a crystal oscillator circuit, thereby increasing the product appeal of the microcontroller.

[0072] Furthermore, generally, the frequency of the clock generation circuit 110 does not suddenly deviate in either the communication device 100 or the counterpart device 200. Therefore, according to the communication device 100, as long as communication is continued and adjustment is continued, even if the baud rate value deviates gradually from the ideal baud rate value, communication can be maintained with an accuracy exceeding the accuracy specified for communication (for example, the 2.5% accuracy specified for UART).

[0073] In this case, the communication device 100 according to the present embodiment may determine whether to enable the first signal level or the second signal level based on the first number and the second number, and select either the first time period or the second time period according to the determination result. In this way, the communication device 100 according to the present embodiment can select which time period to use for adjusting the communication speed based on objective grounds.

[0074] In particular, the communication device 100 according to the present embodiment may determine to enable the first signal level when the first number reaches the set value before the second number, and may determine to enable the second signal level when the second number reaches the set value before the first number. As a result, the communication device 100 according to the present embodiment can enable the signal level that reaches the set value first, regardless of the bit pattern of the communication data B.

[0075] In this case, the communication device 100 according to the present embodiment may adjust the communication speed according to the result of dividing the selected first time period or the selected second time period by a set value. As a result, the communication device 100 according to the present embodiment can recognize the baud rate of the opposite device 200 by simply performing a relatively simple calculation, namely, division.

[0076] At this time, the communication device 100 according to this embodiment may adjust the number of clock cycles per bit according to the result of the division. As a result, the communication device 100 according to this embodiment can respond to fluctuations in the baud rate simply by changing the value registered in the baud rate setting register 120, for example.

[0077] Furthermore, the communication device 100 according to this embodiment may change the set value based on the communication quality of the communication data B. As a result, the communication device 100 according to this embodiment can increase the set value as much as possible within a range that does not incorporate the bit immediately before or after the intended bit.

[0078] This disclosure also includes the following:

[0079] (Appendix 1) a timer that measures a first time indicating a duration of a first signal level and a second time indicating a duration of a second signal level in communication data input from an opposite device; a counting unit that counts a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level; a selection unit that selects either the first time period or the second time period based on the first number and the second number; an adjustment unit that adjusts a communication speed in asynchronous serial communication with the opposing device based on either the first time period or the second time period in accordance with the result of the selection; A communication device comprising: (Appendix 2) a determination unit that determines whether the first signal level or the second signal level is to be enabled based on the first number and the second number, the selection unit selects either the first time period or the second time period according to the result of the determination. 10. A communications device as defined in claim 1. (Appendix 3) the determination unit determines that the first signal level is enabled when the first number reaches a predetermined set value before the second number, and determines that the second signal level is enabled when the second number reaches the set value before the first number. 10. A communications device as defined in claim 2. (Appendix 4) a calculation unit that divides either the first time period or the second time period by the set value according to the selected result, the adjusting unit adjusts the communication speed in accordance with the result of the division. 10. A communications device as defined in claim 3. (Appendix 5) the adjusting unit adjusts the number of clock cycles per bit in the asynchronous serial communication in accordance with the result of the division, thereby adjusting the communication speed. 5. A communications device as defined in claim 4. (Appendix 6) the determination unit changes the setting value based on the communication quality of the communication data. 6. A communications device according to any one of claims 3 to 5. (Appendix 7) The asynchronous serial communication is a UART, The communication data includes a start bit, a data bit, a parity bit, and a stop bit. 7. A communications device according to any one of claims 1 to 6. (Appendix 8) a communication device according to any one of Supplementary Notes 1 to 7; the opposite device; A communication system comprising: (Appendix 9) The computer measuring a first time indicating a duration of a first signal level and a second time indicating a duration of a second signal level in communication data input from the opposite device; counting a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level; selecting either the first time period or the second time period based on the first number and the second number; adjusting a communication speed in asynchronous serial communication with the opposing device based on either the first time period or the second time period according to the selected result; Communication method. [Explanation of symbols]

[0080] 10. Communication Systems 100 Communication Devices 101 Timing section 102 Counting Unit 103 Judgment section 104 Selection section 105 Arithmetic section 106 Adjustment section 110 Clock generation circuit 120 Baud rate setting register 130 Baud rate generation counter 141 First Time Counter 142 Second Time Counter 151 First Counting Counter 152 Second counting counter 160-bit number setting register 170 Judgment circuit 180 Selector 190 Division circuit 200 Opposite device

Claims

1. a timer that measures a first time indicating a duration of a first signal level and a second time indicating a duration of a second signal level in communication data input from an opposite device; a counting unit that counts a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level; a selection unit that selects either the first time period or the second time period based on the first number and the second number; an adjustment unit that adjusts a communication speed in asynchronous serial communication with the opposing device based on either the first time period or the second time period in accordance with the result of the selection; A communication device comprising:

2. a determination unit that determines whether the first signal level or the second signal level is to be enabled based on the first number and the second number, the selection unit selects either the first time period or the second time period in accordance with the result of the determination. The communication device of claim 1 .

3. the determination unit determines that the first signal level is enabled when the first number reaches a predetermined set value before the second number, and determines that the second signal level is enabled when the second number reaches the set value before the first number. The communication device of claim 2 .

4. a calculation unit that divides either the first time period or the second time period by the set value according to the selected result, the adjusting unit adjusts the communication speed in accordance with the result of the division. The communication device of claim 3 .

5. the adjusting unit adjusts the number of clock cycles per bit in the asynchronous serial communication in accordance with the result of the division, thereby adjusting the communication speed. The communication device of claim 4 .

6. the determination unit changes the setting value based on the communication quality of the communication data. The communication device of claim 3 .

7. The asynchronous serial communication is UART, The communication data includes a start bit, a data bit, a parity bit, and a stop bit. A communication device according to any one of claims 1 to 6.

8. A communication device according to any one of claims 1 to 6; the opposite device; A communication system comprising:

9. The computer measuring a first time indicating a duration of a first signal level and a second time indicating a duration of a second signal level in communication data input from the opposite device; counting a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level; selecting either the first time period or the second time period based on the first number and the second number; adjusting a communication speed in asynchronous serial communication with the opposing device based on either the first time period or the second time period in accordance with the selected result; Communication method.

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