Semiconductor device
The semiconductor device addresses power loss and signal instability in level shift circuits by using transistor configurations to stabilize output signals and reduce noise, simplifying circuit design and reducing power consumption.
Patent Information
- Application Number
- JP2024035884
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-08
- Publication Date
- 2025-09-19
AI Technical Summary
Conventional level shift circuits for interfacing different power supplies experience significant power loss due to current flow through pull-up and pull-down resistors, leading to unstable output signals and potential noise generation.
A semiconductor device incorporating a level shifter with specific transistor configurations, including first and second transistors of a first polarity and a third transistor of a second polarity, which control the potential of the output signal without relying on pull-up and pull-down resistors, ensuring stable signal levels and reducing power loss.
The proposed configuration stabilizes output signals, suppresses large currents and unwanted noise, simplifies circuit design, and reduces power loss by eliminating the need for pull-up and pull-down resistors, while maintaining operational stability across varying power supply states.
Smart Images
Figure 2025136944000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to semiconductor devices. [Background technology]
[0002] A technique for fixing (setting) an output signal of a level shift circuit for interfacing between different power supplies to a specific potential is known to ensure normal operation of an LSI (Large Scale Integration) that requires multiple power supply supplies. Patent Document 1 discloses a semiconductor integrated circuit device that includes a level shift circuit that converts a signal amplitude corresponding to a first power supply voltage to a signal amplitude corresponding to a second power supply voltage, and a pull-up resistor that prevents the potential of the signal output from the level shift circuit from becoming unstable. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-129963 Summary of the Invention [Problem to be solved by the invention]
[0004] However, in conventional technology, a pull-up resistor, a pull-down resistor, or the like is used in a level shift circuit to prevent the signal potential from becoming unstable, i.e., to fix the potential of the output signal at a specific potential. In this case, a current may flow through the pull-up resistor, etc., which may result in a large power loss. As such, the conventional technology has room for improvement in fixing the output signal of a level shift circuit for interfacing different power supplies at a specific potential.
[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device capable of reducing power loss when an output signal of a level shift circuit for interfacing different power supplies is fixed to a specific potential. [Means for solving the problem]
[0006] In order to solve the above problem, the semiconductor device according to the present disclosure includes: a level shifter that receives a first signal of a specific potential output from a circuit operating on a first power supply voltage via an input signal terminal and an inverting input signal terminal, converts the first signal into a second signal having a potential different from that of the first signal, and outputs the second signal via an output signal terminal to a circuit operating on a second power supply voltage having a potential different from that of the first power supply voltage; an inverter whose signal input section is connected to the output signal terminal and that inverts and outputs a signal generated at the output signal terminal; a first transistor of a first polarity having a gate to which the first power supply voltage is applied and a drain connected to a pull-up resistor; a second transistor of the first polarity having a gate connected to the drain of the first transistor and the pull-up resistor; and a third transistor of a second polarity having a gate connected to the drain of the second transistor and the gate of a transistor of the first polarity provided in the level shifter, and having a drain connected to the output signal terminal and the signal input section of the inverter. [Brief explanation of the drawings]
[0007] [Figure 1] FIG. 1 is a diagram illustrating a configuration example of a power supply including a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a level shift circuit. [Figure 3] FIG. 3 is a timing chart for explaining the operation of the semiconductor device. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of a level shift circuit according to a comparative example. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a power supply including a level shift circuit according to a comparative example. [Figure 6] FIG. 6 is a diagram showing the function of a power supply including a level shift circuit according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION
[0008] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.
[0009] (Embodiment) 1 is a diagram showing an example of the configuration of a power supply including a semiconductor device according to an embodiment of the present disclosure. Two external power supplies provided outside the LSI are shown in FIG. Specifically, the two external power supplies may be interpreted as a circuit A that supplies a first power supply voltage DVDD and a circuit B that supplies a second power supply voltage SPVDD.
[0010] The circuit A that supplies the first power supply voltage DVDD may include an internal power supply generating circuit 1, a control circuit 2, a level shift circuit 3, and a level shift circuit 4. In this disclosure, the term "level shift circuit" may be interpreted as a level shifter.
[0011] The internal power supply generating circuit 1 may generate an internal power supply voltage VDDL based on the first power supply voltage DVDD.
[0012] The control circuit 2 may be considered as a circuit that operates on the internal power supply voltage VDDL generated by the internal power supply generating circuit 1. The control circuit 2 may generate and output a specific signal S whose potential is the internal power supply voltage VDDL.
[0013] The level shift circuit 3 may receive the signal S output from the control circuit 2. The level shift circuit 3 may convert the signal S into a signal (first signal AMPEN) whose potential is a first power supply voltage DVDD different from the potential of the internal power supply voltage VDDL, and output the converted signal.
[0014] The level shift circuit 4 may be considered as a semiconductor device of the present disclosure. The level shift circuit 4 may input a first signal AMPEN of a specific potential output from the level shift circuit 3 that operates on the first power supply voltage DVDD, for example. The level shift circuit 4 may convert the first signal AMPEN into a second signal AMPEN_HV whose potential is different from that of the first signal AMPEN.
[0015] The level shift circuit 4 may output the second signal AMPEN_HV to a circuit that operates on a second power supply voltage SPVDD, which is a potential different from the first power supply voltage DVDD. The configuration of the level shift circuit 4 will be described in detail later.
[0016] The external power supply SPVDD may include a level shift circuit 5 and a class D amplifier 6.
[0017] The level shift circuit 5 may be considered as a circuit that operates on the internal power supply voltage VDDL generated by the internal power supply generation circuit 1. The level shift circuit 5 may receive the signal S output from the control circuit 2 and the second signal AMPEN_HV output from the level shift circuit 4.
[0018] Next, the configuration of the level shift circuit 4 will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of the configuration of the level shift circuit.
[0019] The level shift circuit 4 may include a level shift section 10, a first transistor 20, a second transistor 30, a third transistor 40, an input signal terminal IN1, an inverting input signal terminal IN2, an output signal terminal OUT1, an inverting output signal terminal OUT2, an inverter 41, an inverter 50, a transistor 60, and a transistor 70.
[0020] (Level shift section 10) The level shift unit 10 may receive a first signal AMPEN of a specific potential output from a circuit operating on the first power supply voltage DVDD via the input signal terminal IN1 and the inverting input signal terminal IN2. The circuit operating on the first power supply voltage DVDD may be interpreted as the circuit operating on the internal power supply voltage VDDL shown in FIG. 1, for example, as the level shift circuit 3 shown in FIG.
[0021] The level shift unit 10 may convert the first signal AMPEN into a second signal AMPEN_HV having a potential different from that of the first signal AMPEN. The level shift unit 10 may output the second signal AMPEN_HV via the output signal terminal OUT1 to a circuit that operates on a second power supply voltage SPVDD having a potential different from that of the first power supply voltage DVDD.
[0022] The level shift unit 10 may include a second polarity transistor 11, a second polarity transistor 12, a first polarity transistor 13, a second polarity transistor 14, a second polarity transistor 15, a first polarity transistor 16, and a first polarity transistor 17.
[0023] In the embodiments of the present disclosure, a transistor of the first polarity may be interpreted as an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET), and a transistor of the second polarity may be interpreted as a P-channel MOSFET.
[0024] The transistor 11 may have a source to which a first power supply voltage DVDD is applied and a drain connected to the source of the transistor 12. The transistor 11 may have a gate connected to the output signal terminal OUT1, the drain of the transistor 15, and the drain of the transistor 16.
[0025] The source of the transistor 12 may be connected to the drain of the transistor 11, and the drain may be connected to the drain of the transistor 13, the inverted output signal terminal OUT2, and the gate of the transistor 14. The gate of the transistor 12 may be connected to the output terminal of the inverter 41, the input signal terminal IN1, and the gate of the transistor 13.
[0026] The source of the transistor 13 may be grounded, and the gate may be connected to the output terminal of the inverter 41, the input signal terminal IN1, and the gate of the transistor 12. The drain of the transistor 13 may be connected to the drain of the transistor 12, the inverted output signal terminal OUT2, and the gate of the transistor 14.
[0027] The transistor 14 may have a source to which a first power supply voltage DVDD is applied, a drain connected to the source of the transistor 15, and a gate connected to the drain of the transistor 12, the inverted output signal terminal OUT2, and the drain of the transistor 13.
[0028] The source of the transistor 15 may be connected to the drain of the transistor 14. The drain of the transistor 15 may be connected to the gate of the transistor 11, the output signal terminal OUT1, the drain of the transistor 16, and the gate of the inverter 50. The gate of the transistor 15 may be connected to the inverted input signal terminal IN2, the gate of the transistor 16, the drain of the transistor 60, and the drain of the transistor 70.
[0029] The source of the transistor 16 may be connected to the drain of the transistor 17. The drain of the transistor 16 may be connected to the gate of the transistor 11, the drain of the transistor 15, the output signal terminal OUT1, and the gate of the inverter 50. The gate of the transistor 16 may be connected to the inverted input signal terminal IN2, the gate of the transistor 15, the drain of the transistor 60, and the drain of the transistor 70.
[0030] The source of the transistor 17 may be grounded, and the drain may be connected to the source of the transistor 16. The gate of the transistor 17 may be connected to the drain of the second transistor 30 and the gate of the third transistor 40.
[0031] (first transistor 20) The first transistor 20 may be interpreted as a first transistor of a first polarity, having a gate to which a first power supply voltage is applied and a drain to which a pull-up resistor R is connected. Specifically, the first transistor 20 may have a gate to which the first power supply voltage DVDD is applied, a source to which the first transistor 20 is grounded, and a drain to which the pull-up resistor R and the gate of the second transistor 30 are connected. One end of the pull-up resistor R may be connected to the drain of the first transistor 20, and the other end of the pull-up resistor R may be applied with the first power supply voltage DVDD.
[0032] (Second transistor 30) The second transistor 30 may be interpreted as a second transistor of a first polarity, the gate of which is connected to the drain of the first transistor 20 and the pull-up resistor R. Specifically, the source of the second transistor 30 may be grounded, and the gate of the second transistor 30 may be connected to the drain of the first transistor 20 and the pull-up resistor R. The drain of the second transistor 30 may be connected to the gate of the third transistor 40 and the gate of the transistor 17.
[0033] (Third transistor 40) The third transistor 40 may be interpreted as a third transistor of a second polarity, the gate of which is connected to the drain of the second transistor 30 and the gate of the transistor 17 of a first polarity provided in the level shifter (level shift unit 10), and the drain of which is connected to the output signal terminal OUT1 and the signal input unit of the inverter 50. Specifically, the third transistor 40 may have a source to which the second power supply voltage SPVDD is applied, and the gate of which is connected to the drain of the second transistor 30. The drain of the third transistor 40 may be connected to the gate of the inverter 50, the output signal terminal OUT1, the gate of the transistor 11, the drain of the transistor 15, and the drain of the transistor 16.
[0034] The transistor 60 may be interpreted as a second polarity transistor having a gate connected to the output terminal of the inverter 41, a source to which a specific power supply voltage (e.g., the first power supply voltage DVDD) is applied, and a drain connected to the drain of the transistor 70. The drain of the transistor 60 may be connected to the inverting input signal terminal IN2, the gate of the transistor 15, and the gate of the transistor 16.
[0035] The transistor 70 may be interpreted as a transistor of a first polarity, with its gate connected to the output terminal of the inverter 41, its source grounded, and its drain connected to the drain of the transistor 60. The drain of the transistor 70 may be connected to the inverting input signal terminal IN2, the gate of the transistor 15, and the gate of the transistor 16.
[0036] In the level shift circuit 4 configured in this manner, when the first power supply voltage DVDD is not supplied and the second power supply voltage SPVDD is supplied to the pull-up resistor R, the first transistor 20 is in the off state and the second transistor 30 is turned on by the pull-up resistor R, causing the potential of the signal input terminal of the inverter 50 to become high level and the potential of the signal output terminal of the inverter 50 to become low level.
[0037] Furthermore, by maintaining the first transistor 20 in the off state until the first power supply voltage DVDD reaches a specific potential, the potential of the signal input section of the inverter 50 remains at a high level and the potential of the signal output section of the inverter 50 remains at a low level.
[0038] Furthermore, when the first power supply voltage DVDD exceeds a specific potential, the first transistor 20 changes from an off state to an on state and the second transistor 30 changes from an on state to an off state, and the potential at the signal input section of the inverter 50 becomes a potential that can be controlled by the first signal, the AMPEN signal.
[0039] Next, the operation of the semiconductor device will be described with reference to Fig. 3. Fig. 3 is a timing chart for explaining the operation of the semiconductor device.
[0040] At time t1, when the first power supply voltage DVDD is not supplied and the second power supply voltage SPVDD is supplied, the first transistor 20 and the second transistor 30 are in an off state. At this time, the second power supply voltage SPVDD is applied to the drain of the first transistor 20 and the gate of the second transistor 30 by the pull-up resistor R. In other words, when a current flows through the pull-up resistor R, the current is converted into a voltage, and this voltage is applied to the drain of the first transistor 20 and the gate of the second transistor 30.
[0041] This causes the gate voltage level of the second transistor 30 to become H level, and the second transistor 30 to be in an ON state. Therefore, the drain voltage level of the second transistor 30 becomes L level, and the gate voltage of the third transistor 40 becomes L level. As a result, the third transistor 40 is in an ON state, and the gate voltage of the inverter 50 becomes H level, so that the voltage level of the output (AMPEN_HV) of the inverter 50 is fixed at L level.
[0042] Thereafter, at time t1′, the supply of the first power supply voltage DVDD begins, and the first transistor 20 remains in the off state until time t2, when the first power supply voltage DVDD reaches the threshold voltage thV. As a result, the gate voltage of the inverter 50 remains at the H level until time t2. Therefore, the voltage level of the output (AMPEN_HV) of the inverter 50 remains fixed at the L level. The threshold voltage thV may be interpreted as VSS+the Vt voltage (approximately 0.7V) of the first transistor 20. The Vt voltage of the first transistor 20 may be interpreted as the gate voltage at which conduction occurs between the source and drain and current flows. The threshold voltage thV may be interpreted as a specific potential. Note that VSS may be interpreted as the GND potential or 0V.
[0043] When the first power supply voltage DVDD reaches the threshold voltage thV, the first transistor 20 turns on, causing the drain voltage level of the first transistor 20 to become L level, and the gate voltage of the second transistor 30 to become L level, causing the second transistor 30 to turn off.
[0044] Therefore, the drain voltage level of the second transistor 30 becomes H level, and the gate voltage of the third transistor 40 becomes H level. As a result, the third transistor 40 is turned off, and the gate voltage of the inverter 50 becomes L level, so that the voltage level of the output (AMPEN_HV) of the inverter 50 becomes H level.
[0045] 1 is fixed to a specific potential regardless of the state of the control signal, i.e., regardless of whether the voltage level of the control signal is H level or L level. Specifically, even when the first power supply voltage DVDD is not supplied (0 V) and the second power supply voltage SPVDD is supplied, the output signal OUT of the level shift circuit 5 can be prevented from becoming unstable.
[0046] Therefore, it is possible to prevent the potentials of the output terminals SPP and SPM of the class-D amplifier 6 from becoming unstable. In other words, the class-D amplifier 6 can control the potentials of the output terminals SPP and SPM to become desired potentials (i.e., expected states). Note that the control signal may be interpreted as the signal S output from the control circuit 2, or as the signal of the first power supply voltage DVDD (first signal AMPEN) output from the level shift circuit 3.
[0047] When the potentials of the output terminals SPP and SPM of the class-D amplifier 6 are in an unstable state, a large current may be generated through an external speaker, or unwanted sounds may be generated, for example.
[0048] In the level shift circuit 4, which is a semiconductor device according to the present disclosure, the first transistor 20 is turned on while the potential of the first power supply voltage DVDD is lower than a specific potential, thereby applying the second power supply voltage SPVDD to the input signal terminal IN1. Furthermore, the third transistor 40 is turned on while the potential of the first power supply voltage DVDD is lower than the specific potential, thereby applying the second power supply voltage SPVDD to the output signal terminal OUT1. This allows the transistor 12 to remain off and the transistor 13 to remain on while the potential of the first power supply voltage DVDD is lower than the specific potential. Furthermore, while the potential of the first power supply voltage DVDD is lower than the specific potential, the voltage level of the output AMPEN_HV of the inverter 50 can be fixed at the L level. In other words, by fixing the output signal OUT of the level shift circuit 5, it is possible to suppress the generation of large currents and unwanted noise, as described above.
[0049] (Comparative Example) 4 is a diagram showing an example of the configuration of a level shift circuit according to a comparative example. A level shift section 10A of a level shift circuit 4A according to the comparative example includes a pull-down resistor R1 and a pull-up resistor R2. The voltage level of the output (AMPEN_HV) of the inverter 50 is fixed to the L level by the pull-down resistor R1 and the pull-up resistor R2.
[0050] 5 is a diagram showing an example of the configuration of a power supply including a level shift circuit according to a comparative example. As shown in Fig. 5, the circuit that supplies the first power supply voltage DVDD includes an internal power supply generating circuit 1, a control circuit 2, a level shift circuit 3, a level shift circuit 4, a reset circuit 7, and a level shift circuit 8. The external power supply SPVDD may include a level shift circuit 5, a class D amplifier 6, and a logical product circuit 9.
[0051] In the configuration shown in FIG. 5, when a power supply voltage (first power supply voltage DVDD) is supplied and the power supply voltage rises to a voltage at which the level shift circuit 8 can operate normally, the voltage level of the output signal (POR_HV) of the level shift circuit 8 is fixed to an L level using the output signal (POR) of the reset circuit 7.
[0052] The AND circuit 9 fixes the voltage level of the LVSFTEN signal at the L level until the logical AND of the output signal (AMPEN_HV) of the level shift circuit 4A and the output signal (POR_HV) of the level shift circuit 8 is established. That is, the voltage level of the LVSFTEN signal is fixed at the L level until the first power supply voltage DVDD rises (until the first power supply voltage DVDD reaches a voltage at which the level shift circuit 8 can operate normally). As a result, the output signal OUT of the level shift circuit 5 is fixed.
[0053] The level shift circuit 4A includes a pull-down resistor R1 and a pull-up resistor R2, thereby setting the voltage level of the gate of the inverter 50 to the H level and fixing the voltage level of the output AMPEN_HV of the inverter 50 to the L level.
[0054] However, in this circuit configuration, when the voltage level of the first signal, the AMPEN signal, is set to H level during normal operation, two current paths are generated as shown in Figure 4, and current flows through the pull-down resistor R1 and the pull-up resistor R2, resulting in power loss.
[0055] Furthermore, because this circuit is only effective up to about 1 V, it is necessary to use it in conjunction with a reset circuit 7 and a level shift circuit 8. Therefore, adjustments are required to prevent the level shift circuit 5 from malfunctioning until the first power supply voltage DVDD is supplied, which makes the circuit configuration more complex. In particular, the reset circuit 7, which is powered by a power supply different from that supplied to the class-D amplifier 6, is an analog circuit, so the wiring W for transmitting analog signals from the reset circuit 7 to the level shift circuit 8 and other circuits must be routed manually (see Figure 6).
[0056] (Actions and Effects) In the level shift circuit 4, which is a semiconductor device according to the present disclosure, while the potential of the first power supply voltage DVDD is lower than a specific potential, that is, when the first power supply voltage DVDD is not being supplied, the first transistor 20 and the second transistor 30 are maintained in an off state, thereby fixing the voltage level of the output (AMPEN_HV) of the inverter 50 to an L level. In other words, since the output signal OUT of the level shift circuit 5 can be fixed, it is possible to suppress the generation of large currents and unnecessary sounds as described above.
[0057] Furthermore, the level shift circuit 4 can fix the voltage level of the output AMPEN_HV of the inverter 50 to the L level without using the pull-down resistor R1 and the pull-up resistor R2, thereby reducing the power loss occurring in the pull-down resistor R1 and the pull-up resistor R2.
[0058] Furthermore, since the reset circuit 7 and the level shift circuit 8 shown in Fig. 5 are not used in combination, adjustments to prevent malfunction of the level shift circuit 5 are not required, and the circuit configuration is simplified. Furthermore, routing of the wiring W for transmitting analog signals shown in Fig. 6 is unnecessary, which reduces the manufacturing cost of the circuit. Furthermore, measures against noise generated from the wiring W are not required.
[0059] Furthermore, similar to the comparative example, even if a potential difference occurs between the first power supply voltage DVDD and the second power supply voltage SPVDD, the level shift circuit 8 can operate normally.
[0060] Furthermore, even when the level shift circuit 4 has a configuration in which an external control signal of a specific potential is input to the external input terminal EN shown in FIG. 2, for example, to control the gate voltage level of the third transistor 40 and fix the initial value of the level shift circuit 4, the initial value can be fixed inside the level shift circuit 4 even when no external control signal is supplied.
[0061] In addition, the following supplementary notes are provided in relation to the above description.
[0062] (Appendix 1) a level shifter that receives a first signal of a specific potential output from a circuit operating on a first power supply voltage via an input signal terminal and an inverted input signal terminal, converts the first signal into a second signal having a potential different from that of the first signal, and outputs the second signal via an output signal terminal to a circuit operating on a second power supply voltage having a potential different from that of the first power supply voltage; an inverter having a signal input section connected to the output signal terminal, which inverts and outputs a signal generated at the output signal terminal; a first transistor of a first polarity, the gate of which is applied with the first power supply voltage and the drain of which is connected to a pull-up resistor; a second transistor of the first polarity, the gate of which is connected to the drain of the first transistor and to the pull-up resistor; a third transistor of a second polarity, the gate of which is connected to the drain of the second transistor and the gate of the transistor of the first polarity provided in the level shifter, and the drain of which is connected to the output signal terminal and the signal input portion of the inverter; A semiconductor device comprising:
[0063] (Appendix 2) when the first power supply voltage is not supplied and the second power supply voltage is supplied to the pull-up resistor, the first transistor is in an off state and the second transistor is in an on state due to the pull-up resistor, so that the potential of the signal input section of the inverter becomes high level and the potential of the signal output section of the inverter becomes low level; the first transistor is maintained in an off state until the first power supply voltage reaches a specific potential, whereby the potential of the signal input section of the inverter is maintained at a high level and the potential of the signal output section of the inverter is maintained at a low level; 2. The semiconductor device according to claim 1, wherein when the first power supply voltage exceeds a specific potential, the first transistor changes from an off state to an on state and the second transistor changes from an on state to an off state, causing the potential of the signal input section of the inverter to become a potential controllable by the first signal.
[0064] (Appendix 3) 3. The semiconductor device according to claim 1, wherein the level shifter outputs the second signal to be applied to a class-D amplifier. [Explanation of symbols]
[0065] 1 Internal power generation circuit 2. Control circuit 3 Level shift circuit 4 Level shift circuit 5 Level shift circuit 6 Class D Amplifiers 7 Reset Circuit 8 Level Shift Circuit 9 Logical AND Circuit 10 Level shift section 11 Transistor 12 transistors 13 Transistor 14 Transistor 15 transistors 16 transistors 17 Transistor 20 First transistor 30 Second transistor 40 Third transistor 41, 50 Inverter
Claims
1. a level shifter that receives a first signal of a specific potential output from a circuit operating on a first power supply voltage via an input signal terminal and an inverted input signal terminal, converts the first signal into a second signal having a potential different from that of the first signal, and outputs the second signal via an output signal terminal to a circuit operating on a second power supply voltage having a potential different from that of the first power supply voltage; an inverter having a signal input section connected to the output signal terminal, which inverts and outputs a signal generated at the output signal terminal; a first transistor of a first polarity, the gate of which is applied with the first power supply voltage and the drain of which is connected to a pull-up resistor; a second transistor of the first polarity, the gate of which is connected to the drain of the first transistor and to the pull-up resistor; a third transistor of a second polarity, the gate of which is connected to the drain of the second transistor and the gate of the transistor of the first polarity provided in the level shifter, and the drain of which is connected to the output signal terminal and the signal input portion of the inverter; A semiconductor device comprising:
2. when the first power supply voltage is not supplied and the second power supply voltage is supplied to the pull-up resistor, the first transistor is in an off state and the second transistor is in an on state due to the pull-up resistor, so that the potential of the signal input section of the inverter becomes high level and the potential of the signal output section of the inverter becomes low level; the first transistor is maintained in an off state until the first power supply voltage reaches a specific potential, whereby a potential of the signal input section of the inverter is maintained at a high level and a potential of the signal output section of the inverter is maintained at a low level; 2. The semiconductor device according to claim 1, wherein when the first power supply voltage exceeds a specific potential, the first transistor changes from an off state to an on state and the second transistor changes from an on state to an off state, causing a potential of the signal input section of the inverter to become a potential controllable by the first signal.
3. The semiconductor device according to claim 1 , wherein the level shifter outputs the second signal to be applied to a class D amplifier.
Citation Information
Patent Citations
Semiconductor integrated circuit device
JP2011129963A