Circuit board and manufacturing method of the circuit board

Abstract

To provide a circuit board capable of reducing design constraints of a circuit and miniaturizing a circuit pattern, and a manufacturing method of the same.SOLUTION: A circuit board 10A includes: an insulating layer 100 having a via hole 110 penetrating in a first direction; a first pad 120P disposed on the insulating layer to cover the via hole; and a first circuit wiring 120C disposed on the insulating layer to be spaced apart from the first pad 120P. The first pad 120P and a first circuit wiring 120C each include a plurality of stacked metal layers, and the number of metal layers of the first pad 120P is greater than the number of metal layers of the first circuit wiring.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit board and a method for manufacturing the circuit board, and more particularly to a circuit board and a method for manufacturing the circuit board that can reduce restrictions on circuit design and allow for finer circuit patterns. [Background technology]

[0002] As electronic devices in the IT field, including mobile phones, become lighter, thinner, and smaller, the degree of circuit integration is increasing, the number of input / output integrated circuits is increasing, and the width of the circuit patterns applied to package PCBs (Printed Circuit Boards) is becoming finer.

[0003] The key technology for wiring fine circuits is to reduce the line width and spacing. However, there is a problem in that it is difficult to miniaturize the circuit due to the process of forming the circuit pattern through plating and etching. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems with conventional circuit boards, and an object of the present invention is to provide a circuit board that reduces circuit design constraints and enables finer circuit patterns, and a method for manufacturing the circuit board. [Means for solving the problem]

[0005] The circuit board according to the present invention, which has been made to achieve the above-mentioned object, comprises an insulating layer having a via hole penetrating in a first direction, a first pad arranged on the insulating layer so as to cover the via hole, and a first circuit wiring arranged on the insulating layer at a distance from the first pad, wherein the first pad and the first circuit wiring each include a plurality of stacked metal layers, and the number of metal layers of the first pad is greater than the number of metal layers of the first circuit wiring.

[0006] The first pad preferably includes a larger electroplated layer than the first circuit wiring. Preferably, the first pad and the first circuit wiring each include at least one electroless plated layer, and the electroless plated layer of the first circuit wiring has a thickness greater than that of the electroless plated layer of the first pad. The first pad includes a first pad seed layer pattern, a through via extension, a second pad seed layer pattern, and a first pad electroplating layer pattern, which are sequentially stacked on the insulating layer, and the first circuit wiring includes a first circuit seed layer pattern, a second circuit seed layer pattern, and a first circuit electroplating layer pattern, which are sequentially stacked on the insulating layer, and it is preferable that the through via extension extends in a direction perpendicular to the first direction from both ends of the through portion extended in the first direction to cover the inner wall of the via hole. It is preferable that the extension portion is an electroplated layer pattern, and the first pad seed layer pattern, the second pad seed layer pattern, the first circuit seed layer pattern, and the second circuit seed layer pattern are electroless plated layer patterns. The thickness of the first circuit electroplating layer pattern is preferably greater than the thickness of the first pad electroplating layer pattern. The second pad seed layer pattern preferably covers at least a portion of the sidewall of the extension. The first pad electroplating layer pattern preferably covers at least a portion of the sidewall of the extension. The through portion preferably includes a hollow portion passing through in the first direction. It is preferable that the semiconductor device further comprises a plug that fills the hollow portion and protrudes outward from the surface of the insulating layer. The extension preferably surrounds the portion of the plug that protrudes outside the surface of the insulating layer.

[0007] To achieve the above object, a method for manufacturing a circuit board according to the present invention includes the steps of: forming a via hole penetrating a first insulating layer; forming a first seed layer on the surface of the first insulating layer on which the via hole is formed; forming a first mask pattern on the first seed layer to expose the via hole and the first seed layer in its peripheral area; forming a through via having a hollow portion therein on the first seed layer exposed by the first mask pattern; forming a preliminary plug to fill the hollow portion of the through via; and planarizing the preliminary plug, the first mask pattern, and the through via. removing the first mask pattern remaining after the planarization; forming a second seed layer on the first seed layer, the extension of the through via that extends onto the first insulating layer, and the plug formed by planarizing the preliminary plug; forming a second mask pattern that exposes regions of the second seed layer on the plug and at least a portion of the extension of the through via and other regions of the second seed layer spaced from the regions; and forming an electroplating layer pattern on the regions of the second seed layer exposed by the second mask pattern.

[0008] Preferably, the method further comprises the step of removing the second seed layer and the first seed layer exposed by the electroplating layer pattern after removing the second mask pattern. Preferably, the method further comprises forming a second insulating layer on the first insulating layer to bury the electroplated layer pattern. Preferably, the step of forming the electroplating layer pattern includes the step of plating the opened region of the second mask pattern to form a pad electroplating layer pattern having a step with the extension. Preferably, forming the pad electroplating layer pattern includes forming the pad electroplating layer pattern to cover a portion of the second seed layer extending from one end onto the first seed layer. Preferably, forming the plug includes forming the plug to comprise a non-conductive material. It is preferable that the method further includes forming a copper foil (Cu-foil) layer on the first insulating layer, and that the step of forming the first seed layer includes forming the first seed layer on the copper foil layer. Preferably, the method further includes the step of forming a first pad by sequentially stacking the copper foil layer, the first seed layer, the extension of the through via, the second seed layer, and the electroplating layer on the first insulating layer. Preferably, the method further includes the step of forming a first circuit wiring by sequentially stacking the copper foil layer, the first seed layer, the second seed layer, and the electroplating layer on the first insulating layer. Preferably, the step of forming the first seed layer includes forming the first seed layer through electroless plating. Preferably, the step of forming the second seed layer includes forming the second seed layer through electroless plating. [Effects of the Invention]

[0009] According to the circuit board and the method for manufacturing the circuit board of the present invention, restrictions on circuit design imposed by the metal thickness of the circuit layer can be reduced, and the circuit pattern can be made finer. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view schematically illustrating a structure of a circuit board according to an embodiment of the present invention. [Figure 2] 2 is an enlarged cross-sectional view of a portion A of the circuit board shown in FIG. 1. FIG. [Figure 3] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 4] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 5] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 6] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 7] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 8] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 9] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 10] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 11] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 12] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 13] FIG. 10 is a cross-sectional view schematically illustrating the structure of a circuit board according to another embodiment of the present invention. [Figure 14] 14 is an enlarged cross-sectional view of a portion A of the circuit board shown in FIG. 13. FIG. [Figure 15] 14A to 14C are cross-sectional views for explaining a method of manufacturing the circuit board shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, specific examples of embodiments for carrying out the circuit board and the method for manufacturing the circuit board according to the present invention will be described with reference to the drawings.

[0012] In order to clearly illustrate the present invention in the drawings, parts unnecessary for explanation are omitted, and the same reference numerals are used throughout the specification to refer to the same or similar components. In addition, in the accompanying drawings, some components are exaggerated, omitted, or illustrated schematically, and the size of each component does not completely reflect the actual size. The attached drawings are merely for the purpose of facilitating understanding of the embodiments disclosed in this specification, and it should be understood that the attached drawings do not limit the technical ideas disclosed in this specification, and include any modifications, equivalents, or alternatives included in the idea and technical scope of the present invention.

[0013] Terms including ordinal numbers, such as first, second, etc., may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only to distinguish one component from another. Furthermore, when a layer, film, region, plate, or other part is said to be "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when one part is said to be "directly above" another part, it means that there are no other parts in between. Furthermore, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the direction opposite to gravity. Throughout the specification, the use of terms such as "comprises" or "having" is intended to specify the presence of any features, numbers, steps, operations, components, parts, or combinations thereof stated in the specification, but should be understood as not precluding the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Therefore, when a part is said to "comprise" a certain element, this does not exclude other elements, unless specifically stated to the contrary, and means that it may further include other elements.

[0014] Also, throughout the specification, "on a plane" means when the part in question is viewed from above, and "on a cross section" means when the part in question is cut vertically and viewed from the side. Furthermore, throughout the specification, when the term "connected" is used, it does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected via other components, that two or more components are not only physically connected but also electrically connected, or that two or more components are referred to by different names depending on their position or function but are nonetheless integrated.

[0015] A circuit board 10A according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view schematically showing the structure of a circuit board according to an embodiment of the present invention, and FIG. 2 is an enlarged cross-sectional view showing part A of the circuit board shown in FIG. 1 and 2, a circuit board 10A according to an embodiment of the present invention includes a first insulating layer 100 provided as a core layer.

[0016] A first circuit layer 120 is disposed on both sides of the first insulating layer 100, and the first circuit layer 120 includes first pads 120P and first circuit wiring 120C. A second insulating layer 200 is disposed on the first insulating layer 100 so as to cover the first circuit layer 120 . On the second insulating layer 200, a second circuit layer 220 including second pads 220P and second circuit wiring 220C is disposed. The second pad 220P is connected to the first pad 120P through a stacked via 210 that penetrates the second insulating layer 200. A protective layer 300 is disposed on the second insulating layer 200 . The protective layer 300 protects the internal components from external physical and chemical damage. The protective layer 300 covers one surface of the second insulating layer 200 and exposes at least a portion of the second pad 220P. The protective layer 300 may be made of a photosensitive resin, for example, a solder resist layer.

[0017] The first insulating layer 100 and the second insulating layer 200 include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing such a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric), and may be a photosensitive material and / or a non-photosensitive material. As an example, insulating materials such as SR (Solder Resist), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), RCC (Resin Coated Copper), and CCL (Copper Clad Laminate) may be used, but are not limited to these and may include other polymeric materials. For example, but not limited to, prepreg may be used. 1 and 2, the first insulating layer 100 is shown as a single layer, but is not limited to this, and the first insulating layer 100 can also be formed by stacking a plurality of thin layers.

[0018] The first and second circuit layers (120, 220) each transmit signals within the circuit board 10A. The first and second circuit layers (120, 220) may be made of metal. The metallic material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first and second circuit layers (120, 220) performs various functions according to the design, such as a ground pattern, a power pattern, and a signal pattern. These patterns have a line, a plane, or a pad shape, respectively. In the case of a circuit layer located on the outermost layer of a plurality of circuit layers, it can function as a pad for connection to another substrate or component.

[0019] The first insulating layer 100 has a via hole 104 penetrating in a first direction. The first direction is the stacking direction. The through via 110 has a hollow portion that penetrates in a first direction and extends to fill the via hole 104 . The plug 112 fills the hollow portion of the through via 110 and protrudes outward from the surface of the first insulating layer 100 . The through via 110 includes a through portion 110a extending in a first direction to cover the inner wall of the via hole 104, and an extension portion 110b extending perpendicular to the first direction from both ends of the through portion 110a and surrounding a plug 112 that protrudes outside the surface of the first insulating layer 100. The through vias 110 connect the first pads 120P on both sides of the first insulating layer 100 to each other.

[0020] The through via 110 and the stacked via 210 may be made of a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the through vias 110 and stacked vias 210 may include a signal via, a ground via, a power via, etc. depending on the design. The plug 112 may include plugging ink having insulating properties. The plug 112 can prevent oxidation of the through via 110 by filling the empty space inside the via hole 104 .

[0021] Hereinafter, the first pad 120P and the first circuit wiring 120C of the circuit board 10A according to the embodiment of the present invention will be described in more detail with reference to FIG. 2 in addition to FIG. 1 and 2, the first pad 120P and the first circuit wiring 120C are disposed on the first insulating layer 100 and have different layer structures. The first pad 120P is interposed between the extension 110b of the through via 110 and the first insulating layer 100, and includes a first pad copper foil layer pattern 102P and a first pad seed layer pattern 106P stacked sequentially in a first direction on the first insulating layer 100.

[0022] The first pad 120P also includes a second pad seed layer pattern 114P and a first pad electroplating layer pattern 118P, which are sequentially stacked on the extension 110b. The second pad seed layer pattern 114P covers the top surface of the extension 110b. In some cases, the second pad seed layer pattern 114P covers the top surface of the extension 110b and at least a portion of the side surface of the extension 110b. As will be described later, the first pad seed layer pattern 106P and the second pad seed layer pattern 114P are metal layers, for example, Cu layers, formed by electroless plating. The extension 110b and the first pad electroplating layer pattern 118P are metal layers, for example, Cu layers, formed on the first pad seed layer pattern 106P and the second pad seed layer pattern 114P by electroplating, respectively.

[0023] In contrast, the first circuit wiring 120C includes a first circuit copper foil layer pattern 102C, a first circuit seed layer pattern 106C, a second circuit seed layer pattern 114C, and a first circuit electroplated layer pattern 118C stacked in sequence on the first insulating layer 100. The first and second circuit seed layer patterns (106C, 114C) are metal layers, for example, Cu layers, formed by electroless plating. The first circuit electroplating layer pattern 118C is a metal layer, such as a Cu layer, formed on the second circuit seed layer pattern 114C by electroplating.

[0024] The first pad 120P includes two electrolytic plating layers (the extension 110b and the first pad electrolytic plating layer pattern 118P) and one electroless plating layer (the second pad seed layer pattern 114P) interposed therebetween. In contrast, the first circuit wiring 120C includes two electroless plated layers (first circuit seed layer pattern 106C and second circuit seed layer pattern 114C) and one electrolytic plated layer (first circuit electrolytic plated layer pattern 118C) that are stacked in succession. The two successively stacked electroless plating layers (first circuit seed layer pattern 106C and second circuit seed layer pattern 114C) may appear as a single layer. In this case, the electroless plated layer of the first circuit wiring 120C has a thickness greater than that of the electroless plated layer of the first pad 120P.

[0025] The first pad 120P and the first circuit wiring 120C have substantially the same thickness, but as described below, the first pad electrolytic plating layer pattern 118P and the first circuit electrolytic plating layer pattern 118C, which are formed in the same process, have different thicknesses. That is, the thickness of the first circuit electrolytic plating layer pattern 118C is greater than the thickness of the first pad electrolytic plating layer pattern 118P. According to the circuit board according to the above-described embodiment of the present invention, restrictions on circuit design due to the metal thickness of the circuit layer are reduced, and finer circuit patterns can be realized.

[0026] A method for manufacturing the circuit board 10A according to the embodiment of the present invention will be described below with reference to FIGS. 3 to 12 are cross-sectional views illustrating steps in a method for manufacturing a circuit board according to an embodiment of the present invention.

[0027] Referring to FIG. 3, a first insulating layer 100 having copper foil layers 102 formed on both sides thereof is prepared. The copper foil layer 102 is formed by laminating copper foil (Cu-foil) on both sides of the first insulating layer 100 and pressing them together. A via hole 104 is formed through the first insulating layer 100 and the copper foil layer 102 . The via holes 104 can be formed in multiple numbers by laser, mechanical drilling, or the like.

[0028] Referring to FIG. 4, a first seed layer 106 is formed on the surface of the first insulating layer 100 in which the via hole 104 is formed. The first seed layer 106 is formed on the copper foil layer 102 and on the inner wall of the via hole 104 . The first seed layer 106 is formed of a copper (Cu) layer by electroless plating. A first mask pattern 108P is formed on the first seed layer 106 to expose the via hole 104 and the first seed layer 106 around it. The first mask pattern 108P exposes a region on the first seed layer 106 that is located along the edge of the via hole 104 . The first mask pattern 108P is patterned by exposing and developing a photosensitive dry film.

[0029] Referring to FIG. 5, a through via 110 is formed on the first seed layer 106 exposed by the first mask pattern 108P. The through via 110 includes a through portion 110 a on the inner wall of the via hole 104 and extension portions 110 b connected to the through portion 110 a and extending onto the upper and lower surfaces of the first insulating layer 100 . The through vias 110 may be formed by electrolytic plating on the exposed first seed layer 106 using the first mask pattern 108P as a plating mask, and may be made of copper (Cu).

[0030] Referring to FIG. 6, a preliminary plug 112P is formed by filling the interior of the via hole 104 in which the through via 110 is formed and extending onto the extension portion 110b. The spare plug 112P is formed by printing insulating ink.

[0031] Referring to FIG. 7, the preliminary plug 112P formed on the extension 110b of the through via 110, the extension 110b of the through via 110, and the first mask pattern 108P are polished to planarize their surfaces. In this process, the preliminary plug 112P of the portion extended on the extension portion 110b is removed to form the plug 112. Also, the thickness of the extension 110b and the first mask pattern 108P may be small, and the surfaces of the plug 112, the extension 110b, and the first mask pattern 108P may be substantially flush with each other. The plug 112 is surrounded by the through portion 110 a of the through via 110 . The plug 112 is formed to include a non-conductive material.

[0032] Referring to FIG. 8, after the remaining first mask pattern 108P is peeled and removed, a second seed layer 114 is formed on the first seed layer 106, the extension 110b of the through via 110, and the plug 112. The second seed layer 114 is formed of a copper (Cu) layer by electroless plating.

[0033] Referring to FIG. 9, a second mask pattern 116P is formed on the second seed layer 114. The second mask pattern 116P continuously exposes the second seed layer 114 on the plug 112 and on at least a portion of the extension 110b. The second mask pattern 116P also exposes the second seed layer 114 in the region where circuit wiring will be formed. The second mask pattern 116P is patterned by exposing and developing a photosensitive dry film.

[0034] 9 and 10, a first pad electroplating layer pattern 118P and a first circuit electroplating layer pattern 118C are formed on the exposed second seed layer 114 using the second mask pattern 116P as a plating mask. The first pad electroplating layer pattern 118P and the first circuit electroplating layer pattern 118C are formed of a copper (Cu) layer. Thereafter, the second mask pattern 116P is peeled off and removed. On the other hand, when the second mask pattern 116P of FIG. 9 is formed to be partially or completely separated from the second seed layer 114 formed on the sidewall of the extension portion 110b, the first pad electroplating layer pattern 118P may be formed to partially or completely cover the second seed layer 114 formed on the sidewall of the extension portion 110b (see FIG. 13).

[0035] Referring to FIG. 11, after removing the second mask pattern 116P, the exposed second seed layer 114, the underlying first seed layer 106, and the copper foil layer 102 are removed to form the first pad 120P and the first circuit wiring 120C. As a result, the first pad 120P includes a first pad copper foil layer pattern 102P, a first pad seed layer pattern 106P, an extension 110b of the through via 110, a second pad seed layer pattern 114P, and a first pad electroplating layer pattern 118P stacked sequentially on the first insulating layer 100. The first circuit wiring 120C includes a first circuit copper foil layer pattern 102C, a first circuit seed layer pattern 106C, a second circuit seed layer pad pattern 114C, and a first circuit electroplating layer pattern 118C, which are sequentially stacked on the first insulating layer 100.

[0036] The first pad 120P includes two electrolytic plating layers, namely, the extension 110b and the first pad electrolytic plating layer pattern 118P, while the first circuit wiring 120C includes one electrolytic plating layer, namely, the first circuit electrolytic plating layer pattern 118C. In addition, the first pad 120P may be formed so that an electrolytic plated layer is interposed between two electroless plated layers, whereas the first circuit wiring 120C may be formed so that it includes two electroless plated layers that are in direct contact with each other overall. Meanwhile, the exposed second seed layer 114, the underlying first seed layer 106, and the copper foil layer 102 are removed by wet etching using a chemical solution, and depending on the degree and method of etching, the second seed layer 114 on the sidewall of the extension portion 110b may be partially or completely removed. For example, if the chemical solution is sprayed perpendicular to the stacking direction, the second seed layer 114 on the sidewalls of the extension 110b may partially remain.

[0037] Referring to FIG. 12, a second insulating layer 200 is formed on the first insulating layer 100 so that the first pads 120P and the first circuit wiring 120C are embedded therein. Then, the second pad 220P and the second circuit wiring 220C are formed on the second insulating layer 200. Furthermore, a buildup via 210 is formed through the second insulating layer 200 to connect the first pad 120P and the second pad 220P. The second pad 220P, the second circuit wiring 220C, and the stacked via 210 can be formed using a conventional wiring formation method, such as a subtractive method, an AP (Additive Process), a SAP (Semi Additive Process), or an MSAP (Modified Semi Additive Process).

[0038] 12 and 1, a protective layer 300 exposing a portion of the second pad 220P is formed on the second insulating layer 200 on which the second pad 220P and the second circuit wiring 220C are formed. The protective layer 300 is a solder resist layer formed by exposing and developing a photosensitive resin. According to a method for manufacturing a circuit board according to an embodiment of the present invention, a mask pattern is formed on a copper foil layer and a seed layer laminated on an insulating layer, and then a through via is formed. This allows the through via to be formed more finely and precisely than when the entire top surface of the insulating layer is plated and then etched. In addition, according to the method for manufacturing a circuit board according to an embodiment of the present invention, the circuit wiring is formed using the MSAP method, which reduces circuit design constraints due to the metal thickness of the circuit wiring without affecting the formation of through vias and plugs, thereby enabling circuit miniaturization.

[0039] A circuit board 10B according to another embodiment of the present invention and a method for manufacturing the same will now be described. FIG. 13 is a cross-sectional view schematically showing the structure of a circuit board according to another embodiment of the present invention, FIG. 14 is a cross-sectional view showing an enlarged portion of the circuit board shown in FIG. 13, and FIG. 15 is a cross-sectional view for explaining a method for manufacturing the circuit board shown in FIG. 14. 13 and 14, a circuit board 10B according to another embodiment of the present invention is similar to the circuit board 10A according to the embodiment of the present invention described with reference to FIGS. A detailed description of the same components will be omitted.

[0040] Referring to Figures 13 and 14, a circuit board 10B according to another embodiment of the present invention differs from the circuit board 10A according to the embodiment of the present invention shown in Figures 1 and 2 in that the extension portion 110b and the first pad electroplating layer pattern 118P are arranged so as to have a step at one end. The first pad electroplating layer pattern 118P includes a portion that does not overlap with the extension portion 110b in the stacking direction. The first pad electroplating layer pattern 118P is disposed so as to expose a portion of the second pad seed layer pattern 114P from the first pad electroplating layer pattern 118P at one end and cover another portion of the second pad seed layer pattern 114P at the other end.

[0041] Referring to FIG. 15, a method for manufacturing a circuit board 10B according to another embodiment of the present invention is similar to the method for manufacturing the circuit board 10A according to the embodiment of the present invention described with reference to FIGS. A detailed description of the same components will be omitted.

[0042] 13 to 15, the manufacturing method of circuit board 10B according to another embodiment of the present invention differs from the manufacturing method of circuit board 10A according to the embodiment of the present invention shown in FIGS. 3 to 12 in that the centers of the extension portion 110b and the opened area of ​​second mask pattern 116P do not coincide, and a portion of second mask pattern 116P is formed to overlap with extension portion 110b in the stacking direction. Therefore, the second pad seed layer pattern 114P and the first pad electroplating layer pattern 118P can be formed by plating the opened region of the second mask pattern 116P so as to have a step with the extension 110b. The second pad seed layer pattern 114P is formed to extend at one end onto the first pad seed layer pattern 106P. The first pad electroplating layer pattern 118P is formed to cover the second pad seed layer pattern 114P, which is extended at one end onto the first pad seed layer pattern 106P.

[0043] According to the circuit board and manufacturing method thereof according to the other embodiment of the present invention, the extension of the via electrode and the circuit layer are not formed simultaneously through a single plating process, but are formed separately through separate plating processes. This reduces the circuit design constraints imposed by the metal thickness of the circuit layer without affecting the formation of the via electrode and plug, and enables circuit miniaturization.

[0044] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0045] 10A, 10B circuit board 100 First insulating layer 102 Copper foil layer 102C 1st circuit copper foil layer pattern 102P 1st pad copper foil layer pattern 104 Beer Hall 106 First seed layer 106C First circuit seed layer pattern 106P 1st pad seed layer pattern 110 Through Via 110a Penetration 110b Extension 112 Plug 114 Second seed layer 114C Second circuit seed layer pattern 114P Second pad seed layer pattern 118C First circuit electrolytic plating layer pattern 118P 1st pad electroplating layer pattern 120C 1st circuit wiring 120P 1st Pad 200 Second insulating layer 210 stacked vias 220C 2nd circuit wiring 220P 2nd Pad 300 protective layer

Claims

1. an insulating layer having a via hole penetrating in a first direction; a first pad disposed on the insulating layer so as to cover the via hole; a first circuit wiring disposed on the insulating layer and spaced apart from the first pad; the first pad and the first circuit wiring each include a plurality of stacked metal layers; The circuit board according to claim 1, wherein the number of metal layers of the first pad is greater than the number of metal layers of the first circuit wiring.

2. The circuit board according to claim 1 , wherein the first pad includes a larger electroplated layer than the first circuit wiring.

3. the first pad and the first circuit wiring each include at least one electroless plating layer; 2. The circuit board according to claim 1, wherein the electroless plating layer of the first circuit wiring has a thickness greater than that of the electroless plating layer of the first pad.

4. the first pad includes a first pad seed layer pattern, an extension of a through via, a second pad seed layer pattern, and a first pad electroplating layer pattern, which are sequentially stacked on the insulating layer; the first circuit wiring includes a first circuit seed layer pattern, a second circuit seed layer pattern, and a first circuit electroplating layer pattern, which are sequentially stacked on the insulating layer; The circuit board of claim 1 , wherein the extension portion of the through via extends in a direction perpendicular to the first direction from both ends of the through portion extending in the first direction to cover the inner wall of the via hole.

5. the extension is an electroplated layer pattern, 5. The circuit board according to claim 4, wherein the first pad seed layer pattern, the second pad seed layer pattern, the first circuit seed layer pattern, and the second circuit seed layer pattern are electroless plating layer patterns.

6. 5. The circuit board according to claim 4, wherein the thickness of the first circuit electroplating layer pattern is greater than the thickness of the first pad electroplating layer pattern.

7. The circuit board according to claim 4 , wherein the second pad seed layer pattern at least partially covers a sidewall of the extension.

8. The circuit board according to claim 4 , wherein the first pad electroplating layer pattern covers at least a portion of the sidewall of the extension.

9. The circuit board according to claim 4 , wherein the through-hole includes a hollow portion penetrating in the first direction.

10. 10. The circuit board according to claim 9, further comprising a plug that fills the hollow portion and protrudes outward from the surface of the insulating layer.

11. 11. The circuit board according to claim 10, wherein the extension surrounds the portion of the plug that protrudes outward from the surface of the insulating layer.

12. forming a via hole penetrating the first insulating layer; forming a first seed layer on a surface of the first insulating layer in which the via hole is formed; forming a first mask pattern on the first seed layer to expose the via hole and the first seed layer in a peripheral portion thereof; forming a through via having a hollow portion therein on the first seed layer exposed by the first mask pattern; forming a preliminary plug to fill a hollow portion of the through via; planarizing the preliminary plug, the first mask pattern, and the through via; removing the first mask pattern remaining after the planarization; forming a second seed layer on the first seed layer, the extension of the through via that extends onto the first insulating layer, and a plug formed by planarizing the preliminary plug; forming a second mask pattern exposing regions of the second seed layer over at least a portion of the plug and the extension of the through via and other regions of the second seed layer spaced apart from the regions; and forming an electroplating layer pattern on the region of the second seed layer exposed by the second mask pattern.

13. 13. The method of claim 12, further comprising removing the second seed layer and the first seed layer exposed by the electroplating layer pattern after removing the second mask pattern.

14. The method of claim 12, further comprising forming a second insulating layer on the first insulating layer to bury the electroplated layer pattern.

15. 13. The method of claim 12, wherein the forming of the electroplating layer pattern comprises plating the opened area of ​​the second mask pattern so as to have a step with the extension portion, thereby forming a pad electroplating layer pattern.

16. 16. The method of claim 15, wherein forming the pad electroplating layer pattern includes forming the pad electroplating layer pattern to cover a portion of the second seed layer extending from one end onto the first seed layer.

17. The method of claim 12, wherein forming the plug comprises forming the plug containing a non-conductive material.

18. forming a copper foil layer on the first insulating layer, The method of claim 12 , wherein forming the first seed layer comprises forming the first seed layer on the copper foil layer.

19. 20. The method of claim 18, further comprising forming a first pad by sequentially stacking the copper foil layer, the first seed layer, the extension of the through via, the second seed layer, and the electroplating layer on the first insulating layer.

20. 20. The method of claim 18, further comprising forming a first circuit wiring by sequentially stacking the copper foil layer, the first seed layer, the second seed layer, and the electroplating layer on the first insulating layer.

21. The method of claim 12, wherein the forming of the first seed layer comprises forming the first seed layer through electroless plating.

22. The method of claim 12, wherein the forming of the second seed layer comprises forming the second seed layer through electroless plating.

Images