Operational amplifier circuit

Abstract

To provide an operational amplifier circuit in which influences of noise and input offset are reduced while the number of transistors is reduced.SOLUTION: An aspect of an operational amplifier circuit according to the present invention includes a first switch 21 having one end connected to a positive electrode input terminal of an operational amplifier 10 and the other end receiving an input signal, a second switch 22 having one end connected to a negative electrode input terminal of the operational amplifier 10, a third switch 23 having one end connected to the other end of the second switch 22 and the other end receiving an input signal, and a capacitor Cofs connected between the positive electrode input terminal of the operational amplifier 10 and the other end of the second switch 22. Each of the first switch 21 to the third switch 23 includes a switch transistor, and a capacitor transistor connected in series to the switch transistor while being disposed on a side close to the capacitor Cofs, having a source and a drain connected to each other, and having a conductive state controlled with a phase opposite to that of the corresponding switch transistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an operational amplifier circuit, for example, an operational amplifier circuit having an input offset voltage between input terminals of the operational amplifier. [Background technology]

[0002] An operational amplifier is a circuit that amplifies and outputs the voltage difference between its positive and negative input terminals. However, even when the same voltage is input to the positive and negative input terminals, an operational amplifier may output an output voltage that represents a difference between the two input voltages. The difference between the ideal voltage difference between the input voltages and the voltage difference actually amplified by the operational amplifier is called the input offset. This input offset arises from the characteristics of the circuit elements that make up the operational amplifier. When attempting to perform high-precision voltage amplification, it is ideal to reduce this input offset to zero. Therefore, a technology for correcting the input offset of this operational amplifier is disclosed in Patent Document 1.

[0003] The driving device for an image display device described in Patent Document 1 comprises an operational amplifier that operates as a voltage follower, a capacitor that accumulates charge equivalent to an offset voltage generated in the operational amplifier, and control means that, when an image signal indicating an image to be displayed on an image display device to be driven is input to the operational amplifier, connects a load to which a voltage based on the image signal is applied to an output terminal of the operational amplifier and inputs the image signal to the operational amplifier, and when charge equivalent to the offset voltage generated in the operational amplifier is accumulated in the capacitor, controls the image signal to be input to the operational amplifier together with the charge accumulated in the capacitor while maintaining the connection between the load and the output terminal of the operational amplifier.

[0004] However, when attempting to perform voltage amplification with higher precision, noise occurs when the switch used to switch the capacitor's connection destination switches between a conductive state and a cutoff state. If the switch is configured with a transistor, noise occurs due to injection current, as described in Patent Document 2, for example. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-210687 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-19075 Summary of the Invention [Problem to be solved by the invention]

[0006] However, when the selector circuit described in Patent Document 2 is applied as a switch for the operational amplifier circuit described in Patent Document 1, the number of transistors constituting the switch is large, which causes a problem of an increase in circuit size. [Means for solving the problem]

[0007] One aspect of the operational amplifier circuit of the present invention includes an operational amplifier, a first switch having one end connected to the positive input terminal of the operational amplifier and the other end receiving an input signal, a second switch having one end connected to the negative input terminal of the operational amplifier, a third switch having one end connected to the other end of the second switch and the other end receiving an input signal, a capacitor connected between the positive input terminal of the operational amplifier and the other end of the second switch, and an offset cancellation control circuit that controls the on / off states of the first switch to the third switch, wherein each of the first switch to the third switch includes a switch transistor that is switched between a conductive state and a cutoff state based on an instruction from the offset cancellation control circuit, and a capacitance transistor that is arranged closer to the capacitor and connected in series with the switch transistor, has a source and a drain connected to each other, and has its conductive state controlled in reverse phase to that of the corresponding switch transistor.

[0008] The operational amplifier circuit according to the present invention has a switch transistor that functions as a switch, and a capacitance transistor that is connected in series with the switch transistor and functions as a capacitance element, so that the capacitance transistor absorbs the injection current that occurs when the conductive state of the switch transistor is switched. [Effects of the Invention]

[0009] According to the operational amplifier circuit of the present invention, an operational amplifier circuit that suppresses the influence of switch noise and input offset can be realized with a small circuit scale. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a circuit diagram of an operational amplifier circuit according to a first embodiment. [Figure 2] FIG. 2 is a detailed circuit diagram of the operational amplifier circuit according to the first embodiment. [Figure 3] 4 is a timing chart showing the operation of the operational amplifier circuit according to the first embodiment. [Figure 4]FIG. 10 is a circuit diagram of an operational amplifier circuit according to a second embodiment. [Figure 5] FIG. 10 is a circuit diagram of an operational amplifier circuit according to a third embodiment. [Figure 6] 10 is a first circuit example of an operational amplifier circuit according to a fourth embodiment. [Figure 7] 10 is a second circuit example of the operational amplifier circuit according to the fourth embodiment. [Figure 8] 10 is a third circuit example of the operational amplifier circuit according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiment 1 For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In addition, the same elements in each drawing are given the same reference numerals, and duplicate explanations have been omitted as necessary.

[0012] First, Fig. 1 shows a circuit diagram of an operational amplifier circuit according to the first embodiment. As shown in Fig. 1, the operational amplifier circuit 1 includes an operational amplifier 10, an offset cancellation control circuit 12, and an offset cancellation circuit 20. Fig. 1 also shows an example in which a closed-loop gain is set in the operational amplifier circuit 1 by inserting a feedback circuit 11 between the output terminal and the negative input terminal of the operational amplifier 10. Various circuits are possible for the feedback circuit 11, and specific examples will be described in detail later.

[0013] The offset cancellation control circuit 12 outputs a control signal that switches the on / off state of a switch provided in the offset cancellation circuit 20. In the example shown in FIG. 1, the offset cancellation control circuit 12 outputs a calibration control signal CAL and an output monitor signal MONI. The calibration control signal CAL is a signal that controls the accumulation of charge corresponding to the input offset voltage of the operational amplifier 10 in a cancellation capacitor Cofs connected between the positive and negative input terminals of the operational amplifier 10 in a calibration state. The output monitor signal MONI is a signal that controls the offset cancellation circuit 20 to an output monitor state in which the operational amplifier 10 outputs an output signal VO based on the input signal VI with the input offset voltage canceled.

[0014] The offset cancellation circuit 20 transmits the input signal VI to the positive input terminal of the operational amplifier 10, and applies a correction to the input signal VI to cancel the input offset voltage ΔVds of the operational amplifier 10. In addition, the offset cancellation circuit 20 switches the operational amplifier 10 between a calibration state and an output monitor state in response to input of a calibration control signal CAL and an output monitor signal MONI.

[0015] Specifically, the offset cancellation circuit 20 includes a first switch 21, a second switch 22, a third switch 23, and a cancellation capacitor Cofs. One end of the first switch 21 is connected to the positive input terminal of the operational amplifier 10, and the other end receives an input signal VI. One end of the second switch 22 is connected to the negative input terminal of the operational amplifier 10. One end of the third switch 23 is connected to the other end of the second switch 22, and the other end receives the input signal VI. The cancellation capacitor Cofs is connected between the positive input terminal of the operational amplifier 10 and the other end of the second switch 22. The set of the first switch 21 and the second switch 22 and the third switch are controlled exclusively with each other.

[0016] One of the features of the operational amplifier circuit according to the first embodiment is the configuration of the first switch 21 to the third switch 23. A detailed circuit diagram of the operational amplifier circuit according to the first embodiment is shown in Fig. 2. Fig. 2 shows the detailed circuit configuration of the first switch 21 to the third switch 23.

[0017] As shown in FIG. 2, the first switch 21 to the third switch 23 each have a switch transistor (e.g., switch transistors Tr1 to Tr3) and a capacitance transistor (e.g., capacitance transistors CTr1 to CTr3). The switch transistors Tr1 to Tr3 are switched between a conductive state and a cut-off state based on an instruction from the offset cancellation control circuit 12. The capacitance transistors CTr1 to CTr3 are connected in series with the switch transistors Tr1 to Tr3 while being arranged closer to the cancellation capacitor Cofs, with their sources and drains connected to each other and their conductive states controlled in reverse phase to the corresponding switch transistors. The capacitance transistors CTr1 to CTr3 function as capacitors when a low-level signal is applied to their gates, and function as wiring when a high-level signal is applied to their gates.

[0018] Furthermore, when the gate lengths of the switch transistors Tr1 to Tr3 and the capacitance transistors CTr1 to CTr3 are set to be the same, the gate width of the switch transistors Tr1 to Tr3 is set to be twice as long as that of the capacitance transistors CTr1 to CTr3.

[0019] More specifically, the first switch 21 has a switch transistor Tr1 and a capacitance transistor CTr1. An input signal VI is applied to one of the source and drain of the switch transistor Tr1, and the other of the source and drain is connected to one of the source and drain of the capacitance transistor CTr1. A calibration control signal CAL is applied to the gate of the switch transistor Tr1. The source and drain of the capacitance transistor CTr1 are connected to each other, and an inverted signal of the calibration control signal CAL is applied to the gate.

[0020] The second switch 22 has a switch transistor Tr2 and a capacitance transistor CTr2. One of the source and drain of the switch transistor Tr2 is connected to the negative input terminal of the operational amplifier 10, and the other of the source and drain is connected to one of the source and drain of the capacitance transistor CTr2. A calibration control signal CAL is applied to the gate of the switch transistor Tr2. The source and drain of the capacitance transistor CTr2 are connected to each other, and an inverted signal of the calibration control signal CAL is applied to the gate. The other of the source and drain of the capacitance transistor CTr2 is connected to a cancel capacitor Cofs.

[0021] The third switch 23 has a switch transistor Tr3 and a capacitance transistor CTr3. An input signal VI is applied to one of the source and drain of the switch transistor Tr3, and the other of the source and drain is connected to one of the source and drain of the capacitance transistor CTr3. An output monitor control signal MONI is applied to the gate of the switch transistor Tr3. The source and drain of the capacitance transistor CTr3 are connected to each other, and an inverted signal of the output monitor signal MONI is applied to the gate. The other of the source and drain of the capacitance transistor CTr3 is connected to a cancel capacitor Cofs.

[0022] Next, the operation of the operational amplifier circuit 1 according to the first embodiment will be described. Fig. 3 shows a timing chart illustrating the operation of the operational amplifier circuit 1 according to the first embodiment. As shown in Fig. 3, the operational amplifier circuit 1 switches between a calibration state and an output monitor state by switching the logic levels of the calibration control signal CAL and the output monitor signal MONI output by the offset cancellation control circuit 12.

[0023] Specifically, in the calibration state of the operational amplifier circuit 1, the calibration control signal CAL is set to a high level and the output monitor signal MONI is set to a low level, thereby turning the first switch 21 and the second switch 22 on and the third switch off. As a result, the operational amplifier circuit 1 is configured such that the input signal VI is transmitted to the operational amplifier 10 and the cancellation capacitor Cofs is connected between the positive and negative input terminals of the operational amplifier 10. In this calibration state, the offset cancellation circuit 20 accumulates a charge equivalent to the input offset voltage ΔVds of the operational amplifier 10 in the cancellation capacitor Cofs.

[0024] On the other hand, in the output monitor state, the operational amplifier circuit 1 sets the calibration control signal CAL to a low level and the output monitor signal MONI to a high level, thereby turning the first switch 21 and the second switch 22 off and turning the third switch on. This causes the operational amplifier circuit 1 to have a circuit configuration in which the input signal VI is transmitted to the operational amplifier 10 via the cancellation capacitor Cofs. In this output monitor state, the offset cancellation circuit 20 transmits the input signal VI to the operational amplifier 10 with the cancellation capacitor Cofs offsetting the input signal VI by the input offset voltage ΔVds. This corrects the input offset of the operational amplifier circuit 1.

[0025] As described above, the operational amplifier circuit 1 according to the first embodiment switches the on / off states of the first switch 21 to the third switch 23, but when the switch transistors Tr1 to Tr3 switch from a conductive state to a cut-off state, an injection current flows through the parasitic capacitance formed between the gate and source (or drain), and this injection current causes a deviation in the charge stored in the cancel capacitor Cofs, or switch noise is amplified by the operational amplifier 10, affecting the output signal VO and reducing accuracy. However, in the operational amplifier circuit 1, a capacitance capacitor is provided on the cancel capacitor Cofs side of the switch transistor to absorb the injection current generated by the switching of the switch transistor, thereby preventing noise generated by the switching of the switch transistor from being transmitted to the cancel capacitor Cofs or the operational amplifier 10.

[0026] 3, when the offset cancellation control circuit 12 switches the operational amplifier circuit 1 from the calibration state to the output monitor state, it provides a dead time period (for example, timings T2 to T3 and T5 to T6 in FIG. 3) during which all switches are in the OFF state. By providing this dead time period, it is possible to prevent the operation of the operational amplifier 10 from affecting the charge accumulated in the cancel capacitor Cofs in the output monitor state. In other words, providing the dead time period can reduce the difference between the amount of charge accumulated in the cancel capacitor Cofs and the input offset voltage ΔVds of the operational amplifier 10.

[0027] The cycle at which the offset cancellation control circuit 12 switches the logic levels of the calibration control signal CAL and the output monitor signal MONI, and the ratio between the calibration state and the output monitor state can be set arbitrarily depending on the specifications of the operational amplifier circuit 1.

[0028] As described above, the operational amplifier circuit 1 according to the first embodiment can prevent noise caused by injection current into the cancellation capacitor Cofs by arranging the capacitance transistor in series with the switch transistor on the cancellation capacitor Cofs side of the switch transistor. This allows the operational amplifier circuit 1 according to the first embodiment to improve the correction accuracy of the input offset voltage ΔVds while suppressing an increase in circuit size.

[0029] Furthermore, in the operational amplifier circuit 1 according to the first embodiment, when switching from the calibration state to the output monitor state, a dead time period is provided in which the first switch 21 to the third switch 23 are all in the OFF state, thereby improving the accuracy of charge accumulation in the cancel capacitor Cofs.

[0030] Embodiment 2 In the second embodiment, another example of the configuration of the switches in the operational amplifier circuit 1 of the first embodiment will be described. In the description of the second embodiment, the components described in the first embodiment will be assigned the same reference numerals as in the first embodiment, and the description thereof will be omitted.

[0031] Fig. 4 shows a circuit diagram of the operational amplifier circuit 2 according to the second embodiment. As shown in Fig. 4, the operational amplifier circuit 2 according to the second embodiment uses PMOS transistors as transistors constituting the first switch 21 to the third switch 23.

[0032] Although not shown, in the operational amplifier circuit 2 according to the second embodiment, the control logic of the calibration control signal CAL and the output monitor signal MONI output by the offset cancellation control circuit 12 is inverted compared to that in the first embodiment.

[0033] In the operational amplifier circuit 1 according to the first embodiment, which uses NMOS transistors as transistors constituting the switches, a problem occurs in that the resistance of the switches increases when the voltage of the input signal VI becomes high (for example, a voltage equal to or higher than half the voltage of the input dynamic range of the operational amplifier 10). However, in the operational amplifier circuit 2 according to the second embodiment, which uses PMOS transistors as transistors constituting the switches, the resistance of the switches can be reduced even when the voltage of the input signal VI is high. In other words, the operational amplifier circuit 1 according to the first embodiment is advantageous when the amplitude of the input voltage VI is in a low voltage range, and the operational amplifier circuit 2 according to the second embodiment is advantageous when the amplitude of the input voltage VI is in a high voltage range.

[0034] Embodiment 3 In the third embodiment, another example of the configuration of the switches in the operational amplifier circuit 1 of the first embodiment will be described. In the description of the third embodiment, the components described in the first embodiment will be assigned the same reference numerals as in the first embodiment, and the description thereof will be omitted.

[0035] 5 shows a circuit diagram of the operational amplifier circuit 3 according to the third embodiment. As shown in Fig. 5, the operational amplifier circuit 3 according to the third embodiment uses transfer switches as transistors constituting the first switch 21 to the third switch 23.

[0036] More specifically, the first switch 21 comprises a transfer switch including a switch transistor Tr1n and a switch transistor Tr1p. The first switch 21 also includes a capacitance transistor CTr1n and a capacitance transistor CTr1p on the cancel capacitor Cofs side of the switch transistor Tr1n and the switch transistor Tr1p. The pair of the switch transistor Tr1n and the capacitance transistor CTr1p and the pair of the switch transistor Tr1p and the capacitance transistor CTr1n are controlled by signals of opposite phases.

[0037] The second switch 22 comprises a transfer switch made up of a switch transistor Tr2n and a switch transistor Tr2p. The second switch 22 also includes a capacitance transistor CTr2n and a capacitance transistor CTr2p on the cancel capacitor Cofs side of the switch transistor Tr2n and the switch transistor Tr2p. The pair of the switch transistor Tr2n and the capacitance transistor CTr2p and the pair of the switch transistor Tr2p and the capacitance transistor CTr2n are controlled by signals of opposite phases.

[0038] The third switch 23 comprises a transfer switch made up of a switch transistor Tr3n and a switch transistor Tr3p. The third switch 23 also includes a capacitance transistor CTr3n and a capacitance transistor CTr3p on the cancel capacitor Cofs side of the switch transistor Tr3n and the switch transistor Tr3p. The pair of the switch transistor Tr3n and the capacitance transistor CTr3p and the pair of the switch transistor Tr3p and the capacitance transistor CTr3n are controlled by signals of opposite phases.

[0039] In the operational amplifier circuit 3 according to the third embodiment, the first switch 21 to the third switch 23 are configured as transistors with a transfer switch configuration, which has the advantage that the resistance of the switches can be kept low even when the amplitude of the input signal VI is large (for example, an amplitude range similar to the input dynamic range of the operational amplifier 10).

[0040] Embodiment 4 In the fourth embodiment, a specific example of the feedback circuit 11 shown in the first embodiment will be described. First, FIG. 6 shows an operational amplifier circuit 4a, which is a first circuit example of the operational amplifier circuit according to the fourth embodiment. In the first circuit example shown in FIG. 6, the wiring connecting the output terminal and the negative input terminal of the operational amplifier 10 is shown as a feedback circuit 11a. By including this feedback circuit 11a, the operational amplifier circuit 4a according to the fourth embodiment forms a buffer circuit that outputs an output signal VO having the same voltage value as the input signal VI.

[0041] FIG. 7 shows an operational amplifier circuit 4b, which is a second circuit example of an operational amplifier circuit according to the fourth embodiment. In the operational amplifier circuit 4b, resistors R1 and R2 are connected in series between the output terminal and the ground terminal of an operational amplifier 10, and a wiring is shown connecting the junction of the resistors R1 and R2 to the negative input terminal of the operational amplifier 10. In this operational amplifier circuit 4b, a feedback circuit 11b includes a resistor R1 and a wiring connecting the junction of the resistors R1 and R2 to the negative input terminal of the operational amplifier 10. By including this feedback circuit 11b, the operational amplifier circuit 4b according to the fourth embodiment forms an inverting amplifier whose gain is determined by the resistance ratio of the resistors R1 and R2.

[0042] FIG. 8 shows an operational amplifier circuit 4c, a third circuit example of an operational amplifier circuit according to the fourth embodiment. In the operational amplifier circuit 4c, a resistor R11, a PMOS level shift transistor PTrp, and a resistor R12 are connected in series between an input power supply VIN and a ground terminal, in that order from the input power supply side toward the ground terminal side. The gate of the PMOS level shift transistor PTrp is driven by the output signal of the operational amplifier 10. The operational amplifier circuit 4c includes a wiring connecting the junction between the resistor R11 and the PMOS level shift transistor PTrp to the negative input terminal of the operational amplifier 10. In this operational amplifier circuit 4c, a feedback circuit 11c includes the PMOS level shift transistor PTrp and a wiring connecting the junction between the resistor R11 and the PMOS level shift transistor PTrp to the negative input terminal of the operational amplifier 10. By including this feedback circuit 11c, the operational amplifier circuit 4c according to the fourth embodiment constitutes a level shift circuit having an amplification function that outputs an output signal VO corresponding to the input signal and the values ​​of R11 and R12 via the operational amplifier 10.

[0043] The configuration including the operational amplifier 10, offset cancellation control circuit 12, and offset cancellation circuit 20 described in the first to third embodiments can improve the accuracy of the output voltage of the operational amplifier 10 for feedback circuits 11 having various circuit types, while suppressing an increase in the circuit size of the offset cancellation control circuit 12, and reducing the influence of injection current generated due to switching.

[0044] The present invention is not limited to the above-described embodiment, and can be modified as appropriate within the scope of the invention. [Explanation of symbols]

[0045] 1~3, 4a~4c Op-amp circuits 10 operational amplifiers 11, 11a to 11c Feedback circuit 12 Offset cancellation control circuit 20 Offset cancellation circuit 21 First Switch 22 Second Switch 23 The Third Switch Tr Switch Transistor CTr Capacitor Transistor Cofs Cancellation Capacitor CAL Calibration control signal MONI Output monitor signal ΔVds Input offset voltage

Claims

1. An operational amplifier and a first switch having one end connected to the positive input terminal of the operational amplifier and having the other end to which an input signal is applied; a second switch having one end connected to the negative input terminal of the operational amplifier; a third switch having one end connected to the other end of the second switch and having the other end to which an input signal is applied; a capacitor connected between the positive input terminal of the operational amplifier and the other end of the second switch; an offset cancellation control circuit that controls the on / off states of the first switch to the third switch, The first switch to the third switch each include: a switch transistor that is switched between a conductive state and a cut-off state based on an instruction from the offset cancellation control circuit; a capacitance transistor that is arranged closer to the capacitor and connected in series with the switch transistor, the source and drain of which are connected to each other, and the conduction state of which is controlled in reverse phase to the corresponding switch transistor.

2. 2. The operational amplifier circuit according to claim 1, wherein when the gate lengths of the switch transistor and the capacitance transistor are set to be the same, the gate width of the switch transistor is set to be twice as long as that of the capacitance transistor.

3. The offset cancellation control circuit includes: a calibration state is established in which the operational amplifier outputs an output signal based on the input signal by turning on the pair of the first switch and the second switch and turning off the third switch; an output monitor state is established in which a charge corresponding to the input offset voltage of the operational amplifier is accumulated in the capacitor by turning off the pair of the first switch and the second switch and turning on the third switch; 2. The operational amplifier circuit according to claim 1, wherein, when switching from the calibration state to the output monitor state, the third switch is maintained in an off state for a preset dead time period after the pair of the first switch and the second switch is changed from an on state to an off state, and then the third switch is switched to an on state.

4. 2. The operational amplifier circuit according to claim 1, further comprising a feedback circuit for transmitting an output signal of said operational amplifier to a negative input terminal of said operational amplifier.

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