Switching power supply device

Abstract

To provide a switching power supply device with COT control that can minimize a withstand voltage of an element while expanding a range of an input voltage Vin and suppressing variations in a control frequency.SOLUTION: A Ton calculation circuit 10 generates a time for maintaining an ON state of an FET. A current source circuit 11 has a high withstand voltage FET 21 that applies an input voltage Vin to a first resistive element R1, and performs V / I conversion via the first resistive element R1. A reference voltage circuit 12 generates a reference voltage Vc by including a parallel circuit of a second resistive element R2 and a capacitor C connected between an input switch 16 which intermittently switches the V / I-converted current on the basis of a switching control signal D, and a ground, and a low-pass filter circuit 17. A ramp wave generation circuit 13 has a capacitor C2 supplied with a current output from the current source circuit 11 and generates a ramp wave signal Vramp2. A comparator 14 compares the reference voltage VC with the ramp wave signal Vramp2.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a switching power supply device that generates a stepped-down output voltage by controlling the switching of an input voltage using a switching element. [Background technology]

[0002] COT (Constant On Time) control, which is a control method for switching power supplies, has excellent responsiveness of the output voltage, but has a technical problem in that the frequency varies depending on the input voltage and load current. To address this problem, Patent Document 1 proposes a method for controlling a reference voltage Vin that depends on the input voltage Vin. The reference voltage is generated by switching the inverter circuit connected between Vref1 and ground and smoothing it through a low-pass filter. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 8,531,166 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above configuration, when the voltage Vref1 shown in Figure 7 of Patent Document 1 is high, it is necessary to increase the breakdown voltage of the gate of the switching element and the capacitance element. On the other hand, when this voltage is low, there is a risk of insufficient gate voltage. Because the reference voltage Vref1 depends on the input voltage Vin, if the voltage range becomes narrower, there is an issue that the operating range of the switching power supply also becomes narrower. Furthermore, if there is variation in the voltages Vref2 and VC shown in the same figure, there is also an issue that the on-time Ton of the switching element will vary, resulting in variation in the frequency of COT control.

[0005] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a COT controlled switching power supply device that can minimize the number of high voltage withstand elements even when the range of input voltage Vin is expanded, and that can suppress variations in control frequency. [Means for solving the problem]

[0006] According to the switching power supply device of claim 1, an input voltage is switched and controlled by switching elements (1, 2) to generate an output voltage. An on-timing generating unit (5) generates timing for turning on the switching elements, and an on-time generating unit (10) generates time for maintaining the on state of the switching elements. A current source circuit (11, 41) of the on-time generating unit has a high-voltage input switching element that applies the input voltage to a first resistor element (R1), and V / I conversion is performed by the first resistor element.

[0007] The reference voltage circuit (12) includes an input switch (16) for intermittently supplying the V / I converted current based on the switching control signal, a parallel circuit of a second resistive element (R2) and a first capacitive element (C) connected between the input switch and ground, and a low-pass filter circuit (17). The ramp wave generating circuit (13) generates a ramp wave signal by charging and discharging the second capacitive element (C2), which receives the current output from the current source circuit, using a charge / discharge switch (18). The comparison circuit (14) compares the reference voltage with the ramp wave signal.

[0008] In a current source circuit, the input voltage is received by a high-voltage input switching element, allowing other circuit elements connected to this input switching element to use low-voltage elements. In a reference voltage circuit, the reference voltage output from the low-pass filter circuit can be adjusted by intermittently supplying current from the current source circuit using an input switch. The input current supplied from the current source circuit is a current dependent on the input voltage, having undergone V / I conversion by a first resistor element. Variations can be suppressed by using the same material for the second resistor element as for the first resistor element. Furthermore, because both the reference voltage and the ramp wave signal are generated based on the input current, frequency variations in COT control can be suppressed.

[0009] According to a switching power supply device of claim 2, a first current mirror circuit (24) constituting a current source circuit is connected between a first resistor element and ground and mirrors the current flowing through the first resistor element. A second current mirror circuit (35) generates an error current by applying the threshold voltage of a transistor constituting the first current mirror circuit to the first resistor element. An error current supply circuit (30) supplies the error current to a common connection point between the first resistor element and a main transistor (22) constituting the first current mirror circuit. A V / I converted current is then supplied to an output transistor (38) that forms a mirror pair with the main transistor. Note that a "main transistor" is a transistor arranged in a path through which a main current flows in a current mirror circuit, and a transistor arranged in a mirror current path through which a current mirrored from the main current flows is called a "secondary transistor."

[0010] The current converted from V / I by the first resistor element contains an error in the input voltage equivalent to the threshold voltage of the main transistor that makes up the first current mirror circuit. Therefore, the error current supply circuit cancels out the threshold voltage error by passing the error current generated by the second current mirror circuit through the common connection point between the first resistor element and the main transistor that makes up the first current mirror circuit. The transistors that make up the first current mirror circuit are the same as those used for the input switching element. The current with the error canceled out is mirrored to produce the final output current of the current source circuit.

[0011] According to a switching power supply device of claim 3, a first current mirror circuit (44) constituting a current source circuit (41) is connected to the power supply side and flows a V / I converted current through a mirror current path. A second current mirror circuit (50) is connected between the ground side and the first current mirror circuit, and the mirror current path serves as a main current path. A threshold voltage generating transistor (51) is connected between ground and a main transistor (49) constituting the second current mirror circuit. A third resistor element (R3) is connected between ground and a secondary transistor (48) constituting the second current mirror circuit, and its resistance value is set equal to that of the first resistor element.

[0012] A series circuit of first and second output transistors (52 and 53) is provided between the output terminal of the current source circuit and ground, and the first output transistor forms a mirror pair with the main transistor of the second current mirror circuit. The conduction control terminals of the threshold voltage generating transistor and the second output transistor are connected to a common connection point between the sub transistor of the second current mirror circuit and the third resistor element, and the mirror ratio of the first current mirror circuit is set to 1:2.

[0013] Here, the input voltage is Vin, and the threshold voltage of the main transistor of the second current mirror circuit is V th1 , the threshold voltage of the threshold voltage generating transistor is V th2 ,The resistance values ​​of the first and third resistor elements are R1 and R3, respectively. Then, the current I1 flowing through the first resistor element is (Vin-Vth1 -V th2 ) / R1. The current I3 flowing through the third resistor element is (V th1 ) / R3.

[0014] The current I2 is doubled by the mirror ratio of the first current mirror circuit and added to the current I1. Therefore, the main current path of the second current mirror circuit has the following current I2 I2=(Vin-V th1 -V th2 ) / R1+2(V th1 ) / R3 V th1 =V th2 If R1 = R3, then I2C = Vin / R1, and the mirrored current I2C becomes the final output current of the current source circuit. With this configuration, the current obtained by directly V / I converting the input voltage using the first resistor element becomes smaller, thereby reducing current consumption. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a switching power supply device according to a first embodiment. [Figure 2] The diagram shows the configuration of the ON timing generation circuit. [Figure 3] Diagram showing the configuration of the Ton time generation circuit [Figure 4] Circuit diagram showing the detailed configuration of the current source circuit [Figure 5] Waveform diagram of each signal showing the operation of the Ton time generation circuit [Figure 6] Waveform diagram of each signal showing the operation of COT control [Figure 7] FIG. 2 is a circuit diagram showing a detailed configuration of a current source circuit according to a second embodiment. [Figure 8] 1 shows an example of the configuration of an ON timing generation circuit and other circuits. [Figure 9] Diagram showing another example of power stage configuration (part 1) [Figure 10] Diagram showing another example of power stage configuration (part 2) [Figure 11]Diagram showing another example of power stage configuration (part 3) DETAILED DESCRIPTION OF THE INVENTION

[0016] (First embodiment) The first embodiment will be described below. As shown in Fig. 1, switching elements 1 and 2, such as N-channel MOSFETs, are connected in series between an input power supply Vin and ground. The common connection point of the switching elements 1 and 2 is connected to ground via a series circuit of an inductor 3 and a capacitor 4. The common connection point of the inductor 3 and the capacitor 4 serves as an output terminal for a voltage VOUT.

[0017] The output voltage VOUT is input to an ON timing generation circuit 5. As shown in FIG. 2, the ON timing generation circuit 5 includes a series circuit of resistor elements 6 and 7 connected between the output voltage VOUT and ground, and a comparator 8. The common connection point of the resistor elements 6 and 7 is connected to the inverting input terminal of the comparator 8, to which a voltage FB obtained by dividing the output voltage VOUT is input. A reference voltage VREF is applied to the non-inverting input terminal of the comparator 8. The output terminal of the comparator 8 is connected to the set terminal S of an RS flip-flop 9.

[0018] 3, the Ton time generation circuit 10 includes a current source circuit 11, a reference voltage circuit 12, a ramp wave generation circuit 13, and a comparator 14, which is a comparison circuit. Between the input power supply Vin and ground, a series circuit of the current source circuit 11, a coefficient multiplier 15 that constitutes the ramp wave generation circuit 13, and a capacitor C2 is connected. A common connection point of the current source circuit 11 and the coefficient multiplier 15 is connected to a movable contact of an input switch 16 that constitutes the reference voltage circuit 12.

[0019] A fixed contact a of the input switch 16 is connected to the inverting input terminal of the comparator 14 via a resistor R, and is also connected to ground via a parallel circuit of a capacitor C, which is a first capacitance element, and a second resistor R2. A fixed contact b of the input switch 16 is connected to ground. A capacitor C1 is connected between the inverting input terminal of the comparator 14 and ground, and the capacitor C1 and the resistor R form a low-pass filter circuit 17. The output terminal of the low-pass filter circuit 17 is the output terminal of the reference voltage circuit 12, and outputs a voltage VC.

[0020] As will be described later, the switching of the movable contact of the input switch 16 is controlled by a switching control signal D output from an output terminal Q of the RS flip-flop 9. The movable contact is connected to a fixed contact a while the switching control signal D indicates a high level, and is connected to a fixed contact b while the signal D indicates a low level.

[0021] The common connection point of the coefficient multiplier 15 and the capacitor C2, which is the second capacitance element, is connected to the non-inverting input terminal of the comparator 14 and also to ground via the switch 18. The on / off of the switch 18 is controlled by a signal DB obtained by inverting the logic of the switching control signal D, and the switch 18 is turned on while the signal DB indicates a high level. The ramp wave generating circuit 13 outputs a ramp wave signal Vramp2 to the comparator 14. The "duty cycle information" shown in FIG. 1 means the switching control signal D and its inverted signal DB.

[0022] In FIG. 1, the output terminal of comparator 14 is connected to the reset terminal R of RS flip-flop 9. The output terminal Q of RS flip-flop 9 is connected to the input terminal of pre-driver 19. When RS flip-flop 9 is set and the output terminal Q becomes high level, pre-driver 19 turns switching element 1 ON and switching element 2 OFF. At this time, capacitor 4 is charged via inductor 3. When RS flip-flop 9 is reset and the output terminal Q becomes low level, pre-driver 19 turns switching element 1 OFF and switching element 2 ON. At this time, capacitor 4 is discharged via inductor 3.

[0023] If the signal output from output terminal Q is D, switch 18 of ramp wave generating circuit 13 is turned on by signal DB, which is the inverse of signal D. ON timing generating circuit 6 sets RS flip-flop 9 and sets signal D to high level based on the result of comparing the voltage obtained by dividing output voltage VOUT with a reference voltage. RS flip-flop 9 is reset dominant. The above constitutes switching power supply device 20.

[0024] 4, a series circuit of an N-channel MOSFET 21, a resistor element R1, and an N-channel MOSFET 22 is connected between an input voltage Vin and ground. The gate of the FET 21, which is a conduction control terminal, serves as an enable terminal of the current source circuit 11. The N-channel MOSFET 23 and the FET 22 form a first current mirror circuit 24, and the gates of both are connected to the drain of the FET 22.

[0025] A current mirror circuit 27 consisting of P-channel MOSFETs 25 and 26 is connected to the power supply VCC side, with the gates of both connected to the drain of FET 25. Similarly, a current mirror circuit 30 consisting of P-channel MOSFETs 28 and 29 is connected, with the gates of both connected to the drain of FET 28. The current mirror circuit 30 corresponds to the error current supply circuit.

[0026] The drain of FET 25 is connected to the drain of FET 23 via an N-channel MOSFET 31. The drain of FET 26 is connected to ground via N-channel MOSFETs 32 and 33. The drain of FET 28 is connected to ground via an N-channel MOSFET 34 and a resistor R1. The resistor R1 is the same type of resistor as the resistor R1, but with a resistance value set equal to that of the resistor R1. FETs 32 and 34 form a second current mirror circuit 35, with their gates connected to the drain of FET 32.

[0027] The drain of FET 29 is connected to the gate and source of N-channel MOSFET 36 and the drain of FET 22. The gate of FET 24 and the drain of FET 36 are connected to the drain of FET 32. A series circuit of N-channel MOSFETs 37 and 38 is connected between the output terminal of the current source circuit 11 and ground. The gate of FET 37 is connected to the drain of FET 32, and the gate of FET 38 is connected to the drain of FET 22. Of the elements constituting the current source circuit 11, only FET 21, which is the input switching element, is a high-voltage element, and the other FETs are low-voltage elements.

[0028] Next, the operation of this embodiment will be described. In the current source circuit 11, the current I is converted into V / I by the resistor element R1 via the FET 21. R1a If the threshold voltage of the FET 22 is Vgs, then I R1a =(Vin-Vgs) / R1 The error is the threshold voltage Vgs. The current I R1b If the threshold voltage of FET33 is also Vgs, I R1b =Vgs / R1 is.

[0029] This current is mirrored by the current mirror circuit 30 and supplied to the drain of the FET 22. Then, the current is (I R1a+I R1b ) so I R1a +I R1b =(Vin-Vgs) / R1+Vgs / R1=Vin / R1 This current (Vin / R1) is mirrored by the current mirror circuit of FETs 22 and 38 and flows to the output terminal of current source circuit 11. Therefore, the output current of current source circuit 11 is V / I converted so that it becomes a current that depends only on the input current Vin.

[0030] 5, the Ton time generation circuit 10 operates by comparing the level of the sawtooth wave Vramp2 generated by the ramp wave generation circuit 13 with the reference voltage VC generated by the reference voltage circuit 12 using the comparator 14. When the level of the sawtooth wave Vramp2 reaches the reference voltage VC, the comparator 14 goes high, resetting the RS flip-flop 9. The time it takes for the level of the sawtooth wave Vramp2 to reach the reference voltage VC from zero is the time during which the FET1 remains on.

[0031] Therefore, the switching control signal D output by the RS flip-flop 9 has a constant switching frequency Tsw, as shown in Figure 6, and COT control is performed. Since both the sawtooth wave Vramp2 and the reference voltage VC are generated based on the input voltage Vin, any variations in the input voltage Vin are canceled out when the switching control signal D is generated.

[0032] As described above, according to this embodiment, the switching power supply device 20 controls the switching of the input voltage Vin using FETs 1 and 2 to generate the output voltage VOUT. The ON timing generation circuit 5 generates the timing to turn on FET 1, and the Ton calculation circuit 10 generates the time for which FET 1 is maintained in the ON state. The current source circuit 11 has a high-voltage FET 21 that applies the input voltage Vin to the first resistor element R1, and performs V / I conversion using the first resistor element R1.

[0033] The reference voltage circuit 12 generates a reference voltage VC and includes an input switch 16 for intermittently supplying the V / I converted current based on a switching control signal D, a parallel circuit of a second resistor R2 and a capacitor C connected between the input switch 16 and ground, and a low-pass filter circuit 17. The ramp wave generating circuit 13 has a capacitor C2 supplied with the current output from the current source circuit 11 and generates a ramp wave signal Vramp2. The comparator 14 compares the reference voltage VC with the ramp wave signal Vramp2.

[0034] In the current source circuit 11, the input voltage Vin is received by the high-voltage FET 21, allowing other circuit elements connected to this FET 21 to use low-voltage elements. In the reference voltage circuit 12, the reference voltage VC output from the low-pass filter circuit 17 can be adjusted by intermittently supplying current from the current source circuit 11 via the input switch 16. The input current supplied from the current source circuit 11 is a current dependent on the input voltage Vin, having been V / I converted by the first resistor R1. Variations can be suppressed by using the same material for the second resistor R2 as for the first resistor R1. Furthermore, because both the reference voltage VC and the ramp signal Vramp2 are generated based on the input current, frequency variations in COT control can be suppressed.

[0035] The first current mirror circuit 24, which constitutes the current source circuit 11, is connected between the first resistor R1 and ground and mirrors the current flowing through the first resistor R1. The second current mirror circuit 35 generates an error current by applying the threshold voltage Vgs of the FET 22, which constitutes the first current mirror circuit 24, to the first resistor R1. The current mirror circuit 30 passes this error current to the common connection point between the first resistor R1 and the FET 22. The current mirror circuit 30 then passes a V / I converted current through the FET 38, which forms a mirror pair with the FET 22.

[0036] The current V / I converted by the first resistor R1 contains an error corresponding to the threshold voltage Vgs of the FET 22 with respect to the input voltage Vin. Therefore, the current mirror circuit 30 cancels out the error corresponding to the threshold voltage by causing the error current generated by the second current mirror circuit 35 to flow to the common connection point between the first resistor R1 and the FET 22. The current with the error canceled out is then mirrored to become the final output current of the current source circuit 11.

[0037] (Second embodiment) In the following, the same parts as in the first embodiment are denoted by the same reference numerals and their explanations are omitted, and only the differences will be explained. In the second embodiment, a current source circuit 41 shown in FIG. 7 is used instead of the current source circuit 11. A first current mirror circuit 44 consisting of P-channel MOSFETs 42 and 43 is connected to the power supply side, and the gates of both are connected to the drain of the FET 42. A current mirror circuit 47 consisting of P-channel MOSFETs 45 and 46 is cascade-connected to the current mirror circuit 44, and the gates of both are connected to the drain of the FET 45. The mirror ratio of the first current mirror circuit 44 is 1:2.

[0038] A second current mirror circuit 50 consisting of N-channel MOSFETs 48 and 49 is cascade-connected to the current mirror circuit 47, with the gates of both connected to the drain of the FET 49. A third resistor R3 is connected between the source of the FET 48 and ground, and an FET 51 corresponding to a threshold voltage generating transistor is connected between the source of the FET 49 and ground. The gate of the FET 51 is connected to the source of the FET 48.

[0039] A series circuit of N-channel MOSFETs 52 and 53 is connected between the output terminal of the current source circuit 41 and ground. The gate of the FET 53 is connected to the source of the FET 48, and the gate of the FET 54 is connected to the drain of the FET 49. The input voltage Vin is applied to the source of the FET 48 via the series circuit of the first resistor R1 and the FET 21. The FETs 52 and 53 correspond to the first and second output transistors.

[0040] Next, the operation of the second embodiment will be described. If the threshold voltage of the FET 49 is Vth1 and the threshold voltage of the FET 52 is Vth2, the current I1 flowing through the first resistor R1 is I1=(Vin-Vth1-Vth2) / R1 The current I3 flowing through the third resistor element R3 is I3=(Vth1) / R3 This becomes:

[0041] The current I3 is doubled by the mirror ratio of the first current mirror circuit 44 and added to the current I1. Therefore, the main current path of the second current mirror circuit 50 is filled with the following current I2 I2=(Vin-Vth1-Vth2) / R1+2(Vth1) / R3 If Vth1=Vth2 and R1=R3, then I2=Vin / R1, and the current I2 mirrored by the FET 52 becomes the final output current of the current source circuit 41.

[0042] As described above, according to the second embodiment, the first current mirror circuit 44 constituting the current source circuit 41 is connected to the power supply side, and a V / I converted current flows through the mirror current path. The second current mirror circuit 50 is connected between the first current mirror circuit 44 and ground, and the mirror current path serves as the main current path. The FET 51 is connected between the FET 49 and ground, and the second resistor R2, whose resistance value is set equal to that of the first resistor, is connected between the FET 48 and ground.

[0043] A series circuit of FETs 52 and 53 is provided between the output terminal of the current source circuit 41 and ground, and the FET 52 forms a mirror pair with the FET 49. The gates of the FETs 51 and 53 are connected to the source of the FET 48. This reduces the current obtained by directly V / I converting the input voltage Vin using the first resistor element R1, thereby reducing current consumption.

[0044] (Other embodiments) 8 shows an ON timing generation circuit 55 that replaces the ON timing generation circuit 5. A multiplier 56 may be inserted into the inverting input terminal of the comparator 8 to superimpose a ripple voltage. 9 to 11 show other configuration examples of power stages that perform switching. FIG. 9 shows a configuration in which the switching element 1 and the inductor 3 are interchanged. FIG. 10 shows a configuration in which a diode 57 is arranged in place of the switching element 2. FIG. 11 shows a configuration in which a diode 57 is arranged in place of the switching element 1 in the configuration shown in FIG.

[0045] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0046] In the drawings, 1 indicates a switching element, 5 indicates an ON timing generation circuit, 8 indicates a capacitor, 10 indicates a Ton time generation circuit, 11 indicates a current source circuit, 12 indicates a reference voltage circuit, 13 indicates a ramp wave signal generation circuit, 14 indicates a comparator, 20 indicates a switching power supply device, 21 indicates an N-channel MOSFET, 24 indicates a first current mirror circuit, 30 indicates a current mirror circuit, and 35 indicates a first current mirror circuit.

Claims

1. An input voltage is switched by switching elements (1, 2) to generate an output voltage, an on-timing generating unit (5) that generates timing for turning on the switching element; an on-time generating unit (10) that generates a time for maintaining the on-state of the switching element, The on-time generating unit includes a current source circuit (11, 41) having a high-voltage input switching element (21) that applies the input voltage to a first resistor element (R1), and performing V / I conversion by the first resistor element; a reference voltage circuit (12) including an input switch for intermittently supplying the V / I converted current based on the switching control signal, a parallel circuit of a second resistor element (R2) and a first capacitor element (C) made of the same material as the first resistor element, connected between the input switch and ground, and a low-pass filter circuit (17); a ramp wave generating circuit (13) that generates a ramp wave signal and that includes a second capacitance element (C2) to which the current output from the current source circuit is supplied and a charge / discharge switch (18) that charges / discharges the second capacitance element based on the switching control signal; a comparison circuit (14) that compares the reference voltage with the ramp wave signal.

2. The current source circuit (11) includes a first current mirror circuit (24) connected between a first resistor element and ground, and mirroring a current flowing through the first resistor element; a second current mirror circuit (35) that generates an error current by applying a threshold voltage of a transistor that constitutes the first current mirror circuit to the first resistor; an error current supply circuit (30) that supplies the error current to a common connection point between the first resistor element and a main transistor (22) that constitutes the first current mirror circuit; 2. A switching power supply device according to claim 1, wherein the V / I converted current flows through an output transistor (38) that forms a mirror pair with the main transistor of the first current mirror circuit.

3. The current source circuit (41) includes a first current mirror circuit (44) connected to a power supply side and passing the V / I converted current through a mirror current path; a second current mirror circuit (50) connected between a ground side and the first current mirror circuit, the mirror current path being a main current path; a threshold voltage generating transistor (51) connected between ground and the main transistor constituting the second current mirror circuit; a third resistor (R3) connected between ground and the secondary transistor (48) constituting the second current mirror circuit, the third resistor (R3) having a resistance equal to that of the first resistor; a series circuit of a first output transistor (52) and a second output transistor (53) connected between the output terminal and ground; the first output transistor forms a mirror pair with the main transistor (49) of the second current mirror circuit; conduction control terminals of the threshold voltage generating transistor and the second output transistor are connected to a common connection point between the secondary transistor of the second current mirror circuit and the second resistor element; 2. The switching power supply device according to claim 1, wherein the mirror ratio of said first current mirror circuit is 1:2.

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