Field effect transistor

Abstract

To provide a field effect transistor capable of improving the current-voltage characteristic.SOLUTION: A field effect transistor includes a first well region (P-type well region 52) of a first conductivity type (P type), a source region SR of a second conductivity type (N type) formed in the first well region, a second well region (N-type well region 51) of the second conductivity type (N type), a drain region DR of the second conductivity type (N type) formed in the second well region, a gate electrode G1 disposed on a region adjacent to the source region SR, and an insulating region 18 disposed between an end part 51E of the second well region on the first well region side and the drain region DR. In plan view, the first well region includes a tapered region 51T with the width narrowing toward the first well region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to field effect transistors. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a field effect transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 153693

[0004] [overview] The present disclosure provides a field effect transistor capable of improving current-voltage characteristics.

[0005] The field effect transistor of the present disclosure comprises a first well region of a first conductivity type, a source region of a second conductivity type formed in the first well region, a second well region of a second conductivity type, a drain region of the second conductivity type formed in the second well region, a gate electrode arranged on a region adjacent to the source region, and an insulating region arranged between the end of the second well region on the first well region side and the drain region, and in a planar view, the second well region has a tapered region whose width narrows toward the first well region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor chip 100. As shown in FIG. [Figure 2] 2A and 2B are a diagram showing a longitudinal cross-sectional configuration of a device 50 according to the first embodiment (FIG. 2A) and a plan view (FIG. 2B). [Figure 3] 3A and 3B are a diagram showing a vertical cross-sectional configuration of the transistor shown in FIG. 2B taken along the line AA (FIG. 3A) and a diagram showing a vertical cross-sectional configuration taken along the line J (FIG. 3B). [Figure 4] 4A and 4B are a diagram showing a longitudinal cross-sectional configuration of a device 50 according to the second embodiment (FIG. 4A) and a plan view (FIG. 4B). [Figure 5] 5A and 5B are a diagram showing a vertical cross-sectional configuration of the transistor shown in FIG. 4B taken along the line AA (FIG. 5A) and a diagram showing a vertical cross-sectional configuration taken along the line J (FIG. 5B). [Figure 6] 6A and 6B are a diagram showing a longitudinal cross-sectional configuration of a device 50 according to the third embodiment (FIG. 6A) and a plan view (FIG. 6B). [Figure 7] 7A and 7B are a diagram showing a vertical cross-sectional configuration of the transistor shown in FIG. 6B along the arrow line AA (FIG. 7A) and a diagram showing a vertical cross-sectional configuration along the line J including the line J1 (FIG. 7B). [Figure 8] FIG. 8 is a diagram showing a vertical cross-sectional configuration of the transistor shown in FIG. 6(B) taken along line J, including line J0. [Figure 9] FIG. 9 is a diagram for explaining the planar shape of the edge of the insulating region 18. As shown in FIG. [Figure 10] FIG. 10 is a graph showing the relationship between the drain voltage Vd (V) and |Ibody / Id| (%). [Figure 11] FIG. 11 is a graph showing the relationship between drain voltage Vd (V) and Ibody (A). [Figure 12] 12A and 12B are a diagram showing a longitudinal cross-sectional configuration of the device 50 (FIG. 12A) and a plan view (FIG. 12B). [Figure 13] FIG. 13 is a diagram for explaining a planar configuration of a transistor. [Figure 14] FIG. 14 is a graph showing the relationship between the drain voltage Vd (V) and the drain current Id (A) of a transistor.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] FIG. 1 is a plan view of a semiconductor chip 100. As shown in FIG.

[0009] The semiconductor chip 100 (semiconductor device) has a rectangular parallelepiped shape. The semiconductor chip 100 has a first main surface 3 on one side. A back surface is located on the opposite side of the first main surface 3. The semiconductor chip 100 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the back surface. The thickness direction of the semiconductor chip 100 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The depth direction of the semiconductor chip 100 is defined as the positive direction of the Z-axis, and the negative direction of the Z-axis indicates the direction from the back surface of the semiconductor substrate toward the first main surface 3 (top surface).

[0010] The first main surface 3 and the back surface are each perpendicular to the Z axis. The planar shape (shape in plan view) of the first main surface 3 when viewed from the normal direction (Z axis direction) of the first main surface 3 is rectangular (quadrilateral). The back surface of the semiconductor substrate also has a rectangular (quadrilateral) shape in plan view. The first side surface 5A and the second side surface 5B, which constitute two opposing sides of the rectangle in plan view, each extend along the X axis direction. The third side surface 5C and the fourth side surface 5D, which constitute the other two opposing sides of the rectangle in plan view, each extend along the Y axis direction. These adjacent side surfaces are orthogonal in plan view, but can also intersect at an angle other than orthogonal.

[0011] The semiconductor chip 100 includes a plurality of device regions 10 provided on the first main surface 3. There is a gap between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the semiconductor chip 100. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0012] Various devices are formed in each device region 10. At least one device region 10 includes a device 50.

[0013] An example of the device 50 is a field-effect transistor. The field-effect transistor in this example is a metal insulator semiconductor field-effect transistor (MISFET). A metal-oxide-semiconductor field-effect transistor (MOSFET) can be used as the MISFET. The MOSFET in this embodiment is an extended drain (ED) MOSFET. An exemplary EDMOS-FET has an N-type well region where N-type carriers drift on the drain region side. Field-effect transistors can also be used as power transistors. Known drain-source voltages for MISFETs include high voltage (HV: e.g., 100 V to 1000 V), medium voltage (MV: e.g., 30 V to 100 V), and low voltage (LV: e.g., 1 V to 30 V).

[0014] 2A and 2B are a vertical cross-sectional view and a plan view, respectively, of a device 50 according to the first embodiment. FIG. 2A shows the cross-sectional configuration taken along the line AA in FIG. 2B. The line AA is parallel to the X-axis and passes through the center of the source region SR in the Y-axis direction.

[0015] The device 50 of this example is an EDMOS-FET and includes a substrate 11, an epitaxial semiconductor layer 14, a P-type well region 52 (first well region), an N-type well region 51 (second well region), a third well region 53, a source region SR, a drain region DR, a gate insulating film GX, and a gate electrode G1. The device 50 further includes a first contact region 56 for a back gate, a second contact region 57, an upper conductive region 55U, and a lower conductive region 55L.

[0016] In this example, the semiconductor regions constituting the device have a first conductivity type of P-type and a second conductivity type of N-type, but these conductivity types are interchangeable. An exemplary P-type impurity (trivalent element) is boron (B). An exemplary N-type impurity (pentavalent element) is phosphorus (P) or arsenic (As).

[0017] The substrate 11 is a semiconductor substrate of a first conductivity type (P type).

[0018] The epitaxial semiconductor layer 14 is formed on the substrate 11. The conductivity type of the epitaxial semiconductor layer 14 in this example is the second conductivity type (N type).

[0019] The P-type well region 52 is formed in an upper layer portion of the epitaxial semiconductor layer 14. The conductivity type of the P-type well region 52 is a first conductivity type (P type). The P-type well region 52 has a rectangular shape in a plan view (in the XY plane), with the long sides extending along the Y-axis direction and the short sides extending along the X-axis direction.

[0020] The N-type well region 51 is formed in an upper layer portion of the epitaxial semiconductor layer 14. The conductivity type of the N-type well region 51 is the second conductivity type (N type). The P-type well region 52 and the N-type well region 51 are adjacent to each other. The N-type well region 51 has a tapered region 51T whose width in the Y-axis direction narrows toward the P-type well region 52 in a plan view.

[0021] The third well region 53 is formed in an upper portion of the epitaxial semiconductor layer 14, and is located on the opposite side of the N-type well region 51 from the P-type well region 52. The conductivity type of the third well region 53 is the first conductivity type (P-type). The third well region 53 has a rectangular shape in a plan view (in the XY plane), with its long sides extending along the Y-axis direction and its short sides extending along the X-axis direction.

[0022] The source region SR is formed in the P-type well region 52. The conductivity type of the source region SR is the second conductivity type (N-type). A source electrode S (terminal) is electrically connected to the source region SR.

[0023] The drain region DR is formed in the N-type well region 51. The conductivity type of the drain region DR is the second conductivity type (N-type). A drain electrode D (terminal) is electrically connected to the drain region DR.

[0024] The gate insulating film GX is formed on the surface of a semiconductor substrate including an epitaxial semiconductor layer. The gate insulating film GX is formed on the P-type well region 52 adjacent to the source region SR, extends in the X-axis direction, and is also formed on the insulating region 18 on the drain region DR side, beyond the N-type well region 51. The insulating region 18 is a shallow trench isolation (STI) made of an insulating layer such as SiO2, but may also be made of a field oxide film.

[0025] The gate electrode G1 is formed on the gate insulating film GX. In other words, the gate electrode G1 is formed on a region adjacent to the drain region DR side of the source region SR via the gate insulating film GX. The gate electrode G1 is connected to the gate terminal G.

[0026] The first contact region 56 is formed on the surface side of the epitaxial semiconductor layer 14. The conductivity type of the first contact region 56 is P-type. A P-type upper conductive region 55U is formed below the first contact region 56. A P-type lower conductive region 55L is provided continuously below the upper conductive region 55U. The lower conductive region 55L is connected to the substrate 11. Therefore, the first contact region 56 is electrically connected to the substrate 11. A background potential application terminal BG may be electrically connected to the first contact region 56.

[0027] The second contact region 57 is formed on the surface side of the epitaxial semiconductor layer 14. The conductivity type of the second contact region 57 is P-type, and it is connected to the substrate 11 as necessary. A substrate potential application terminal SUB may be electrically connected to the second contact region 57. The first contact region 56 and the second contact region 57 are each annular in plan view, and a transistor including a source region SR and a drain region DR is located inside the first contact region 56 and the second contact region 57.

[0028] As shown in FIG. 2A, the dimensions of each region (distance in the X-axis direction) are set in an XZ cross section passing through the center position of the source region SR in the Y-axis direction. Dimension A indicates the shortest distance from the end 52E of the P-type well region 52 on the N-type well region 51 side to the source region SR. Dimension C is the distance from the end 51E of the N-type well region 51 on the P-type well region 52 side to the end 18E of the insulating region 18. The end 18E is the end of the insulating region 18 in the N-type well region 51 located on the P-type well region 52 side. Dimension D1 is the distance between the end 18E and the end of the gate electrode G1 on the drain region DR side. Dimension AI is the distance between the end of the gate electrode G1 on the drain region DR side and the end of the N-type well region 51 on the opposite side from the P-type well region 52. Dimension BI is the shortest distance between the end of the N-type well region 51 on the opposite side from the P-type well region 52 and the third well region 53. The dimension CI is the dimension in the X-axis direction of the third well region 53. The dimension DI is the shortest distance between the end of the third well region 53 opposite the N-type well region 51 and the first contact region 56. The dimension Ld is the shortest distance between the end 18E and the drain region DR.

[0029] The specific dimensions of each element in the AA cross section are A = 4 μm, C = 0.5 μm, and Ld = 2.4 μm. As an example, the dimensions can be set as follows: 0.1 μm ≦ A ≦ 50 μm, 0 μm ≦ C ≦ 1 μm, and 0.2 μm ≦ Ld ≦ the thickness of the epitaxial layer (10 μm). In the case of an EDMOS-FET, the dimension (C + Ld) may be set as follows: 0.2 μm ≦ C + Ld ≦ 10.2 μm. Note that there is no portion corresponding to dimension C in the path of the bypass electron flow. If the gap between dimension A and dimension C is dimension B, then an exemplary value of dimension B can be set between 0 μm and 0.1 μm. Furthermore, exemplary dimensions are D1 = 0.72 μm, AI = BI = 3 μm, and CI = DI = 0.5 μm. The AI ​​value may be set to a value of ±95%, the BI value may be set to a value of ±50%, and the CI and DI values ​​may each be set to a value of ±100%.

[0030] In the design of EDMOS-FETs, when reducing the device size, simulation analysis has shown that increasing the dimension AI relatively improves operational balance. For similar reasons, increasing the dimension AI also improves the Y-axis width of the source region SR. However, as described below, this approach results in insufficient current-voltage characteristics. Specifically, in the drain current saturation region, the drain current increases above the reference level as the drain voltage increases. This is because a detour electron flow (current) occurs from the widthwise edge of the source region SR along the paths indicated by arrows J1 and J2 in Figure 2(B). This detour electron flow leads to carrier concentration and impact ion generation near the carrier branch points and insulating regions during the detour. Note that normal carriers (electrons) travel parallel to the X-axis, as indicated by the arrows in Figure 2(B).

[0031] Therefore, in the semiconductor device according to the first embodiment, the N-type well region 51 is provided with a tapered region 51T to suppress the bypass electron flow. The existence of the tapered region 51T blocks the path of the bypass electron flow. An end 51E of the tapered region 51T on the P-type well region 52 side is parallel to the Y-axis in a plan view, and the dimension of the end 51E in the Y-axis direction is the same as the dimension of the source region SR in the Y-axis direction. The dimension of the source region SR in the Y-axis direction is the distance (Y1-Y0) between the position of one end (Y0) and the position of the other end (Y1) in the Y-axis direction (see FIG. 9).

[0032] In plan view, the width Y of the N-type well region 51 on the Y axis passing through the drain region DR MAX is the dimension (Y1-Y0) of the drain region DR in the Y-axis direction plus twice the distance ΔY51. The distance ΔY51 is the distance from the end of the drain region DR in the Y-axis direction to the end of the N-type well region 51 in the Y-axis direction. The width of the tapered region 51T in the Y-axis direction is the width Y MAX The width of the tapered region 51T in the Y-axis direction varies from (Y1-Y0) to (Y1-Y0). The tapered region 51T has a dimension (Ld+C) in the X-axis direction, and its width in the Y-axis direction decreases by 2×ΔY51. In this example, the width reduction rate ((2×ΔY51) / (Ld+C)) is greater than or equal to 1 and less than or equal to 2, which sufficiently suppresses the bypass electron flow. An epitaxial semiconductor layer 14 is interposed between the hypotenuse of the tapered region 51T and the P-type well region 52 in a plan view. The gap in the X-axis direction between the P-type well region 52 and the N-type well region 51 at a position, for example, 2.9 μm in the Y-axis direction (negative direction) from one end position (Y0) of the source region SR in the Y-axis direction is, for example, 3 μm, and this gap can be set to be greater than or equal to 0.1 μm and less than or equal to 7 μm. This gap may be set to be equal to or less than the width of the N-type well region 51 in the X-axis direction at a point that is ΔY51 away from Y0 in the negative Y-axis direction.

[0033] 3A and 3B show a longitudinal cross-sectional view of the transistor shown in FIG. 2B taken along the line AA (FIG. 3A) and a longitudinal cross-sectional view of the transistor shown in FIG. 2B taken along the line J (FIG. 3B). Note that since the line J includes a curve, the dimensions of the line J portion in FIG. 3B are reduced in size along the X-axis direction.

[0034] 3A, in a vertical cross section passing through the center of the source region SR in the Y-axis direction, carriers (electrons) travel from the source region SR to the drain region DR, as indicated by the dotted arrow. Specifically, when a positive potential is applied to the gate electrode G1, an electron channel is generated in the surface layer of the P-type well region 52 directly below the gate electrode G1, and electrons travel from the source region SR to the end 18E of the insulating region 18. Since electrons can travel within the N-type well region 51, they travel below the end 18E, pass below the insulating region 18, and reach the drain region DR. Naturally, the potential of the drain region DR is higher than the potential of the source region SR.

[0035] As shown in FIG. 3B, when carriers (electrons) attempt to travel along the detour path along line J1 in FIG. 2B, the carriers in the source region SR can reach the epitaxial semiconductor layer 14, as indicated by the dotted arrow, but cannot move below the end 18E3 of the insulating region 18, thereby preventing the detour electron flow. This prevents the degradation of the current-voltage characteristics described above. As shown in FIGS. 2A and 2B, the end 18E3 of the insulating region 18 is located at one end on the Y-axis within the region defining the dimensions A and C described above. Its position in the Y-axis direction coincides with the position of one end of the source region SR in the Y-axis direction (corresponding to Y0 in FIG. 9). Note that FIG. 2B also shows an end 18E4 located opposite end 18E3. The end 18E4 of the insulating region 18 is the end of the insulating region 18 located at the other end on the Y axis within the region defining the above-mentioned dimensions A and C, and its position in the Y axis direction coincides with the other end position of the source region SR in the Y axis direction (corresponding to Y1 in Figure 9).

[0036] 4A and 4B are a vertical cross-sectional view and a plan view, respectively, of a device 50 according to a second embodiment. Note that FIG. 4A shows the cross-sectional configuration taken along the line AA in FIG. 4B.

[0037] The device 50 according to the second embodiment differs from the device according to the first embodiment only in that regions near both ends in the Y-axis direction of the P-type well region 52 are protruded to the position of the hypotenuse of the tapered region 51T. In other words, a first end 52E1 on the N-type well region 51 side of a region near one end in the Y-axis direction of the P-type well region 52 contacts one hypotenuse of the tapered region 51T in a plan view. Similarly, a second end 52E2 on the N-type well region 51 side of a region near the other end in the Y-axis direction of the P-type well region 52 contacts the other hypotenuse of the tapered region 51T in a plan view. In other words, in a plan view, the P-type well region 52 has a protruding region 52T facing the tapered region 51T. The dimension of the protruding region 52T in the X-axis direction when projected onto the AA cross section is, for example, 0.8 μm.

[0038] Since the P-type well region 52 tends to be a factor that hinders the movement of N-type carriers, the presence of the protruding region 52T can further hinder the bypass electron flow.

[0039] 5A and 5B show a longitudinal cross-sectional view of the transistor shown in FIG. 4B taken along the line AA (FIG. 5A) and a longitudinal cross-sectional view of the transistor shown in FIG. 4B taken along the line J (FIG. 5B). Note that since the line J includes a curve, the dimensions of the line J portion in FIG. 5B are reduced in size along the X-axis direction.

[0040] As shown in FIG. 5(A), the running of the carrier in the cross section AA in the second embodiment is the same as that in the first embodiment, as indicated by the dotted arrow.

[0041] As shown in Figure 5(B), when carriers (electrons) attempt to travel along the detour path along line J1 in Figure 4(B), the carriers in the source region SR can reach the end 18E3 of the insulating region 18, as indicated by the dotted arrow, but cannot move below it. Furthermore, the protruding region 52T is located in the path leading to the drain region DR. Therefore, the detour electron flow is blocked. This can suppress the degradation of the current-voltage characteristics described above.

[0042] 6A and 6B are a vertical cross-sectional view and a plan view, respectively, of a device 50 according to a third embodiment. Note that FIG. 6A shows the cross-sectional configuration taken along the line AA in FIG. 6B.

[0043] The device according to the third embodiment differs from the device according to the first embodiment in only the following two respects, with the remaining configuration being the same. One difference is that the N-type well region 51 does not have a tapered region and has a rectangular shape in a plan view. Another difference is that the shape of the insulating region 18 on the drain region side, including the end 18E, has a first end 18E1 and a second end 18E2 that protrude toward the P-type well region 52 at both ends in the Y-axis direction. The insulating region 18 has protrusions defined by the first end 18E1 and the second end 18E2, making it possible to block bypass electron flow.

[0044] 7A and 7B show a longitudinal cross-sectional view of the transistor shown in FIG. 6B along the line AA (FIG. 7A) and a longitudinal cross-sectional view of the transistor shown in FIG. 6B along the line J including the line J1 (FIG. 7B). Note that the line J includes a curve, so the dimensions of the line J portion in FIG. 7B are reduced in size along the X-axis direction.

[0045] As shown in FIG. 7(A), the running of the carrier in the cross section AA in the third embodiment is the same as that in the first embodiment, as indicated by the dotted arrow.

[0046] As shown in Figure 7(B), when carriers (electrons) attempt to travel along the detour path along line J1 in Figure 6(B), the carriers in the source region SR can reach the first end 18E1 of the insulating region 18, as indicated by the dotted arrow, but cannot move below it. Therefore, the detour electron flow is blocked. This can suppress the degradation of the current-voltage characteristics described above.

[0047] FIG. 8 is a diagram showing a longitudinal cross-sectional configuration of the transistor shown in FIG. 6(B) along line J, including line J0. Since line J0 is a line parallel to the X-axis, this figure is an XZ cross-section. In a plan view, the direction from the source region SR toward the drain region DR is the X-axis direction. The position of J0 in the Y-axis direction is slightly inside the end position of the source region SR in the Y-axis direction. Specifically, it is a position closer to the center of the source region SR than the end position by a distance ΔY (0<ΔY≦0.1 μm). The distance defined by dimension C in the figure is small, and carriers indicated by the dotted arrow cannot move below the N-type well region 51.

[0048] This dimension C is the shortest distance C between the end 51E and the end 18E1, and is 0 μm or more and 0.4 μm or less. It is even more preferable that C is 0 μm or more and 0.35 μm or less. It is even more preferable that C is 0 μm or more and 0.3 μm or less. More specifically, on the X-axis line including J0, the shortest distance C between the end 51E of the N-type well region 51 on the P-type well region 52 side and the end 18E1 of the insulating region 18 on the P-type well region 52 side satisfies the above range. The X-axis line including J0 is an X-axis line that passes through a position a distance ΔY (0 < ΔY ≦ 0.1 μm) from one end (position Y0) of the source region SR in the Y-axis direction toward the center position of the source region SR in the Y-axis direction. The value of the aforementioned dimension Ld in the cross section passing through J0 increases by the amount that dimension C is shortened, and becomes, for example, 3.71 μm.

[0049] FIG. 9 is a diagram for explaining the planar shape of the edge of the insulating region 18. As shown in FIG.

[0050] One end position of the source region SR in the Y-axis direction is Y0. The other end position of the source region SR in the Y-axis direction is Y1. In plan view, the insulating region 18 has an opening between the end of the source region SR on the negative side of the X-axis and end 18E. The figure shows the shape of this opening. In the third embodiment, end 18E of the insulating region 18 is located at position X1 on the X-axis and extends along the Y-axis direction. The position indicating J0 (dotted line in the X-axis direction) described above is located ΔY in the positive direction of the Y-axis from position Y0 and crosses first end 18E1. Similarly, the position indicating J0' (dotted line in the X-axis direction) in the figure is located ΔY in the negative direction of the Y-axis from position Y0 and crosses second end 18E2. Ends 18E3 and 18E4 are located at the ends in the Y-axis direction that define the opening of the insulating region 18.

[0051] First end 18E1 extends such that the width of the opening narrows between positions X0 and X1 on the X axis in a plan view. Similarly, second end 18E2 extends such that the width of the opening narrows between positions X0 and X1 on the X axis in a plan view.

[0052] Figure 10 is a graph showing the relationship between drain voltage Vd (V) and |Ibody / Id| (%). Ibody is the current that increases through a portion of the substrate and can be interpreted as the hole current flowing through the substrate, and Id is the drain current. The current-voltage characteristics were measured with the distance C shown in Figure 8 set to C = 0 μm, C = 0.1 μm, C = 0.2 μm, C = 0.3 μm, C = 0.4 μm, and C = 0.5 μm.

[0053] As shown in the graph, the smaller the value of C, the smaller the rate of the increased current. At C=0.4 μm, the increased current decreased more significantly than at C=0.5 μm, and at C=0.3 μm, the increased current decreased even further. At C=0 μm, the increased current decreased even further. It is believed that if C is at least 0 μm or more and 0.4 μm or less, the increased current can be sufficiently suppressed. If C is at least 0 μm or more and 0.35 μm or less, the increased current can be further suppressed. If C is at least 0 μm or more and 0.3 μm or less, the increased current can be further suppressed.

[0054] FIG. 11 is a graph showing the relationship between drain voltage Vd (V) and Ibody (A).

[0055] As shown in the graph, the structure of the third example (third embodiment) achieved the smallest value of the increased current Ibody. In the third embodiment, the value of C can be set to 0 μm. The second example (second embodiment) exhibited slightly better characteristics than the first example (first embodiment). The first example was also superior to the fourth example (structure of FIG. 12) used for comparison.

[0056] 12A and 12B are a vertical cross-sectional view and a plan view, respectively, of a device 50. In this device, the planar shape of the N-type well region 51 in the first embodiment is simply rectangular, and the other structures are the same as those in the first embodiment.

[0057] FIG. 13 is a diagram for explaining a planar configuration of a transistor.

[0058] In plan view, the insulating region 18 has a first opening OP1 including the source region SR and a second opening OP2 including the drain region DR. Carriers moving from the source region SR can move to the drain region DR, as indicated by the dotted arrow extending in the X-axis direction. On the other hand, a bypass electron flow I1 can start from the end of the P-type well region 52 on the N-type well region 51 side and reach the drain region DR. The behavior of the bypass electron flow I1 can be approximately simulated as bending at a right angle in plan view. In the structure of FIG. 12, the generation of the bypass electron flow I1 deteriorates the voltage-current characteristics.

[0059] FIG. 14 is a graph showing the relationship between the drain voltage Vd (V) and the drain current Id (A) of a transistor.

[0060] The graph shows the characteristics of the fourth example (the device shown in FIG. 12). When the drain voltage Vd is increased, the drain current Id increases above the normal reference level in the saturation region (10 V≦Vd). In the devices of the first to third embodiments, this increase in drain current can be suppressed, improving the current-voltage characteristics.

[0061] Next, the materials and impurity concentrations of the above-mentioned semiconductor regions will be described.

[0062] The semiconductor material constituting the semiconductor chip 100 described above is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor chip 100. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Si-containing semiconductors such as SiC and SiGe can be used as IV-IV compound semiconductors.

[0063] More specifically, the material of the substrate 11 is silicon (Si). The material of the substrate 11 can also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). The conductivity type of the substrate 11 is P-type (first conductivity type), and the impurity concentration (C 11 ) is, for example, 1×10 14 cm -3 ~5×10 18 cm -3 The thickness of the substrate 11 is, for example, 250 μm to 800 μm.

[0064] The material of the epitaxial semiconductor layer 14 can be the same as the semiconductor material of the substrate 11. The conductivity type of the epitaxial semiconductor layer 14 is N-type (second conductivity type), and the impurity concentration (C 14 ) is, for example, 5×10 14 cm -3 ~1×10 17 cm -3 The thickness of the epitaxial semiconductor layer 14 can be set to, for example, 3 μm to 20 μm.

[0065] The material of the N-type well region 51 can be the same as the semiconductor material of the substrate 11. The conductivity type of the N-type well region 51 is N-type (second conductivity type), and the impurity concentration (C 51 ) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 The thickness of the N-type well region 51 can be set to, for example, 0.5 μm to 4 μm.

[0066] The material of the P-type well region 52 can be the same as the semiconductor material of the substrate 11. The conductivity type of the P-type well region 52 is P type (first conductivity type), and the impurity concentration (C 52 ) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 The thickness of the P-type well region 52 can be set to, for example, 0.5 μm to 4 μm.

[0067] The material of the source region SR and the drain region DR can be the same as the semiconductor material of the substrate 11. The conductivity type of the source region SR and the drain region DR is N-type (second conductivity type), and the impurity concentrations (C SR , C DR ) is, for example, 1×10 19 cm -3 ~5×10 21 cm -3 The thickness of the source region SR and the drain region DR can be set to, for example, 0.2 μm to 1 μm, but a structure in which the depth is made shallower or deeper is also possible.

[0068] (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0069] [A1] A field effect transistor comprising: a first well region (P-type well region 52) of a first conductivity type (P-type), a source region SR of a second conductivity type (N-type) formed in the first well region, a second well region (N-type well region 51) of the second conductivity type (N-type), a drain region DR of the second conductivity type (N-type) formed in the second well region, a gate electrode G1 arranged on a region adjacent to the source region SR, an end portion 51E of the second well region on the first well region side, and an insulating region 18 arranged between the end portion 51E and the drain region DR, wherein in plan view the second well region has a tapered region 51T whose width narrows toward the first well region.

[0070] [A2] The field-effect transistor according to [A1], wherein the first well region (P-type well region 52) has a protruding region 52T facing the tapered region 51T in plan view.

[0071] [A3] A semiconductor device including a first well region (P-type well region 52) of a first conductivity type (P-type), a source region SR of a second conductivity type (N-type) formed in the first well region, a second well region (N-type well region 51) of the second conductivity type (N-type), a drain region DR of the second conductivity type (N-type) formed in the second well region, a gate electrode G1 arranged on a region adjacent to the source region SR, an end 51E of the second well region on the first well region side, and an insulating region 18 arranged between the drain region DR, and a field-effect transistor in which, when the Y-axis direction is defined as the Y-axis direction and the X-axis direction is defined as the direction perpendicular to the Y-axis direction, the direction from the source region SR to the drain region DR is the X-axis direction, and on the X-axis line passing from one end (Y0) of the source region SR in the Y-axis direction to a position a distance ΔY (0 < ΔY ≦ 0.1 μm) away from the center position of the source region SR in the Y-axis direction, the shortest distance C between an end 51E of the second well region on the first well region side and an end 18E1 of the insulating region 18 on the first well region side is 0 μm or more and 0.4 μm or less. [A4] The field effect transistor according to any one of [A1] to [A3], further comprising an epitaxial semiconductor layer 14 of a second conductivity type (N type) in which a first well region (P type well region 52) and a second well region (N type well region 51) are formed in a surface layer portion.

[0072] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0073] 14...Epitaxial semiconductor layer 18...Isolation area 18E1,52E1…First end 18E2,52E2…Second end 18E, 18E3, 18E4, 51E, 52E...End 51...N-type well region (second well region) 52...P-type well region (first well region) 52T…Protruding area DR...Drain region G1: Gate electrode SR...Source region 3...First main surface 5A…1st side 5B…Second side 5C…Third side 5D…Fourth side 10...Device area 11... Circuit board 50…devices 51T...Tapered area 53...Third well region 55L,55U…Conductive area 56...First contact area 57...Second contact area 100...Semiconductor chip BG: Background potential application terminal D: Drain electrode G...Gate terminal GX...Gate insulating film I1…Detour electron flow OP1…1st opening OP2...Second opening S...Source electrode SUB: Substrate potential application terminal

Claims

1. a first well region of a first conductivity type; a source region of a second conductivity type formed in the first well region; a second well region of a second conductivity type; a drain region of a second conductivity type formed in the second well region; a gate electrode disposed on a region adjacent to the source region; an insulating region disposed between the drain region and an end of the second well region on the first well region side; Equipped with In a plan view, the second well region has a tapered region whose width narrows toward the first well region. Field effect transistor.

2. In a plan view, the first well region has a protruding region facing the tapered region.

2. The field effect transistor of claim 1.

3. a first well region of a first conductivity type; a source region of a second conductivity type formed in the first well region; a second well region of a second conductivity type; a drain region of a second conductivity type formed in the second well region; a gate electrode disposed on a region adjacent to the source region; an insulating region disposed between the drain region and an end of the second well region on the first well region side; Equipped with In a plan view, when a longitudinal direction of the source region is defined as a Y-axis direction and a direction perpendicular to the Y-axis direction is defined as an X-axis direction, a direction from the source region toward the drain region is defined as the X-axis direction, a shortest distance C between an end of the second well region on the first well region side and an end of the insulating region on the first well region side on an X-axis line passing through a position a distance ΔY (0<ΔY≦0.1 μm) from one end of the source region in the Y-axis direction toward a center position of the source region in the Y-axis direction is 0 μm or more and 0.4 μm or less; Field effect transistor.

4. the first well region and the second well region further include a second conductivity type epitaxial semiconductor layer formed in a surface layer portion thereof; The field effect transistor according to any one of claims 1 to 3.

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