Vector processor, vector operation method, and program

Abstract

To solve deterioration of the performance of a vector processor.SOLUTION: A vector processor 100 according to the present disclosure includes: a plurality of vector operation units 120 each including a vector resistor 121 and a vector operation section 122; and a control unit 110 for dividing a vector command into pieces and controlling the plurality of vector operation units 120 to execute the pieces of the command respectively. The control unit 110 determines whether or not the vector command can be divisionally executed on the basis of a content of the vector command, and, if the vector command cannot be divisionally executed, performs control to cause the vector operation section of one of the vector operation units to execute the divided pieces of the vector command collectively.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a vector processor, a vector operation method, and a program. [Background technology]

[0002] Vector instructions process a large amount of data with a single instruction, but this requires that all operand data be available. Furthermore, as processors have become increasingly multi-core in recent years, latency from memory has become longer, leading to variations in the latency of each element depending on whether data is cached in each core. Therefore, with instructions with long latency, such as vector loads, the instruction must wait for a long time for the operands to be ready before execution. If the instruction is not executed for a long time, resources such as the instruction buffer will be occupied for a long time, resulting in poor utilization of the instruction buffer and poor instruction issuance efficiency. This results in a problem of reduced performance for vector processors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-174961 Summary of the Invention [Problem to be solved by the invention]

[0004] To address the above-mentioned problem, it is possible to divide a vector instruction and execute it in the executable part, as described in Patent Document 1. However, there are vector instructions that cannot be executed until all operands are available, such as instructions that calculate the maximum, minimum, or sum of elements. This still poses the problem of reduced performance for vector processors.

[0005] An object of the present disclosure is to solve the above-mentioned problem of performance degradation of vector processors. [Means for solving the problem]

[0006] A vector processor according to one embodiment of the present disclosure includes: a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; Equipped with the control unit determines whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, controls the divided vector instruction to be executed together by the vector operation unit included in any one of the vector operation units. The structure is as follows. Furthermore, a vector calculation method according to an embodiment of the present disclosure includes: a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; A vector calculation method in a vector processor comprising: the control unit determines whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, controls the divided vector instruction to be executed together by the vector operation unit provided in any one of the vector operation units. The structure is as follows. Furthermore, a program according to an embodiment of the present disclosure includes: a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; The control unit of the vector processor includes: determining whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, executing a process of controlling the divided vector instruction to be executed together by the vector operation unit provided in any one of the vector operation units; The structure is as follows. [Effects of the Invention]

[0007] With the above-described configuration, the present disclosure can suppress performance degradation of a vector processor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a configuration of a vector processor according to the present disclosure. [Figure 2] FIG. 1 is a diagram illustrating processing by a vector processor according to the present disclosure. [Figure 3] 10 is a flowchart illustrating a processing operation of a vector processor according to the present disclosure. [Figure 4] FIG. 1 is a diagram illustrating processing by a vector processor according to the present disclosure. [Figure 5] FIG. 1 is a diagram illustrating processing by a vector processor according to the present disclosure. [Figure 6] 1 is a block diagram showing an outline of the configuration of a vector processor according to the present disclosure; DETAILED DESCRIPTION OF THE INVENTION

[0009] First Embodiment A first embodiment of the present disclosure will be described with reference to the drawings, which may be relevant to any embodiment.

[0010] [composition] The vector processor of this embodiment is configured with a vector operation control circuit as shown in FIG. 1. Specifically, the vector operation control circuit includes an instruction issue unit 1, a unit execution status management unit 2, a unit 0 overtake buffer 30, a unit 1 overtake buffer 31, a unit 0 vector operation unit 4, a unit 1 vector operation unit 5, a memory 6, a memory network 7, and a store control unit 8. The unit execution status management unit 2 also includes a division determination unit 21 and an entry control unit 22. The unit 0 vector operation unit 4 includes a read control unit 41, a vector register 42, and an arithmetic unit 43, and the unit 1 vector operation unit 5 also includes a read control unit 51, a vector register 52, and an arithmetic unit 53. The functions of the above-described unit execution status management unit 2 and other components are realized by a program executed by an arithmetic device mounted on the vector operation control circuit.

[0011] The functions of each component will be described in detail below. The instruction issue unit 1, memory 6, memory network 7, and store control unit 8 are well known to those skilled in the art and are not directly related to the present invention, so detailed descriptions thereof will be omitted. The basic operations of the overtake buffers 30 and 31 and the read control units 41 and 51, vector registers 42 and 52, and arithmetic units 43 and 53 included in the vector operation units 4 and 5 are well known to those skilled in the art, so descriptions of parts not directly related to the present invention will be omitted.

[0012] The unit execution status management unit 2 (control unit) receives a vector instruction issued by the instruction issue unit 1, and the division determination unit 21 determines whether the vector instruction is executable in a divided manner based on its opcode. In this embodiment, a vector instruction that can be executed in a divided manner means that the vector instruction can be divided and the divided vector instructions can be executed, as described below. In other words, if the operation can be executed using only some of the divided elements of the vector instruction, the vector instruction is considered to be executable in a divided manner. However, if the operation cannot be executed using only some of the divided elements of the vector instruction and cannot be executed unless all elements are present, the vector instruction is considered to be inexecutable in a divided manner. In addition, the entry control unit 22 controls the allocation and release of entries in the pass-through buffers 30 and 31. The pass-through buffers 30 and 31 issue vector instructions that satisfy issuance conditions such as dependency relationships and available operation units.

[0013] The unit 0 vector operation unit 4 and the unit 1 vector operation unit 5 each constitute a vector operation unit that performs vector operations on vector instructions. In other words, the vector operation unit in this embodiment is implemented by being divided into two units (0, 1), the unit 0 vector operation unit 4 and the unit 1 vector operation unit 5. Furthermore, the vector operation control circuit in this embodiment is equipped with two vector operation units 4 and 5 (vector operation units), each of which has vector registers 42 and 52 and arithmetic units 43 and 53 (vector operation units). Note that, although this embodiment illustrates an example in which two vector operation units 4 and 5 are equipped, more vector operation units may be equipped.

[0014] As will be described later, under the control of the unit execution status management unit 2, if the vector instruction to be executed can be divided and executed, the vector operation units 4 and 5 treat the divided vector instruction as each unit (0, 1) and execute the vector operation on a unit-by-unit basis. In this embodiment, the instruction issue unit 1 and the unit execution status management unit 2 divide the vector instruction into two to form units 0 and 1, and the vector operation units 4 and 5 execute the vector operation on each of the units 0 and 1. For example, if a vector instruction consists of 64 elements as shown in FIG. 2, it is divided into two, the first half and the second half, to form units 0 and 1, each with 32 elements.

[0015] Furthermore, when a vector instruction cannot be divided and executed, the vector operation units 4 and 5 must process the data in the vector register 42 in the unit 0 vector operation unit 4 and the vector register 52 in the unit 1 vector operation unit 5 as a single unit, as will be described later. For this reason, the vector operation units 4 and 5 are connected to enable mutual data transmission and reception; specifically, a path is implemented that allows data to be transmitted and received from the vector register 52 in the unit 1 vector operation unit 5 to the calculator 43 in the unit 0 vector operation unit 4. Then, under the control of the unit execution status management unit 2, as will be described later, the data in both vector registers 42 and 52 are operated as a single unit by the calculator 43 in the unit 0 vector operation unit 4. Thereafter, the unit 0 vector operation unit 4 writes back the data in the first half of the divided operation result, from element 0 to element 31, to the vector register 42 in the unit 0 vector operation unit 4, and writes back the data in the second half of the divided operation result, from element 32 to element 63, to the vector register 52 in the unit 1 vector operation unit 5.

[0016] [Operation] Next, the operation of the vector operation control circuit shown in Fig. 2 will be described mainly with reference to the flowchart in Fig. 3. Here, an example will be described in which a vector instruction is executed in the order of vector load, vector operation instruction, and vector store. Note that the instruction issue unit 1, vector operation units 4 and 5, memory 6, memory network 7, and store control unit 8 are well known to those skilled in the art and are not directly related to the present invention, so detailed explanations will be omitted. The following description will begin with the unit execution status management unit 2 receiving the decoded instruction.

[0017] First, when the unit execution status management unit 2 receives an instruction, the division determination unit 21 determines whether or not the series of instructions can be divided and executed (step S1). For this determination, an opcode that can determine the instruction type is used. The entry control unit 22 flags instructions that can be divided and reserves entries in the pass-by buffers 30 and 31 (step S2). Here, load / store instructions such as vector load and vector store are determined to be divided and executed because there is no dependency between units. On the other hand, vector instructions that calculate the maximum, minimum, and sum of elements are determined to be not divided and executed because there is dependency between units.

[0018] If there is no preceding instruction, the divided vector load instructions are issued to the vector operation units 4 and 5, respectively, and the read control units 41 and 51 start reading operand data from the memory 6 to the vector registers 42 and 52, respectively (step S3). The vector instruction is divided by the instruction issuing unit 1, the unit execution status management unit 2, etc., as shown in FIG.

[0019] Next, a case where the vector operation instruction following the vector load instruction can be divided and executed will be described (Yes in step S4). In this case, the entry control unit 22 of the unit execution status management unit 2, which is notified by the vector operation units 4 and 5 that the vector load has been completed for each unit, releases the vector load entry in the overtake buffer of the corresponding unit, and sends the subsequent divided vector operation instructions to the corresponding vector operation units 4 and 5. The divided vector operation instructions are then executed for each unit by the arithmetic units 43 and 53 of the vector operation units 4 and 5, respectively, and written back to the corresponding vector registers 42 and 52 (step S5). After that, when the execution of the vector operation instruction for each unit is completed, the subsequent vector store instruction can also be divided and executed, so the vector store instruction is also divided and executed, and the operation results written back to the vector registers 42 and 52 of each vector operation unit 4 and 5 for each unit are written to memory 6 (step S6).

[0020] Next, we will explain the case where the vector operation instruction following the vector load instruction cannot be executed in a divided manner (No in step S4). In this case, the preceding vector load instruction must be completely completed. Therefore, the subsequent vector operation instruction cannot be issued to the vector operation units 4 and 5 even if the preceding vector load instruction of its own unit is completed. Here, we will consider an example where the vector load instruction of unit 0 is completed before the vector load instruction of unit 1. If the instruction to be sent next to the unit 0 vector operation unit 4 is an instruction that cannot be executed in a divided manner, the unit 0 overtake buffer 30 presents the entry ID information of that instruction to the entry control unit 22. At this time, if the same entry ID information is also presented by the unit 1 overtake buffer 31 in the same cycle, the entry control unit 22 issues an execution permission signal to both units; otherwise, it returns an execution prohibition signal (step S7). In other words, if the instructions to be sent in both buffers 30 and 31 are divided instructions of the same vector operation instruction that cannot be executed in a divided manner, the entry control unit 22 controls both buffers 30 and 31 to issue such instructions.

[0021] If an execution-prohibited signal is returned from the entry control unit 22, the unit 0 overtake buffer 30 sends other executable instructions, if any, to the unit 0 vector operation unit 4. If execution permission is returned from the entry control unit 22, the unit 0 overtake buffer 30 and the unit 1 overtake buffer 31 issue instructions to the corresponding vector operation units 4 and 5. The issued instruction must treat each of the vector registers 42 and 52 of each of the vector operation units 4 and 5 as a single unit with all 64 elements, so the vector registers 42 and 52 are virtually regarded as a single register. Therefore, the data stored in the vector register 42 of the unit 0 vector operation unit 4, including the data stored in the vector register 52 of the unit 1 vector operation unit 5, is sent to the calculator 43 in the unit 0 vector operation unit 4, where calculation processing is performed (step S8). In other words, the vector operation instructions divided and stored in the separate vector registers 42 and 52 are combined and vector calculation is performed in the single calculator 43. The elements of the calculation result of the vector calculation instruction are divided and written back to the vector registers 42, 52 where they were stored before execution. When the execution of the vector calculation instruction is completed, the subsequent vector store instruction can be divided and executed by each of the vector calculation units 4, 5. Then, the calculation results written back to the vector registers 42, 52 in the previous unit units are written to the memory 6 (step S9).

[0022] As described above, the vector operation control circuit can execute vector instructions for each divided unit using the unit execution status management unit 2 and the divided vector registers 42 and 52, thereby enabling efficient instruction execution. In other words, vector instructions that can be executed in divided units can be executed by each vector operation unit 4 and 5. FIG. 4 illustrates processing in this embodiment and a comparative example. When a vector load is performed, only the elements corresponding to unit 1 are loaded immediately, but it takes time to read the elements corresponding to unit 0. In the comparative example, the operation instruction is not executed until all operands are available, whereas in this embodiment, the instruction can be executed starting from unit 1. This shortens the number of cycles from when the elements of unit 0 arrive to when the vector is stored.

[0023] On the other hand, even for instructions that cannot be executed in a divided manner, as described above, multiple vector registers 42, 52 can be treated as one, and vector operations can be executed by one arithmetic unit 43. Generally, instructions that cannot be executed in a divided manner account for a smaller proportion than instructions that can be executed in a divided manner, so a significant improvement in performance can be expected by sequentially processing instructions that can be executed in a divided manner as described above.

[0024] In the above, for the sake of simplicity, the maximum number of vector elements is 64, and the number of divisions of a vector instruction is 2. However, other numbers of vector elements or any number of divisions that can equally divide the vector element number may be used. Furthermore, a larger number of vector operation units and buffers may be provided depending on the number of divisions.

[0025] Furthermore, the vector operation control circuit in this embodiment may divide instructions that cannot be executed in a divided manner, such as an instruction that calculates the sum of all elements or an instruction that returns the maximum or minimum, into multiple steps and process them in multiple stages in each of the vector operation units 4 and 5. To achieve this, the compiler or instruction issue unit 1 may prepare instructions in advance so that they are processed in multiple stages. For example, as shown in FIG. 5 , an instruction that calculates the maximum value of all elements is divided into multiple instructions (units 0 and 1) as a first-stage instruction, and the content of the instruction is changed so that each divided instruction executes a process to calculate the maximum value for each unit. Furthermore, as a second-stage instruction, the content of the instruction is changed so that the maximum value of all elements is calculated by obtaining the maximum value from the maximum value element of each unit. In this way, by changing the vector instruction to an instruction that can be processed in multiple stages, instructions that cannot be executed in a divided manner can be efficiently executed by multiple vector operation units.

[0026] <Second embodiment> Next, a second embodiment of the present disclosure will be described with reference to the drawings. This embodiment shows an outline of the configuration of the vector processor described in the above embodiment. Note that FIG. 6 is a diagram for explaining the configuration, and this diagram may be relevant to any embodiment.

[0027] The vector processor 100 is configured by a computer or electronic circuit having an arithmetic unit and a memory unit, and as shown in Fig. 6, includes a control unit 110 and a plurality of vector operation units 120. Each of the vector operation units 120 includes a vector register 121 and a vector operation unit 122. The functions of the control unit 110, which will be described later, are realized by the arithmetic unit executing a program.

[0028] The control unit 110 then divides the vector instruction and controls it to be executed by each of the multiple vector operation units 120, and further determines whether the vector instruction can be divided and executed based on the content of the vector instruction.For vector instructions that cannot be divided and executed, the control unit 110 controls the divided vector instructions to be executed together by the vector operation unit 122 provided in one of the vector operation units 120.

[0029] With the above-described configuration, the present disclosure allows vector instructions that can be executed in a divided manner to be executed sequentially by a plurality of vector operation units, and also allows vector instructions that cannot be executed to be executed by one of the vector operation units 122. This allows for improved processing efficiency by the vector processor, and allows for improved performance of the vector processor.

[0030] Although the present disclosure has been described above with reference to the above-described embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each of the above-described embodiments can be combined with other embodiments as appropriate.

[0031] <Additional Notes> A part or all of the above-described embodiments can be described as follows: Below, an outline of the configuration of the vector processor, vector calculation method, and program according to the present disclosure will be described. However, the present disclosure is not limited to the following configuration. (Appendix 1) a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; Equipped with the control unit determines whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, controls the divided vector instruction to be executed together by the vector operation unit included in any one of the vector operation units. Vector processor. (Appendix 2) 10. The vector processor of claim 1, a plurality of the vector registers and at least one of the vector operation units are connected to be able to transmit and receive data; For the vector instruction that cannot be divided and executed, the control unit controls the divided vector instruction stored in the vector registers included in each of the plurality of vector operation units to be executed collectively by the vector operation unit included in any one of the vector operation units. Vector processor. (Appendix 3) 3. The vector processor of claim 2, For the vector instruction that cannot be divided and executed, the control unit controls the vector operation unit of any one of the vector operation units to execute the divided vector instruction together, and to divide and store the operation results in the vector registers of each of the plurality of vector operation units. Vector processor. (Appendix 4) 4. The vector processor of claim 3, For the vector instruction that cannot be executed in a divided manner, the control unit controls the vector operation unit of any one of the vector operation units to divide and store the operation results in the plurality of vector registers in which the divided vector instruction was stored before execution. Vector processor. (Appendix 5) 10. The vector processor of claim 1, a plurality of buffers corresponding to the plurality of vector operation units, which issue the vector instructions divided among the vector operation units; the control unit controls the plurality of buffers to issue the divided vector instructions that are to be issued when the plurality of buffers are each scheduled to issue divided versions of the same vector instruction that cannot be divided and executed. Vector processor. (Appendix 6) 10. The vector processor of claim 1, The control unit modifies the content of the vector instruction that cannot be executed in a divided manner so that the vector instruction can be executed in a divided manner by executing it in multiple stages using multiple vector operation units based on the content of the vector instruction, and controls the execution of the modified vector instruction. Vector processor. (Appendix 7) a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; A vector calculation method in a vector processor comprising: the control unit determines whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, controls the divided vector instruction to be executed together by the vector operation unit provided in any one of the vector operation units. Vector operation method. (Appendix 8) 8. The vector calculation method according to claim 7, further comprising: the vector processor is connected to a plurality of the vector registers and at least one of the vector operation units so as to be able to transmit and receive data; For the vector instruction that cannot be divided and executed, the control unit controls the divided vector instruction stored in the vector registers included in each of the plurality of vector operation units to be executed collectively by the vector operation unit included in any one of the vector operation units. Vector operation method. (Appendix 9) 9. A vector calculation method according to claim 8, comprising: For the vector instruction that cannot be divided and executed, the control unit controls the vector operation unit of any one of the vector operation units to execute the divided vector instruction together, and then to divide and store the operation results in the vector registers of each of the plurality of vector operation units. Vector operation method. (Appendix 10) a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; The control unit of the vector processor includes: determining whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, executing a process of controlling the divided vector instruction to be executed together by the vector operation unit provided in any one of the vector operation units; Program for. [Explanation of symbols]

[0032] 1. Command issuing department 2 Unit Execution Status Management Department 21 Division judgment section 22 Entry control section 30 Unit 0 Overtake Buffer 31 Unit 1 Overtaking Buffer 4 Unit 0 Vector Calculation Unit 41 Lead control section 42 Vector Registers 43 Arithmetic unit 5 Unit 1 Vector Calculation Section 51 Lead control section 52 Vector Registers 53 Arithmetic unit 6. Memory 7 Memory Network 8 Store control section 100 Vector Processors 110 control section 120 Vector Processing Units 121 Vector Registers 122 Vector Calculation Unit

Claims

1. a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; Equipped with the control unit determines whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, controls the divided vector instruction to be executed together by the vector operation unit included in any one of the vector operation units. Vector processor.

2. 2. The vector processor of claim 1, a plurality of the vector registers and at least one of the vector operation units are connected to each other so as to be able to transmit and receive data; For the vector instruction that cannot be divided and executed, the control unit controls the divided vector instruction stored in the vector registers included in each of the plurality of vector operation units to be executed collectively by the vector operation unit included in any one of the vector operation units. Vector processor.

3. 3. The vector processor of claim 2, For the vector instruction that cannot be divided and executed, the control unit controls the vector operation unit of any one of the vector operation units to execute the divided vector instruction together, and to store the operation results in the vector registers of each of the plurality of vector operation units. Vector processor.

4. 4. The vector processor of claim 3, For the vector instruction that cannot be divided and executed, the control unit controls the vector operation unit of any one of the vector operation units to divide and store the operation results in the plurality of vector registers in which the divided vector instruction was stored before execution. Vector processor.

5. 2. The vector processor of claim 1, a plurality of buffers corresponding to the plurality of vector operation units, which issue the vector instructions divided among the vector operation units; the control unit controls the plurality of buffers to issue the divided vector instructions that are to be issued when the plurality of buffers are each scheduled to issue divided versions of the same vector instruction that cannot be divided and executed. Vector processor.

6. 2. The vector processor of claim 1, The control unit modifies the content of the vector instruction that cannot be executed in a divided manner so that the vector instruction can be executed in a divided manner by executing it in multiple stages using multiple vector operation units based on the content of the vector instruction, and controls the execution of the modified vector instruction. Vector processor.

7. a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; A vector calculation method in a vector processor comprising: the control unit determines whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, controls the divided vector instruction to be executed together by the vector operation unit provided in any one of the vector operation units. Vector operation method.

8. 8. The vector calculation method according to claim 7, the vector processor is connected to the plurality of vector registers and at least one of the vector operation units so as to be able to transmit and receive data; For the vector instruction that cannot be divided and executed, the control unit controls the divided vector instruction stored in the vector registers included in each of the plurality of vector operation units to be executed collectively by the vector operation unit included in any one of the vector operation units. Vector operation method.

9. 9. The vector calculation method according to claim 8, For the vector instruction that cannot be divided and executed, the control unit controls the vector operation unit of any one of the vector operation units to execute the divided vector instruction together, and then to divide and store the operation results in the vector registers of each of the plurality of vector operation units. Vector operation method.

10. a plurality of vector operation units each including a vector register and a vector operation unit; a control unit that divides a vector instruction and controls the vector instruction to be executed by each of the plurality of vector operation units; The control unit of the vector processor includes: determining whether the vector instruction can be divided and executed based on the content of the vector instruction, and for the vector instruction that cannot be divided and executed, executing a process of controlling the divided vector instruction to be executed together by the vector operation unit provided in any one of the vector operation units; Program for.

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