Capacitive load drive circuit, liquid discharge device, and head unit

Abstract

To provide a capacitive load drive circuit capable of reducing power consumption.SOLUTION: A capacitive load drive circuit includes: an amplification circuit that modulates a base drive signal and outputs a first amplified modulation signal obtained by amplifying the modulated signal; a level switching signal output circuit that outputs a level switching signal varying between a first potential and a second potential; a level shift circuit that outputs the first amplified modulation signal as a second amplified modulation signal when the level switching signal is at the first potential, and outputs a signal obtained by shifting the potential of the first amplified modulation signal as the second amplified modulation signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulation signal and outputs a drive signal; and a feedback circuit that outputs a feedback signal corresponding to the drive signal. The state of the level switching signal output circuit includes: a first state in which the level switching signal varying between the first potential and the second potential in accordance with the feedback signal is output during a period in which the value of the base drive signal changes; and a second state in which the level switching signal fixed at either the first potential or the second potential is output.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present invention relates to a capacitive load drive circuit, a liquid ejection device, and a head unit. [Background technology]

[0002] Liquid ejection devices that eject liquid to form images or documents on a medium are known to use piezoelectric elements. In such liquid ejection devices, a piezoelectric element is provided corresponding to each of a plurality of nozzles that eject liquid, and each is driven according to a drive signal. Driving the piezoelectric element causes liquid to be ejected from the nozzle provided corresponding to that piezoelectric element. A sufficient current must be supplied to operate such a piezoelectric element. Therefore, a drive circuit that outputs a drive signal to drive the piezoelectric element includes an amplifier circuit that amplifies a source signal that is the basis of the drive signal.

[0003] Patent Document 1 discloses a circuit that pulse-modulates a base drive signal that is the basis of a drive signal, amplifies the pulse-modulated modulated signal, and outputs it as a drive signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-124040 Summary of the Invention [Problem to be solved by the invention]

[0005] However, from the viewpoint of reducing the power consumption in the drive circuit, the technique described in Patent Document 1 alone is not sufficient, and there is room for improvement. [Means for solving the problem]

[0006] One aspect of the capacitive load drive circuit according to the present invention is A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal output circuit outputs the level switching signal that changes between the first potential and the second potential in response to the feedback signal during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal output circuit outputs the level switching signal that is constant at the first potential or the second potential.

[0007] One aspect of the liquid ejection device according to the present invention is a transport unit that transports the medium; a liquid ejection head that ejects liquid onto the medium in response to driving of a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal output circuit outputs the level switching signal that changes between the first potential and the second potential in response to the feedback signal during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal output circuit outputs the level switching signal that is constant at the first potential or the second potential.

[0008] One aspect of the head unit according to the present invention is a liquid ejection head that ejects liquid onto a medium in response to driving of a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal output circuit outputs the level switching signal that changes between the first potential and the second potential in response to the feedback signal during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal output circuit outputs the level switching signal that is constant at the first potential or the second potential. [Brief explanation of the drawings]

[0009] [Figure 1] 1A and 1B are diagrams illustrating an example of the structure of a liquid ejection device. [Figure 2] FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. [Figure 3] FIG. 2 is a diagram showing an example of the arrangement of a plurality of ejection sections in a head unit. [Figure 4] FIG. 2 is a diagram illustrating an example of a configuration of a discharge unit. [Figure 5] FIG. 2 is a diagram illustrating an example of a configuration of a voltage conversion circuit. [Figure 6] 4A and 4B are diagrams for explaining the operation of the voltage conversion circuit; [Figure 7] 10 is a diagram showing an example of a signal waveform of a drive signal COM. FIG. [Figure 8] FIG. 2 is a diagram illustrating an example of a functional configuration of a drive circuit. [Figure 9] FIG. 4 is a diagram for explaining the operation of a drive circuit. [Figure 10] FIG. 2 is a diagram illustrating an example of a configuration of a level switching signal output circuit. [Figure 11] FIG. 10 is a diagram illustrating an example of the configuration of a high-pass filter included in a feedback circuit. [Figure 12] 10A and 10B are diagrams for explaining the operation of the level switching signal output circuit; [Figure 13] FIG. 10 is a diagram illustrating an example of the configuration of a voltage conversion circuit according to a first modified example. [Figure 14] FIG. 10 is a diagram illustrating an example of the configuration of a voltage conversion circuit according to a second modification. [Figure 15] FIG. 10 is a diagram showing the configuration of a drive circuit included in a liquid ejection device according to a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for the convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0011] In the following description, a serial printing consumer inkjet printer is used as an example of a liquid ejection apparatus according to the present invention. However, the liquid ejection apparatus is not limited to a serial printing apparatus and may be a line printing apparatus. Furthermore, the liquid ejection apparatus is not limited to a consumer inkjet printer and may be a business inkjet printer for office use, or a portable inkjet printer that is powered by a battery or the like and can be carried around. Furthermore, the liquid ejection apparatus is not limited to an inkjet printer and may be, for example, a color material ejection apparatus used in the manufacture of color filters for liquid crystal displays and the like, an electrode material ejection apparatus used in the formation of electrodes for organic electroluminescence displays and surface-emitting displays, a bioorganic material ejection apparatus used in the manufacture of biochips, or the like.

[0012] 1. Overview of the liquid ejection device Fig. 1 is a diagram showing an example of the structure of a liquid ejection device 1. As shown in Fig. 1, the liquid ejection device 1 includes a moving body 2 and a moving unit 3 that moves the moving body 2 back and forth along the main scanning direction.

[0013] The moving unit 3 has a carriage motor 31 which serves as the driving source for the reciprocating movement of the moving body 2 along the main scanning direction, a carriage guide shaft 32 with both ends fixed, and a timing belt 33 which extends approximately parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0014] The movable body 2 has a carriage 24. The carriage 24 is supported by a carriage guide shaft 32 so as to be freely movable back and forth, and is fixed to a part of a timing belt 33. The carriage motor 31 drives the timing belt 33 forward and backward, causing the movable body 2 having the carriage 24 to move back and forth while being guided by the carriage guide shaft 32. A head unit 20 is located on a portion of the movable body 2 that faces the medium P. That is, the head unit 20 is mounted on the carriage 24. A large number of nozzles that eject ink, an example of a liquid, are located on the surface of the head unit 20 that faces the medium P. Various control signals for controlling the operation of the head unit 20 are supplied to the head unit 20 via a cable 190. A flexible flat cable that can slide in accordance with the reciprocating movement of the movable body 2 can be used as this cable 190.

[0015] The liquid ejection device 1 also includes a transport unit 4 that transports the medium P along the transport direction on a platen 40. The transport unit 4 has a transport motor 41 that is a drive source for transporting the medium P, and a transport roller 42 that rotates in response to the driving force of the transport motor 41 to transport the medium P along the transport direction.

[0016] In the liquid ejection device 1 configured as described above, the head unit 20 ejects ink onto the medium P in synchronization with the timing at which the medium P is transported by the transport unit 4. As a result, the ink ejected by the head unit 20 lands at the desired position on the medium P, and the desired image or characters are formed on the surface of the medium P.

[0017] Next, we will explain the functional configuration of the liquid ejection device 1. Fig. 2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in Fig. 2, the liquid ejection device 1 includes a control unit 10, a head unit 20, a moving unit 3, a transport unit 4, and a cable 190. The cable 190 electrically connects the control unit 10 and the head unit 20.

[0018] The control unit 10 includes a voltage supply circuit 11 and a control circuit 100 .

[0019] The voltage supply circuit 11 outputs a voltage signal VDD, which is a DC voltage signal having a constant voltage value of vdd, from a commercial AC power source supplied from outside the liquid ejection device 1. The voltage signal VDD output by the voltage supply circuit 11 is supplied to various components of the control unit 10 and also to the head unit 20. Here, in the liquid ejection device 1 of this embodiment, the voltage vdd, which is the voltage value of the voltage signal VDD output by the voltage supply circuit 11, is described as 5 V. Such a voltage supply circuit 11 may be configured to include, for example, an AC / DC converter that generates a DC voltage signal of a predetermined voltage value from a commercial AC power source. The voltage supply circuit 11 may also be various types of batteries, such as primary batteries or secondary batteries. Furthermore, the liquid ejection device 1 may not have the voltage supply circuit 11, and may instead receive the voltage signal VDD as a DC voltage signal from a power supply circuit provided outside the liquid ejection device 1.

[0020] Image data is supplied to the control circuit 100 from an external device (not shown), such as a host computer, that is provided outside the liquid ejection device 1. The control circuit 100 performs various image processing and the like on the supplied image data to generate various control signals for controlling each part of the liquid ejection device 1 and outputs the signals to each part.

[0021] Specifically, the control circuit 100 generates a control signal Ctrl1 for controlling the reciprocating movement of the movable body 2 based on the image data, and outputs it to a carriage motor 31 included in the movement unit 3. The control circuit 100 also generates a control signal Ctrl2 for controlling the transport of the medium P based on the image data, and outputs it to a transport motor 41 included in the transport unit 4. In this way, the control circuit 100 controls the reciprocating movement of the movable body 2 along the main scanning direction and the transport of the medium P along the transport direction. In other words, the head unit 20 can eject ink onto the medium P at a predetermined timing synchronized with the transport of the medium P. This makes it possible to cause ink to land at desired positions on the medium P, and to form desired images and characters on the medium P.

[0022] In addition, the control circuit 100 may convert the control signal Ctrl1 for controlling the reciprocating movement of the moving body 2 into a signal by a carriage motor driver not shown, and then supply it to the moving unit 3.Similarly, the control signal Ctrl2 for controlling the transport of the medium P may be converted into a signal by a transport motor driver not shown, and then supply it to the transport unit 4.

[0023] The control circuit 100 also generates a drive data signal DATA for controlling the operation of the head unit 20 and a basic drive signal dA, and outputs them to the head unit 20.

[0024] The head unit 20 has a drive circuit 50, a voltage conversion circuit 70, a selection control circuit 200, and a liquid ejection head 21. The selection control circuit 200 has a selection control unit 210 and a plurality of selection units 230, and the liquid ejection head 21 has a plurality of ejection units 600 including piezoelectric elements 60. At this time, each of the plurality of selection units 230 included in the selection control circuit 200 selects a liquid The ejection head 21 is provided with the piezoelectric elements 60 corresponding to the respective ejection sections 600 .

[0025] The voltage signal VDD output by the voltage supply circuit 11 is input to the voltage conversion circuit 70. The voltage conversion circuit 70 boosts the input voltage signal VDD and outputs it as voltage signals VD1 to VD5 used in the head unit 20. In this embodiment, the voltage signal VD1 will be described as a DC voltage signal having a constant voltage value of voltage vd1, where voltage vd1 is 8.4 V; the voltage signal VD2 will be described as a DC voltage signal having a constant voltage value of voltage vd2, where voltage vd2 is 16.8 V; the voltage signal VD3 will be described as a DC voltage signal having a constant voltage value of voltage vd3, where voltage vd3 is 25.2 V; the voltage signal VD4 will be described as a DC voltage signal having a constant voltage value of voltage vd4, where voltage vd4 is 33.6 V; and the voltage signal VD5 will be described as a DC voltage signal having a constant voltage value of voltage vd5, where voltage vd5 is 42 V. The configuration and operation of the voltage conversion circuit 70 will be described in detail later.

[0026] The basic drive signal dA output by the control unit 10 is input to the drive circuit 50. At least one of the voltage signals VD1 to VD5 output by the voltage conversion circuit 70 is also input to the drive circuit 50. The basic drive signal dA is a digital signal that includes information that defines the signal waveform of a drive signal COM that drives the piezoelectric element 60, which will be described later. The drive circuit 50 converts the basic drive signal dA into an analog signal, and then amplifies the converted analog signal to generate and output the drive signal COM. The configuration and operation of the drive circuit 50 will be described in detail below.

[0027] The drive data signal DATA output by the control unit 10 is input to a selection control section 210 included in the selection control circuit 200. The selection control section 210 is also supplied with a voltage signal VD5 output by the voltage conversion circuit 70. The selection control section 210 generates a signal for each of the multiple selection sections 230, based on the drive data signal DATA, instructing each selection section 230 whether to select or not select the drive signal COM. The selection control section 210 then converts the logic level of the generated signal into a high-amplitude logic signal based on a voltage vd5, which is the voltage value of the voltage signal VD5, and outputs the converted signal as a selection signal S to the corresponding selection section 230.

[0028] The drive signal COM and a corresponding selection signal S are input to each of the multiple selection units 230. Each of the multiple selection units 230 generates a drive signal VOUT by selecting or deselecting the drive signal COM based on the selection signal S. The multiple selection units 230 then supply the generated drive signal VOUT to one end of the piezoelectric element 60 included in the corresponding ejection unit 600 included in the liquid ejection head 21.

[0029] A reference voltage signal VBS is commonly supplied to the other ends of the piezoelectric elements 60 included in the multiple ejection parts 600. The reference voltage signal VBS is a signal of a constant voltage value that functions as a reference potential for driving the piezoelectric elements 60 driven by the drive signal VOUT, and may be, for example, a DC voltage signal of 5.5 V or 6 V, or may be a signal of a constant voltage value at ground potential.

[0030] The piezoelectric elements 60 are provided corresponding to each of the multiple nozzles in the head unit 20. The piezoelectric elements 60 are driven in response to the potential difference between a drive signal VOUT supplied to one end and a reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the drive amount of the piezoelectric elements 60 is ejected from an ejection section 600 including the piezoelectric elements 60.

[0031] Although FIG. 2 illustrates a case where the head unit 20 has one liquid ejection head 21, the head unit 20 may have a plurality of liquid ejection heads 21 depending on the type and number of inks to be ejected.

[0032] As described above, the liquid ejection device 1 in this embodiment includes a transport unit 4 that transports a medium P, a liquid ejection head 21 that includes a plurality of ejection sections 600 each including a piezoelectric element 60 and that eject ink onto the medium P by driving the piezoelectric element 60, and that ejects liquid onto the medium P by driving the piezoelectric element 60, a voltage conversion circuit 70 that boosts the voltage signal VDD and outputs a voltage signal VD1 of voltage vd1, a voltage signal VD2 of voltage vd2, a voltage signal VD3 of voltage vd3, a voltage signal VD4 of voltage vd4, and a voltage signal VD5 of voltage vd5, and a drive circuit 50 that receives at least one of the voltage signals VD1 to VD5 and outputs a drive signal COM that drives the piezoelectric element 60.

[0033] 2. Discharge section configuration Next, an example of the configuration of the multiple ejection sections 600 included in the liquid ejection head 21 and an arrangement of the multiple ejection sections 600 in the head unit 20 will be described. Fig. 3 is a diagram showing an example of the arrangement of the multiple ejection sections 600 in the head unit 20. Fig. 3 illustrates an example where the head unit 20 has four liquid ejection heads 21.

[0034] As shown in FIG. 3, each of the four liquid ejection heads 21 has a plurality of ejection sections 600 arranged in a row in one direction. That is, the liquid ejection head 21 includes a nozzle row L in which nozzles 651, which will be described later and are included in the ejection section 600, are arranged in one direction. The liquid ejection heads 21 are also positioned in the head unit 20 in a row in a direction intersecting the nozzle row L. That is, the head unit 20 has the same number of nozzle rows L as the liquid ejection heads 21. The arrangement of the nozzles 651 in the nozzle row L is not limited to a single row. For example, the nozzles 651 may be arranged in a staggered pattern so that even-numbered nozzles 651 counting from one end of the plurality of nozzles 651 are positioned at different positions from odd-numbered nozzles 651 counting from one end of the plurality of nozzles 651. Alternatively, one nozzle row L may be formed by arranging a plurality of nozzles 651 side by side in two or more rows.

[0035] Next, an example of the configuration of the ejection unit 600 will be described. FIG. 4 is a diagram showing an example of the configuration of the ejection unit 600. As shown in FIG. 4, the ejection unit 600 includes a piezoelectric element 60, a diaphragm 621, a cavity 631, and a nozzle 651. The diaphragm 621 is displaced in response to the driving of the piezoelectric element 60 provided on the upper surface in FIG. 4. The diaphragm 621 functions as a diaphragm that expands and contracts the internal volume of the cavity 631. The cavity 631 is filled with ink. The cavity 631 functions as a pressure chamber whose internal volume changes in response to the displacement of the diaphragm 621 caused by the driving of the piezoelectric element 60. The nozzle 651 is formed in the nozzle plate 632 and is an opening portion that communicates with the cavity 631. Then, as the internal volume of the cavity 631 changes, ink stored in the cavity 631 is ejected from the nozzle 651.

[0036] Piezoelectric element 60 has a structure in which piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In this structure, piezoelectric body 601 has electrodes 611 and 612 and a central portion of diaphragm 621 that bends in the vertical direction in FIG.

[0037] Specifically, a drive signal VOUT is supplied to an electrode 611 at one end of the piezoelectric element 60, and a reference voltage signal VBS is supplied to an electrode 612 at the other end. When the piezoelectric element 60 is driven upward in response to a change in the voltage of the drive signal VOUT, the vibration plate 621 is displaced upward. As a result, the internal volume of the cavity 631 expands. Therefore, ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven downward in response to a change in the voltage value of the drive signal VOUT, the vibration plate 621 is displaced downward. As a result, the internal volume of the cavity 631 shrinks. Therefore, an amount of ink corresponding to the degree of shrinkage of the internal volume of the cavity 631 is ejected from the nozzle 651. do.

[0038] As described above, the liquid ejection head 21 includes the piezoelectric element 60, and ejects ink onto the medium P by driving the piezoelectric element 60. Note that the ejection section 600 and the piezoelectric element 60 included in the ejection section 600 are not limited to the configuration shown in the figure, and any configuration is acceptable as long as the piezoelectric element 60 is driven based on the drive signal VOUT and ink can be ejected from the corresponding nozzle 651 by driving the piezoelectric element 60.

[0039] 3. Configuration and operation of voltage conversion circuit Next, a description will be given of the configuration and operation of the voltage conversion circuit 70. Fig. 5 is a diagram showing an example of the configuration of the voltage conversion circuit 70. As shown in Fig. 5, the voltage conversion circuit 70 has an inductor Lsw, a transistor Msw, capacitors Co1 to Co5, Cb1 to Cb4, diodes Do1 to Do5, Db1 to Db4, resistors Rf1 and Rf2, and a boost control circuit 75.

[0040] One end of the inductor Lsw is supplied with a voltage signal VDD output by the voltage supply circuit 11. The transistor Msw is an N-channel MOSFET, with its drain terminal electrically connected to the other end of the inductor Lsw, its source terminal supplied with ground potential, and its gate terminal receiving a gate drive signal DSW output by the boost control circuit 75. The anode terminal of the diode Do1 is electrically connected to the other end of the inductor Lsw. The capacitor Co1 has one end electrically connected to the cathode terminal of the diode Do1 and the other end supplied with ground potential. The resistor Rf1 has one end electrically connected to the cathode terminal of the diode Do1 and one end of the capacitor Co1. The resistor Rf2 has one end electrically connected to the other end of the resistor Rf1 and the other end supplied with ground potential. The voltage value of the signal generated at the junction electrically connecting the other end of the resistor Rf1 and one end of the resistor Rf2 is input to the boost control circuit 75 as a constant-voltage feedback signal Vfbc. The boost control circuit 75 controls the duty ratio of the gate drive signal DSW to be output so that the voltage value of the input constant voltage feedback signal Vfbc becomes a predetermined value.

[0041] One end of the capacitor Cb1 is electrically connected to the anode terminal of the diode Do1. The anode terminal of the diode Db1 is electrically connected to the cathode terminal of the diode Do1. The anode terminal of the diode Do2 is electrically connected to the other end of the capacitor Cb1 and the cathode terminal of the diode Db1. One end of the capacitor Co2 is electrically connected to the cathode terminal of the diode Do2, and the other end is supplied with ground potential.

[0042] One end of capacitor Cb2 is electrically connected to the anode terminal of diode Do2. The anode terminal of diode Db2 is electrically connected to the cathode terminal of diode Do2. The anode terminal of diode Do3 is electrically connected to the other end of capacitor Cb2 and the cathode terminal of diode Db2. One end of capacitor Co3 is electrically connected to the cathode terminal of diode Do3, and the other end is supplied with ground potential.

[0043] One end of capacitor Cb3 is electrically connected to the anode terminal of diode Do3. The anode terminal of diode Db3 is electrically connected to the cathode terminal of diode Do3. The anode terminal of diode Do4 is electrically connected to the other end of capacitor Cb3 and the cathode terminal of diode Db3. One end of capacitor Co4 is electrically connected to the cathode terminal of diode Do4, and the other end is supplied with ground potential.

[0044] One end of capacitor Cb4 is electrically connected to the anode terminal of diode Do4. The anode terminal of diode Db4 is electrically connected to the cathode terminal of diode Do4. The anode terminal of diode Do5 is electrically connected to the other end of capacitor Cb4 and the cathode terminal of diode Db4. One end of capacitor Co5 is electrically connected to the cathode terminal of diode Do5, and the other end is supplied with ground potential.

[0045] That is, the voltage conversion circuit 70 has an inductor Lsw to one end of which a voltage signal VDD is supplied, a transistor Msw having one end, which is a drain terminal, electrically connected to the other end of the inductor Lsw, a diode Do1 having an anode terminal electrically connected to one end, which is the drain terminal of the transistor Msw, a capacitor Co1 having one end, which is electrically connected to the cathode terminal of the diode Do1, a capacitor Cb1 having one end, which is electrically connected to one end, which is the drain terminal of the transistor Msw, a diode Db1 having an anode terminal electrically connected to the cathode terminal of the diode Do1, a diode Do2 having an anode terminal electrically connected to the cathode terminal of the diode Db1 and the other end of the capacitor Cb1, and a capacitor Co2 having one end, which is electrically connected to the cathode terminal of the diode Do2, and the voltage conversion circuit 70 outputs the voltage value at one end of the capacitor Co1 as a voltage signal VD1 and outputs the voltage value at one end of the capacitor Co2 as a voltage signal VD2.

[0046] The voltage conversion circuit 70 has diodes Do3, Do4, and Do5, capacitors Co3, Co4, and Co5, diodes Db2, Db3, and Db4, and capacitors Cb2, Cb3, and Cb4, and outputs voltage signals VD3, VD4, and VD5.

[0047] Specifically, one end of capacitor Cb2 is electrically connected to the anode terminal of diode Do2 and the other end is electrically connected to the anode terminal of diode Do3, diode Db2 has an anode terminal electrically connected to the cathode terminal of diode Do2 and a cathode terminal electrically connected to the anode terminal of diode Do3, and diode Do3 has a cathode terminal electrically connected to one end of capacitor Co3, capacitor Cb3 has one end electrically connected to the anode terminal of diode Do3 and the other end is electrically connected to the anode terminal of diode Do4, diode Db3 has an anode terminal electrically connected to the cathode terminal of diode Do3 and a cathode terminal electrically connected to the anode terminal of diode Do4, and diode Do4 has a cathode terminal electrically connected to one end of capacitor Co4. One end of capacitor Cb4 is electrically connected to the anode terminal of diode Do4 and the other end is electrically connected to the anode terminal of diode Do5, the anode terminal of diode Db4 is electrically connected to the cathode terminal of diode Do4 and the cathode terminal is electrically connected to the anode terminal of diode Do5, and the cathode terminal of diode Do5 is electrically connected to one end of capacitor Co5. The voltage conversion circuit 70 outputs the voltage value of one end of capacitor Co3 as voltage signal VD3, outputs the voltage value of one end of capacitor Co4 as voltage signal VD4, and outputs the voltage value of one end of capacitor Co5 as voltage signal VD5.

[0048] The voltage conversion circuit 70 configured as described above boosts the voltage vdd, which is the voltage value of the input voltage signal VDD, and generates and outputs a voltage signal VD1 having a voltage value of voltage vd1, a voltage signal VD2 having a voltage value of voltage vd2, a voltage signal VD3 having a voltage value of voltage vd3, a voltage signal VD4 having a voltage value of voltage vd4, and a voltage signal VD5 having a voltage value of voltage vd5.

[0049] Here, in the liquid ejection device 1 of this embodiment, the voltage conversion circuit 70 is described as outputting signals of five different voltage values, namely, voltage signals VD1 to VD5, but the voltage conversion circuit 70 may be capable of outputting signals of more than five different voltage values.

[0050] Specifically, the voltage conversion circuit 70 may have diodes Do1 and Do2, capacitors Co1 and Co2, diode Db1, and capacitor Cb1, as well as diodes Do3 to Do[n] (n is an integer greater than or equal to 3), capacitors Co3 to Co[n], diodes Db2 to Db[n-1], and capacitors Cb2 to Cb[n-1], and may be able to output voltage signals VD3 to VD[n] in addition to voltage signals VD1 and VD2.

[0051] At this time, one end of capacitor Cb[i-1] (i is an integer greater than or equal to 3 and less than or equal to n) is electrically connected to the anode terminal of diode Do[i-1] and the other end is electrically connected to the anode terminal of diode Do[i], the anode terminal of diode Do[i-1] is electrically connected to the cathode terminal of diode Do[i-1] and the cathode terminal is electrically connected to the anode terminal of diode Do[i], the cathode terminal of diode Do[i] is electrically connected to one end of capacitor Co[i], and the voltage conversion circuit 70 outputs the voltage value of one end of capacitor Co[i] as a voltage signal VDi.

[0052] 6 is a diagram illustrating the operation of the voltage conversion circuit 70. In the following description, the drain terminal and source terminal of the transistor Msw being controlled to be conductive may be referred to as "on," and the drain terminal and source terminal of the transistor Msw being controlled to be non-conductive may be referred to as "off." The operation of the transistor Msw repeatedly turning off and on may be referred to as a switching operation. In the following description, the forward drop voltage of each of the diodes Do1 to Do5 and Db1 to Db4 included in the voltage conversion circuit 70 is assumed to be 0V.

[0053] 6, before time ts when the transistor Msw starts switching operation, the voltage conversion circuit 70 outputs voltage signals VD1 to VD5 whose voltage values ​​are constant at voltage vdd. Therefore, before time ts when the transistor Msw starts switching operation, each of the voltages vd1 to vd5 is approximately equal to voltage vdd.

[0054] Then, at time ts1, the boost control circuit 75 starts outputting a gate drive signal DSW whose logic level changes between H level and L level at a predetermined cycle. This starts the switching operation of the transistor Msw. As a result, the voltage values ​​of the voltage signals VD1 to VD5 output by the boost control circuit 75 increase.

[0055] Specifically, while the transistor Msw is turned on, the current generated by the propagation of the voltage signal VDD flows through the inductor Lsw and the transistor Msw to the wiring pattern at ground potential. At this time, energy corresponding to the current generated by the propagation of the voltage signal VDD is stored in the inductor Lsw.

[0056] Then, by turning off the transistor Msw, the capacitor Co1 is supplied with a current generated by the propagation of the voltage signal VDD, as well as a current generated by the release of the energy stored in the inductor Lsw, via the diode Do1. Therefore, the capacitor Co1 accumulates a charge corresponding to the current generated by the propagation of the voltage signal VDD and a charge corresponding to the current generated by the release of the energy stored in the inductor Lsw. As a result, the voltage difference across the capacitor Co1 increases, and the voltage value at one end of the capacitor Co1 becomes greater than the voltage value of the voltage signal VDD. The voltage conversion circuit 70 then outputs a signal representing the voltage value at one end of the capacitor Co1 as the voltage signal VD1.

[0057] During the period when the transistor Msw is controlled to be on, as described above, the inductor Lsw stores energy according to the current generated by the propagation of the voltage signal VDD. A ground potential is supplied to one end of the capacitor Cb1, and a voltage signal VD1 is supplied to the other end of the capacitor Cb1 via a diode Db1, so that an electric charge according to the voltage VD1 is accumulated in the capacitor Cb1.

[0058] Then, by turning off the transistor Msw, the capacitor Co2 is supplied with a current generated by the propagation of the voltage signal VDD, as well as a current generated by the release of energy stored in the inductor Lsw and a current corresponding to the release of charge stored in the capacitor Cb1 via the diode Do2. Therefore, the capacitor Co2 accumulates charge corresponding to the current generated by the propagation of the voltage signal VDD, a current corresponding to the release of energy stored in the inductor Lsw, and a current corresponding to the release of charge stored in the capacitor Cb1. That is, the capacitor Co2 accumulates a charge equivalent to the charge stored in the capacitor Co1, plus an amount corresponding to the voltage vd1. As a result, the potential difference across the capacitor Co2—the voltage value at one end of the capacitor Co2—is the sum of the voltage value at one end of the capacitor Co1 and the voltage vd1, which is approximately twice the voltage vd1. The voltage conversion circuit 70 then outputs a signal representing the voltage value at one end of the capacitor Co2 as the voltage signal VD2.

[0059] Furthermore, during the period when the transistor Msw is controlled to be on, energy corresponding to the current generated by the propagation of the voltage signal VDD is stored in the inductor Lsw, as described above. Furthermore, during the period when the transistor Msw is controlled to be on, the voltage signal VD1 is supplied to one end of the capacitor Cb2, and the voltage signal VD2 is supplied to the other end of the capacitor Cb2 via the diode Db2, causing a charge corresponding to the voltage vd1, which is the difference between the voltage values ​​of the voltage signals VD1 and VD2, to be stored in the capacitor Cb2.

[0060] Then, by turning off the transistor Msw, the capacitor Co3 is supplied with a current generated by the propagation of the voltage signal VDD, as well as a current generated by the release of energy stored in the inductor Lsw and a current corresponding to the release of charge stored in the capacitors Cb1 and Cb2 via the diode Do3. Therefore, the capacitor Co3 accumulates charge corresponding to the current generated by the propagation of the voltage signal VDD, a current corresponding to the release of energy stored in the inductor Lsw, and a current corresponding to the release of charge stored in the capacitors Cb1 and Cb2. That is, in addition to the charge stored in the capacitor Co1, the capacitor Co3 accumulates a charge corresponding to the voltage vd2, which is the voltage value of the voltage signal VD2, and is approximately twice the voltage vd1. As a result, the potential difference across the capacitor Co3, i.e., the voltage value at one end of the capacitor Co3, is the sum of the voltage value at one end of the capacitor Co2 and the voltage vd1, and is approximately three times the voltage vd1. The voltage conversion circuit 70 then outputs a signal of the voltage value at one end of the capacitor Co3 as a voltage signal VD3.

[0061] Furthermore, during the period when the transistor Msw is controlled to be on, energy corresponding to the current generated by the propagation of the voltage signal VDD is stored in the inductor Lsw, as described above. Furthermore, during the period when the transistor Msw is controlled to be on, the voltage signal VD2 is supplied to one end of the capacitor Cb3, and the voltage signal VD3 is supplied to the other end of the capacitor Cb3 via the diode Db3, causing a charge corresponding to the voltage vd1, which is the difference between the voltage values ​​of the voltage signals VD2 and VD3, to be stored in the capacitor Cb3.

[0062] After that, when the transistor Msw is turned off, the capacitor Co4 receives the current generated by the propagation of the voltage signal VDD, as well as the current generated by the release of the energy stored in the inductor Lsw and the charge stored in the capacitors Cb1, Cb2, and Cb3. A current corresponding to the discharge of the voltage signal Vd is supplied via diode Do4. Therefore, capacitor Co4 accumulates a charge corresponding to the current generated by the propagation of the voltage signal VDD, a charge corresponding to the current associated with the discharge of the energy stored in inductor Lsw, and a charge corresponding to the current associated with the discharge of the charge stored in capacitors Cb1, Cb2, and Cb3. That is, in addition to the charge stored in capacitor Co1, capacitor Co4 accumulates a charge corresponding to voltage vd3, which is the voltage value of voltage signal VD3, approximately three times voltage vd1. As a result, the potential difference across capacitor Co4, i.e., the voltage value at one end of capacitor Co4, is the sum of the voltage value at one end of capacitor Co3 and voltage vd1, which is approximately four times voltage vd1. The voltage conversion circuit 70 then outputs a signal representing the voltage value at one end of capacitor Co4 as voltage signal VD4.

[0063] Furthermore, during the period when the transistor Msw is controlled to be on, energy is stored in the inductor Lsw due to the current generated by the propagation of the voltage signal VDD, as described above. Furthermore, during the period when the transistor Msw is controlled to be on, the voltage signal VD3 is supplied to one end of the capacitor Cb4, and the voltage signal VD4 is supplied to the other end of the capacitor Cb4 via the diode Db4, causing a charge corresponding to the voltage vd1, which is the difference between the voltage values ​​of the voltage signals VD3 and VD4, to be stored in the capacitor Cb4.

[0064] Thereafter, by controlling the transistor Msw to be off, the capacitor Co5 is supplied with a current generated in accordance with the propagation of the voltage signal VDD, as well as a current generated by the release of energy stored in the inductor Lsw and a current corresponding to the release of charge stored in the capacitors Cb1, Cb2, Cb3, and Cb4 via the diode Do5. Therefore, the capacitor Co5 stores charge corresponding to the current generated in accordance with the propagation of the voltage signal VDD, charge corresponding to the current generated by the release of energy stored in the inductor Lsw, and charge corresponding to the current generated by the release of charge stored in the capacitors Cb1, Cb2, Cb3, and Cb4. In other words, in addition to a charge approximately equal to the charge stored in the capacitor Co1, the capacitor Co5 stores a charge corresponding to the voltage vd4, which is the voltage value of the voltage signal VD4, and which is approximately four times the voltage vd1. As a result, the voltage value at one end of capacitor Co5, which is the potential difference across both ends of capacitor Co5, is the sum of the voltage value at one end of capacitor Co4 and voltage vd1, which is approximately five times voltage vd1. Then, voltage conversion circuit 70 outputs a signal of this voltage value at one end of capacitor Co5 as voltage signal VD5.

[0065] That is, the voltage conversion circuit 70 outputs a voltage vd1, a voltage vd2 that is approximately twice the voltage vd1, a voltage vd3 that is approximately three times the voltage vd1, a voltage vd4 that is approximately four times the voltage vd1, and a voltage vd5 that is approximately five times the voltage vd1.

[0066] As described above, the voltage conversion circuit 70 outputs voltage signals VD1 to VD5, which are obtained by boosting the input voltage signal VDD through the switching operation of the transistor Msw. At this time, the voltages vd1 to vd5, which are the voltage values ​​of the voltage signals VD1 to VD5 output by the voltage conversion circuit 70, are determined by the duty ratio of the switching operation of the transistor Msw. In the voltage conversion circuit 70 of this embodiment, the voltage vd1, which is the voltage value of the voltage signal VD1 among the voltage signals VD1 to VD5 output by the voltage conversion circuit 70, is divided by resistors Rf1 and Rf2, and the divided signal is fed back to the boost control circuit 75 as the constant-voltage feedback signal Vfbc. The boost control circuit 75 then controls the duty ratio of the gate drive signal DSW to be output so that the voltage value of the constant-voltage feedback signal Vfbc, which corresponds to the voltage vd1, which is the voltage value of the voltage signal VD1, is a predetermined value. As a result, the voltage vd1, which is the voltage value of the voltage signal VD1 output from the voltage conversion circuit 70, is controlled to a predetermined value, and the voltage vd2, which is the voltage value of the voltage signal VD2 obtained by approximately doubling the voltage vd1, and the voltage vd3, which is the voltage value of the voltage signal VD3 obtained by approximately tripling the voltage vd1, are controlled to a predetermined value. The voltage vd3, the voltage vd4 which is the voltage value of the voltage signal VD4 obtained by multiplying the voltage vd1 by approximately four, and the voltage vd5 which is the voltage value of the voltage signal VD5 obtained by multiplying the voltage vd1 by approximately five are also controlled to predetermined values.

[0067] The voltage conversion circuit 70 may feed back to the boost control circuit 75 a signal corresponding to the voltage value of one of the voltage signals VD2 to VD5 instead of the voltage signal VD1, so that the boost control circuit 75 controls the duty ratio of the gate drive signal DSW output so that the voltage value of one of the voltage signals VD2 to VD5 becomes a predetermined value.

[0068] Furthermore, in the voltage conversion circuit 70 shown in Figure 5, it has been explained that the other end of capacitor Co2, the other end of capacitor Co3, the other end of capacitor Co4, and the other end of capacitor Co5 are each supplied with ground potential, but the other end of capacitor Co2 may be electrically connected to one end of capacitor Co1, the other end of capacitor Co3 may be electrically connected to one end of capacitor Co2, the other end of capacitor Co4 may be electrically connected to one end of capacitor Co3, and the other end of capacitor Co5 may be electrically connected to one end of capacitor Co4.

[0069] In the voltage conversion circuit 70 shown in FIG. 5, a ground potential is supplied to the other end of capacitor Co2, the other end of capacitor Co3, the other end of capacitor Co4, and the other end of capacitor Co5, thereby stabilizing the reference potential of each of capacitors Co2 to Co5. This improves the accuracy of the voltage values ​​of voltage signals VD2 to VD5 output from one end of each of capacitors Co2 to Co5. Meanwhile, by electrically connecting the other end of capacitor Co2 to one end of capacitor Co1, the other end of capacitor Co3 to one end of capacitor Co2, the other end of capacitor Co4 to one end of capacitor Co3, and the other end of capacitor Co5 to one end of capacitor Co4, it is possible to reduce the capacitance and withstand voltage of each of capacitors Co2 to Co5. This allows for the miniaturization of capacitors Co2 to Co5 and the voltage conversion circuit 70.

[0070] 4. Configuration and operation of the drive circuit Next, the configuration and operation of the drive circuit 50 will be described.

[0071] 4.1 Signal waveform of drive signal COM Before describing the configuration and operation of the drive circuit 50, an example of the signal waveform of the drive signal COM output by the drive circuit 50 will be described. FIG. 7 is a diagram showing an example of the signal waveform of the drive signal COM. As shown in FIG. 7, the drive signal COM includes a trapezoidal waveform Adp every period T. The trapezoidal waveform Adp includes a fixed period at voltage vc, a fixed period at voltage vb lower than voltage vc following the fixed period at voltage vc, a fixed period at voltage vb following the fixed period at voltage vt higher than voltage vc, and a fixed period at voltage vt following the fixed period at voltage vc. In other words, the drive signal COM changes voltage between voltage vt and voltage vb, and includes a trapezoidal waveform Adp that starts at voltage vc and ends at voltage vc during period T.

[0072] The voltage vc corresponds to a potential that serves as a reference for the displacement of the piezoelectric element 60. When the voltage of the drive signal COM supplied to the piezoelectric element 60 changes from voltage vc to voltage vb, the piezoelectric element 60 is driven in the upward direction shown in FIG. 4. As a result, the vibration plate 621 is displaced in the upward direction shown in FIG. 4. When the vibration plate 621 is displaced in the upward direction shown in FIG. 4, the internal volume of the cavity 631 expands, and ink is drawn into the cavity 631 from the reservoir 641. Thereafter, when the voltage of the drive signal COM supplied to the piezoelectric element 60 changes from voltage vb to voltage vt, the piezoelectric element 60 is driven in the downward direction shown in FIG. 4. As a result, the vibration plate 621 is displaced in the upward direction shown in FIG. 4. 4, the internal volume of cavity 631 is reduced, and ink stored in cavity 631 is ejected from nozzle 651.

[0073] Furthermore, the ink near the nozzle 651 and the diaphragm 621 may continue to vibrate for a certain period after ink is ejected from the nozzle 651 by driving the piezoelectric element 60. The certain period of time at which the voltages vc, vt, and vb included in the drive signal COM are present also functions as a period for stopping such vibrations that occur in the ink and the diaphragm 621 and do not contribute to the ejection of ink.

[0074] Here, the signal waveform of the drive signal COM shown in Figure 7 is an example and is not limited to this, and may include signal waveforms of various shapes depending on the physical properties of the ink ejected by the liquid ejection head 21, the length of the period T of the drive signal COM, the transport speed of the medium P, etc.

[0075] 4.2 Drive circuit configuration Next, a description will be given of the configuration of the drive circuit 50. Fig. 8 is a diagram showing an example of the functional configuration of the drive circuit 50. As shown in Fig. 8, the drive circuit 50 has a D / A conversion circuit 510, an adder 511, a modulation circuit 520, an inverter 521, an amplifier circuit 550, a demodulation circuit 560, a feedback circuit 570, a level switching signal output circuit 710, and a level shift circuit 750.

[0076] The D / A conversion circuit 510 receives a digital reference drive signal dA from the control circuit 100. The D / A conversion circuit 510 performs digital-to-analog conversion on the reference drive signal dA that is received, and then outputs the converted analog signal as the reference drive signal aA. The voltage amplitude of this reference drive signal aA is, for example, 1 to 2 V, and the drive circuit 50 outputs an amplified signal of the reference drive signal aA as the drive signal COM. In other words, the reference drive signal aA corresponds to a target signal before amplification of the drive signal COM.

[0077] The base drive signal aA is input to the positive input terminal of the adder 511. A feedback signal VFB2, which is the drive signal COM fed back via a feedback circuit 570 (described later), is input to the negative input terminal of the adder 511. The adder 511 outputs a signal obtained by subtracting the feedback signal VFB2 from the base drive signal aA to the modulation circuit 520.

[0078] The modulation circuit 520 generates a modulated signal MS by pulse-modulating the signal output by the adder 511. The modulation circuit 520 then outputs the generated modulated signal MS to the amplifier circuit 550. The modulation circuit 520 generates a pulse density modulated signal (PDM signal) by modulating the signal output by the adder 511 using a pulse density modulation (PDM) method, and outputs the PDM signal to the amplifier circuit 550 as the modulated signal MS. Specifically, the modulation circuit 520 compares the voltage of the output signal of the adder 511 with a predetermined reference voltage vref. The modulation circuit 520 then generates a modulated signal MS that goes to an H level when the voltage of the output signal of the adder 511 is greater than the reference voltage vref, and goes to an L level when the voltage of the output signal of the adder 511 is smaller than the reference voltage vref, and outputs the modulated signal MS to the amplifier circuit 550.

[0079] The amplifier circuit 550 includes a gate drive circuit 530, a diode D1, a capacitor C1, and transistors M1 and M2. The amplifier circuit 550 amplifies the input modulated signal MS to generate a first amplified modulated signal AMS1 and outputs it from a first output point OP1.

[0080] The gate drive circuit 530 outputs gate signals HGD1 and LGD1 based on the modulation signal MS. Specifically, the modulation signal MS is input to a gate driver 531 included in the gate drive circuit 530. The gate driver 531 generates a gate signal HGD1 by level-shifting the input modulation signal MS, and outputs the gate signal HGD1 to the transistor M1. The modulation signal MS has its logic level inverted by an inverter 521 and is then input to a gate driver 532 included in a gate drive circuit 530. The gate driver 532 generates a gate signal LGD1 by level-shifting the inverted logic level of the input modulation signal MS, and outputs the gate signal LGD1 to a transistor M2.

[0081] The transistors M1 and M2 are both configured as N-channel MOSFETs. The source terminal of the transistor M1 is electrically connected to the first output point OP1, the drain terminal is supplied with a voltage signal VD3, and the gate terminal is operated based on a gate signal HGD1 input. The drain terminal of the transistor M2 is electrically connected to the first output point OP1, the source terminal is supplied with a ground potential, and the gate terminal is operated based on a gate signal LGD1 input. As the transistor M1 operates based on the gate signal HGD1 and the transistor M2 operates based on the gate signal LGD1, a first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS by a voltage vd3, which is the voltage value of the voltage signal VD3, is generated at the first output point OP1.

[0082] Here, the operation of the gate drive circuit 530 will be described. The gate drive circuit 530 includes gate drivers 531 and 532. As described above, the gate driver 531 receives the modulation signal MS, and the gate driver 532 receives a signal obtained by inverting the logic level of the modulation signal MS by the inverter 521. That is, the signal input to the gate driver 531 and the signal input to the gate driver 532 are exclusively at the H level. Here, "exclusively at the H level" includes the case where an H level signal is not input to the gate driver 531 and the gate driver 532 at the same time. That is, it does not exclude the case where an L level signal is input to the gate driver 531 and the gate driver 532 at the same time.

[0083] The low-potential power supply terminal of the gate driver 531 is electrically connected to the first output point OP1. Therefore, the first amplified modulation signal AMS1 generated at the first output point OP1 is supplied to the low-potential power supply terminal of the gate driver 531 as a voltage signal HVS1. The high-potential power supply terminal of the gate driver 531 is electrically connected to the cathode terminal of the diode D1 and one end of the capacitor C1. The anode terminal of the diode D1 is supplied with a voltage signal VD1, and the other end of the capacitor C1 is electrically connected to the first output point OP1. That is, the diode D1 and the capacitor C1 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 531. Therefore, the high-potential power supply terminal of the gate driver 531 is supplied with a voltage signal HVD1 whose voltage value is higher by a voltage vd1 than the voltage value of the voltage signal HVS1 input to the low-potential power supply terminal of the gate driver 531.

[0084] Therefore, when an H-level modulation signal MS is input, the gate driver 531 outputs a gate signal HGD1 based on a voltage signal HVD1 whose voltage value is higher than the voltage value of the first output point OP1 by the voltage vd1, and when an L-level modulation signal MS is input, the gate driver 531 outputs a gate signal HGD1 based on a voltage signal HVS1 which is the voltage value of the first output point OP1. Here, the voltage vd1 is a voltage value capable of driving each of the transistors M1 and M2 and the transistors M3 and M4 described below, and in the liquid ejection device 1 of this embodiment, as described above, it is a DC voltage of 8.4 V.

[0085] The ground potential is supplied as a voltage signal LVS1 to the low-potential power supply terminal of the gate driver 532. Furthermore, the voltage vd1, which is the voltage value of the voltage signal VD1, is supplied as a voltage signal LVD1 to the high-potential power supply terminal of the gate driver 532. Therefore, when an H-level signal obtained by inverting the logic level of the L-level modulation signal MS by the inverter 521 is input, the gate driver 532 outputs the voltage signal L, whose voltage value is the voltage vd1. When an L-level signal obtained by inverting the logical level of the H-level modulation signal MS by inverter 521 is input, it outputs a gate signal LGD1 with a voltage value based on the voltage signal LVS1 of ground potential. Then, transistor M1 operates based on the gate signal HGD1, and transistor M2 operates based on the gate signal LGD1, so that a first amplified modulation signal AMS1 obtained by amplifying the modulation signal MS by voltage vd3, which is the voltage value of the voltage signal VD3, is output from first output point OP1.

[0086] The level switching signal output circuit 710 receives the reference drive signal aA and a feedback signal VFB1 output by a feedback circuit 570, which will be described later. The level switching signal output circuit 710 outputs a level switching signal LS, the logic level of which changes based on the reference drive signal aA and feedback signal VFB1 that are input. Specifically, the level switching signal output circuit 710 outputs an H-level level switching signal LS during a period when the value of the reference drive signal aA is constant and greater than a predetermined threshold, outputs an L-level level switching signal LS during a period when the value of the reference drive signal aA is constant and smaller than a predetermined threshold, and outputs a level switching signal LS, the logic level of which changes based on the reference drive signal aA and the feedback signal VFB1 during a period when the value of the reference drive signal aA changes. The configuration and operation of the level switching signal output circuit 710 will be described in detail below.

[0087] The level shift circuit 750 includes a gate drive circuit 730, diodes D11 and D12, capacitors C11 and C12, transistors M3 and M4, and a boost circuit BS. The level shift circuit 750 outputs the first amplified modulated signal AMS1 or a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 from a second output point OP2 in response to an input level switching signal LS.

[0088] The gate drive circuit 730 outputs gate signals HGD2 and LGD2 based on the level switching signal LS. Specifically, the level switching signal LS is input to a gate driver 731 included in the gate drive circuit 730. The gate driver 731 generates a gate signal HGD2 by level-shifting the input level switching signal LS and outputs the gate signal HGD2 to transistor M3. The logical level of the level switching signal LS is inverted by an inverter 721, and then the level switching signal LS is input to a gate driver 732 included in the gate drive circuit 730. The gate driver 732 generates a gate signal LGD2 by level-shifting the logical level of the input level switching signal LS, and outputs the gate signal LGD2 to transistor M4.

[0089] The transistors M3 and M4 are both configured as N-channel MOSFETs. The source terminal of the transistor M3 is electrically connected to the second output point OP2, the drain terminal is supplied with the voltage signal VBST, and the gate terminal is operated based on the gate signal HGD2 input. The drain terminal of the transistor M4 is electrically connected to the second output point OP2, the source terminal is supplied with the first amplified modulation signal AMS1, and the gate terminal is operated based on the gate signal LGD2. The transistor M3 operates based on the gate signal HGD2, and the transistor M4 operates based on the gate signal LGD2, so that the first amplified modulation signal AMS1 or a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 is output from the second output point OP2 as the second amplified modulation signal AMS2.

[0090] The boost circuit BS includes a diode D13 and a capacitor C13. One end of the capacitor C13 is electrically connected to the first output point OP1, the first amplified modulation signal AMS1 is supplied to the one end, and the other end is electrically connected to the drain terminal of the transistor M3. The anode terminal of the diode D13 is supplied with the voltage signal VD2, and the cathode terminal of the diode D13 is electrically connected to the other end of the capacitor C13 and the drain terminal of the transistor M3. In FIG. 8, the boost circuit BS includes one diode D1 Although the boost circuit BS is illustrated as having a diode D13, the boost circuit BS may also include multiple diodes D13 connected in series. To be precise, the drain terminal of the transistor M3 is supplied with a voltage signal VBST based on a voltage value obtained by subtracting the forward drop voltage of the diode D13 from the voltage vd2, which is the voltage value of the voltage signal VD2. However, in the following explanation, the forward drop voltage of the diode D13 is assumed to be 0V.

[0091] The boost circuit BS then generates a voltage signal VBST by adding the voltage value of the first amplified modulation signal AMS1 to the voltage vd2, which is the voltage value across the capacitor 13, and outputs it to the drain terminal of the transistor M3. In other words, the boost circuit BS generates a voltage signal VBST by level-shifting the reference potential of the first amplified modulation signal AMS1 by the voltage vd2, which is the voltage value of the voltage signal VD2, and outputs it to the drain terminal of the transistor M3.

[0092] Here, the operation of the gate drive circuit 730 will be described. The gate drive circuit 730 includes gate drivers 731 and 732. As described above, the level switching signal LS is input to the gate driver 731, and a signal obtained by inverting the logical level of the level switching signal LS by the inverter 721 is input to the gate driver 732. That is, the signal input to the gate driver 731 and the signal input to the gate driver 732 are exclusively at H level. Here, "exclusively at H level" includes the case where an H level signal is not input to the gate driver 731 and the gate driver 732 at the same time. That is, it does not exclude the case where an L level signal is input to the gate driver 731 and the gate driver 732 at the same time.

[0093] The low-potential power supply terminal of the gate driver 731 is electrically connected to the second output point OP2. Therefore, the signal generated at the second output point OP2 is supplied to the low-potential power supply terminal of the gate driver 731 as a voltage signal HVS2. The high-potential power supply terminal of the gate driver 731 is electrically connected to the cathode terminal of the diode D11 and one end of the capacitor C11. The anode terminal of the diode D11 is supplied with a voltage signal VD1, and the other end of the capacitor C11 is electrically connected to the second output point OP2. That is, the diode D11 and the capacitor C11 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 731. Therefore, the high-potential power supply terminal of the gate driver 731 is supplied with a voltage signal HVD2 whose voltage value is higher by a voltage vd1 than the voltage value of the voltage signal HVS2 input to the low-potential power supply terminal of the gate driver 731.

[0094] Therefore, when an H-level level switching signal LS is input, the gate driver 731 outputs a gate signal HGD2 based on a voltage signal HVD2 having a voltage value that is higher by a voltage vd1 than the voltage value of the second output point OP2, and when an L-level level switching signal LS is input, the gate driver 731 outputs a gate signal HGD2 based on a voltage signal HVS2 having a voltage value that is the voltage value of the second output point OP2.

[0095] The low-potential power supply terminal of the gate driver 732 is connected to the first output point OP1. Therefore, the first amplified modulation signal AMS1 output from the first output point OP1 is supplied to the low-potential power supply terminal of the gate driver 732 as a voltage signal LVS2. Furthermore, the high-potential power supply terminal of the gate driver 732 is electrically connected to the cathode terminal of the diode D12 and one end of the capacitor C12. The anode terminal of the diode D12 is supplied with a voltage signal VD1, and the other end of the capacitor C12 is electrically connected to the first output point OP1. That is, the diode D12 and the capacitor C12 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 732. Therefore, the high-potential power supply terminal of the gate driver 732 is supplied with the voltage signal LVS2 input to the low-potential power supply terminal of the gate driver 732. A voltage signal LVD2 having a voltage value higher than the voltage value of VS2 by a voltage vd1 is supplied.

[0096] Therefore, when the gate driver 732 receives an H-level signal inverted by the inverter 721 from the logical level of the L-level level switching signal LS, it outputs a gate signal LGD2 based on a voltage signal LVD2 having a voltage value higher than the voltage value of the first output point OP1 by a voltage vd1, and when the gate driver 732 receives an L-level signal inverted by the inverter 721 from the logical level of the H-level level switching signal LS, it outputs a gate signal HGD2 based on the voltage signal LVS2, which is the voltage value of the first output point OP1.

[0097] When an L-level level switching signal LS is input to the level shift circuit 750 configured as described above, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the transistor M4. Therefore, when the input level switching signal LS is L-level, the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 from the second output point OP2.

[0098] On the other hand, when an H-level level switching signal LS is input to the level shift circuit 750, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the boost circuit BS and the transistor M3. Therefore, when the level switching signal LS is H, the level shift circuit 750 outputs, from the second output point OP2, as the second amplified modulation signal AMS2, a voltage signal VBST, which is a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 by the voltage vd2, which is the voltage value of the voltage signal VD2.

[0099] The second amplified modulated signal AMS2 output by the level shift circuit 750 is input to the demodulation circuit 560. The demodulation circuit 560 demodulates the second amplified modulated signal AMS2 output by the level shift circuit 750 by smoothing it, and outputs the demodulated signal as the drive signal COM.

[0100] The demodulation circuit 560 includes an inductor 561 and a capacitor 562. One end of the inductor 561 is electrically connected to the second output point OP2. The other end of the inductor 561 is electrically connected to one end of the capacitor 562. The other end of the capacitor 562 is supplied with a ground potential. That is, the inductor 561 and the capacitor 562 form a low-pass filter circuit. This low-pass filter circuit smoothes the second amplified modulated signal AMS2 output from the level shift circuit 750. Then, the signal obtained by smoothing the second amplified modulated signal AMS2 is output from the drive circuit 50 as the drive signal COM.

[0101] The feedback circuit 570 generates a feedback signal VFB1 according to the drive signal COM generated by the demodulation circuit 560, and outputs it to the level switching signal output circuit 710. The feedback signal VFB1 output by the feedback circuit 570 is a signal obtained by dividing the drive signal COM using a voltage divider circuit (not shown) and extracting high-frequency components of the signal obtained by dividing the drive signal COM using a high-pass filter (not shown) or the like.

[0102] Furthermore, the feedback circuit 570 generates a feedback signal VFB2 corresponding to the drive signal COM generated by the demodulation circuit 560 and outputs it to the adder 511. The feedback signal VFB2 output by the feedback circuit 570 includes a signal obtained by dividing the drive signal COM, and a signal obtained by dividing the drive signal COM using a voltage divider circuit (not shown) and extracting high-frequency components of the signal obtained by dividing the drive signal COM using a high-pass filter (not shown) or the like. The adder 511 then outputs a signal obtained by subtracting the feedback signal VFB2 from the basic drive signal aA to the modulation circuit 520, and the modulation circuit 520 outputs a modulated signal MS based on the feedback signal VFB2 according to the output of the adder 511. This improves the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0103] Here, in the feedback circuit 570, the voltage divider circuit for generating the feedback signal VFB2 and the voltage divider circuit for generating the feedback signal VFB1 may be a common circuit, and the high-pass filter for generating the feedback signal VFB2 and the high-pass filter for generating the feedback signal VFB1 may be a common circuit.

[0104] As described above, the drive circuit 50 of this embodiment is a so-called capacitive load drive circuit that outputs a drive signal COM for driving a capacitive load such as a piezoelectric element 60, and includes a modulation circuit 520 that modulates the basic drive signal aA according to the basic drive signal dA that is the basis of the drive signal COM and outputs a modulated signal MS, a gate drive circuit 530 that outputs gate signals HGD1 and LGD1 according to the modulated signal MS, an amplifier circuit 550 that amplifies the modulated signal MS and outputs a first amplified modulated signal AMS1 according to the gate signals HGD1 and LGD1, and a voltage level L level a level shift circuit 750 that outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 when the level switching signal LS is at L level, and outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 when the level switching signal LS is at H level; a demodulation circuit 560 that demodulates the second amplified modulated signal AMS2 and outputs a drive signal COM; and a feedback circuit 570 that outputs a feedback signal VFB1 according to the drive signal COM.

[0105] At least one of the voltage signals VD1 and VD2, and both the voltage signals VD1 and VD2, are supplied to the drive circuit 50 of this embodiment. Specifically, of the voltage signals VD1 to VD5 output by the voltage conversion circuit 70, the voltage signal VD1 is supplied to the gate drive circuit 530 and the gate drive circuit 730, the voltage signal VD3 is supplied to the amplifier circuit 550, and the voltage signal VD2 is supplied to the level shift circuit 750.

[0106] Here, the signal output from the voltage conversion circuit 70 and input to the amplifier circuit 550, which is supplied to the drain terminal of the transistor M1 of the amplifier circuit 550, is not limited to the voltage signal VD3 but may be any of the voltage signals VD1 to VD5. Furthermore, the signal output from the voltage conversion circuit 70 and input to the level shift circuit 750, which is supplied to the boost circuit BS of the level shift circuit 750, is not limited to the voltage signal VD2 but may be any of the voltage signals VD1 to VD5. However, as shown in the liquid ejection device 1 of this embodiment, it is preferable that the voltage value of the signal supplied to the drain terminal of the transistor M1 of the amplifier circuit 550 be equal to or greater than the voltage value of the signal supplied to the boost circuit BS of the level shift circuit 750. That is, when the voltage signal VDi is supplied to the drain terminal of the transistor M1 of the amplifier circuit 550, it is preferable that any of the voltage signals VD1 to VDi is supplied to the boost circuit BS of the level shift circuit 750.

[0107] Furthermore, in this case, it is more preferable that the value of the base drive signal aA corresponding to a predetermined threshold value used for switching whether the level switching signal output circuit 710 outputs an L-level level switching signal LS or an H-level level switching signal LS is equal to or less than the value of the base drive signal aA when the voltage value of the drive signal COM is the voltage value of the signal supplied to the drain terminal of transistor M1 of the amplifier circuit 550, and is equal to or greater than the value of the base drive signal aA when the voltage value of the signal is the voltage value of the signal supplied to the boost circuit BS of the level shift circuit 750.

[0108] When the level switching signal output circuit 710 outputs an L-level level switching signal LS and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2, the voltage value of the drive signal COM output by the drive circuit 50 changes between the ground potential and the voltage value of the signal supplied to the drain terminal of the transistor M1 of the amplifier circuit 550. In contrast, when the level switching signal output circuit 710 outputs an H-level level When the amplifier circuit 50 is outputting a level switching signal LS and the level shift circuit 750 is outputting a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2, the voltage value of the drive signal COM output by the drive circuit 50 changes between the voltage value of the signal supplied to the boost circuit BS of the level shift circuit 750 and the voltage value obtained by adding the voltage value of the signal supplied to the drain terminal of the transistor M1 of the amplifier circuit 550 to the voltage value of the signal supplied to the boost circuit BS of the level shift circuit 750.

[0109] In such a liquid ejection device 1, the voltage value of the signal supplied to the drain terminal of transistor M1 of the amplifier circuit 550 is set to be equal to or greater than the voltage value of the signal supplied to the boost circuit BS of the level shift circuit 750, and the value of the base drive signal aA, which corresponds to a predetermined threshold for switching whether the level switching signal output circuit 710 outputs an L-level level switching signal LS or an H-level level switching signal LS, is set to be equal to or less than the value of the base drive signal aA when the voltage value of the drive signal COM is the voltage value of the signal supplied to the drain terminal of transistor M1 of the amplifier circuit 550, and equal to or greater than the value of the base drive signal aA when the voltage value of the signal supplied to the boost circuit BS of the level shift circuit 750.This causes a portion of the voltage range of the drive signal COM that the drive circuit 50 can output during the period when the level switching signal output circuit 710 is outputting an L-level level switching signal LS to overlap with a portion of the voltage range of the drive signal COM that the drive circuit 50 can output during the period when the level switching signal output circuit 710 is outputting an H-level level switching signal LS.

[0110] This allows the drive circuit 50 to continuously control the voltage value of the drive signal COM within a range from the ground potential to a voltage value obtained by adding the voltage value of the signal supplied to the drain terminal of the transistor M1 of the amplifier circuit 550 to the voltage value of the signal supplied to the boost circuit BS of the level shift circuit 750. As a result, the waveform accuracy of the drive signal COM output by the drive circuit 50 is improved.

[0111] Furthermore, it is preferable that the maximum voltage value that the drive circuit 50 can output as the drive signal COM, which is the voltage value of the signal supplied to the drain terminal of transistor M1 of amplifier circuit 550 plus the voltage value of the signal supplied to boost circuit BS of level shift circuit 750, is equal to or less than voltage vd5, which is the voltage value of voltage signal VD5 input to selection control circuit 200.

[0112] As described above, the drive signal COM output by the drive circuit 50 is input to a plurality of selection units 230. Each of the plurality of selection units 230 selects or deselects the input drive signal COM based on the selection signal S converted into a high-amplitude logic signal based on the voltage vd5 output by the selection control unit 210, thereby generating a drive signal VOUT and outputting it to the corresponding ejection unit 600. In such a liquid ejection device 1, by making the maximum voltage value that the drive circuit 50 can output as the drive signal COM smaller than the voltage vd5 that defines the logic level of the selection signal S, it becomes possible for each of the plurality of selection units 230 to select or deselect the drive signal COM without exceeding the withstand voltage of the selection control circuit 200. That is, as shown in the drive circuit 50 of this embodiment, by making the sum of voltage vb3, which is the voltage value of the voltage signal VD3 supplied to the drain terminal of transistor M1 of amplifier circuit 550, and voltage vd2, which is the voltage value of the voltage signal VD2 supplied to boost circuit BS of level shift circuit 750, equal to or less than voltage vd5, which is the voltage value of the voltage signal VD5 input to the selection control circuit 200, a drive signal VOUT is supplied to the ejection section 600, and as a result, ink can be ejected from the ejection section 600.

[0113] In the following description, the level switching signal output circuit 710 outputs the L-level level switching signal LS, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2, and the value of the basic drive signal aA is constant. The operating mode of the drive circuit 50 during this period, in which the level switching signal output circuit 710 outputs an H-level level switching signal LS, causing the level shift circuit 750 to output a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2, and in which the value of the base drive signal aA is constant, is sometimes referred to as a second mode MD2, and the operating mode of the drive circuit 50 during this period, in which the value of the base drive signal aA changes regardless of the logical level of the level switching signal LS output by the level switching signal output circuit 710, is sometimes referred to as a third mode MD3.

[0114] As described above, when the value of the reference drive signal aA is smaller than a predetermined threshold, the level switching signal output circuit 710 outputs an L-level level switching signal LS, and when the value of the reference drive signal aA is larger than the predetermined threshold, the level switching signal output circuit 710 outputs an H-level level switching signal LS. That is, the first mode MD1 corresponds to the operating mode of the drive circuit 50 when the value of the reference drive signal aA is smaller than the predetermined threshold and is constant, the second mode MD2 corresponds to the operating mode of the drive circuit 50 when the value of the reference drive signal aA is larger than the predetermined threshold and is constant, and the third mode MD3 corresponds to the operating mode of the drive circuit 50 when the value of the reference drive signal aA changes.

[0115] 4.3 Operation of the drive circuit Next, the operation of the drive circuit 50 will be described. FIG. 9 is a diagram for explaining the operation of the drive circuit 50. Note that FIG. 9 illustrates only the drive signal COM at an arbitrary period T among the drive signals COM output by the drive circuit 50. For ease of illustration and explanation, FIG. 9 illustrates a signal waveform in an ideal case where there is no circuit delay or wiring delay. FIG. 9 also illustrates the threshold value dvth of the basic drive signal aA that switches the logical level of the level switching signal LS output by the level switching signal output circuit 710, and the voltage value of the drive signal COM corresponding to the threshold value dvth is illustrated as voltage vth. FIG. 9 also illustrates the values ​​of the basic drive signal aA corresponding to voltages vt, vb, and vc, which are the voltage values ​​of the drive signal COM, as voltages dvt, dvb, and dvc, respectively. Note that FIG. 9 illustrates a case where voltage vth is lower than voltage vc and threshold dvth is smaller than voltage dvc, but voltage vth may be higher than voltage vc and threshold dvth may be higher than voltage dvc.

[0116] 9, during the period from time t0 to time t10, the D / A conversion circuit 510 outputs a reference drive signal aA whose voltage value is greater than threshold value dvth and which is constant at voltage dvc in response to the reference drive signal dA input, and the drive circuit 50 outputs a drive signal COM whose voltage value is greater than voltage vth and which is constant at voltage vc in response to the reference drive signal dA and the reference drive signal aA. That is, during the period from time t0 to time t10, the operation mode of the drive circuit 50 is the second mode MD2.

[0117] During the period from time t10 to time t20, the D / A conversion circuit 510 outputs the basic drive signal aA, which is a basic drive signal aA whose voltage value changes from voltage dvc below threshold value dvth to voltage dvb, in accordance with the basic drive signal dA input, and the drive circuit 50 outputs the drive signal COM, whose voltage value changes from voltage vc below voltage vth to voltage vb, in accordance with the basic drive signal dA and the basic drive signal aA. That is, during the period from time t10 to time t20, the operation mode of the drive circuit 50 is the third mode MD3.

[0118] During the period from time t20 to time t30, the D / A conversion circuit 510 outputs a reference drive signal aA whose voltage value is smaller than the threshold value dvth and whose voltage is constant at dvb in accordance with the reference drive signal dA input, and the drive circuit 50 outputs a drive signal COM whose voltage value is smaller than voltage vth and whose voltage is constant at vb in accordance with the reference drive signal dA and the reference drive signal aA. That is, during the period from time t20 to time t30, the operation mode of the drive circuit 50 is the first mode MD1.

[0119] During the period from time t30 to time t40, the D / A conversion circuit 510 outputs a basic drive signal aA whose value changes in accordance with the basic drive signal dA input, the basic drive signal aA being a basic drive signal aA whose voltage value changes from voltage dvb to exceeding threshold value dvth to voltage dvt, and the drive circuit 50 outputs a drive signal COM whose voltage value changes from voltage vb to exceeding voltage vth to voltage vt in accordance with the basic drive signal dA and the basic drive signal aA. That is, during the period from time t30 to time t40, the operation mode of the drive circuit 50 is the third mode MD3.

[0120] During the period from time t40 to time t50, the D / A conversion circuit 510 outputs a reference drive signal aA whose voltage value is greater than threshold value dvth and is constant at voltage dvt in response to the input reference drive signal dA, and the drive circuit 50 outputs a drive signal COM whose voltage value is greater than voltage vth and is constant at voltage vt in response to the reference drive signal dA and the reference drive signal aA. That is, during the period from time t40 to time t50, the operation mode of the drive circuit 50 is the second mode MD2.

[0121] During the period from time t50 to time t60, the D / A conversion circuit 510 outputs the reference drive signal aA, which is a reference drive signal aA whose voltage value changes from voltage dvt to voltage dvc in accordance with the reference drive signal dA input, and the drive circuit 50 outputs a drive signal COM whose voltage value changes from voltage vt to voltage vc in accordance with the reference drive signal dA and the reference drive signal aA. That is, during the period from time t50 to time t60, the operating mode of the drive circuit 50 is the third mode MD3.

[0122] During the period from time t60 to time t70, the D / A conversion circuit 510 outputs a reference drive signal aA whose voltage value is greater than threshold value dvth and which is constant at voltage dvc in response to the reference drive signal dA input, and the drive circuit 50 outputs a drive signal COM whose voltage value is greater than voltage vth and which is constant at voltage vc in response to the reference drive signal dA and the reference drive signal aA. That is, during the period from time t60 to time t70, the operation mode of the drive circuit 50 is the second mode MD2.

[0123] Here, time t70 corresponds to the above-mentioned time t0. That is, the period from time t0 to time t70 corresponds to cycle T. Then, as shown in Fig. 9, the operation mode of the drive circuit 50 is switched to a first mode MD1, a second mode MD2, and a third mode MD3 according to the input basic drive signals dA and aA.

[0124] Here, the operation of the drive circuit 50 in each operation mode will be described.

[0125] In the first mode MD1, the D / A conversion circuit 510 outputs a constant basic drive signal aA whose voltage value is smaller than the threshold value dvth. At this time, the modulation circuit 520 outputs a modulated signal MS with an approximately constant duty ratio because the voltage value of the basic drive signal aA input thereto is constant and the voltage value of the drive signal COM output by the drive circuit 50 is constant. Therefore, the amplifier circuit 550 amplifies the modulated signal MS based on the voltage vd3 to generate and output a first amplified modulated signal AMS1 with an approximately constant duty ratio.

[0126] Furthermore, in the first mode MD1, the D / A conversion circuit 510 outputs a constant basic drive signal aA whose voltage value is smaller than the threshold value dvth, and therefore the level switching signal output circuit 710 outputs an L-level level switching signal LS. Therefore, the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. That is, in the first mode MD1, the level shift circuit 750 outputs the first amplified modulated signal AMS1 whose duty ratio is approximately constant as the second amplified modulated signal AMS2. Then, the second amplified modulated signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560. As a result, in the first mode MD1, the drive circuit 50 outputs a drive signal COM whose voltage value is smaller than the voltage vth and is constant.

[0127] In the second mode MD2, the D / A conversion circuit 510 outputs a constant basic drive signal aA whose voltage value is greater than the threshold value dvth. At this time, the modulation circuit 520 outputs a modulated signal MS with an approximately constant duty ratio because the voltage value of the basic drive signal aA input thereto is constant and the voltage value of the drive signal COM output by the drive circuit 50 is constant. Therefore, the amplifier circuit 550 amplifies the modulated signal MS based on the voltage vd3 to generate and output a first amplified modulated signal AMS1 with an approximately constant duty ratio.

[0128] Furthermore, in the second mode MD2, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value is greater than the threshold value dvth and is constant, and therefore the level switching signal output circuit 710 outputs an H-level level switching signal LS. Therefore, the level shift circuit 750 outputs, as the second amplified modulated signal AMS2, a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 by a voltage vd2. That is, in the second mode MD2, the level shift circuit 750 outputs, as the second amplified modulated signal AMS2, a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1, which has a substantially constant duty ratio, from the ground potential to a voltage vb2. The second amplified modulated signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, and therefore, in the second mode MD2, the drive circuit 50 outputs a drive signal COM whose voltage value is greater than the voltage vth and is constant.

[0129] In the third mode MD3, the D / A conversion circuit 510 outputs a reference drive signal aA whose voltage value changes. At this time, the modulation circuit 520 outputs a modulated signal MS whose duty ratio changes based on the difference between the voltage value of the input variable reference drive signal aA and a feedback signal VFB2 that corresponds to the drive signal COM output by the drive circuit 50. Therefore, the amplifier circuit 550 amplifies the modulated signal MS based on the voltage vd3, thereby generating and outputting a first amplified modulated signal AMS1 whose duty ratio changes based on the difference between the voltage value of the variable reference drive signal aA and the feedback signal VFB2.

[0130] Furthermore, in the third mode MD3 in which the voltage value of the reference drive signal aA changes, if both the voltage value of the reference drive signal aA before the change and the voltage value of the reference drive signal aA after the change are smaller than the threshold value dvth, the level switching signal output circuit 710 continues to output the L-level level switching signal LS. At this time, the level shift circuit 750 outputs the first amplified modulated signal AMS1, whose duty ratio changes in accordance with the change in the reference drive signal aA, as the second amplified modulated signal AMS2. Then, the second amplified modulated signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, and the drive circuit 50 outputs a drive signal COM whose voltage value changes while being smaller than the voltage vth in accordance with the change in the voltage value of the reference drive signal aA. In addition, in the third mode MD3 in which the voltage value of the reference drive signal aA changes, when both the voltage value of the reference drive signal aA before the change and the voltage value of the reference drive signal aA after the change are smaller than the threshold value dvth, the level switching signal output circuit 710 may output a level switching signal LS whose logical level changes based on the reference drive signal aA and the feedback signal VFB1.

[0131] Furthermore, in the third mode MD3 in which the voltage value of the reference drive signal aA changes, when both the voltage value of the reference drive signal aA before the change and the voltage value of the reference drive signal aA after the change are greater than the threshold value dvth, the level switching signal output circuit 710 continues to output the H level level switching signal LS. At this time, the level shift circuit 750 outputs, as the second amplified modulated signal AMS2, a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1, whose duty ratio changes, by a voltage vd2 in accordance with the change in the reference drive signal aA. Then, the second amplified modulated signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, so that the drive circuit 50 outputs a signal in a state in which the voltage value is greater than the voltage vth in accordance with the change in the voltage value of the reference drive signal aA. In the third mode MD3 in which the voltage value of the reference drive signal aA changes, when both the voltage value of the reference drive signal aA before the change and the voltage value of the reference drive signal aA after the change are greater than the threshold value dvth, the level switching signal output circuit 710 may output a level switching signal LS whose logic level changes based on the reference drive signal aA and the feedback signal VFB1.

[0132] Furthermore, in the third mode MD3 in which the voltage value of the reference drive signal aA changes, when the voltage value of the reference drive signal aA before the change is smaller than the threshold dvth and the voltage value of the reference drive signal aA after the change is larger than the threshold dvth, or when the voltage value of the reference drive signal aA before the change is larger than the threshold dvth and the voltage value of the reference drive signal aA after the change is smaller than the threshold dvth, that is, when the voltage value of the reference drive signal aA changes across the threshold dvth, the level switching signal output circuit 710 outputs a level switching signal LS whose logic level changes based on the reference drive signal aA and the feedback signal VFB1. At this time, the level shift circuit 750 outputs a second amplified modulated signal AMS2 in which the reference potential of the first amplified modulated signal AMS1, whose duty ratio changes in accordance with changes in the reference drive signal aA, changes between ground potential and voltage vd2 based on the reference drive signal aA and the feedback signal VFB1. Then, the second amplified modulation signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, and the drive circuit 50 outputs a drive signal COM whose voltage value changes across the voltage vth in accordance with changes in the voltage value of the base drive signal aA.

[0133] If the voltage value of the basic drive signal aA changes across the threshold value dvth, and the level switching signal output circuit 710 changes the logic level of the level switching signal LS that it outputs based only on the result of comparing the value of the basic drive signal aA with the threshold value dvth, the reference potential of the second amplified modulation signal AMS2 that the level shift circuit 750 outputs will change abruptly from ground potential to voltage vd2, or from voltage vb2 to ground potential. If the response speed of the drive circuit 50 cannot keep up with this abrupt change in the reference potential, distortion will occur in the signal waveform of the drive signal COM, and the waveform accuracy of the drive signal COM may deteriorate.

[0134] In contrast to this, in the drive circuit 50 of this embodiment, the level switching signal output circuit 710 generates the level switching signal LS using the feedback signal VFB2 that feeds back the drive signal COM together with the base drive signal aA, thereby reducing the risk of the reference potential of the second amplified modulation signal AMS2 output by the level shift circuit 750 changing abruptly and reducing the risk of the waveform accuracy of the drive signal COM deteriorating.

[0135] 4.4 Configuration and operation of level switching signal output circuit 10 is a diagram showing an example of the configuration of the level switching signal output circuit 710. As shown in Fig. 10, the level switching signal output circuit 710 includes a differentiating circuit 712, a comparing circuit 714, a level switching control circuit 716, a memory circuit 718, and an output switching circuit 720.

[0136] The base drive signal aA is input to the differentiation circuit 712. The differentiation circuit 712 outputs a signal obtained by differentiating the input base drive signal aA, which is a signal corresponding to the change over time in the voltage value of the input base drive signal aA, as a reference signal REF to the comparison circuit 714. Such a differentiation circuit 712 may be composed of a capacitor element and a resistor element, or may be composed to include an operational amplifier or the like.

[0137] The comparison circuit 714 includes, for example, a comparator or other such comparator. The reference signal REF output by the differentiation circuit 712 is input to a positive input terminal of the comparison circuit 714. The feedback signal VFB1 is input to a negative input terminal of the comparison circuit 714. The comparison circuit 714 compares the voltage value of the reference signal REF with the voltage value of the feedback signal VFB1. If the voltage value of the reference signal REF is greater than the voltage value of the feedback signal VFB1, the comparison circuit 714 outputs a high When the voltage value of the reference signal REF is lower than the voltage value of the feedback signal VFB1, the output switching circuit 720 generates a pulse signal LSP that is at L level.

[0138] Here, the relationship between the reference signal REF input to the comparison circuit 714 and the feedback signal VFB1 will be described. FIG. 11 is a diagram showing an example of the configuration of a high-pass filter included in the feedback circuit 570. As shown in FIG. 11, the high-pass filter included in the feedback circuit 570 includes a resistor 572 and a capacitor 574. A signal obtained by dividing the voltage value of the drive signal COM is input to this high-pass filter. In this high-pass filter, if the capacitance of capacitor 574 is capacitance value C, the resistance of resistor 572 is resistance value R, and a current i(t) flows through capacitor 574, when voltage vfb1, which is the voltage value of the feedback signal VFB1, satisfies equation (1), a proportional relationship is established between the drive signal COM and the reference drive signal aA. Here, in equation (1), α is a constant, and v(t) is the voltage value of the reference drive signal aA.

[0139]

number

[0140] In such a high-pass filter, if the product RC of the resistance value R and the capacitance value C is made sufficiently smaller than the time tx over which the voltage v(t) changes, the feedback signal VFB1 can be regarded as a signal containing a so-called square wave in which a voltage vfb1 corresponding to the amount of change in voltage v(t) is generated when the voltage v(t), which is the voltage value of the basic drive signal aA, changes. Here, the product RC of the resistance value R and the capacitance value C being sufficiently smaller than the time tx over which the voltage v(t) changes means, for example, that when the time tx is about 1 μs, the product RC is 100×10 -9 This includes the following cases:

[0141] If the voltage value of the square wave based on the feedback signal VFB1 obtained by making the product RC of the resistance value R and the capacitance value C sufficiently smaller than the time tx over which the voltage v(t) changes is voltage vb, then this voltage vb can be expressed as in equation (2). Here, in equation (2), voltage va is the amount of change in the voltage of the basic drive signal aA at time tx.

[0142]

number

[0143] That is, the feedback signal VFB1 can be regarded as a square wave by making the product RC of the resistance value R and the capacitance value C sufficiently small relative to the time tx over which the voltage v(t) changes, and the voltage vb of this square wave is proportional to the voltage va which is the amount of change in the voltage of the reference drive signal aA at time tx. Therefore, the reference signal REF which is a signal corresponding to the change over time in the voltage value of the reference drive signal aA output by the differentiation circuit 712 and which is a signal obtained by differentiating the reference drive signal aA is proportional to the feedback signal VFB1.

[0144] The comparator circuit 714 compares the voltage value of the reference signal REF with the voltage value of the feedback signal VFB1, taking the proportionality coefficient into account, and outputs a pulse signal LSP with a logic level corresponding to the comparison result. Here, taking the proportionality coefficient between the voltage value of the reference signal REF and the voltage value of the feedback signal VFB1 into account may mean correcting at least one of the voltage value of the reference signal REF and the voltage value of the feedback signal VFB1 corresponding to the voltage value of the reference signal REF, based on the proportionality coefficient, or adjusting the voltage division ratio of the drive signal COM in the feedback circuit 570.

[0145] Returning to FIG. 10, the memory circuit 718 stores the level output from the level switching control circuit 716, which will be described later. Timing information ST that defines the timing of switching the logic levels of the bell switching control signals SIG1 and SIG2 is stored.

[0146] The level switching control circuit 716 receives input of a reference signal REF and a reference drive signal aA. The level switching control circuit 716 also acquires timing information ST from a memory circuit 718. Based on the input reference signal REF and reference drive signal aA, the level switching control circuit 716 determines whether the value of the reference drive signal aA is greater than or less than a predetermined threshold value and whether the value of the reference drive signal aA is constant or changing, thereby determining the operation mode of the drive circuit 50. The level switching control circuit 716 then generates level switching control signals SIG1 and SIG2, the logical levels of which are switched based on the determined operation mode of the drive circuit 50 and the acquired timing information ST, and outputs these to the output switching circuit 720.

[0147] The output switching circuit 720 includes an AND circuit 722 and an OR circuit 724. Level switching control signals SIG1, SIG2 and a pulse signal LSP are input to the output switching circuit 720. The output switching circuit 720 then generates a level switching signal LS according to the level switching control signals SIG1, SIG2 and the pulse signal LSP, and outputs the level switching signal LS to the level shift circuit 750.

[0148] The level switching control signal SIG1 and the pulse signal LSP are input to the AND circuit 722. When the logic level of the level switching control signal SIG1 is L level, the AND circuit 722 outputs an L level signal, and when the logic level of the level switching control signal SIG1 is H level, the AND circuit 722 outputs a signal whose logic level is switched in accordance with the pulse signal LSP.

[0149] The level switching control signal SIG2 and the output signal of the AND circuit 722 are input to the OR circuit 724. When the logic level of the level switching control signal SIG2 is L level, the OR circuit 724 outputs the output signal of the AND circuit 722, and when the logic level of the level switching control signal SIG2 is L level, the OR circuit 724 outputs an L-level signal. The signal output by the OR circuit 724 is then output from the level switching signal output circuit 710 as the level switching signal LS.

[0150] That is, when the logic level of the level switching control signal SIG2 is H level, the output switching circuit 720 outputs an H level level switching signal LS regardless of the logic level of the level switching control signal SIG1, when the logic level of the level switching control signal SIG2 is L level and the logic level of the level switching control signal SIG1 is L level, the output switching circuit 720 outputs an L level level switching signal LS, and when the logic level of the level switching control signal SIG2 is L level and the logic level of the level switching control signal SIG1 is H level, the output switching circuit 720 outputs the pulse signal LSP as the level switching signal LS.

[0151] As described above, the level switching signal output circuit 710 includes a level switching control circuit 716 that outputs the level switching control signal SIG1 and the level switching control signal SIG2 that control switching of the potential of the level switching signal LS in accordance with the basic drive signal aA, a differentiation circuit 712 that outputs the reference signal REF in accordance with the basic drive signal aA, a comparison circuit 714 that compares the reference signal REF with the feedback signal VFB1 and outputs a pulse signal LSP in accordance with the comparison result, an output switching circuit 720 that switches between outputting a constant level switching signal LS at an L level, outputting a constant level switching signal LS at an H level, or outputting a level switching signal LS that changes between an L level and an H level in accordance with the pulse signal LSP in accordance with the logical levels of the level switching control signal SIG1 and the level switching control signal SIG2, and a memory circuit 718 that stores timing information ST.

[0152] Here, the operation of the level switching signal output circuit 710 will be described. Fig. 12 is a diagram for explaining the operation of the level switching signal output circuit 710. Fig. 12 shows the level switching signal when the voltage value of the basic drive signal aA changes across the threshold value dvth in the third mode MD3. This is an example of the operation of the switching signal output circuit 710, and illustrates the operation of the level switching signal output circuit 710 when the operating mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, before and after the third mode MD3.

[0153] The comparator circuit 714 compares the voltage value of the reference signal REF with the voltage value of the feedback signal VFB1, and outputs a pulse signal LSP that goes high when the voltage value of the reference signal REF is higher than the voltage value of the feedback signal VFB1, and goes low when the voltage value of the reference signal REF is lower than the voltage value of the feedback signal VFB1.

[0154] When the operation mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2 or from the second mode MD2 to the first mode MD1 before and after the third mode MD3, the level switching control circuit 716 acquires, as timing information ST, measurement times ta1 and ta2 that define the timing for controlling the logic level of the level switching control signal SIG1 and measurement times tb1 and tb2 that define the timing for controlling the logic level of the level switching control signal SIG2 from the memory circuit 718. The level switching control circuit 716 then outputs the level switching control signals SIG1 and SIG2, whose logic levels change according to the acquired measurement times ta1, ta2, tb1, and tb2, and the input reference signal REF and basic drive signal aA.

[0155] Specifically, when the operation mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2 before and after the third mode MD3, the voltage value of the reference drive signal aA increases. The level switching control circuit 716 detects the transition of the operation mode of the drive circuit 50 from the first mode MD1 to the third mode MD3 by detecting the rise in the voltage value of the reference drive signal aA and the rising edge of the reference signal REF. The level switching control circuit 716 then begins measuring the elapsed time since the operation mode of the drive circuit 50 transitioned to the third mode MD3.

[0156] The level switching control circuit 716 also detects the voltage value of the reference drive signal aA immediately before or immediately after the operation mode of the drive circuit 50 transitions from the first mode MD1 to the third mode MD3. At this time, because the operation mode of the drive circuit 50 is in the first mode MD1 or has just transitioned from the first mode MD1 to the third mode MD3, the voltage value of the reference drive signal aA is smaller than the threshold value dvth. When the voltage value of the reference drive signal aA is smaller than the threshold value dvth, the level switching control circuit 716 sets the logic level of the level switching control signal SIG1 to an L level, and sets the logic level of the level switching control signal SIG2 to an L level. Therefore, the output switching circuit 720 outputs an L-level level switching signal LS.

[0157] Thereafter, when the elapsed time since the operation mode of the drive circuit 50 shifted to the third mode MD3, as measured by the level switching control circuit 716, reaches the measured time ta1, the level switching control circuit 716 sets the logic level of the level switching control signal SIG1 to the H level. At this time, the logic level of the level switching control signal SIG2 output by the level switching control circuit 716 continues to be the L level. Therefore, the output switching circuit 720 outputs the pulse signal LSP output by the comparison circuit 714 as the level switching signal LS.

[0158] Then, when the elapsed time measured by the level switching control circuit 716 since the operation mode of the drive circuit 50 has shifted to the third mode MD3 reaches the counted time tb1, the level switching control circuit 716 detects the voltage value of the reference drive signal aA. Here, the counted time tb1 is set to be longer than the time from when the operation mode of the drive circuit 50 has shifted to the third mode MD3 until the voltage value of the reference drive signal aA becomes greater than the threshold value dvth. Therefore, at the counted time tb1, the voltage value of the reference drive signal aA detected by the level switching control circuit 716 is greater than the threshold value dvth. The level switching control circuit 716 detects the voltage value of the reference drive signal aA when the voltage value of the reference drive signal aA becomes greater than the threshold value dvth. If it is greater, the logic level of the level switch control signal SIG1 is set to L level, and the logic level of the level switch control signal SIG2 is set to H level. Therefore, the output switch circuit 720 outputs an H level level switch signal LS.

[0159] After that, the voltage value of the reference drive signal aA reaches a predetermined voltage value, and the voltage value of the reference drive signal aA becomes constant, causing the operation mode of the drive circuit 50 to transition from the third mode MD3 to the second mode MD2.

[0160] Furthermore, when the operation mode of the drive circuit 50 transitions from the second mode MD2 to the first mode MD1 before and after the third mode MD3, the voltage value of the reference drive signal aA decreases. The level switching control circuit 716 detects a transition of the operation mode of the drive circuit 50 from the second mode MD2 to the third mode MD3 by detecting a drop in the voltage value of the reference drive signal aA and a falling edge of the reference signal REF. The level switching control circuit 716 then begins measuring the elapsed time since the operation mode of the drive circuit 50 transitioned to the third mode MD3.

[0161] The level switching control circuit 716 also detects the voltage value of the reference drive signal aA immediately before or immediately after the operation mode of the drive circuit 50 transitions from the second mode MD2 to the third mode MD3. At this time, because the operation mode of the drive circuit 50 is in the second mode MD2 or has just transitioned from the second mode MD2 to the third mode MD3, the voltage value of the reference drive signal aA is greater than the threshold value dvth. Because the voltage value of the reference drive signal aA is greater than the threshold value dvth, the level switching control circuit 716 sets the logical level of the level switching control signal SIG1 to an L level and the logical level of the level switching control signal SIG2 to an H level. Therefore, the output switching circuit 720 outputs an H-level level switching signal LS.

[0162] Thereafter, when the elapsed time since the operation mode of the drive circuit 50 shifts to the third mode MD3, as measured by the level switching control circuit 716, reaches the measured time ta2, the level switching control circuit 716 sets the logic level of the level switching control signal SIG1 to H level and sets the logic level of the level switching control signal SIG2 to L level. Therefore, the output switching circuit 720 outputs the pulse signal LSP output by the comparison circuit 714 as the level switching signal LS.

[0163] Then, when the elapsed time measured by the level switching control circuit 716 since the operating mode of the drive circuit 50 shifted to the third mode MD3 reaches the measurement time tb2, the level switching control circuit 716 detects the voltage value of the reference drive signal aA. Here, the measurement time tb2 is set to be longer than the time from when the operating mode of the drive circuit 50 shifts to the third mode MD3 until the voltage value of the reference drive signal aA becomes smaller than the threshold value dvth. Therefore, at the measurement time tb2, the voltage value of the reference drive signal aA detected by the level switching control circuit 716 is smaller than the threshold value dvth. Because the voltage value of the reference drive signal aA is smaller than the threshold value dvth, the level switching control circuit 716 sets the logic level of the level switching control signal SIG1 to the L level and the logic level of the level switching control signal SIG2 to the L level. Therefore, the output switching circuit 720 outputs the level switching signal LS at the L level.

[0164] After that, the voltage value of the reference drive signal aA reaches a predetermined voltage value, and the voltage value of the reference drive signal aA becomes constant, causing the operation mode of the drive circuit 50 to transition from the third mode MD3 to the first mode MD1.

[0165] As described above, in the third mode MD3 when the operation mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, the level switching signal output circuit 710 includes a period in which it outputs a constant level switching signal LS at an L level, a period in which it outputs the pulse signal LSP as the level switching signal LS, and a period in which it outputs a constant level switching signal LS at an H level.

[0166] Specifically, the level switching signal output circuit 710 switches the logical levels of the level switching control signal SIG1 and the level switching control signal SIG2 based on timing information ST stored in the memory circuit 718, thereby switching the logical levels of the level switching control signal SIG1 and the level switching control signal SIG2 to a third mode MD3 in which the value of the reference drive signal aA changes, and when the voltage value of the reference drive signal aA changes across a threshold value dvth, this includes a state in which it outputs a level switching signal LS that changes between L level and H level in accordance with the feedback signal VFB1, and a state in which it outputs a constant level switching signal LS at L level or H level. Immediately after transitioning from the first mode MD1 or the second mode MD2, in which the value of the reference drive signal aA does not change, to the third mode MD3 in which the value of the reference drive signal aA changes, and immediately before transitioning from the third mode MD3, in which the value of the reference drive signal aA changes, to the first mode MD1 or the second mode MD2 in which the value of the reference drive signal aA does not change, the level switching signal output circuit 710 is in a state in which it outputs a constant level switching signal LS at L level or H level.

[0167] In the level switching signal output circuit 710 configured as described above, the pulse signal LSP is a signal obtained by comparing the voltage value of the feedback signal VFB1 with the voltage value of the reference signal REF, and is generated so that the voltage value of the feedback signal VFB1 follows the voltage value of the reference signal REF. By generating the level switching signal LS using such a pulse signal LSP, even if the load capacitance of the piezoelectric element 60 or the like to which the drive signal COM to be output changes in the drive circuit 50, the influence of the change in the load capacitance is reduced, and the waveform accuracy of the drive signal COM is improved.

[0168] On the other hand, if the level switching signal output circuit 710 outputs the level switching signal LS corresponding to the pulse signal LSP during the entire period of the third mode MD3 when the operation mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2 or from the second mode MD2 to the first mode MD1, the period during which the switching operation in the amplifier circuit 550 and the switching operation in the level shift circuit 750 are performed in parallel increases, which may increase the power consumption of the drive circuit 50.

[0169] In contrast to this, in the drive circuit 50 of this embodiment, in the third mode MD3 when the operation mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, a period in which a constant level switching signal LS is output at an L level, a period in which a pulse signal LSP is output as the level switching signal LS, and a period in which a constant level switching signal LS is output at an H level are included, thereby making it possible to improve the waveform accuracy of the drive signal COM and reduce the risk of an increase in power consumption in the drive circuit 50.

[0170] In the third mode MD3, the measurement times ta1, ta2, tb1, and tb2 that define the period during which a constant level switching signal LS is output at an L level, the period during which the pulse signal LSP is output as the level switching signal LS, and the period during which a constant level switching signal LS is output at an H level may be appropriately adjusted depending on the signal waveform of the drive signal COM output by the drive circuit 50 and the number of piezoelectric elements 60 driven by the drive signal COM. The measurement times ta1, ta2, tb1, and tb2 may be adjusted by storing previously adjusted measurement times ta1, ta2, tb1, and tb2 in the memory circuit 718 and having the level switching control circuit 716 acquire optimal measurement times ta1, ta2, tb1, and tb2 depending on the operating conditions, or by adding a predetermined coefficient to the measurement times ta1, ta2, tb1, and tb2 depending on the operating conditions of the liquid ejection device 1, or by adjusting them depending on information input from outside the liquid ejection device 1.

[0171] For example, if the period during which the voltage value of the basic drive signal aA changes is long, the measurement times ta1 and ta2 may be adjusted to be longer. This reduces the period during which the switching operation in the level shift circuit 750 and the switching operation in the level shift circuit 750 are performed in parallel, further reducing the risk of an increase in power consumption in the drive circuit 50. Furthermore, for example, when the drive circuit 50 has a large number of piezoelectric elements 60 to which the drive signal COM is supplied and the load capacitance to which the drive signal COM is supplied is large, the measurement times ta1 and ta2 may be adjusted to be shorter. This increases the period during which the pulse signal LSP is output as the level switching signal LS, further improving the waveform accuracy of the drive signal COM output by the drive circuit 50. Furthermore, when the slew rate is high in the third mode MD3, the measurement times ta1 and ta2 may be adjusted to be shorter. This increases the period during which the pulse signal LSP is output as the level switching signal LS, further improving the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0172] Furthermore, it is preferable that the measurement times ta1 and ta2 be shorter than the time until the voltage value of the reference drive signal aA crosses the threshold value dvth after transitioning to the third mode MD3, and that the measurement times tb1 and tb2 be longer than the time until the voltage value of the reference drive signal aA crosses the threshold value dvth after transitioning to the third mode MD3, as shown in Fig. 12. In other words, it is preferable that the level switching signal output circuit 710 outputs the pulse signal LSP as the level switching signal LS at the timing when the voltage value of the reference drive signal aA crosses the threshold value dvth.

[0173] As described above, the drive circuit 50 operates in the first mode MD1 during a period in which the voltage value of the reference drive signal aA is smaller than the threshold value dvth, and operates in the second mode MD2 during a period in which the voltage value of the reference drive signal aA is greater than the threshold value dvth. Therefore, at the timing when the voltage value of the reference drive signal aA crosses the threshold value dvth, the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 changes sharply. At such an operating mode switching timing when the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 changes sharply, the level switching signal output circuit 710 outputs the level switching signal LS in accordance with the pulse signal LSP, thereby reducing the risk of distortion occurring in the signal waveform of the drive signal COM when the operating mode of the drive circuit 50 is switched.

[0174] As described above, in the drive circuit 50 of this embodiment, by adjusting the measurement times ta1, ta2, tb1, and tb2, it is possible to optimally control the period during which a constant L-level level switching signal LS is output, the period during which the pulse signal LSP is output as the level switching signal LS, and the period during which a constant H-level level switching signal LS is output in the third mode MD3. This improves the waveform accuracy of the drive signal COM and reduces the risk of an increase in power consumption in the drive circuit 50.

[0175] Here, the piezoelectric element 60 is an example of a capacitive load, the drive signal COM is an example of a drive signal, and the drive circuit 50 corresponds to a capacitive load drive circuit. The reference drive signal aA is an example of a reference drive signal, and considering that the reference drive signal aA is a signal obtained by converting the reference drive signal dA into an analog signal, the reference drive signal dA is also an example of a reference drive signal. Furthermore, the differentiation circuit 712 is an example of a reference signal output circuit, the comparison circuit 714 is an example of a pulse signal output circuit, and the timing information ST stored in the memory circuit 718 is an example of information stored in a memory circuit. Furthermore, a period during which the operating mode of the drive circuit 50 is at least one of the first mode MD1 and the second mode MD2 is an example of an invariable period, and a period during which the operating mode of the drive circuit 50 is the third mode MD3 is an example of a variable period. Furthermore, when the operation mode of the drive circuit 50 is the third mode MD3, the state of the level switching signal output circuit 710 when the level switching control signal SIG1 is at H level and the level switching control signal SIG2 is at L level is an example of the first state, and when the operation mode of the drive circuit 50 is the third mode MD3, the state of the level switching signal output circuit 710 when the level switching control signal SIG1 is at L level and the level switching control signal SIG2 is at H level, and At least one of the states of the level switching signal output circuit 710 when the level switching control signal SIG2 is at an L level is an example of the second state. The L level among the logical levels of the level switching signal LS is an example of a first potential, the H level among the logical levels of the level switching signal LS is an example of a second potential, the feedback signal VFB1 is an example of a feedback signal, the level switching control signal SIG1 is an example of a first switching control signal, and the level switching control signal SIG2 is an example of a second switching control signal.

[0176] 5. Effects In the liquid ejection device 1 of this embodiment configured as described above, a plurality of types of signals with different voltage values ​​are input to the drive circuit 50 of the head unit 20, including a voltage signal VD1 whose voltage value is vd1 obtained by boosting the voltage signal VDD, and a voltage signal VD2 whose voltage value is vd2 different from the voltage vd1 obtained by boosting the voltage signal VDD. The voltage conversion circuit 70 that outputs the voltage signals VD1 and VD2 includes an inductor Lsw to one end of which the voltage signal VDD is supplied, a transistor Msw whose drain terminal as one end is electrically connected to the other end of the inductor Lsw, and a diode whose anode terminal is electrically connected to the drain terminal as one end of the transistor Msw. The transistor Msw has a diode Do1, a capacitor Co1 having one end electrically connected to the cathode terminal of the diode Do1, a capacitor Cb1 having one end electrically connected to the drain terminal which is one end of the transistor Msw, a diode Db1 having an anode terminal electrically connected to the cathode terminal of the diode Do1, a diode Do2 having an anode terminal electrically connected to the cathode terminal of the diode Db1 and the other end of the capacitor Cb1, and a capacitor Co2 having one end electrically connected to the cathode terminal of the diode Do2, and outputs the voltage value of one end of the capacitor Co1 as a voltage signal VD1 and the voltage value of one end of the capacitor Co2 as a voltage signal VD2.

[0177] As a result, the voltage conversion circuit 70 does not need to have separate inductor elements used in the boost circuit that generates the voltage signal VD1 from the voltage signal VDD and inductor elements used in the boost circuit that generates the voltage signal VD2 from the voltage signal VDD. In other words, in the liquid ejection device 1 of this embodiment, the voltage conversion circuit 70 included in the head unit 20 can boost the voltage signal VDD and output voltage signals VD1 and VD2 of a plurality of different voltage values ​​using only one inductor element, inductor Lsw. This makes it possible to reduce the size of the voltage conversion circuit 70, reducing the risk of the liquid ejection device 1 and head unit 20 becoming larger.

[0178] Furthermore, in the liquid ejection device 1 of this embodiment, the voltage conversion circuit 70 of the head unit 20 can boost the voltage signal VDD using only one inductor element, the inductor Lsw, and output voltage signals VD3 to VD5 in addition to voltage signals VD1 and VD2 of a plurality of different voltage values. This makes it possible to reduce the size of the voltage conversion circuit 70, further reducing the risk of the liquid ejection device 1 and head unit 20 becoming larger.

[0179] Furthermore, in the liquid ejection device 1 of this embodiment configured as described above, the drive circuit 50 is in the third mode MD3 in which the value of the reference drive signal aA varies, and when the voltage value of the reference drive signal aA varies across the threshold value dvth, the level switching signal output circuit 710 includes a state in which it outputs a level switching signal LS that varies between L level and H level in response to the feedback signal VFB1, and a state in which it outputs a constant level switching signal LS at L level or H level. As a result, in the drive circuit 50 of this embodiment, during the period in which the level switching signal output circuit 710 generates the level switching signal LS that varies between L level and H level in response to the feedback signal VFB1, it is possible to improve the waveform accuracy of the drive signal COM output by the drive circuit 50, and to reduce the risk of an increase in power consumption in the drive circuit 50 during the period in which the level switching signal output circuit 710 outputs a constant level switching signal LS at L level or a period in which it outputs a constant level switching signal LS at H level.

[0180] That is, in the liquid ejection device 1 of this embodiment configured as described above, in the third mode MD3 when the operating mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, the level switching signal output circuit 710 includes a period in which it outputs a constant level switching signal LS at an L level, a period in which it outputs the pulse signal LSP as the level switching signal LS, and a period in which it outputs a constant level switching signal LS at an H level, thereby improving the waveform accuracy of the drive signal COM and reducing the risk of an increase in power consumption in the drive circuit 50.

[0181] 6. Variations 6.1 Variation 1 In the liquid ejection device 1 of this embodiment described above, the voltage conversion circuit 70 outputs a signal of the voltage value at one end of the capacitor Co1 as a voltage signal VD1, a signal of the voltage value at one end of the capacitor Co2 as a voltage signal VD2, a signal of the voltage value at one end of the capacitor Co3 as a voltage signal VD3, a signal of the voltage value at one end of the capacitor Co4 as a voltage signal VD4, and a signal of the voltage value at one end of the capacitor Co5 as a voltage signal VD5. However, in the liquid ejection device 1 of Modification 1, as shown in FIG. The voltage conversion circuit 70 further includes a diode Dk1 and a capacitor Ck1 provided in the propagation path along which the voltage signal VD1 propagates, a diode Dk2 and a capacitor Ck2 provided in the propagation path along which the voltage signal VD2 propagates, a diode Dk3 and a capacitor Ck3 provided in the propagation path along which the voltage signal VD3 propagates, a diode Dk4 and a capacitor Ck4 provided in the propagation path along which the voltage signal VD4 propagates, and a diode Dk5 and a capacitor Ck5 provided in the propagation path along which the voltage signal VD5 propagates.

[0182] FIG. 13 is a diagram showing an example of the configuration of a voltage conversion circuit 70 of Modification 1. As shown in FIG. 13, the anode terminal of a diode Dk1 is electrically connected to the cathode terminal of a diode Do1 and one end of a capacitor Co1. The cathode terminal of the diode Dk1 is electrically connected to one end of a capacitor Ck1. A ground potential is supplied to the other end of the capacitor Ck1. A voltage signal VD1, which is a signal of the voltage value of one end of the capacitor Co1, is output from the voltage conversion circuit 70 via the diode Dk1.

[0183] The anode terminal of diode Dk2 is electrically connected to the cathode terminal of diode Do2 and one end of capacitor Co2. The cathode terminal of diode Dk2 is electrically connected to one end of capacitor Ck2. The other end of capacitor Ck2 is supplied with ground potential. A voltage signal VD2, which is a signal representing the voltage value of one end of capacitor Co2, is output from voltage conversion circuit 70 via diode Dk2.

[0184] The anode terminal of diode Dk3 is electrically connected to the cathode terminal of diode Do3 and one end of capacitor Co3. The cathode terminal of diode Dk3 is electrically connected to one end of capacitor Ck3. The other end of capacitor Ck3 is supplied with ground potential. A voltage signal VD3, which is a signal representing the voltage value of one end of capacitor Co3, is output from voltage conversion circuit 70 via diode Dk3.

[0185] The anode terminal of diode Dk4 is electrically connected to the cathode terminal of diode Do4 and one end of capacitor Co4. The cathode terminal of diode Dk4 is electrically connected to one end of capacitor Ck4. The other end of capacitor Ck4 is supplied with ground potential. A voltage signal VD4, which is a signal representing the voltage value of one end of capacitor Co4, is output from voltage conversion circuit 70 via diode Dk4.

[0186] The anode terminal of the diode Dk5 is electrically connected to the cathode terminal of the diode Do5 and one end of the capacitor Co5. The capacitor Ck5 is electrically connected to one end of the capacitor Ck5. The other end of the capacitor Ck5 is supplied with ground potential. A voltage signal VD5, which is a signal representing the voltage value at one end of the capacitor Ck5, is output from the voltage conversion circuit 70 via a diode Dk5.

[0187] That is, the voltage conversion circuit 70 of variant 1 has a diode Dk1 having an anode terminal electrically connected to one end of capacitor Co1, a capacitor Ck1 having one end electrically connected to the cathode terminal of diode Dk1, a diode Dk2 having an anode terminal electrically connected to one end of capacitor Co2, a capacitor Ck2 having one end electrically connected to the cathode terminal of diode Dk2, a diode Dk3 having an anode terminal electrically connected to one end of capacitor Co3, a capacitor Ck3 having one end electrically connected to the cathode terminal of diode Dk3, a diode Dk4 having an anode terminal electrically connected to one end of capacitor Co4, a capacitor Ck4 having one end electrically connected to the cathode terminal of diode Dk4, a diode Dk5 having an anode terminal electrically connected to one end of capacitor Co5, and a capacitor Ck5 having one end electrically connected to the cathode terminal of diode Dk5.

[0188] In the voltage conversion circuit 70 of the first modification configured as described above, even if the power consumption of the load supplied with the voltage signal VD1 fluctuates, the diode Dk1 reduces the risk of the voltage value at one end of the capacitor Co1 fluctuating. Similarly, even if the power consumption of the load supplied with the voltage signal VD2 fluctuates, the diode Dk2 reduces the risk of the voltage value at one end of the capacitor Co2 fluctuating. Even if the power consumption of the load supplied with the voltage signal VD3 fluctuates, the diode Dk3 reduces the risk of the voltage value at one end of the capacitor Co3 fluctuating. Even if the power consumption of the load supplied with the voltage signal VD4 fluctuates, the diode Dk4 reduces the risk of the voltage value at one end of the capacitor Co4 fluctuating. Even if the power consumption of the load supplied with the voltage signal VD5 fluctuates, the diode Dk1 reduces the risk of the voltage value at one end of the capacitor Co5 fluctuating.

[0189] As a result, the accuracy of the voltage values ​​of the voltage signals VD2 to VD5 generated based on the voltage signal VD1 is also improved in the voltage conversion circuit 70. That is, the voltage conversion circuit 70 of the first modification can improve the voltage accuracy of each of the voltage signals VD1 to VD5 to be output.

[0190] Furthermore, at this time, it is preferable that the capacitance of capacitor Ck1 is larger than the capacitance of capacitor Co1, it is preferable that the capacitance of capacitor Ck2 is larger than the capacitance of capacitor Co2, it is preferable that the capacitance of capacitor Ck3 is larger than the capacitance of capacitor Co3, it is preferable that the capacitance of capacitor Ck4 is larger than the capacitance of capacitor Co4, and it is preferable that the capacitance of capacitor Ck5 is larger than the capacitance of capacitor Co5.

[0191] As a result, even if the power consumption of the loads to which the voltage signals VD1-VD5 are supplied fluctuates significantly, the fluctuations in power consumption are more efficiently absorbed by the charges stored in the capacitors Ck1-Ck5. This further reduces the risk of fluctuations in the voltage value at one end of each of the capacitors Co1-Co5, and further improves the voltage accuracy of each of the voltage signals VD1-VD5 output by the voltage conversion circuit 70.

[0192] The diodes Dk1 to Dk5 and the capacitors Ck1 to Ck5 may be used only when the fluctuations in power consumption of the loads to which the corresponding voltage signals VD1 to VD5 are supplied are large, in which case any of the diodes Dk1 to Dk5 and the capacitors Ck1 to Ck5 may not be provided.

[0193] 6.2 Variation 2 Furthermore, in the liquid ejection device 1 of this embodiment described above, the voltage conversion circuit 70 has been described as having a voltage signal VD3 supplied to the drain terminal of transistor M1 of amplifier circuit 550 and a voltage signal VD2 supplied to boost circuit BS of level shift circuit 750, but the signal supplied to the drain terminal of transistor M1 of amplifier circuit 550 may be selectable from voltage signals VD1 to VD5, and the signal supplied to boost circuit BS of level shift circuit 750 may be selectable from voltage signals VD1 to VD5. Here, in Modification 2 of the liquid ejection device 1, the signal supplied to the drain terminal of transistor M1 of amplifier circuit 550 is referred to as voltage signal VMS, and the signal supplied to boost circuit BS of level shift circuit 750 is referred to as voltage signal VLS.

[0194] Fig. 14 is a diagram showing an example of the configuration of a voltage conversion circuit 70 of Modification 2. As shown in Fig. 14, the voltage conversion circuit 70 of the liquid ejection device 1 of Modification 2 includes multiplexers MUX1 and MUX2.

[0195] The voltage signals VD1 to VD5 are input to the input terminal of the multiplexer MUX1. A selection control signal Sel1 is input to the control terminal of the multiplexer MUX1. The multiplexer MUX1 selects one of the voltage signals VD1 to VD5 based on the selection control signal Sel1 input to the control terminal, and outputs the selected voltage signal as a voltage signal VMS. This voltage signal VMS is supplied to the drain terminal of the transistor M1 included in the amplifier circuit 550 of the drive circuit 50.

[0196] The voltage signals VD1 to VD5 are input to the input terminal of the multiplexer MUX2. A selection control signal Sel2 is input to the control terminal of the multiplexer MUX2. The multiplexer MUX2 selects one of the voltage signals VD1 to VD5 based on the selection control signal Sel2 input to the control terminal, and outputs the selected voltage signal as a voltage signal VLS. This voltage signal VLS is supplied to a boost circuit BS included in the level shift circuit 750 of the drive circuit 50.

[0197] That is, the voltage conversion circuit 70 has a multiplexer MUX1 that selects whether to supply the voltage signal VD1 to the transistor M1 of the amplifier circuit 550 of the drive circuit 50 and whether to supply the voltage signal VD2 to the transistor M1 of the amplifier circuit 550 of the drive circuit 50, and a multiplexer MUX2 that selects whether to supply the voltage signal VD1 to the boost circuit BS of the level shift circuit 750 of the drive circuit 50 and whether to supply the voltage signal VD2 to the boost circuit BS of the level shift circuit 750 of the drive circuit 50.

[0198] Here, the selection control signal Sel1 input to the control terminal of the multiplexer MUX1 and the selection control signal Sel2 input to the control terminal of the multiplexer MUX2 may be output by, for example, the control circuit 100. The control circuit 100 may output the selection control signals Sel1 and Sel2 according to the voltage amplitude of the drive signal COM. The control circuit 100 may also obtain the ambient temperature of the liquid ejection head 21 and output the selection control signals Sel1 and Sel2 according to the obtained temperature. The control circuit 100 may also output the selection control signals Sel1 and Sel2 according to the number of piezoelectric elements 60 driven by the drive signal COM. In this way, the voltage value of the voltage signal VMS supplied to the transistor M1 of the amplifier circuit 550 and the voltage value of the voltage signal VLS supplied to the boost circuit BS of the level shift circuit 750 can be arbitrarily selected from among the voltages vd1 to vd5 according to the operating conditions of the liquid ejection device 1, such as the temperature of the liquid ejection head 21 and the number of piezoelectric elements 60 being driven.

[0199] As a result, in the liquid ejection device 1 of the second modification, the first amplified modulated signal output from the amplifier circuit 550 is It is possible to control the voltage value of the first amplified modulation signal AMS1 and the amount of shift in the reference potential of the first amplified modulation signal AMS1 that is level-shifted in the level shift circuit 750 according to the operating status of the liquid ejection device 1, making it possible to output a drive signal COM with an optimal signal waveform according to the operating status of the liquid ejection device 1 and to amplify the signal at an appropriate voltage value.

[0200] As described above, in the liquid ejection device 1 of Modification 2, it is possible to easily adjust the signal waveform of the drive signal COM output by the drive circuit 50 in accordance with the operating conditions of the liquid ejection device 1. This improves the ejection accuracy of ink ejected from the ejection unit 600. Furthermore, in the liquid ejection device 1 of Modification 2, the voltage value of the voltage signal VMS supplied to the amplifier circuit 550 and the voltage value of the voltage signal VLS supplied to the level shift circuit 750 can be changed in accordance with the operating conditions of the liquid ejection device 1. Therefore, when outputting a drive signal COM with a small voltage amplitude, it is possible to reduce switching losses in the amplifier circuit 550 and the level shift circuit 750 by selecting a low voltage vd. This also makes it possible to further reduce the power consumption of the drive circuit 50.

[0201] 6.3 Variation 3 In the liquid ejection device 1 of the present embodiment described above, the drive circuit 50 includes a modulation circuit 520 that modulates the basic drive signal aA according to the basic drive signal dA that is the basis of the drive signal COM and outputs a modulated signal MS, a gate drive circuit 530 that outputs gate signals HGD1, LGD1 according to the modulated signal MS, an amplifier circuit 550 that outputs a first amplified modulated signal AMS1 according to the gate signals HGD1, LGD1 and that amplifies the modulated signal MS, a level switching signal output circuit 710 that outputs a level switching signal LS whose voltage value changes between an L level and an H level, and a level switching signal output circuit 720 that outputs a level switching signal L The drive circuit 50 has been described as including a level shift circuit 750 that outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 when S is at an L level, and outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 when the level switching signal LS is at an H level, a demodulation circuit 560 that demodulates the second amplified modulated signal AMS2 and outputs a drive signal COM, and a feedback circuit 570 that outputs a feedback signal VFB1 corresponding to the drive signal COM, but the drive circuit 50 is not limited to the configuration described above and may be a so-called class D amplifier circuit that modulates the base drive signal aA and then amplifies it.

[0202] Fig. 15 is a diagram showing the configuration of a drive circuit 50 included in the liquid ejection device 1 of Modification 3. As shown in Fig. 15, the drive circuit 50 of Modification 3 includes an integrated circuit 800, an amplifier circuit 850, a demodulation circuit 860, feedback circuits 870 and 872, and other electronic components.

[0203] The integrated circuit 800 has a plurality of terminals including a terminal In, a terminal Bst, a terminal Hdr, a terminal Sw, a terminal Gvd, a terminal Ldr, a terminal Gnd, a terminal Vf, and a terminal If. The integrated circuit 800 is electrically connected to an external substrate (not shown) via the plurality of terminals. The integrated circuit 800 also includes a DAC (Digital to Analog Converter) 811, a modulation circuit 810, and a gate drive circuit 820.

[0204] A digital reference drive signal dA that defines the signal waveform of the drive signal COM is input to the DAC 811. The DAC 811 converts the input reference drive signal dA into a reference drive signal aA, which is an analog signal, and outputs it to the modulation circuit 810. The amplified reference drive signal aA output by the DAC 811 corresponds to the drive signal COM.

[0205] The modulation circuit 810 generates a modulation signal Mss by modulating the master drive signal aA, and outputs the modulation signal Mss to the gate drive circuit 820. The modulation circuit 810 includes adders 812 and 813, a comparator 814, an inverter 815, an integral attenuator 816, and an attenuator 817.

[0206] The integral attenuator 816 attenuates and integrates the voltage value of the drive signal COM input via terminal Vf, and outputs the result to the negative input terminal of the adder 812. The basic drive signal aA is input to the positive input terminal of the adder 812. The adder 812 then outputs a signal obtained by subtracting and integrating the voltage value of the signal input to the negative input terminal from the voltage value of the signal input to the positive input terminal to the positive input terminal of the adder 813.

[0207] Attenuator 817 attenuates the high-frequency components of drive signal COM input via terminal If and outputs the resulting signal to the negative input terminal of adder 813. The signal output from adder 812 is input to the positive input terminal of adder 813. Adder 813 generates a signal by subtracting the voltage value of the signal input to its negative input terminal from the voltage value of the signal input to its positive input terminal, and outputs the signal to comparator 814.

[0208] The comparator 814 outputs a modulated signal Mss that is pulse-modulated from the signal input from the adder 813. Specifically, the comparator 814 generates and outputs a modulated signal Mss that goes to H level when the voltage value of the signal input from the adder 813 is equal to or greater than a predetermined threshold voltage if the voltage value of the signal input from the adder 813 is rising, and goes to L level when the voltage value of the signal input from the adder 813 is falling below the predetermined threshold voltage if the voltage value of the signal input from the adder 813 is falling.

[0209] The modulated signal Mss output by the comparator 814 is input to a gate driver 821 included in the gate drive circuit 820, and is also input to a gate driver 822 included in the gate drive circuit 820 via an inverter 815. That is, signals having an exclusive relationship in terms of logical levels are input to the gate drivers 821 and 822. Here, the exclusive relationship in terms of logical levels means that the logical levels of the signals input to the gate driver 821 and the gate driver 822 are not H level at the same time.

[0210] The gate drive circuit 820 includes a gate driver 821 and a gate driver 822. The gate driver 821 generates an amplification control signal Hgd by level-shifting the modulation signal Mss input from the comparator 814, and outputs it from a terminal Hdr.

[0211] Specifically, of the power supply voltages of the gate driver 821, the high-potential power supply voltage is supplied via terminal Bst, and the low-potential power supply voltage is supplied via terminal Sw. Terminal Bst is connected to one end of capacitor C85 and the cathode of a backflow prevention diode D81. Terminal Sw is connected to the other end of capacitor C85. The anode of diode D81 is connected to terminal Gvd. Terminal Gvd is supplied with a voltage signal VD1. That is, the voltage signal VD1 is supplied to the anode of diode D81. Therefore, the potential difference between terminal Bst and terminal Sw is approximately equal to voltage vd1, which is the voltage value of the voltage signal VD1. As a result, the gate driver 821 generates an amplification control signal Hgd with a voltage value higher than that of terminal Sw by voltage vd1 in accordance with the input modulation signal Mss, and outputs it from terminal Hdr.

[0212] The gate driver 822 operates at a lower potential side than the gate driver 821. The gate driver 822 generates an amplification control signal Lgd by level-shifting a signal obtained by inverting the logical level of the modulation signal Mss output from the comparator 814 using an inverter 815, and outputs the signal from the terminal Ldr.

[0213] Specifically, of the power supply voltages of the gate driver 822, a voltage signal VD1 is supplied as a high-potential power supply voltage, and a ground potential is supplied via a terminal Gnd as a low-potential power supply voltage. Then, the gate driver 822 outputs an amplification control signal Lgd, which is a voltage value that is higher than the terminal Gnd by a voltage vd1, to the terminal Gnd in accordance with a signal obtained by inverting the logical level of the input modulation signal Mss. Output from Ldr.

[0214] The amplifier circuit 850 includes a transistor M81 and a transistor M82.

[0215] A voltage signal VD5 is supplied to the drain terminal of the transistor M81 as the amplification power supply voltage for the amplifier circuit 850. The gate terminal of the transistor M81 is electrically connected to one end of a resistor R81, and the other end of the resistor R81 is electrically connected to the terminal Hdr of the integrated circuit 800. That is, an amplification control signal Hgd is input to the gate terminal of the transistor M81. The source terminal of the transistor M81 is electrically connected to the terminal Sw of the integrated circuit 800.

[0216] The drain terminal of the transistor M82 is electrically connected to the terminal Sw of the integrated circuit 800. That is, the drain terminal of the transistor M82 and the source terminal of the transistor M81 are electrically connected to each other. The gate terminal of the transistor M82 is electrically connected to one end of the resistor R82, and the other end of the resistor R82 is electrically connected to the terminal Ldr of the integrated circuit 800. That is, an amplification control signal Lgd is input to the gate terminal of the transistor M82. Furthermore, the ground potential is supplied to the source terminal of the transistor M82.

[0217] When the drain terminal and source terminal of transistor M81 are controlled to be non-conductive and the drain terminal and source terminal of transistor M82 are controlled to be conductive, the potential of terminal Sw becomes ground potential. Therefore, voltage vd1 is supplied to terminal Bst. On the other hand, when the drain terminal and source terminal of transistor M81 are controlled to be conductive and the drain terminal and source terminal of transistor M82 are controlled to be non-conductive, the potential of terminal Sw becomes voltage vd5. Therefore, a signal with a voltage value equal to the sum of voltage vd5 and voltage vd1 is supplied to terminal Bst. That is, the gate driver 821 that drives the transistor M81 uses the capacitor C85 as a floating power supply, and generates an amplification control signal Hgd whose L level is voltage vd1 and whose H level is the sum of voltage vd5 and voltage vd1 by changing the potential of the terminal Sw to ground potential or voltage vd5 depending on the operation of the transistors M81 and M82, and outputs this to the gate of the transistor M81.

[0218] On the other hand, the gate driver 822 that drives the transistor M82 generates an amplification control signal Lgd whose L level is the ground potential and whose H level is the voltage vd1, regardless of the operation of the transistors M81 and M82, and outputs it to the gate terminal of the transistor M82.

[0219] The amplifier circuit 850 configured as described above generates an amplified modulated signal AMS3 by amplifying the modulated signal Mss based on the voltage vd5 at the connection point between the source terminal of the transistor M81 and the drain terminal of the transistor M82. The amplifier circuit 850 then outputs the generated amplified modulated signal AMS3 to the demodulation circuit 860.

[0220] The demodulation circuit 860 demodulates the amplified modulated signal AMS3 output by the amplifier circuit 850 to generate a drive signal COM, which is output from the drive circuit 50. The demodulation circuit 860 includes an inductor L81 and a capacitor C81. One end of the inductor L81 is connected to one end of the capacitor C81. The amplified modulated signal AMS3 is input to the other end of the inductor L81. The ground potential is supplied to the other end of the capacitor C81. That is, in the demodulation circuit 860, the inductor L81 and the capacitor C81 form a low pass filter. The demodulation circuit 860 demodulates the amplified modulated signal AMS3 by smoothing it using the low pass filter, and outputs the demodulated signal as Output as drive signal COM.

[0221] The feedback circuit 870 includes resistors R83 and R84. The drive signal COM is supplied to one end of the resistor R83, and the other end is connected to the terminal Vf and one end of the resistor R84. A voltage signal VD5 is supplied to the other end of the resistor R84. As a result, the drive signal COM that has passed through the feedback circuit 870 is fed back to the terminal Vf in a state where it has been pulled up by the voltage vd5.

[0222] The feedback circuit 872 includes capacitors C82, C83, and C84 and resistors R85 and R86. The drive signal COM is input to one end of the capacitor C82, and the other end is connected to one end of the resistor R85 and one end of the resistor R86. A ground potential is supplied to the other end of the resistor R85. This allows the capacitor C82 and the resistor R85 to function as a high-pass filter. The other end of the resistor R86 is connected to one end of the capacitor C84 and one end of the capacitor C83. A ground potential is supplied to the other end of the capacitor C83. This allows the resistor R86 and the capacitor C83 to function as a low-pass filter. In other words, the feedback circuit 872 includes a high-pass filter and a low-pass filter, and functions as a band-pass filter that passes signals in a predetermined frequency range included in the drive signal COM.

[0223] The other end of capacitor C84 is connected to terminal If of integrated circuit 800. As a result, a signal in which the DC component has been cut out from the high-frequency components of drive signal COM that has passed through feedback circuit 872, which functions as a band-pass filter, is fed back to terminal If.

[0224] The drive signal COM is a signal obtained by smoothing the amplified modulation signal AMS3 based on the basic drive signal dA using the demodulation circuit 860. The drive signal COM is also integrated and subtracted via terminal Vf before being fed back to the adder 812. This causes the drive circuit 50 to self-oscillate at a frequency determined by the feedback delay and feedback transfer function. However, the feedback path via terminal Vf has a large delay. Therefore, feedback via terminal Vf alone may not be able to raise the frequency of self-oscillation sufficiently to ensure the accuracy of the drive signal COM. Therefore, by providing a path that feeds back the high-frequency components of the drive signal COM via terminal If, in addition to the path via terminal Vf, the delay in the entire circuit is reduced. This allows the frequency of the modulation signal Mss to be raised sufficiently to ensure the accuracy of the drive signal COM, compared to when the path via terminal If is not provided.

[0225] As described above, in the third modification of the liquid ejection device 1, the drive circuit 50 has an amplifier circuit 850 including a transistor pair consisting of transistors M81 and M82, and a gate drive circuit 820 that drives the transistor pair consisting of transistors M81 and M82. A voltage signal VD1 is supplied to the gate drive circuit 820 that drives the transistor pair consisting of transistors M81 and M82 of the drive circuit 50, and a voltage signal VD5 is supplied to the amplifier circuit 850 including the transistor pair consisting of transistors M81 and M82 together with the selection control circuit 200. That is, of the voltage signals VD1 to VD5 output by the voltage conversion circuit 70, the drive circuit 50 of the third modification of the liquid ejection device 1 is supplied with the voltage signals VD1 and VD5.

[0226] Even when the liquid ejection device 1 has the drive circuit 50 of variant example 3 configured as described above, the voltage conversion circuit 70 can boost the voltage signal VDD and output voltage signals VD1, VD5 of multiple different voltage values ​​using only one inductor element, the inductor Lsw, which makes it possible to miniaturize the voltage conversion circuit 70 and reduces the risk of the liquid ejection device 1 and head unit 20 becoming larger.

[0227] Although the embodiments have been described above, the present invention is not limited to these embodiments. The present invention can be embodied in various forms without departing from the spirit and scope of the present invention. For example, the above-described embodiments can be combined as appropriate.

[0228] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0229] The following can be derived from the above-described embodiment.

[0230] One aspect of the capacitive load drive circuit is A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal output circuit outputs the level switching signal that changes between the first potential and the second potential in response to the feedback signal during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal output circuit outputs the level switching signal that is constant at the first potential or the second potential.

[0231] In this capacitive load drive circuit, the level shift circuit outputs a level switching signal for switching between outputting the first amplified modulated signal as the second amplified modulated signal and outputting a signal obtained by level-shifting the reference potential of the first amplified modulated signal as the second amplified modulated signal, and the level switching signal output circuit includes a first state in which it outputs a level switching signal that changes between a first potential and a second potential in response to a feedback signal during a change period in which the value of the base drive signal changes, thereby improving the ability of the drive signal to follow changes in the value of the base drive signal and increasing the waveform accuracy of the drive signal, and includes a second state in which it outputs a level switching signal that is constant at the first potential or the second potential, thereby reducing switching loss in the level shift circuit and enabling the power consumption of the drive circuit to be reduced. In other words, this capacitive load drive circuit can achieve both improved waveform accuracy of the drive signal during a change period in which the value of the base drive signal changes and reduced power consumption.

[0232] In one aspect of the capacitive load drive circuit, Immediately after a transition from a constant period in which the value of the base drive signal does not change to the changing period, the state of the level switching signal output circuit may be in the second state.

[0233] In one aspect of the capacitive load drive circuit, The state of the level switching signal output circuit may be the second state immediately before the transition from the changing period to the unchanged period in which the value of the base drive signal does not change.

[0234] In one aspect of the capacitive load drive circuit, The level switching signal output circuit includes: a level switching control circuit that outputs a first switching control signal and a second switching control signal that control switching of the potential of the level switching signal in response to the basic drive signal; a reference signal output circuit that outputs a reference signal corresponding to the base drive signal; a pulse signal output circuit that compares the reference signal with the feedback signal and outputs a pulse signal according to the comparison result; an output switching circuit that switches, according to a logic level of the first switching control signal and a logic level of the second switching control signal, whether to output the level switching signal that is constant at the first potential, output the level switching signal that is constant at the second potential, or output the level switching signal that changes between the first potential and the second potential according to the pulse signal; may have

[0235] In one aspect of the capacitive load drive circuit, a memory circuit; The level switching signal output circuit may switch the logic level of the first switching control signal and the logic level of the second switching control signal based on the information stored in the memory circuit.

[0236] In this capacitive load drive circuit, during the change period when the value of the reference drive signal changes, it is possible to easily set the period during which the level switching signal output circuit is in a first state where it outputs a level switching signal that changes between a first potential and a second potential in response to a feedback signal, and the period during which it is in a second state where it outputs a level switching signal that is constant at the first potential or the second potential. This makes it possible to optimally control the state of the level switching signal output circuit in response to the operating state of the capacitive load drive circuit and the waveform of the drive signal it outputs, and it is possible to achieve both improved waveform accuracy of the drive signal during the change period when the value of the reference drive signal changes and reduced power consumption in a more optimal state.

[0237] One aspect of the liquid ejection device is a transport unit that transports the medium; a liquid ejection head that ejects liquid onto the medium in response to driving of a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal output circuit outputs the level switching signal that changes between the first potential and the second potential in response to the feedback signal during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal output circuit outputs the level switching signal that is constant at the first potential or the second potential.

[0238] In this liquid ejection device, the level shift circuit outputs the first amplified modulated signal as the second amplified modulated signal, or outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal as the second amplified modulated signal. The level switching signal output circuit outputs a level switching signal for switching whether to output it as a signal, and includes a first state in which it outputs a level switching signal that changes between a first potential and a second potential in accordance with a feedback signal during a change period in which the value of the reference drive signal changes, thereby improving the ability of the drive signal to follow changes in the value of the reference drive signal and increasing the waveform accuracy of the drive signal, and includes a second state in which it outputs a level switching signal that is constant at the first potential or the second potential, thereby reducing switching loss in the level shift circuit and enabling the power consumption of the drive circuit to be reduced. In other words, this capacitive load drive circuit can achieve both improved waveform accuracy of the drive signal during a change period in which the value of the reference drive signal changes and reduced power consumption.

[0239] In one aspect of the liquid ejection device, Immediately after a transition from a constant period in which the value of the base drive signal does not change to the changing period, the state of the level switching signal output circuit may be in the second state.

[0240] In one aspect of the liquid ejection device, The state of the level switching signal output circuit may be the second state immediately before the transition from the changing period to the unchanged period in which the value of the base drive signal does not change.

[0241] In one aspect of the liquid ejection device, The level switching signal output circuit comprises: a level switching control circuit that outputs a first switching control signal and a second switching control signal that control switching of the potential of the level switching signal in response to the basic drive signal; a reference signal output circuit that outputs a reference signal corresponding to the base drive signal; a pulse signal output circuit that compares the reference signal with the feedback signal and outputs a pulse signal according to the comparison result; an output switching circuit that switches, according to a logic level of the first switching control signal and a logic level of the second switching control signal, whether to output the level switching signal that is constant at the first potential, output the level switching signal that is constant at the second potential, or output the level switching signal that changes between the first potential and the second potential according to the pulse signal; may have

[0242] In one aspect of the liquid ejection device, a memory circuit; The level switching signal output circuit may switch the logic level of the first switching control signal and the logic level of the second switching control signal based on the information stored in the memory circuit.

[0243] In this liquid ejection device, during the change period when the value of the base drive signal changes, it is possible to easily set the period during which the level switching signal output circuit is in a first state, outputting a level switching signal that changes between a first potential and a second potential in response to a feedback signal, and the period during which the level switching signal output circuit is in a second state, outputting a level switching signal that is constant at the first potential or the second potential. This makes it possible to optimally control the state of the level switching signal output circuit in response to the operating state of the capacitive load drive circuit and the waveform of the drive signal it outputs, and it is possible to achieve both improved waveform accuracy of the drive signal during the change period when the value of the base drive signal changes and reduced power consumption in a more optimal state.

[0244] One aspect of the head unit is a liquid ejection head that ejects liquid onto a medium in response to driving of a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal output circuit outputs the level switching signal that changes between the first potential and the second potential in response to the feedback signal during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal output circuit outputs the level switching signal that is constant at the first potential or the second potential.

[0245] In this head unit, the level shift circuit outputs a level switching signal for switching between outputting the first amplified modulated signal as the second amplified modulated signal and outputting a signal obtained by level-shifting the reference potential of the first amplified modulated signal as the second amplified modulated signal, and the level switching signal output circuit includes a first state in which it outputs a level switching signal that changes between a first potential and a second potential in accordance with the feedback signal during a change period in which the value of the base drive signal changes, thereby improving the ability of the drive signal to follow changes in the value of the base drive signal and increasing the waveform accuracy of the drive signal, and includes a second state in which it outputs a constant level switching signal at the first potential or the second potential, thereby reducing switching loss in the level shift circuit and enabling the power consumption of the drive circuit to be reduced. In other words, this capacitive load drive circuit can achieve both improved waveform accuracy of the drive signal during a change period in which the value of the base drive signal changes and reduced power consumption.

[0246] In one aspect of the head unit, Immediately after a transition from a constant period in which the value of the base drive signal does not change to the changing period, the state of the level switching signal output circuit may be in the second state.

[0247] In one aspect of the head unit, The state of the level switching signal output circuit may be the second state immediately before the transition from the changing period to the unchanged period in which the value of the base drive signal does not change.

[0248] In one aspect of the head unit, The level switching signal output circuit includes: a level switching control circuit that outputs a first switching control signal and a second switching control signal that control switching of the potential of the level switching signal in response to the basic drive signal; a reference signal output circuit that outputs a reference signal corresponding to the base drive signal; a pulse signal output circuit that compares the reference signal with the feedback signal and outputs a pulse signal according to the comparison result; an output switching circuit that switches, according to a logic level of the first switching control signal and a logic level of the second switching control signal, whether to output the level switching signal that is constant at the first potential, output the level switching signal that is constant at the second potential, or output the level switching signal that changes between the first potential and the second potential according to the pulse signal; may have

[0249] In one aspect of the head unit, a memory circuit; The level switching signal output circuit outputs the first level switching signal based on the information stored in the memory circuit. The logic level of the switching control signal and the logic level of the second switching control signal may be switched.

[0250] In this head unit, the level shift circuit outputs a level switching signal for switching between outputting the first amplified modulated signal as the second amplified modulated signal and outputting a signal obtained by level-shifting the reference potential of the first amplified modulated signal as the second amplified modulated signal, and the level switching signal output circuit includes a first state in which it outputs a level switching signal that changes between a first potential and a second potential in accordance with the feedback signal during a change period in which the value of the base drive signal changes, thereby improving the ability of the drive signal to follow changes in the value of the base drive signal and increasing the waveform accuracy of the drive signal, and includes a second state in which it outputs a constant level switching signal at the first potential or the second potential, thereby reducing switching loss in the level shift circuit and enabling the power consumption of the drive circuit to be reduced. In other words, this capacitive load drive circuit can achieve both improved waveform accuracy of the drive signal during a change period in which the value of the base drive signal changes and reduced power consumption. [Explanation of symbols]

[0251] 1...liquid ejection device, 2...moving body, 3...moving unit, 4...transport unit, 10...control unit, 11...voltage supply circuit, 13...capacitor, 20...head unit, 21...liquid ejection head, 24...carriage, 31...carriage motor, 32...carriage guide shaft, 33...timing belt, 40...platen, 41...transport motor, 42...transport roller, 50...drive circuit, 60...piezoelectric element, 70...voltage conversion circuit, 75...boost control circuit, 100...control circuit, 190...cable, 200...selection control circuit, 210...selection control section, 2 30...Selection unit, 510...D / A conversion circuit, 511...Adder, 520...Modulation circuit, 521...Inverter, 530...Gate drive circuit, 531, 532...Gate driver, 550...Amplification circuit, 560...Demodulation circuit, 561...Inductor, 562...Capacitor, 570...Feedback circuit, 572...Resistor, 574...Capacitor, 600...Ejection unit, 601...Piezoelectric element, 611, 612...Electrode, 621...Vibration plate, 631...Cavity, 632...Nozzle plate, 641...Reservoir, 651...Nozzle, 710...Level switching signal output circuit, 712...differential circuit, 714...comparison circuit, 716...level switching control circuit, 718...memory circuit, 720...output switching circuit, 721...inverter, 722...AND circuit, 724...OR circuit, 730...gate drive circuit, 731, 732...gate driver, 750...level shift circuit, 800...integrated circuit, 810...modulation circuit, 812, 813...adder, 814...comparator, 815...inverter, 816...integral attenuator, 817...attenuator, 820...gate drive circuit, 821, 822...gate driver, 850...amplification circuit, 860... demodulation circuit, 870, 872... feedback circuit, BS... boost circuit, C1, C11 to C13, C81 to C85, Cb1 to Cb4, Ck1 to Ck5, Co1 to Co5... capacitors, D1, D11 to D13, D81, Db1 to Db4, Dk1 to Dk5, Do1 to Do5... diodes, L... nozzle array, L81, Lsw... inductors, M1 to M4, M81, M82, Msw... transistors, MUX1, MUX2... multiplexer, OP1... first output point, OP2... second output point, P... medium, R81 to R86, Rf1, Rf2... resistors

Claims

1. A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal that changes between the first potential and the second potential in response to the feedback signal is output during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal that is constant at the first potential or the second potential is output. A capacitive load driving circuit comprising:

2. Immediately after the transition from a constant period in which the value of the base drive signal does not change to the changing period, the state of the level switching signal output circuit becomes the second state.

2. The capacitive load driving circuit according to claim 1, wherein:

3. Immediately before the transition from the change period to the unchanged period in which the value of the base drive signal does not change, the state of the level switching signal output circuit is the second state.

2. The capacitive load driving circuit according to claim 1, wherein:

4. The level switching signal output circuit comprises: a level switching control circuit that outputs a first switching control signal and a second switching control signal that control switching of the potential of the level switching signal in response to the basic drive signal; a reference signal output circuit that outputs a reference signal corresponding to the base drive signal; a pulse signal output circuit that compares the reference signal with the feedback signal and outputs a pulse signal according to the comparison result; an output switching circuit that switches, in accordance with a logic level of the first switching control signal and a logic level of the second switching control signal, whether to output the level switching signal that is constant at the first potential, output the level switching signal that is constant at the second potential, or output the level switching signal that changes between the first potential and the second potential in accordance with the pulse signal; having 2. The capacitive load driving circuit according to claim 1, wherein:

5. a memory circuit; the level switching signal output circuit switches the logic level of the first switching control signal and the logic level of the second switching control signal based on the information stored in the memory circuit; 5. The capacitive load driving circuit according to claim 4.

6. a transport unit that transports the medium; a liquid ejection head that ejects liquid onto the medium in response to driving of a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal that changes between the first potential and the second potential in response to the feedback signal is output during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal that is constant at the first potential or the second potential is output. A liquid ejection device characterized by:

7. Immediately after the transition from a constant period in which the value of the base drive signal does not change to the changing period, the state of the level switching signal output circuit becomes the second state.

7. The liquid ejection device according to claim 6.

8. Immediately before the transition from the change period to the unchanged period in which the value of the base drive signal does not change, the state of the level switching signal output circuit is the second state.

7. The liquid ejection device according to claim 6.

9. The level switching signal output circuit comprises: a level switching control circuit that outputs a first switching control signal and a second switching control signal that control switching of the potential of the level switching signal in response to the basic drive signal; a reference signal output circuit that outputs a reference signal corresponding to the base drive signal; a pulse signal output circuit that compares the reference signal with the feedback signal and outputs a pulse signal according to the comparison result; an output switching circuit that switches, in accordance with a logic level of the first switching control signal and a logic level of the second switching control signal, whether to output the level switching signal that is constant at the first potential, output the level switching signal that is constant at the second potential, or output the level switching signal that changes between the first potential and the second potential in accordance with the pulse signal; having 7. The liquid ejection device according to claim 6.

10. a memory circuit; the level switching signal output circuit switches the logic level of the first switching control signal and the logic level of the second switching control signal based on the information stored in the memory circuit; The liquid ejection device according to claim 9 .

11. a liquid ejection head that ejects liquid onto a medium in response to driving of a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by level-shifting a reference potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; a feedback circuit that outputs a feedback signal corresponding to the drive signal; Equipped with The states of the level switching signal output circuit include a first state in which the level switching signal that changes between the first potential and the second potential in response to the feedback signal is output during a change period in which the value of the base drive signal changes, and a second state in which the level switching signal that is constant at the first potential or the second potential is output. A head unit characterized by:

12. Immediately after the transition from a constant period in which the value of the base drive signal does not change to the changing period, the state of the level switching signal output circuit becomes the second state.

12. The head unit according to claim 11.

13. Immediately before the transition from the change period to the unchanged period in which the value of the base drive signal does not change, the state of the level switching signal output circuit is the second state.

12. The head unit according to claim 11.

14. The level switching signal output circuit comprises: a level switching control circuit that outputs a first switching control signal and a second switching control signal that control switching of the potential of the level switching signal in response to the basic drive signal; a reference signal output circuit that outputs a reference signal corresponding to the base drive signal; a pulse signal output circuit that compares the reference signal with the feedback signal and outputs a pulse signal according to the comparison result; an output switching circuit that switches, in accordance with a logic level of the first switching control signal and a logic level of the second switching control signal, whether to output the level switching signal that is constant at the first potential, output the level switching signal that is constant at the second potential, or output the level switching signal that changes between the first potential and the second potential in accordance with the pulse signal; having 12. The head unit according to claim 11.

15. a memory circuit; the level switching signal output circuit switches the logic level of the first switching control signal and the logic level of the second switching control signal based on the information stored in the memory circuit; 15. The head unit according to claim 14.

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