Nonvolatile memory device

Abstract

To accurately detect a defect of a memory element.SOLUTION: A nonvolatile memory device (1) includes a first memory element (M1) capable of outputting a first current (Id1), a second memory element (M2) capable of outputting a second current (Id2), a current supply circuit (2) capable of supplying a reference current (IREF), a sense amplifier (SA) capable of comparing the first current (Id1) with the reference current (IREF) and comparing the second current (Id2) with the reference current (IREF), and a current difference acquiring circuit (3). The current difference acquiring circuit is connected to the sense amplifier (SA) and acquires a difference between the current values of the first current (Id1) and the second current (Id2) based on a comparison result between the first current (Id1) and the reference current (IREF) and a comparison result between the second current (Id2) and the reference current (IREF).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed herein relates to non-volatile memory devices. [Background technology]

[0002] The semiconductor nonvolatile memory circuit proposed in Patent Document 1 is composed of an integrated transistor pair, which is a memory cell for storing one bit of data, and is made up of a first transistor and a second transistor having a higher on-state current than the first transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-103158

[0004] [overview] If analog characteristics of memory cells are directly measured in the shipping test of a semiconductor nonvolatile memory circuit as proposed in Patent Document 1, the shipping test takes a very long time.

[0005] The nonvolatile memory device disclosed in this specification is configured to have a first memory element configured to output a first current, a second memory element arranged in parallel with the first memory element and configured to output a second current, a current supply circuit configured to supply a reference current that fluctuates within a certain range, a sense amplifier configured to compare the magnitudes of the first current and the reference current and the second current and the reference current, and a current difference acquisition circuit connected to the sense amplifier and configured to acquire the difference between the current value of the first current and the current value of the second current based on a first comparison result that is a comparison result of the first current and the reference current and a second comparison result that is a comparison result of the second current and the reference current. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a block diagram showing an example of the overall configuration of a nonvolatile memory device. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a memory array. [Figure 3] FIG. 3 is a diagram showing the gate-source voltage dependence of the drain current of a memory element before and after hot carrier injection. [Figure 4] FIG. 4 is a timing chart showing example waveforms of the signal XRST, the voltage of the first line, and the voltage of the second line. [Figure 5] FIG. 5 is an equivalent circuit diagram of a portion that operates when a pre-test of a memory array is performed. [Figure 6] FIG. 6 is a circuit diagram showing the configuration of the current difference obtaining circuit. [Figure 7] FIG. 7 is a timing chart showing the state of each signal when a pre-test is being performed. [Figure 8] FIG. 8 is a diagram showing the relationship between the reference current, the first comparison signal, the second comparison signal, and the current difference acquisition signal.

[0007] [Detailed explanation] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure consists of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, an N-channel MOS field effect transistor will be referred to as an NMOS transistor, and a P-channel MOS field effect transistor will be referred to as a PMOS transistor.

[0008] <Non-volatile memory device> Fig. 1 is a block diagram showing an example of the overall configuration of a nonvolatile memory device 1. The nonvolatile memory device 1 shown in Fig. 1 has a memory array 10, an X-decoder 20, a Y-decoder 30, and a control circuit 40. Note that the nonvolatile memory device 1 may be configured as an IC (Integrated Circuit) in which the memory array 10, the X-decoder 20, the Y-decoder 30, and the control circuit 40 are integrated into a single package.

[0009] The memory array 10 has m gate lines G1 to Gm (=word lines) laid out in the X-axis direction, 2n bit lines BL1 to BL2n laid out in the Y-axis direction, and a plurality of (=m×n) memory cells CELL arranged in a matrix along the gate lines G1 to Gm and the bit lines BL1 to BL2n. The configuration and operation of the memory array 10 will be described in detail later.

[0010] The X decoder (row decoder) 20 drives the gate lines G1 to Gm in response to an instruction from the control circuit .

[0011] The Y decoder (column decoder) 30 drives the bit lines BL1 to BL2n in response to an instruction from the control circuit .

[0012] The control circuit 40 controls each part of the device in response to commands input from outside the device.

[0013] <Memory array> Fig. 2 is a circuit diagram showing an example of the configuration of the memory array 10. The memory array 10 shown in Fig. 2 includes a first memory element M1, a second memory element M2, a sense amplifier SA, NMOS transistors Q1 and Q2, and PMOS transistors Q3 and Q4. A pair of the first memory element M1 and the second memory element M2 constitutes one memory cell CELL (see Fig. 1).

[0014] In the memory cell CELL, data "0" or data "1" is stored by combining the first memory element M1 and the second memory element M2 shown in FIG.

[0015] 2, the first memory element M1 and the second memory element M2 are each composed of an NMOS transistor. The first memory element M1 and the second memory element M2 are elements that can perform a program operation by changing the transistor characteristics through hot carrier injection, and are also called OTP (One Time Programmable) elements. Note that the first memory element M1 and the second memory element M2 may be elements other than NMOS transistors as long as they are elements that can perform a program operation.

[0016] The gates of the first memory element M1 and the second memory element M2 arranged in the i-th row are connected to a gate line Gi, where i is any natural number between 1 and m. The drain of the first memory element M1 is connected to a first wiring Lm1, and an NMOS transistor Q1 is arranged on the first wiring Lm1. The first wiring Lm1 is connected to a first line Ln1 of the sense amplifier SA. In other words, the drain of the first memory element M1 is connected to a first input terminal of the sense amplifier SA via the NMOS transistor Q1.

[0017] The drain of the second memory element M2 is connected to a second wiring Lm2, and an NMOS transistor Q2 is disposed on the second wiring Lm2. The second wiring Lm2 is connected to a second line Ln2 of the sense amplifier SA. That is, the drain of the second memory element M2 is connected to the second input terminal of the sense amplifier SA via the NMOS transistor Q2.

[0018] The source of the first memory element M1 is connected to the source of the PMOS transistor Q3. The source of the second memory element M2 is connected to the source of the PMOS transistor Q4. The drain of the PMOS transistor Q4 arranged in the j-th column is connected to the bit line BL2j-1. The drain of the PMOS transistor Q3 arranged in the j-th column is connected to the bit line BL2j, where j is any natural number between 1 and n.

[0019] Before the program operation is performed in the first memory element M1 and the second memory element M2, the first current Id1 flowing through the first memory element M1 and the second current Id2 flowing through the second memory element M2 are equal. In this case, there is no difference between the first current Id1 flowing through the first memory element M1 and the second current Id2 flowing through the second memory element M2, so the data becomes indefinite. That is, in the nonvolatile memory device 1, the initial value of the data is not set in the first memory element M1 and the second memory element M2 when the program operation is not performed.

[0020] Here, with respect to transistors, the concept of "structure" includes the size of the transistor. Therefore, for any plurality of transistors, "the same structure" means that the sizes of the plurality of transistors are also the same. If certain transistors have the same structure, and hot carrier injection into the plurality of transistors by a program operation has not been performed on the plurality of transistors, the electrical characteristics (including gate threshold voltage, etc.) of the plurality of transistors will also be the same. However, "the same structure and electrical characteristics" of any plurality of transistors means that they are the same in terms of design, and may actually include errors (i.e., "same" is understood to be a concept that includes errors).

[0021] The nonvolatile memory device 1 can perform a read operation to read data stored in the first memory element M1 and the second memory element M2, and a program operation (write operation) to store data (logical values) in the first memory element M1 and the second memory element M2.

[0022] In the program operation, hot carriers are injected into one of the first memory element M1 and the second memory element M2, thereby changing the electrical characteristics of the other of the first memory element M1 and the second memory element M2. This change causes the gate threshold voltage of the other of the first memory element M1 and the second memory element M2 to increase. In FIG. 3, the solid-line waveform INI represents the gate-source voltage dependence of the drain current of the other of the first memory element M1 and the second memory element M2 before the program operation. Also in FIG. 3, the dotted-line waveform PRG represents the gate-source voltage dependence of the drain current of the other of the first memory element M1 and the second memory element M2 after the program operation. In this way, the program operation increases the gate threshold voltage Vth of the other of the first memory element M1 and the second memory element M2.

[0023] When executing a program operation, the control circuit 40 applies a high voltage (power supply voltage VDD) to the gates of the first memory device M1 and the second memory device M2 that execute the program operation, turns off switch S11 (described later), and turns on switch S12. When the transistor that injects hot carriers is the first memory device M1, the control circuit 40 turns on switch S7 (described later) to ground the drain of the transistor that injects hot carriers, and turns off switch S8 (described later). On the other hand, when the transistor that injects hot carriers is the second memory device M2, the control circuit 40 turns on switch S8 (described later) to ground the drain of the transistor that injects hot carriers, and turns off switch S7 (described later).

[0024] Furthermore, when performing a read operation, the control circuit 40 applies a high voltage (power supply voltage VDD) to the gates of the first memory device M1 and the second memory device M2 that are to perform the read operation, turns on switch S11 (described later), and turns off switch S12. This results in a state in which a first current Id1 of the first memory device M1 and a second current Id2 of the second memory device M2 are supplied. In this state, the sense amplifier SA outputs an output signal DOUT corresponding to the value (logical value) of the data stored in the memory cell CELL, based on the magnitude relationship between the first current Id1 of the first memory device M1 and the second current Id2 of the second memory device M2.

[0025] Before a program operation is performed, hot carriers are injected into the first memory element M1 and the second memory element M2, increasing the gate threshold voltage of the first memory element M1. As a result, after a program operation is performed, the gate threshold voltage of the first memory element M1 becomes higher than the gate threshold voltage of the second memory element M2. When a read operation is performed while a voltage lower than the gate threshold voltage of the first memory element M1 is supplied to the first memory element M1 and the second memory element M2, the first current Id1 of the first memory element M1 becomes smaller than the second current Id2 of the second memory element M2. A state in which the first current Id1 of the first memory element M1 is smaller than the second current Id2 of the second memory element M2 corresponds to a state in which data "0" is stored. Therefore, during a read operation, if the first current Id1 of the first memory element M1 is smaller than the second current Id2 of the second memory element M2, the sense amplifier SA outputs an output signal DOUT (a low-level output signal DOUT) corresponding to data "0."

[0026] Meanwhile, before the program operation, hot carriers are injected into the second memory device M2 during the program operation, raising the gate threshold voltage of the second memory device M2. As a result, after the program operation, the gate threshold voltage of the second memory device M2 becomes higher than the gate threshold voltage of the first memory device M1. Therefore, when a read operation is performed while a voltage lower than the gate threshold voltage of the second memory device M2 is supplied to the first memory device M1 and the second memory device M2, the first current Id1 of the first memory device M1 becomes larger than the second current Id2 of the second memory device M2. A state in which the first current Id1 of the first memory device M1 is larger than the second current Id2 of the second memory device M2 corresponds to a state in which data “1” is stored. Therefore, during a read operation, if the first current Id1 of the first memory device M1 is larger than the second current Id2 of the second memory device M2, the sense amplifier SA outputs an output signal DOUT (high-level DOUT) corresponding to data “1.”

[0027] 2, the sense amplifier SA includes PMOS transistors Q5 and Q6, switches S1 to S4, and inverters IV1 to IV4, and the memory array 10 includes switches S5 to S12.

[0028] The source of the PMOS transistor Q6 is connected to the application terminal of the power supply voltage VDD. The drain of the PMOS transistor Q6 is connected to the first line Ln1. The gate of the PMOS transistor Q6 is connected to the second line Ln2. The first line Ln1 is connected to the drain of the first memory element M1 via the NMOS transistor Q1. The second line Ln2 is connected to the drain of the second memory element M2 via the NMOS transistor Q2.

[0029] The source of the PMOS transistor Q5 is connected to the application terminal of the power supply voltage VDD, the drain of the PMOS transistor Q5 is connected to the second line Ln2, and the gate of the PMOS transistor Q5 is connected to the first line Ln1.

[0030] A switch S1 is connected between the application terminal of the power supply voltage VDD and the first line Ln1, and a switch S2 is connected between the application terminal of the power supply voltage VDD and the second line Ln2.

[0031] The input terminal of the inverter IV1 is connected to the first line Ln1. The output terminal of the inverter IV1 is connected to the input terminal of the inverter IV2. The output terminal of the inverter IV2 is connected to the input terminal of the inverter IV3. The output signal DOUT is output from the inverter IV3.

[0032] Switches S3 and S5 are connected between the first line Ln1 and the ground terminal. The on / off of switch S3 is controlled according to the output of inverter IV1. Switches S4 and S6 are connected between the second line Ln2 and the ground terminal. The input terminal of inverter IV4 is connected to the second line Ln2. The on / off of switch S4 is controlled according to the output of inverter IV4. Switch S7 is connected between the source of NMOS transistor Q1 and the ground terminal. Switch S8 is connected between the source of NMOS transistor Q2 and the ground terminal. Switch S9 is connected between the drain of PMOS transistor Q3 and the terminal to which power supply voltage VDD is applied. Switch S10 is connected between the drain and source of PMOS transistor Q4 and the terminal to which power supply voltage VDD is applied. Switch S11 is connected between the sources of first memory element M1 and second memory element M2 and the ground terminal. Switch S12 is connected between the sources of first memory element M1 and second memory element M2 and the terminal to which power supply voltage VDD is applied.

[0033] The control circuit 40 is capable of outputting a signal XRST, and controls the on / off of the switches S1 and S2 (see FIGS. 1 and 2).

[0034] 4 is a timing chart showing example waveforms of the signal XRST, the voltage V1 of the first line Ln1, and the voltage V2 of the second line Ln2. The operation of the sense amplifier SA will be described with reference to FIG. 4. During a read operation, the period during which the signal XRST is at a low level is referred to as a precharge period, and the period during which the signal XRST is at a high level is referred to as a read period. During the read operation, the control circuit 40 turns on the switches S5 and S6.

[0035] During the precharge period, when the signal XRST is at a low level, the control circuit 40 sets the gate voltages of the first memory element M1 and the second memory element M2 to a low level and turns on the switches S1 and S2. This shorts the gates and sources of the PMOS transistors Q5 and Q6, turning them off. A positive charge is supplied to the first line Ln1 via the on-state switch S1, causing the voltage V1 to reach the level of the power supply voltage VDD. A positive charge is supplied to the second line Ln2 via the on-state switch S2, causing the voltage V2 to reach the level of the power supply voltage VDD. At this time, the outputs of the inverters IV1 and IV4 are at a low level, turning off the switches S3 and S4.

[0036] When the signal XRST is switched from low to high to transition from the precharge period to the read period, the control circuit 40 sets the gate voltages of the first memory element M1 and the second memory element M2 to high and turns off the switches S1 and S2. When the second current Id2 flows through the second memory element M2, the voltage V2 drops, and when the first current Id1 flows through the first memory element M1, the voltage V1 drops.

[0037] During a read operation after a program operation is performed and hot carriers are injected into the first memory element M1, the first current Id1 of the first memory element M1 is substantially "0," and the second current Id2 of the second memory element M2 is greater than the first current Id1 of the first memory element M1, causing the voltage V2 to drop (V2 (Id2>Id1) in FIG. 4). When the voltage V2 reaches the threshold value Th, the output of the inverter IV4 switches from low to high, turning on the switch S4. This results in voltage V2=0V, turning on the PMOS transistor Q6, and setting voltage V1=VDD. At this time, the PMOS transistor Q5 is turned off. Therefore, the output signal DOUT output from the inverter IV3 goes low. That is, the output signal DOUT is output as a signal indicating that "0" is stored.

[0038] On the other hand, during a read operation after a program operation is performed and hot carriers are injected into the second memory device M2, the second current Id2 of the second memory device M2 is substantially "0." Because the second current Id2 of the second memory device M2 is smaller than the first current Id1 of the first memory device M1, the voltage V1 drops. When the voltage V1 reaches the threshold value Th, the output of the inverter IV1 switches from low to high, and the switch S3 is turned on. As a result, the voltage V1 becomes 0V, the PMOS transistor Q5 turns on, and the voltage V2 becomes VDD. At this time, the PMOS transistor Q6 turns off. Therefore, the output signal DOUT output from the inverter IV3 becomes high. That is, the output signal DOUT is output as a signal indicating that "1" is stored.

[0039] That is, the output signal DOUT of the sense amplifier SA goes high when the first current Id1 flowing through the first wire Lm1 is greater than the second current Id2 flowing through the second wire Lm2, and goes low when the opposite is true.

[0040] <Pre-test> A pre-test is performed on the non-volatile memory device 1 before (before) the non-volatile memory device 1 is put into operation. Note that "before" includes before shipping, and also before the operation of the non-volatile memory device 1 is started. In other words, the pre-test may be performed only before shipping, or may be performed every time a system including the non-volatile memory device 1 is started, or may be performed when the system is started after a certain period of time has elapsed. Furthermore, the pre-test may be performed after the system has been started a certain number of times.

[0041] In the nonvolatile memory device 1, data is stored based on a combination of the magnitudes of the first current Id1 output by the first memory element M1 and the second current Id2 output by the second memory element M2. If the difference between the first current Id1 and the second current Id2 is small, the sense amplifier SA may not be able to compare the magnitudes, which may result in data being read that differs from the input data. Furthermore, there is a risk that data may be overwritten due to the escape of hot carriers after shipment. Furthermore, in the nonvolatile memory device 1, repeated data programming operations increase the threshold voltage, making it more difficult for current to flow. As a result, the difference between the first current Id1 and the second current Id2 may become smaller.

[0042] Therefore, a pre-test is performed to confirm that the difference between the first current Id1 and the second current Id2 is equal to or greater than a certain value in the nonvolatile memory device 1. Then, the control circuit 40 determines that the memory cell CELL is defective if the difference between the first current Id1 and the second current Id2 is less than the certain value.

[0043] In the nonvolatile memory device 1, it is possible to detect that the difference between the first current Id1 and the second current Id2 is small by directly measuring the first current Id1 and the second current Id2, but if the first current Id1 and the second current Id2 are measured directly in the pre-test, a problem arises in that the pre-test takes a long time.

[0044] Therefore, the problem of the pre-test taking a long time is solved by configuring the non-volatile memory device 1 to include a current supply circuit 2 and a current difference acquisition circuit 3, and by performing the pre-test using the current supply circuit 2 and the current difference acquisition circuit 3. In other words, the non-volatile memory device 1 can reduce the time required for the pre-test.

[0045] Here, we will explain the current supply circuit 2. The current supply circuit 2 includes a variable current circuit 21, NMOS transistors Q7, Q8, Q9, and Q10, and switches S13 and S14.

[0046] The variable current circuit 21 is a circuit included in the nonvolatile memory device 1 and is configured to generate an arbitrary reference current IREF based on a current specifying signal AIN. By including the variable current circuit 21 in the nonvolatile memory device 1, the time required for the reference current IREF to stabilize can be shortened compared to when the reference current IREF is supplied from an external source. This shortens the time required for pre-testing. The configuration of the variable current circuit 21 is not particularly limited, and a wide range of circuits can be used that are configured to quickly generate an arbitrary reference current IREF. The current specifying signal AIN may be, for example, a signal supplied from the control circuit 40, or a signal supplied from a circuit provided separately from the control circuit 40.

[0047] The variable current circuit 21 is connected to the drains and gates of the NMOS transistors Q7 and Q9 and the gates of the NMOS transistors Q8 and Q10. The source of the NMOS transistor Q7 is connected to the drain of the NMOS transistor Q8. The sources of the NMOS transistors Q8 and Q10 are connected to the ground terminal. The drain of the NMOS transistor Q9, which is arranged in the jth column, is connected to the first terminals of the switches S13 and S14, which are arranged in the jth column. The second terminal of the switch S13 is connected to the second wiring Lm2. The second terminal of the switch S14 is connected to the first wiring Lm1. The value (threshold) of the drain current of the NMOS transistor Q9 corresponds to the value of the reference current IREF.

[0048] The switch S13 is driven based on a first test signal Tg1, and the switch S14 is driven based on a second test signal Tg2. The first test signal Tg1 is an electrical signal that takes a high level or a low level. When the first test signal Tg1 is at a high level, the switch S13 is in an on state, and when the first test signal Tg1 is at a low level, the switch S13 is in an off state. The second test signal Tg2 is an electrical signal that takes a high level or a low level. When the second test signal Tg2 is at a high level, the switch S13 is on.

[0049] The current difference obtaining circuit 3 performs a pre-test to obtain the difference between the first current Id1 and the second current Id2 based on the comparison result between the reference current IREF and the first current Id1 and the comparison result between the reference current IREF and the second current Id2 using the sense amplifier SA while the reference current IREF is being supplied from the current supply circuit 2. Details of the pre-test to obtain the difference between the first current Id1 and the second current Id2 will be described later.

[0050] Fig. 5 is an equivalent circuit diagram of a portion that operates when a pre-test is performed on the memory array 10. Fig. 6 is a circuit diagram showing the configuration of the current difference acquisition circuit 3. As shown in Fig. 5, the current difference acquisition circuit 3 has PMOS transistors Q31, Q32, Q33, and Q34, first holding circuits L35 and L36, an inverter IV37, an OR circuit 38, and an XOR circuit 39.

[0051] The source of the PMOS transistor Q31 is supplied with an output signal DOUT, which is the output of the sense amplifier SA. The drain of the PMOS transistor Q31 is connected to a first holding circuit L35. The gate of the PMOS transistor Q31 is supplied with a second test signal Tg2. The PMOS transistor Q31 is turned on and off by the second test signal Tg2. When the PMOS transistor Q31 is on, it supplies the output signal DOUT (first comparison result) to the first holding circuit L35.

[0052] The source of the PMOS transistor Q32 is supplied with an output signal DOUT, which is the output of the sense amplifier SA. The drain of the PMOS transistor Q32 is connected to a second holding circuit L36. The gate of the PMOS transistor Q32 is supplied with a first test signal Tg1. The PMOS transistor Q32 is turned on and off by the first test signal Tg1. When the PMOS transistor Q32 is on, it supplies the output signal DOUT (second comparison result) to the second holding circuit L36.

[0053] The input terminal of the first holding circuit L35 is connected to the drain of the PMOS transistor Q31. The output of the first holding circuit L35 is connected to the source of the PMOS transistor Q33. The first holding circuit L35 holds the information from the PMOS transistor Q31 and outputs the held information to the PMOS transistor Q33. The output signal of the first holding circuit L35 is referred to as a first comparison signal Tm1.

[0054] The input terminal of the second holding circuit L36 is connected to the drain of the PMOS transistor Q32. The output of the second holding circuit L36 is connected to the source of the PMOS transistor Q34 via an inverter IV37. The second holding circuit L36 holds the information from the PMOS transistor Q32. The second holding circuit L36 outputs the held information to the inverter IV37. The inverter IV37 inverts the signal from the second holding circuit L36 and outputs it to the PMOS transistor Q34. The output signal of the inverter IV37 is referred to as a second comparison signal Tm2.

[0055] A first test signal Tg1 and a second test signal Tg2 are supplied to the OR circuit 38. The output of the OR circuit 38 is supplied as a pre-test signal PRTEST to the gates of the PMOS transistors Q33 and Q34. That is, the PMOS transistors Q33 and Q34 are on / off controlled by the pre-test signal PRTEST.

[0056] The XOR circuit 39 has two input terminals, each connected to the drain of a PMOS transistor Q33 or Q34. That is, the XOR circuit 39 is supplied with output signals output from the drains of the PMOS transistors Q33 or Q34. More specifically, when the PMOS transistor Q33 is on, the XOR circuit 39 is supplied with a first comparison signal Tm1, and when the PMOS transistor Q34 is on, the XOR circuit 39 is supplied with a second comparison signal Tm2. The XOR circuit 39 then performs an exclusive OR (XOR) on the supplied signals and outputs the result as a current difference acquisition signal TmData. The current difference acquisition signal TmData is sent to the control circuit 40. The control circuit 40 is configured to be able to perform a pre-test to acquire the difference in current value between the first current Id1 and the second current Id2 in accordance with the current difference acquisition signal TmData.

[0057] The memory array 10 shown in FIG. 2 further includes an inverter IV5, NAND gates N1 to N3, and buffers B1 and B2.

[0058] A circuit formed by the inverter IV5, NAND gates N1 and N2, and buffers B1 and B2 controls the on / off of the NMOS transistors Q1 and Q2 based on signals SG1 and SG2 output from the control circuit 40.

[0059] A signal SG1 is supplied to each first input terminal of NAND gates N1 and N2. A signal SG2 is supplied to a second input terminal of NAND gate N1. A signal SG2 is supplied to an input terminal of inverter IV5. An output terminal of inverter IV5 is connected to a second input terminal of NAND gate N2. An output terminal of NAND gate N1 is connected to a gate of NMOS transistor Q1 via buffer B1. An output terminal of NAND gate N2 is connected to a gate of NMOS transistor Q2 via buffer B2.

[0060] The signal SG1 becomes high level when a pre-test is being performed and becomes low level when no pre-test is being performed. The signal SG2 is the same signal as the one that becomes low level when injecting hot carriers into the first memory element M1 and becomes high level when injecting hot carriers into the second memory element M2.

[0061] The NAND gate N3 controls the on / off of the PMOS transistors Q3 and Q4 based on the signals SG2 and SG3 output from the control circuit 40. The signal SG2 is supplied to the first input terminal of the NAND gate N3. The signal SG3 is supplied to the second input terminal of the NAND gate N3. The output terminal of the NAND gate N3 is connected to the gates of the PMOS transistors Q3 and Q4.

[0062] Details of the pre-test will be described with reference to the drawings. FIG. 7 is a timing chart showing the states of each signal when the pre-test is being executed. In the pre-test, the variable current circuit 21 of the current supply circuit 2 has a configuration capable of outputting currents with current values of I1, I2, ···, In (n is an integer). It is assumed that the relationship Ik-1 < Ik holds for the current values.

[0063] And it is described assuming that the magnitude relationship of I3 < Id2 < I4 and I6 < Id1 < I7 holds between the first current Id1 output from the first memory element M1 and the second current Id2 output from the second memory element M2.

[0064] The timing chart shown in FIG. 7 shows three different test states. In the timing chart shown in FIG. 7, the left state shows the case where the reference current IREF is smaller than the second current Id2. The middle state shows the case where the reference current IREF is larger than the second current Id2 and smaller than the first current Id1. The right state shows the case where the reference current IREF is larger than the first current Id1. Each state shows the state of the signal when one pre-test is being performed.

[0065] Before the pre-test is performed, the memory cell CELL performs a program operation on the first memory element M1 and the second memory element M2 so as to generate an output signal DOUT whose output value is "1." In this state, when the NMOS transistor Q1 is turned on, a first current Id1 flows through the first wiring Lm1. When the NMOS transistor Q2 is turned on, a second current Id2 flows through the second wiring Lm2.

[0066] First, a case where the reference current IREF is smaller than the first current Id1 and the second current Id2 will be described. In FIG. 7, at time T11, the supply of the current specification signal AIN to the variable current circuit 21 begins. In FIG. 7, the current specification signal AIN is described as a signal that goes high or low, but in reality, it also includes information specifying a current value. For example, when the current specification signal AIN specifying a current value I1 is supplied, the variable current circuit 21 outputs a current of the current value I1 upon receiving the current specification signal AIN. As described above, because the variable current circuit 21 is a circuit included inside the nonvolatile memory device 1, the time required for the output current to stabilize can be shortened compared to when a current is supplied from an external source.

[0067] Also, at time T11, the signal SG1 and the first test signal Tg1 go high. The signal SG2 and the second test signal Tg2 are low. Because the signal SG1 is high and the signal SG2 is low, the output of the NAND gate N1 goes high and the output of the NAND gate N2 goes low. This turns on the NMOS transistor Q1, causing a first current Ld1 to flow through the first wiring Lm1.

[0068] Furthermore, since the first test signal Tg1 is at a high level, the switch S13 is turned on. As a result, the reference current IREF flows through the second wiring Lm2 to which the current supply circuit 2 is connected. This state in which the first current Ld1 flows through the first wiring Lm1 and the reference current flows through the second wiring Lm2 is referred to as a first determination state.

[0069] In the first determination state, the sense amplifier SA outputs a high-level output signal DOUT (first comparison result) when the current flowing through the first line Ln1 connected to the first wiring Lm1 is greater than the current flowing through the second line Ln2 connected to the second wiring Lm2. Between time T11 and time T12, the first current Id1 flows through the first wiring Lm1, and the reference current IREF flows through the second wiring Lm2. As described above, the current value of the reference current IREF is I1, and since Id1>IREF, the output signal DOUT of the sense amplifier SA is the first comparison result and is high.

[0070] From time T11 to time T12, the first test signal Tg1 is at a high level and the second test signal Tg2 is at a low level. Therefore, the PMOS transistor Q31 of the current difference acquisition circuit 3 is on and the PMOS transistor Q32 is off. Therefore, the output signal DOUT is supplied to the first holding circuit L35, which holds the high-level first comparison result and outputs it as the first comparison signal Tm1.

[0071] Between time T11 and time T12, the first test signal Tg1 is at a high level, and the second test signal Tg2 is at a low level. Therefore, the pre-test signal PRTEST output from the OR circuit 38 is at a high level. The PMOS transistors Q33 and Q34 controlled by the pre-test signal PRTEST are both in an off state. Low-level signals are supplied to both XOR circuits 39, and the current difference acquisition signal TmData output from the XOR circuit 39 is at a low level.

[0072] At time T12, the signal SG2 goes high, the first test signal Tg1 goes low, and the second test signal Tg2 goes high. The low level of the first test signal Tg1 turns the switch S13 off, preventing the reference current IREF from flowing through the second wiring Lm2. The high level of the second test signal Tg2 turns the switch S14 on, allowing the reference current IREF to flow through the first wiring Lm1.

[0073] Furthermore, because the signal SG1 is at a high level and the signal SG2 is at a high level, the output of the NAND gate N1 is at a low level and the output of the NAND gate N2 is at a high level. This turns on the NMOS transistor Q2, causing the second current Ld2 to flow through the second wiring Lm2. This state, in which the second current Ld2 flows through the second wiring Lm2 and the reference current flows through the first wiring Lm1, is called the second determination state. The control circuit 40 can switch between the first determination state and the second determination state.

[0074] In the second determination state, a reference current IREF flows through the first wiring Lm1, and a second current Ld2 flows through the second wiring Lm2. Because the current value of the reference current IREF is I1, Id2>IREF. In other words, the current flowing through the first wiring Lm1 is smaller than the current flowing through the second wiring Lm2. Therefore, the output signal DOUT, which is the output of the sense amplifier SA, is the second comparison result and is at a low level.

[0075] From time T12 to time T13, the first test signal Tg1 is at a low level and the second test signal Tg2 is at a high level. Therefore, the PMOS transistor Q31 of the current difference acquisition circuit 3 is in an off state and the PMOS transistor Q32 is in an on state. Therefore, the low-level output signal DOUT is supplied to the second holding circuit L36, which holds the low-level second comparison result. The output of the second holding circuit L36 is connected to the inverter IV37, and the output of the inverter IV37 is the second comparison signal Tm2. In other words, the second comparison signal Tm2 is at a high level.

[0076] Between time T11 and time T12, the first test signal Tg1 is at a low level, and the second test signal Tg2 is at a high level. Therefore, the pre-test signal PRTEST output from the OR circuit 38 is at a high level. The PMOS transistors Q33 and Q34 controlled by the pre-test signal PRTEST are both in an off state. Low-level signals are supplied to both XOR circuits 39, and the current difference acquisition signal TmData output from the XOR circuit 39 is at a low level.

[0077] At time T13, the PMOS transistors Q3 and Q4 (not shown) are turned off. Also, the first test signal Tg1 and the second test signal Tg2 are at a low level. Thereby, no current flows through the first wiring Lm1 and the second wiring Lm2.

[0078] Since both the first test signal Tg1 and the second test signal Tg2 are low, the pre-test signal PRTEST, which is the output of the OR circuit 38, is at a low level. The PMOS transistors Q33 and Q34 controlled by the pre-test signal PRTEST are both in the on state. Therefore, the first comparison signal Tm1 held in the first holding circuit L35 and the second comparison signal Tm2, which is the inverted signal of the output held in the second holding circuit L36, are supplied to the XOR circuit 39. From time T13 to time T14, since both the first comparison signal Tm1 and the second comparison signal Tm2 are at a high level, the current difference acquisition signal TmData, which is the output signal of the XOR circuit 39, becomes a low level.

[0079] Next, the pre-test (times T21 to T24) when Id2 < IREF < Id1 will be described. The operations of each signal, switch, and transistor at each of the times T21 to T24 are the same as those at times T11 to T14. Therefore, details of the signal changes, switch, and transistor operations will be omitted. Assume that the current value of the reference current IREF is I4.

[0080] At time T21, the control circuit 40 operates to enter the first determination state. That is, the switch S13 is turned on and the NMOS transistor Q1 is turned on. Thereby, the first current Id1 flows through the first wiring Lm1 and the reference current IREF flows through the second wiring Lm2. Since Id1 > IREF, the output signal DOUT, which is the first comparison result, becomes a high level. Also, as described above, the PMOS transistor Q31 of the current difference acquisition circuit 3 is turned on. The first holding circuit L35 holds the high-level first comparison result and outputs it as the first comparison signal Tm1.

[0081] At time T22, the control circuit 40 operates so as to be in the second determination state. That is, the switch S14 is turned on and the NMOS transistor Q2 is turned on. As a result, the reference current IREF flows through the first wiring Lm1, and the second current Id2 flows through the second wiring Lm2. Since IREF > Id2, the output signal DOUT which is the second comparison result becomes high level. Also, as described above, the PMOS transistor Q32 of the current difference acquisition circuit 3 is turned on. The second holding circuit L_{36} holds the high-level second comparison result. Then, the second comparison signal Tm2 obtained by inverting the output of the second holding circuit L_{36} by the inverter IV37 is held at low level.

[0082] At time T23, since the first test signal Tg1 and the second test signal Tg2 become low level, the PMOS transistors Q33 and Q34 controlled by the pre-test signal PRTEST are both turned on. As a result, the high-level first comparison signal Tm1 and the low-level second comparison signal Tm2 are supplied to the XOR circuit 39, and the high-level current difference acquisition signal TmData is output.

[0083] At time T31, the control circuit 40 operates so as to be in the first determination state. That is, the switch S13 is turned on and the NMOS transistor Q1 is turned on. As a result, the first current Id1 flows through the first wiring Lm1, and the reference current IREF flows through the second wiring Lm2. Since Id1 < IREF, the output signal DOUT which is the first comparison result becomes low level. Also, as described above, the PMOS transistor Q31 of the current difference acquisition circuit 3 is turned on. The first holding circuit L_{35} holds the low-level first comparison result and outputs it as the first comparison signal Tm1.

[0084] At time T32, the control circuit 40 operates to enter the second determination state. That is, the switch S14 is turned on and the NMOS transistor Q2 is turned on. As a result, the reference current IREF flows through the first wiring Lm1, and the second current Id2 flows through the second wiring Lm2. Because IREF>Id2, the output signal DOUT, which is the second comparison result, becomes high level. Also, as described above, the PMOS transistor Q32 of the current difference acquisition circuit 3 is turned on. The second holding circuit L36 holds the second comparison result at high level. Then, the second comparison signal Tm2, ​​which is the output of the second holding circuit L36 inverted by the inverter IV37, is held at low level.

[0085] At time T33, the first test signal Tg1 and the second test signal Tg2 go low, and the PMOS transistors Q33 and Q34 controlled by the pre-test signal PRTEST are both turned on, causing the low-level first comparison signal Tm1 and the low-level second comparison signal Tm2 to be supplied to the XOR circuit 39, which then outputs a low-level current difference acquisition signal TmData.

[0086] When one of the first comparison signal Tm1 and the second comparison signal Tm2 is at a high level and the other is at a low level, the XOR circuit 39 outputs a high-level current difference acquisition signal TmData. Therefore, when the first comparison signal Tm1 is at a low level and the second comparison signal Tm2 is at a high level, the XOR circuit 39 also outputs a high-level current difference acquisition signal TmData. In other words, the current supply circuit 2 and the current difference acquisition circuit 3 can acquire the current difference acquisition signal TmData for acquiring the current difference regardless of whether the first current Id1 or the second current Id2 is larger.

[0087] The control circuit 40 then acquires the difference between the current value of the first current Id1 and the current value of the second current Id2 based on the current difference acquisition signal TmData. A method for acquiring the difference between the current value of the first current Id1 and the current value of the second current Id2 will be described.

[0088] FIG. 8 is a diagram showing the relationship between the reference current IREF, the first comparison signal Tm1, the second comparison signal Tm2, ​​and the current difference acquisition signal TmData.

[0089] 8, when the first current Id1 and the second current Id2 are both greater than the reference current IREF, the first comparison signal Tm1 and the second comparison signal Tm2 both go high, causing the current difference acquisition signal TmData, which is the exclusive OR of the first comparison signal Tm1 and the second comparison signal Tm2, ​​to go low.

[0090] When the first current Id1 and the second current Id2 are both smaller than the reference current IREF, the first comparison signal Tm1 and the second comparison signal Tm2 both go low, causing the current difference acquisition signal TmData, which is the exclusive OR of the first comparison signal Tm1 and the second comparison signal Tm2, ​​to go low.

[0091] Furthermore, when Id1>IREF>Id2, the first comparison signal Tm1 goes high and the second comparison signal Tm2 goes low, causing the current difference acquisition signal TmData, which is the exclusive OR of the first comparison signal Tm1 and the second comparison signal Tm2, ​​to go high.

[0092] That is, when a pre-test is performed after executing a program operation on the first memory device M1 and the second memory device M2 so that Id1>Id2, the control circuit 40 acquires the current difference acquisition signal TmData. When the current difference acquisition signal TmData is at a high level, the control circuit 40 can determine that Id1>IREF>Id2.

[0093] The control circuit 40 then varies the reference current IREF and acquires the current difference acquisition signal TmData for each reference current IREF. The control circuit 40 then acquires the boundary portion where the current difference acquisition signal TmData switches from low level to high level or from high level to low level, thereby obtaining the difference between the current value of the first current Id1 and the current value of the second current Id2.

[0094] A procedure for obtaining the difference between the current value of the first current Id1 and the current value of the second current Id2 by the control circuit 40 will be specifically described with reference to FIG. 8.

[0095] As shown in FIG. 8, when the current value of the reference current IREF is I3 or less, the current difference acquisition signal TmData is at a low level. Therefore, the control circuit 40 determines that Id1, Id2 > I3. On the other hand, when the current value of the reference current IREF is I4, the current difference acquisition signal TmData is at a high level. Therefore, the control circuit 40 determines that Id1 > I4 > Id2. Further, when the current value of the reference current IREF is I6, the current difference acquisition signal TmData is at a high level. Therefore, the control circuit 40 determines that Id1 > I6 > Id2. And when the current value of the reference current IREF is I7, the current difference acquisition signal TmData is at a low level. Therefore, the control circuit 40 determines that Id1, Id2 < I7.

[0096] The control circuit 40 determines that Id1 > I6 > I4 > Id2. And the control circuit 40 can determine that the difference between the current value of the first current Id1 and the current value of the second current Id2 is (I7 - I3) > (Id1 - Id2) > (I6 - I4).

[0097] As described above, the reference current IREF supplied from the current supply circuit 2 is compared with the first current Id1, and the reference current IREF is compared with the second current Id2. By using the result obtained by processing the comparison result by the current difference acquisition circuit 3, the difference between the current value of the first current Id1 output by the first memory element M1 when programmed so that the data of "1" can be read out and the current value of the second current Id2 output by the second memory element M2 can be obtained.

[0098] The variable current circuit 21 of the current supply circuit 2 is configured with the same circuitry as that of the nonvolatile memory device 1. Therefore, the time required for the supplied current to stabilize can be made shorter than when current is supplied from an external circuit. This makes it possible to shorten the time required to obtain the current difference between the first current Id1 and the second current Id2 by changing each reference current IREF and obtaining the current difference obtaining signal TmData.

[0099] The current value of the reference current IREF may be changed in order from I1 to In, and the current difference acquisition signal TmData may be acquired each time to acquire the difference between the current value of the first current Id1 and the current value of the second current Id2. Meanwhile, the pre-test may also be used as a pre-shipment test for the nonvolatile memory device 1. In this case, the difference between the current value of the first current Id1 and the current value of the second current Id2 in the nonvolatile memory device 1 often falls within a certain range. Therefore, when the pre-test is performed as a pre-shipment test, the control circuit 40 can narrow down the target current value of the reference current IREF.

[0100] That is, the control circuit 40 narrows down the range of current values ​​at which the current difference acquisition signal TmData goes high. The control circuit 40 may acquire the current difference acquisition signal TmData by varying the reference current IREF near the upper and lower limits of that range. This reduces the number of times the reference current IREF is varied, thereby shortening the time required to acquire the difference between the current value of the first current Id1 and the current value of the second current Id2.

[0101] The control circuit 40 may narrow down the target of the reference current IREF based on the results of previous tests. In addition, in a configuration in which the pre-test is performed after a system including the nonvolatile memory device 1 has operated for a certain period of time or a certain number of times, the control circuit 40 may narrow down the target of the reference current IREF based on the results of the previous or multiple previous pre-tests.

[0102] The current difference obtaining circuit 3 outputs a high-level current difference obtaining signal TmData when one of the first comparison signal Tm1 and the second comparison signal Tm2 is high and the other is low. Furthermore, when both the first comparison signal Tm1 and the second comparison signal Tm2 are high or low, the current difference obtaining circuit 3 outputs a low-level current difference obtaining signal TmData. Therefore, even when the first current Id1 is smaller than the second current Id2, the current difference obtaining circuit 3 can obtain the difference between the current values ​​of the first current Id1 and the second current Id2.

[0103] The control circuit 40 can then perform a state detection operation to detect the state of the memory cell CELL based on the difference between the current value of the first current Id1 and the current value of the second current Id2. The state of the memory cell CELL can be, for example, whether or not it is in a state where it can accurately output supplied information. As described above, in the memory cell CELL, the difference between the current value of the first current Id1 and the current value of the second current Id2 must be equal to or greater than a certain magnitude. The control circuit 40 may be configured to be able to detect the state of the tested memory cell CELL.

[0104] Furthermore, when detecting the state of the memory cell CELL, the control circuit 40 may execute a quality determination operation in which the memory cell CELL is determined to be a good product if the difference between the current value of the first current Id1 and the current value of the second current Id2 is equal to or greater than a certain value. Note that in the quality stable operation, the difference between the current value of the first current Id1 and the current value of the second current Id2 may be obtained when the first current Id1 is greater than or smaller than the second current Id2, and the memory cell CELL may be determined to be a good product if both of the current differences are equal to or greater than a certain current difference.

[0105] Furthermore, in a configuration in which a pre-test is performed every time a system including the non-volatile memory device 1 operates for a certain period of time, the difference between the current value of the first current Id1 and the current value of the second current Id2 may be stored every time it is acquired, and the life of the non-volatile memory device 1 may be estimated based on the tendency of fluctuations in the difference in current values. Furthermore, the control circuit 40 may notify the user of the life of the non-volatile memory device 1 every time a pre-test is performed, or may notify the user when the estimated life falls below a certain time.

[0106] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0107] <Additional Notes> The various embodiments described above will be generally described below.

[0108] The nonvolatile memory device (1) described above includes a first memory element (M1) configured to be able to output a first current (Id1); a second memory element (M2) arranged in parallel with the first memory element (M1) and configured to be able to output a second current (Id2); a current supply circuit (2) configured to be able to supply a reference current (IREF) that fluctuates within a certain range; a sense amplifier (SA) configured to be able to compare the magnitudes of a first current (Id1) and a reference current (IREF) and the magnitudes of a second current (Id2) and a reference current (IREF); The configuration (first configuration) includes a current difference acquisition circuit (3) connected to the sense amplifier (SA) and configured to acquire the difference between the current value of the first current (Id1) and the current value of the second current (Id2) based on a first comparison result which is a comparison result between the first current (Id1) and the reference current (IREF) and a second comparison result which is a comparison result between the second current (Id2) and the reference current (IREF).

[0109] In the nonvolatile memory device (1) of the first configuration, the current difference acquisition circuit (3) has a first holding circuit (L35) configured to hold a first comparison result, a second holding circuit (L36) configured to hold a second comparison result, and a configuration (second configuration) to acquire the difference between the current value of the first current (Id1) and the current value of the second current (Id2) based on the information held by the first holding circuit (L35) and the information held by the second holding circuit (L36).

[0110] In the nonvolatile memory device (1) of the first or second configuration, a first wiring (Lm1) and a second wiring (Lm2) configured to be connected to a sense amplifier (SA), This configuration (third configuration) has a control circuit (40) that can switch between a first determination state in which a reference current (IREF) is supplied to the second wiring (Lm2) when a first current (Id1) is flowing through the first wiring (Lm1), and a second determination state in which a reference current (IREF) is supplied to the first wiring (Lm1) when a second current (Id2) is flowing through the second wiring (Lm2).

[0111] In the nonvolatile memory device (1) of the third configuration, the control circuit (40) is configured (fourth configuration) to perform a state detection operation that detects the state of the first memory element (M1) and the second memory element (M2) based on the magnitude of the difference between the current value of the first current (Id1) and the current value of the second current (Id2).

[0112] In the nonvolatile memory device (1) of the third or fourth configuration, the control circuit (40) is configured (fifth configuration) to be able to perform a pass / fail judgment operation based on the difference between the current value of the first current (Id1) and the current value of the second current (Id2).

[0113] In the nonvolatile memory device (1) of any of the third to fifth configurations, the control circuit (40) is configured (sixth configuration) to be able to perform a lifetime estimation operation to estimate the lifetimes of the first memory element (M1) and the second memory element (M2).

[0114] In the nonvolatile memory device (1) of any of the first to sixth configurations, at least the first memory element (M1), the second memory element (M2), and the current supply circuit (2) are configured to be sealed in a single package (seventh configuration). [Explanation of symbols]

[0115] 1. Non-volatile memory device 10 Memory Array 11 Gate control circuit 12 Gate control circuit 20 X Decoders 30 Y decoder 40 Control circuit 2 Current supply circuit 21 Variable current circuit 3 Current difference acquisition circuit B1, B2 buffers BL1~BL2n bit lines CELL memory cell G1~Gm gate lines IV1~IV5 inverters M1 First memory element M2 Second memory element N1~N3 NAND gates Q1, Q2 NMOS transistors Q3~Q6 PMOS transistors Q7~Q10 NMOS transistors Q31~Q34 PMOS transistors L35, L36 latch circuit IV37 Inverter 38 OR Circuit 39 XOR circuit S1~S14 switches SA Sense Amplifier

Claims

1. a first memory element configured to be able to output a first current; a second memory element arranged in parallel with the first memory element and configured to be able to output a second current; a current supply circuit configured to be able to supply a reference current that fluctuates within a certain range; a sense amplifier configured to be able to compare the magnitudes of the first current and the reference current and the second current and the reference current; a current difference acquisition circuit connected to the sense amplifier and configured to acquire the difference between the current value of the first current and the current value of the second current based on a first comparison result which is a comparison result between the first current and the reference current and a second comparison result which is a comparison result between the second current and the reference current.

2. 2. The nonvolatile memory device of claim 1, wherein the current difference acquisition circuit includes a first holding circuit configured to hold the first comparison result, a second holding circuit configured to hold the second comparison result, and is configured to acquire the current difference between the first current and the second current based on the information held by the first holding circuit and the information held by the second holding circuit.

3. a first wiring and a second wiring configured to be connected to the sense amplifier; 2. The nonvolatile memory device of claim 1, configured to have a control circuit capable of switching between a first determination state in which the reference current is supplied to the second wiring when the first current is flowing through the first wiring, and a second determination state in which the reference current is supplied to the first wiring when the second current is flowing through the second wiring.

4. 4. The nonvolatile memory device of claim 3, wherein the control circuit is configured to perform a state detection operation that detects the state of the first memory element and the second memory element based on the magnitude of the difference between the current value of the first current and the current value of the second current.

5. 4. The nonvolatile memory device according to claim 3, wherein the control circuit is configured to be able to execute a quality determination operation based on a difference between a current value of the first current and a current value of the second current.

6. The nonvolatile memory device according to claim 3 , wherein the control circuit is configured to be capable of performing a lifetime estimation operation for estimating lifetimes of the first memory element and the second memory element.

7. 7. The nonvolatile memory device according to claim 1, wherein at least the first memory element, the second memory element, and the current supply circuit are sealed in a single package.

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