Semiconductor integrated circuit, memory controller, and semiconductor integrated circuit control method

Abstract

To provide a semiconductor integrated circuit in which a step-down voltage with small fluctuation caused by the influence of variation of circuit elements can be obtained.SOLUTION: A semiconductor integrated circuit according to an embodiment includes a plurality of step-down circuits, a plurality of input switches, and a plurality of output switches. The step-down circuits step down first or second voltage inputted, and output first or second step-down voltage. The input switches are disposed at input ends of the respective step-down circuits, and switch the input of the first or second voltage. The output switches are disposed at output ends of the respective step-down circuits, and switch the output of the first or second step-down voltage.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor integrated circuit, a memory controller, and a method for controlling the semiconductor integrated circuit. [Background technology]

[0002] Conventionally, in circuits that use diode voltage differences to correct the temperature characteristics of circuit elements, a voltage step-down circuit is used to convert the diode voltage difference into a voltage suitable for the input voltage range of the circuit that receives it. Generally, to achieve a highly accurate temperature characteristic correction function, the step-down voltage output by the voltage step-down circuit must have minimal fluctuation due to variations in the circuit elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0268810 [Patent Document 2] U.S. Patent No. 5,600,186 [Patent Document 3] US Patent Application Publication No. 2001 / 0001544 Summary of the Invention [Problem to be solved by the invention]

[0004] The present embodiment aims to provide a semiconductor integrated circuit, a memory controller, and a method for controlling a semiconductor integrated circuit that can obtain a step-down voltage with little fluctuation due to the influence of variations in circuit elements. [Means for solving the problem]

[0005] The semiconductor integrated circuit of this embodiment includes a plurality of step-down circuits, a plurality of input switches, and a plurality of output switches. The plurality of step-down circuits step down an input first voltage or a second voltage and output the first step-down voltage or the second step-down voltage. The plurality of input switches are provided at input terminals of the plurality of step-down circuits, respectively, and switch between the input of the first voltage or the second voltage. The plurality of output switches are provided at output terminals of the plurality of step-down circuits, respectively, and switch between the output of the first step-down voltage or the second step-down voltage. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram illustrating an example of a configuration of a memory system. [Figure 2] FIG. 2 is a circuit diagram for explaining the configuration of a voltage step-down circuit according to a first comparative example. [Figure 3] FIG. 10 is a circuit diagram for explaining the configuration of a voltage step-down circuit according to Comparative Example 2. [Figure 4] 10 is a timing chart showing control waveforms of switches in a voltage step-down circuit of Comparative Example 2. [Figure 5] 1 is a circuit diagram for explaining the configuration of a voltage step-down circuit according to an embodiment of the present invention; [Figure 6] 4 is a timing chart showing control waveforms of switches in the voltage step-down circuit of the present embodiment. [Figure 7] FIG. 2 is a circuit diagram for explaining the configuration of a current generating circuit. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (First embodiment) (Memory system configuration)

[0008] 1 is a block diagram showing an example of the configuration of a memory system. The memory system 1 of this embodiment includes a memory controller 3 and a nonvolatile memory 2. The nonvolatile memory 2 may include multiple memory chips. The memory system 1 is connectable to a host device 4. The host device 4 is, for example, an electronic device such as a personal computer or a mobile terminal.

[0009] The memory system 1 may be configured by mounting multiple chips that make up the memory system 1 on a motherboard on which the host device 4 is mounted, or may be configured as a system LSI (Large-Scale Integrated Circuit) or SoC (System-on-a-Chip) that realizes the memory system 1 in a single module. Examples of the memory system 1 include memory cards such as SD cards, SSDs (Solid-State Drives), and eMMCs (embedded-Multi-Media-Cards).

[0010] The nonvolatile memory 2 is a NAND type memory having a plurality of memory cells, and stores data in a nonvolatile manner.

[0011] The memory controller 3 issues commands to write (also called program), read, erase, etc. to the nonvolatile memory 2 in response to commands from, for example, a host device 4. The memory controller 3 also manages the memory space of the nonvolatile memory 2. The memory controller 3 includes a host interface (host I / F) circuit 10, a processor 11, a RAM (Random Access Memory) 12, a buffer memory 13, a memory interface circuit (memory I / F) circuit 14, an ECC (Error Checking and Correcting) circuit 15, an analog circuit 16, etc. The nonvolatile memory 2 is an example of a "semiconductor memory device."

[0012] The host I / F circuit 10 is connected to the host device 4 via a host bus, and performs interface processing with the host device 4. The host I / F circuit 10 also transmits and receives commands, addresses, and data to and from the host device 4.

[0013] The processor 11 is composed of, for example, a CPU (Central Processing Unit). The processor 11 controls the operation of the entire memory controller 3. For example, when the processor 11 receives a write command from the host device 4, it issues a write command to the nonvolatile memory 2 in response to the write command from the host device 4 via the memory I / F circuit 14. The same applies to read and erase operations. The processor 11 also executes various processes for managing the nonvolatile memory 2, such as wear leveling. The processor 11 is an example of a "control circuit."

[0014] The RAM 12 is used as a work area for the processor 11, and stores firmware data loaded from the nonvolatile memory 2 and various tables created by the processor 11. The RAM 12 is configured from, for example, a DRAM or an SRAM.

[0015] The buffer memory 13 temporarily stores data transmitted from the host device 4 and also temporarily stores data transmitted from the nonvolatile memory 2 .

[0016] The memory I / F circuit 14 is connected to the nonvolatile memory 2 via a bus, and performs interface processing with the nonvolatile memory 2. The memory I / F circuit 14 also transmits and receives commands, addresses, and data to and from the nonvolatile memory 2.

[0017] When writing data, the ECC circuit 15 generates an error correction code for the write data, adds this error correction code to the write data, and sends the data to the memory I / F circuit 14. When reading data, the ECC circuit 15 performs error detection and / or error correction on the read data using the error correction code included in the read data. The ECC circuit 15 may be provided within the memory I / F circuit 14.

[0018] The analog circuit 16 is an analog circuit intended to support the operation of the memory system. The analog circuit 16 includes an oscillator circuit, a reference voltage circuit, and the like. The oscillator circuit and the reference voltage circuit include a voltage step-down circuit 20 that constitutes the semiconductor integrated circuit of this embodiment. Before describing the configuration of the voltage step-down circuit 20 of this embodiment, a voltage step-down circuit of a comparative example will be described.

[0019] (Voltage step-down circuit of comparative example 1) FIG. 2 is a circuit diagram for explaining the configuration of a voltage step-down circuit according to a first comparative example.

[0020] The voltage step-down circuit 100 of the first comparative example includes constant current sources I1 and I2, diodes D1 and D2, operational amplifiers AMP1 and AMP2, PMOS transistors MP1 and MP2, and a resistor R a1 , R a2 , R b1 and R b2 It is equipped with:

[0021] The constant current source I1 and the diode D1 are connected in series between the power supply voltage VDD and the ground GND, while the constant current source I2 and the diode D2 are connected in series between the power supply voltage VDD and the ground GND.

[0022] One terminal of the operational amplifier AMP1 is connected to a node N1 between the constant current source I1 and the diode D1, and the other terminal is connected to the drain of the PMOS transistor MP1. The output terminal of the operational amplifier AMP1 is connected to the gate terminal of the PMOS transistor MP1. The voltage Va across the diode D1 is input to one terminal of the operational amplifier AMP1.

[0023] The PMOS transistor MP1 has a gate connected to the output terminal of the operational amplifier AMP1, a source connected to the power supply voltage VDD, and a drain connected to the other terminal of the operational amplifier AMP1 and the resistor R a1 is connected to.

[0024] A feedback loop is formed by the operational amplifier AMP1 and the PMOS transistor MP1, and a resistor R a1 , R a2 A voltage Va is applied to the series resistor R a1 and R a2 From the node between a1 , R a2 The voltage Va' that has been stepped down (divided) by the

[0025] One terminal of the operational amplifier AMP2 is connected to a node N2 between the constant current source I2 and the diode D2, and the other terminal is connected to the drain of the PMOS transistor MP2. The output terminal of the operational amplifier AMP2 is connected to the gate terminal of the PMOS transistor MP2. The voltage Vb across the diode D2 is input to one terminal of the operational amplifier AMP2.

[0026] The PMOS transistor MP2 has a gate connected to the output terminal of the operational amplifier AMP2, a source connected to the power supply voltage VDD, and a drain connected to the other terminal of the operational amplifier AMP2 and the resistor R b1 is connected to.

[0027] A feedback loop is formed by the operational amplifier AMP2 and the PMOS transistor MP2, and the resistor R b1 , R b2A voltage Vb is applied to the series resistor R b1 and R b2 From the node between b1 , R b2 The voltage Vb' is stepped down (divided) by the voltage Vb' and output.

[0028] If the current value output by constant current source I1 is N times the current value output by constant current source I2, and the area of ​​diode D2 is M times the area of ​​diode D1, the difference between the voltage Va applied to diode D1 and the voltage Vb applied to diode D2 is given by equation (1).

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[0029] Here, k is the Boltzmann constant, T is the temperature, and q is the elementary charge.

[0030] The operational amplifier AMP1 and the PMOS transistor MP1 form a feedback loop, so the resistor R a1 , R a2 The voltage across the series resistor configured as above is voltage Va.

[0031] Similarly, the operational amplifier AMP2 and the PMOS transistor MP2 form a feedback loop, so the resistor R b1 , R b2 The voltage across the series resistor configured as above is voltage Vb.

[0032] Therefore, the resistance R a1 , R a2 The voltage Va' divided by the resistor R b1 , R b2 The voltage Vb' divided by these is expressed by equations (2) and (3), respectively.

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[0033] where the resistance R a1 , R a2 , R b1 and R b2 The resistance values ​​of all resistors are equal (or resistance R a1 and R b1 and resistance R a2 and R b2 and the step-down ratio is D R Then, the step-down ratio D R , and the diode voltage difference Va'-Vb' are expressed by equations (4) and (5), respectively.

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[0034] This makes it possible to obtain a diode voltage difference Va'-Vb' that changes in proportion to temperature, and to use this diode voltage difference Va'-Vb' to correct the temperature characteristics of other circuit elements.

[0035] Also, the resistance R a1 , R a2 , R b1 and R b2 By changing the resistance value of , the step-down ratio D can be adjusted according to the input voltage range of the circuit that inputs the diode voltage difference Va'-Vb'. R can be changed.

[0036] However, due to the influence of variations in circuit elements in semiconductor integrated circuits, the voltage step-down circuit 100 does not have a perfect match between the step-down ratio when stepping down voltage Va to Va' and the step-down ratio when stepping down voltage Vb to Vb', resulting in fluctuations in the diode voltage difference Va'-Vb'.

[0037] (Voltage step-down circuit of comparative example 2) Fig. 3 is a circuit diagram for explaining the configuration of a voltage step-down circuit according to Comparative Example 2. Fig. 4 is a timing chart showing the control waveforms of the switches of the voltage step-down circuit according to Comparative Example 2. In the timing chart shown in Fig. 4, each switch is turned on when the control waveform is at a high level (High) and turned off when the control waveform is at a low level (Low). In Fig. 3, the same components as those in Fig. 2 are designated by the same reference numerals and their description will be omitted.

[0038] The voltage step-down circuit 200 of the second comparative example includes constant current sources I1 and I2, diodes D1 and D2, and capacitance step-down circuits CDIV11 and CDIV12. The capacitance step-down circuit CDIV11 includes switches SPL1, DIV1, and DIS1, and a capacitance C a1 and C b1 The capacitance step-down circuit CDIV12 includes switches SPL2, DIV2, and DIS2, and a capacitance C a2 and C b2 It is equipped with:

[0039] The switches SPL1 and DIV1 are connected in series to the node N1. a1 , C b1 and the switch DIS1 are connected in parallel to the node N1. a1 One end of the capacitor C is connected to the node between the switches SPL1 and DIV1, and the other end is connected to ground GND. b1 has one end connected to the switch DIV1 and the other end connected to the ground GND.

[0040] When the switches SPL1 and DIS1 are turned on and the switch DIV1 is turned off, the capacitance C a1 is charged to a voltage Va and has a capacitance C b1 When the switches SPL1 and DIS1 are turned off and the switch DIV1 is turned on, the charge of the capacitance C a1 is the capacity C b1 , and the stepped-down voltage Va' is output.

[0041] The switches SPL2 and DIV2 are connected in series to the node N2.a2 , C b2 and switch DIS2 are connected in parallel. a2 One end of the capacitor C is connected to the node between the switches SPL2 and DIV2, and the other end is connected to ground GND. b2 has one end connected to the switch DIV2 and the other end connected to the ground GND.

[0042] When switches SPL2 and DIS2 are turned on and switch DIV2 is turned off, the capacitance C a2 is charged to the voltage Vb, and the capacitance C b2 When the switches SPL2 and DIS2 are turned off and the switch DIV2 is turned on, the charge of the capacitance C a2 is the capacity C b2 , and the stepped-down voltage Vb' is output.

[0043] 4, the switch SPL1 is turned on / off in synchronization with the switch DIS1. The switch DIV1 is off while the switch SPL1 is on, and is on while the switch SPL1 is off.

[0044] Similarly, the switch SPL2 is turned on / off in synchronization with the switch DIS2. The switch DIV2 is turned off while the switch SPL2 is on, and is turned on while the switch SPL2 is off.

[0045] By operating the switches SPL1, DIV1, and DIS1 as shown in the waveform in Figure 4, the capacitance C a1 , C b1 In addition, by operating the switches SPL2, DIV2, and DIS2 as shown in the waveforms in Figure 4, the capacitance C a2 , C b2 This repeats charging and discharging. As a result, the voltages Va' and Vb' are expressed by equations (6) and (7), respectively.

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[0046] Here, the capacitance C a1 , C b1 , C a2 and C b2 The capacitance values ​​of all are equal (or the capacitance C a1 and C a2 and capacitance C b1 and C b2 and the step-down ratio is D C Then, the step-down ratio D C , and the diode voltage difference Va'-Vb' are expressed by equations (8) and (9), respectively.

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[0047] In this way, the voltage step-down circuit 200 of Comparative Example 2 can obtain the diode voltage difference Va'-Vb' that changes in proportion to temperature, similar to the voltage step-down circuit 100 of Comparative Example 1.

[0048] The voltage step-down circuit 200 has fewer circuit elements than the voltage step-down circuit 100, and is therefore less affected by variations in the circuit elements.

[0049] However, in the voltage step-down circuit 200, the switches SPL1, SPL2, DIV1, DIV2, DIS1, and DIS2 and the capacitance C a1 , C b1 , C a2 and C b2 Therefore, in the voltage step-down circuit 200, similar to the voltage step-down circuit 100 of Comparative Example 1, the step-down ratio when stepping down the voltage Va to Va' does not completely match the step-down ratio when stepping down the voltage Vb to Vb', and the diode voltage difference Va'-Vb' fluctuates.

[0050] In addition, even when the switch SPL1 is off, the constant current source I1 is connected to the capacitance Ca1 Similarly, even when the switch SPL2 is off, the output voltage Va' fluctuates due to the leakage current flowing from the constant current source I2 to the capacitance C a2 The leakage current flowing to the output terminal Vb' fluctuates.

[0051] (Voltage step-down circuit of this embodiment) Fig. 5 is a circuit diagram for explaining the configuration of the voltage step-down circuit of this embodiment. In Fig. 5, the same components as those in Fig. 3 are given the same reference numerals and their explanations will be omitted.

[0052] The voltage step-down circuit 20 includes a signal generating circuit 21, constant current sources I1 and I2, diodes D1 and D2, capacitive step-down circuits CDIV1, CDIV2, CDIV3, and CDIV4, switches IN1, IN2, IN3, and IN4, and switches OUT1, OUT2, OUT3, and OUT4. The voltage step-down circuit 20 is an example of a "semiconductor integrated circuit." The capacitive step-down circuits CDIV1, CDIV2, CDIV3, and CDIV4 are an example of a "plurality of step-down circuits (first step-down circuit, second step-down circuit, third step-down circuit, fourth step-down circuit)." The switches IN1, IN2, IN3, and IN4 are an example of a "plurality of input switches (first input switch, second input switch, third input switch, fourth input switch)." The switches OUT1, OUT2, OUT3, and OUT4 are an example of a "plurality of output switches (first output switch, second output switch, third output switch, fourth output switch)." The constant current sources I1 and I2 are examples of a “first constant current source” and a “second constant current source.” The diodes D1 and D2 are examples of a “first diode” and a “second diode.”

[0053] The capacitance step-down circuit CDIV1 is configured by adding a switch HLD1 to the capacitance step-down circuit CDIV11 in Fig. 3. One end of the switch HLD1 is connected to the switch DIV1, and the other end is connected to the switch OUT1.

[0054] The switch SPL1 has a capacitance C a1 The switch DIV1 controls whether to charge the capacitor C a1 Capacity C b1 The switch DIS1 is connected to the capacitor C b1 The switch HLD1 is a switch for discharging the capacitance C b1 The switch OUT1 is a switch for disconnecting the output from the output when discharging or performing a step-down operation. The switch OUT1 is a switch for controlling whether or not the stepped-down voltage Va' or Vb' is output to the node N3 or N4. The voltage Va or the voltage Vb is an example of a "first voltage" or a "second voltage." The voltage Va' or the voltage Vb' is an example of a "first step-down voltage" or a "second step-down voltage."

[0055] The capacitance step-down circuit CDIV2 is configured by adding a switch HLD2 to the capacitance step-down circuit CDIV12 in FIG. 3. One end of the switch HLD2 is connected to the switch DIV2, and the other end is connected to the switch OUT2. The switch HLD2 is connected to the capacitance C b2 The switch OUT2 is used to disconnect the output from the power supply when discharging or stepping down the voltage. The switch OUT2 controls whether the stepped-down voltage Va' or Vb' is output.

[0056] The capacitance step-down circuits CDIV3 and CDIV4 have the same configuration as the capacitance step-down circuit CDIV1. The capacitance step-down circuit CDIV3 includes switches SPL3, DIV3, DIS3, and HLD3, and a capacitance C a3 and C b3 The capacitance step-down circuit CDIV4 includes switches SPL4, DIV4, DIS4, and HLD4, and a capacitance C a4 and C b4 Like the capacitance step-down circuits CDIV1 and CDIV2, the capacitance step-down circuits CDIV3 and CDIV4 correspond to the capacitance step-down circuits CDIV11 and CDIV12 in FIG.

[0057] The switches SPL1, SPL2, SPL3, and SPL4 are examples of "first switches." a1 , C a2 , C a3 , and C a4 is an example of a "first capacitance". b1 , C b2 , C b3 , and C b4 is an example of a "second capacitance." The switches DIV1, DIV2, DIV3, and DIV4 are an example of a "second switch." The switches DIS1, DIS2, DIS3, and DIS4 are an example of a "third switch." The switches HLD1, HLD2, HLD3, and HLD4 are an example of a "fourth switch."

[0058] The switches IN1, IN2, IN3, and IN4 switch whether the inputs (input terminals) of the capacitance step-down circuits CDIV1, CDIV2, CDIV3, and CDIV4 are connected to the node N1 or the node N2. By controlling the switching of the switches IN1, IN2, IN3, and IN4, the voltage Va across the diode D1 or the voltage Vb across the diode D2 is input to the capacitance step-down circuits CDIV1, CDIV2, CDIV3, and CDIV4.

[0059] The switches OUT1, OUT2, OUT3, and OUT4 switch whether the outputs (output terminals) of the capacitance step-down circuits CDIV1, CDIV2, CDIV3, and CDIV4 are output to node N3 or node N4. By controlling the switching of the switches OUT1, OUT2, OUT3, and OUT4, the capacitance step-down circuits CDIV1, CDIV2, CDIV3, and CDIV4 output a stepped-down voltage Va' to node N3, or output a stepped-down voltage Vb' to node N4.

[0060] The signal generation circuit 21 outputs control signals for controlling the switches in the voltage step-down circuit 20. Specifically, the signal generation circuit 21 generates the control signals shown in FIG. 6 to be supplied to the switches IN1 to IN4, OUT1 to OUT4, SPL1 to SPL4, DIV1 to DIV4, DIS1 to DIS4, and HLD1 to HLD4. The signal generation circuit 21 may be configured with dedicated hardware such as an analog circuit, or may be configured with a processor using a CPU, FPGA, or the like. The signal generation circuit 21 may operate according to a program stored in a memory (not shown) to generate the control signals, or may realize some or all of its functions with a hardware analog circuit.

[0061] FIG. 6 is a timing chart showing the control waveforms of the switches in the voltage step-down circuit of this embodiment. 6, switches SPL1, DIS1, SPL3, and DIS3 are turned on / off synchronously. Similarly, switches DIV1 and DIV3 are turned on / off synchronously. Similarly, switches HLD1 and HLD3 are turned on / off synchronously.

[0062] Furthermore, the switches SPL2, DIS2, SPL4, and DIS4 are turned on / off in synchronization with each other. Similarly, the switches DIV2 and DIV4 are turned on / off in synchronization with each other. Similarly, the switches HLD2 and HLD4 are turned on / off in synchronization with each other.

[0063] When switch SPL1 is on (high level), switch SPL2 operates to be off (low level), and when switch SPL1 is off (low level), switch SPL2 operates to be on (high level). The relationships between switches DIS1 and DIS2, switches SPL3 and SPL4, and switches DIS3 and DIS4 are similar.

[0064] The switches DIV1 and DIV3 operate to turn on when the switches SPL1, DIS1, SPL3, and DIS3 are turned off. The switches HLD1 and HLD3 operate to turn on when the switches DIV1 and DIV3 are turned off.

[0065] Furthermore, the switches DIV2 and DIV4 operate to turn on when the switches SPL2, DIS2, SPL4, and DIS4 are turned off. The switches HLD2 and HLD4 operate to turn on when the switches DIV2 and DIV4 are turned off.

[0066] The switches IN1 and OUT1 for selecting the connection destination of the input and output of the capacitance step-down circuit CDIV1 and the switches IN2 and OUT2 for selecting the connection destination of the input and output of the capacitance step-down circuit CDIV2 are turned on / off in synchronization with each other.

[0067] The control signals supplied to the switches IN1, OUT1, IN2, and OUT2 are signals obtained by dividing the signal of the switch SPL1. As described above, these control signals are generated by the signal generation circuit 21. In the example of FIG. 6, the control signals are signals obtained by dividing the signal of the switch SPL1 by four. Note that the division ratio when dividing the signal of the switch SPL1 is not limited to four, but may be any ratio equal to or greater than two. Furthermore, the control signals supplied to the switches IN1, OUT1, IN2, and OUT2 may be signals obtained by dividing the signals of the switches DIS1, SPL3, and DIS3.

[0068] During periods T1 to T5 when the control signals supplied to the switches IN1, OUT1, IN2, and OUT2 are at high level, the inputs of the capacitive step-down circuits CDIV1 and CDIV2 are connected to voltage Va, and the outputs are connected to voltage Va'.

[0069] On the other hand, during the period T5 to T9 when the control signals supplied to the switches IN1, OUT1, IN2, and OUT2 are at a low level, the inputs of the capacitance step-down circuits CDIV1 and CDIV2 are connected to the voltage Vb, and the outputs are connected to the voltage Vb'.

[0070] The switches IN3 and OUT3 for selecting the connection destination of the input and output of the capacitance step-down circuit CDIV3 and the switches IN4 and OUT4 for selecting the connection destination of the input and output of the capacitance step-down circuit CDIV4 are turned on / off in synchronization with each other.

[0071] The control signals supplied to the switches IN3, OUT3, IN4, and OUT4 have the inverted logic of the control signals supplied to the switches IN1, OUT1, IN2, and OUT2. That is, the control signals supplied to the switches IN3, OUT3, IN4, and OUT4 are at low level while the control signals supplied to the switches IN1, OUT1, IN2, and OUT2 are at high level, and are at high level while the control signals are at low level.

[0072] During periods T1 to T5 when the control signals supplied to the switches IN3, OUT3, IN4, and OUT4 are at low level, the inputs of the capacitive step-down circuits CDIV3 and CDIV4 are connected to the voltage Vb, and the outputs are connected to the voltage Vb'.

[0073] On the other hand, during the period T5 to T9 when the control signals supplied to the switches IN3, OUT3, IN4, and OUT4 are at high level, the inputs of the capacitive step-down circuits CDIV3 and CDIV4 are connected to voltage Va, and the outputs are connected to voltage Va'.

[0074] In this way, the voltage step-down circuit 20 steps down the voltage Va across the diode D1 (or the voltage Vb across the diode D2) using the capacitance step-down circuits CDIV1 and CDIV2 as one pair and the capacitance step-down circuits CDIV3 and CDIV4 as one pair.

[0075] Specifically, in the period T1 to T1b, the switches SPL1 and DIS1 of the capacitance step-down circuit CDIV1 are turned on. In this period T1 to T1b, the capacitance step-down circuit CDIV1 reduces the capacitance C a1 and the capacity C b1 is discharging.

[0076] During this period, in the period T1 to T1a, the switch DIV2 of the capacitance step-down circuit CDIV2 is turned on, and the capacitance C a2 is the capacity C b2 Then, in a period T1a to T1b, the switch HLD2 is turned on, and the capacitive step-down circuit CDIV2 outputs a voltage Va' obtained by stepping down the voltage Va.

[0077] On the other hand, during the period T1b to T2, the switches SPL2 and DIS2 of the capacitance step-down circuit CDIV2 are turned on. During this period T1b to T2, the capacitance step-down circuit CDIV2 reduces the capacitance C a2 and the capacity C b2 is discharging.

[0078] During this period, in the period from T1b to T1c, the switch DIV1 of the capacitance step-down circuit CDIV1 is turned on, and the capacitance C a1 is the capacity C b1 Then, in the period T1c to T2, the switch HLD1 is turned on, and the capacitive step-down circuit CDIV1 outputs a voltage Va' obtained by stepping down the voltage Va.

[0079] That is, by alternately operating the capacitance step-down circuits CDIV1 and CDIV2 as a pair, the capacitance C a1 and the capacitance C of the capacitance step-down circuit CDIV2 a2 will be charged.

[0080] As a result, the voltage step-down circuit 20 of this embodiment can reduce fluctuations in output voltage (Va', Vb') due to leakage current, compared to the voltage step-down circuit 200 of the second comparative example.

[0081] Furthermore, by operating switches IN1-IN4 and switches OUT1-OUT4 with the switch control waveforms shown in Fig. 6, it is possible to periodically switch between the capacitance step-down circuit CDIV that steps down the voltage Va across diode D1 and the capacitance step-down circuit CDIV that steps down the voltage Vb across diode D2. In the example of Fig. 6, during periods T1-T5, the pair of capacitance step-down circuits CDIV1 and CDIV2 steps down the voltage Va, and the pair of capacitance step-down circuits CDIV3 and CDIV4 steps down the voltage Vb. Meanwhile, during periods T5-T9, the pair of capacitance step-down circuits CDIV1 and CDIV2 steps down the voltage Vb, and the pair of capacitance step-down circuits CDIV3 and CDIV4 steps down the voltage Va.

[0082] By controlling the switches IN1 to IN4 and the switches OUT1 to OUT4 in this manner, fluctuations in the output voltages (Va', Vb') due to variations in the circuit elements constituting the capacitance step-down circuits CDIV1 and CDIV2 and the circuit elements constituting the capacitance step-down circuits CDIV3 and CDIV4 can be averaged out.

[0083] As a result, the voltage step-down circuit 20 of this embodiment can reduce fluctuations in output voltage due to variations in circuit elements compared to the voltage step-down circuit 200 of Comparative Example 2. Therefore, the voltage step-down circuit 20 of this embodiment can obtain a step-down voltage with little fluctuation due to variations in circuit elements.

[0084] (Second embodiment) Next, a second embodiment will be described.

[0085] 7 is a circuit diagram for explaining the configuration of a current generating circuit 30. Voltages Va' and Vb', which are output voltages of the voltage step-down circuit 20, are input to the current generating circuit 30 shown in FIG.

[0086] The current generating circuit 30 includes PMOS transistors MPB1, MPB2, MPB3, MPOUT, MP11, MP12, MP13, and P14, NMOS transistors MNB1, MNB2, and MNB3, and a resistor R.

[0087] A bias voltage Vbias is input to the gates of the PMOS transistors MPB1, MPB2, and MPB3. Voltages Va' and Vb', which are the output voltages of the voltage step-down circuit 20, are input to the gates of the PMOS transistors MP11 and MP12.

[0088] The reference voltage VREF is input to the gate of the PMOS transistor MP13. The gate of the PMOS transistor MPOUT is connected to the drain of the PMOS transistor MPB3. The feedback voltage VFB is input to the gate of the PMOS transistor MP14.

[0089] The drain of the PMOS transistor MPOUT is connected to a resistor R, and the feedback voltage VFB applied to the resistor R is given by equation (10).

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[0090] Here, the step-down ratio of the capacitance step-down circuits CDIV1, CDIV2, CDIV3, and CDIV4 in Figure 5 is D SC Then, from the above-mentioned equation (9), the diode voltage difference Va'-Vb' is given by equation (11).

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[0091] As a result, the output current Iout is expressed by equation (12) based on equations (10) and (11).

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[0092] As a result, the current generating circuit 30 of this embodiment can obtain an output current with temperature characteristics. The current generating circuit 30 of this embodiment can obtain an output current with temperature characteristics with a step-down ratio D SCThis makes it possible to reduce the influence of temperature on the output current Iout compared to the circuit configuration in Figure 5, thereby obtaining an output current Iout for highly accurate temperature characteristic correction. By inputting this output current Iout to another circuit, it is possible to achieve control that eliminates the temperature dependency of the other circuit as the input destination.

[0093] Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0094] 1...memory system, 2...non-volatile memory, 3...memory controller, 4...host device, 10...host I / F circuit, 11...processor, 12...RAM, 13...buffer memory, 14...memory I / F circuit, 15...ECC circuit, 16...analog circuit, 20...voltage step-down circuit, 21...signal generation circuit, 30...current generation circuit

Claims

1. a plurality of step-down circuits that step down an input first voltage or a second voltage and output a first step-down voltage or a second step-down voltage; a plurality of input switches, each of which is provided at an input terminal of the plurality of step-down circuits and which switches between the input of the first voltage or the second voltage; a plurality of output switches, each of which is provided at an output terminal of the plurality of step-down circuits and which switches between the output of the first step-down voltage or the second step-down voltage; A semiconductor integrated circuit comprising:

2. the plurality of step-down circuits include first, second, third and fourth step-down circuits, the plurality of input switches include first, second, third and fourth input switches; the plurality of output switches include first, second, third and fourth output switches; the first input switch, the second input switch, the first output switch, and the second output switch switch their connections in synchronization with one another; The semiconductor integrated circuit according to claim 1 , wherein the third input switch, the fourth input switch, the third output switch, and the fourth output switch switch their connections in synchronization with one another.

3. 3. The semiconductor integrated circuit according to claim 2, wherein the first, second, third, and fourth step-down circuits each include a first switch that controls charging of the first voltage or the second voltage, a first capacitor that charges with the first voltage or the second voltage, a second capacitor that steps down the voltage by being connected in parallel with the charged first capacitor, a second switch that connects the first capacitor and the second capacitor and controls step-down to the first step-down voltage or the second step-down voltage, a third switch that discharges the charge of the second capacitor, and a fourth switch that controls isolation of the second capacitor from an output when discharging the second capacitor or performing a step-down operation.

4. a signal generating circuit that generates and outputs a control signal for controlling the plurality of input switches; 4. The semiconductor integrated circuit according to claim 3, wherein the control signal is a signal obtained by dividing a frequency of a control signal supplied to the first switch provided in each of the plurality of step-down circuits.

5. the first switch of the first step-down circuit and the first switch of the third step-down circuit are turned on / off in synchronization with each other; 4. The semiconductor integrated circuit according to claim 3, wherein the first switch of the second step-down circuit and the first switch of the fourth step-down circuit are turned on / off in synchronization with each other.

6. the first voltage is a voltage applied to a first diode having one end connected to a first constant current source; 2. The semiconductor integrated circuit according to claim 1, wherein the second voltage is a voltage applied to a second diode having one end connected to a second constant current source and connected in parallel to the first diode.

7. 4. The semiconductor integrated circuit according to claim 3, wherein an output current having a temperature characteristic is generated based on the first step-down voltage or the second step-down voltage, and the generated output current is input to another circuit, thereby enabling control to eliminate temperature dependency in the other circuit.

8. a semiconductor integrated circuit according to claim 1; a control circuit for controlling writing and reading of the semiconductor memory device; A memory controller having

9. A control method for a semiconductor integrated circuit including: a plurality of step-down circuits that step down an input first voltage or a second voltage and output a first step-down voltage or a second step-down voltage; a plurality of input switches that are respectively provided at input terminals of the plurality of step-down circuits and switch between the input of the first voltage or the second voltage; and a plurality of output switches that are respectively provided at output terminals of the plurality of step-down circuits and switch between the output of the first step-down voltage or the second step-down voltage, the plurality of step-down circuits include first, second, third and fourth step-down circuits, the plurality of input switches include first, second, third and fourth input switches; the plurality of output switches include first, second, third and fourth output switches; the first input switch, the second input switch, the first output switch, and the second output switch switch their connections in synchronization with one another; A control method for a semiconductor integrated circuit, wherein the third input switch, the fourth input switch, the third output switch, and the fourth output switch switch their connections in synchronization with one another.

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