Recording element substrate, recording head, and recording device

Abstract

To enable both suppression of peak current and achievement of high-speed recording.SOLUTION: A recording element substrate comprises: a plurality of first recording elements; a plurality of second recording elements; a plurality of first driving elements for driving the plurality of first recording elements; a plurality of second driving elements for driving the plurality of second recording elements; a drive signal generation circuit that generates a first drive signal and a second drive signal; and a drive signal selection circuit that selects both or either of the first drive signal and second drive signal on the basis of an operation switching signal supplied from the outside. At least one first driving element and at least one second driving element operate on the basis of the drive signal selected by the drive signal selection circuit.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a printing element substrate, a printing head, and a printing apparatus. [Background technology]

[0002] One known method for driving an inkjet printhead (hereinafter also referred to as a "printhead") is to provide electrothermal conversion elements (heaters) as printing elements in communication with the nozzles that eject ink droplets, and to supply current to the heaters to generate heat and eject ink droplets through film boiling of the ink. Each heater is connected to a switching element, and current flows through the heater when the switching element is turned on in accordance with data. To drive multiple heaters provided corresponding to multiple nozzles arranged in a row, a method is generally used in which the multiple heaters are divided into multiple blocks and the heaters in each block are driven in a time-division manner. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-235531 [Patent Document 2] Japanese Patent Application Publication No. 2020-189448 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, the number of printing elements within a printing element substrate has been increasing in line with the trend toward higher image quality and faster printing speeds. This has led to challenges in supplying power to printing element substrates equipped with a large number of printing elements to be driven. To suppress the peak value of the current flowing through the printing element substrate, some printing element substrates are configured to shift the timing at which multiple printing elements are driven within a time-division block period. Patent Document 1 discloses a circuit that generates drive signals within the printing element substrate to suppress an increase in the number of terminals for electrically connecting the printing element substrate to the printing device. Patent Document 2 also discloses a configuration in which a single element drive signal generation circuit generates multiple drive signals with different timings to suppress the peak value of current while reducing the number of terminals and circuit size. However, supplying multiple drive signals to separate series of printing elements in a time-division manner increases the time required for printing in proportion to the number of time divisions, making high-speed printing impossible.

[0005] The present disclosure has been made in view of the above-mentioned problems, and aims to make it possible to suppress peak current and to support high-speed recording. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a recording element substrate comprising a plurality of first recording elements, a plurality of second recording elements, a plurality of first drive elements for driving the plurality of first recording elements, a plurality of second drive elements for driving the plurality of second recording elements, a drive signal generation circuit that generates a first drive signal and a second drive signal, and a drive signal selection circuit that selects both or either of the first drive signal and the second drive signal based on an operation switching signal supplied from the outside, wherein at least one first drive element and at least one second drive element operate based on the drive signal selected by the drive signal selection circuit. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to suppress peak current and support high-speed recording. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view showing an example of an external configuration of an inkjet recording apparatus according to an embodiment of the present disclosure. [Figure 2] An example of the functional configuration of the recording device shown in FIG. [Figure 3] Circuit configuration diagram of a print element substrate according to the first embodiment [Figure 4] Configuration example of a drive signal selection circuit according to the first embodiment [Figure 5] 10 is a timing chart showing a first operation of the recording element substrate according to the first embodiment; [Figure 6] 10 is a timing chart showing a second operation of the recording element substrate according to the first embodiment; [Figure 7] 10 is a timing chart showing a third operation of the recording element substrate according to the first embodiment; [Figure 8] Circuit configuration diagram of a recording element substrate according to a second embodiment [Figure 9] Configuration example of a drive signal selection circuit according to the second embodiment [Figure 10] 10 is a timing chart showing the operation of the printing element substrate according to the second embodiment; [Figure 11] Circuit configuration diagram of a print element substrate according to a third embodiment [Figure 12] 10 is a timing chart showing the operation of the printing element substrate according to the third embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the disclosure according to the claims. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the disclosure, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations may be omitted.

[0010] [Recording device overview] FIG. 1 is an external perspective view showing the outline of the configuration of a printing apparatus that performs printing using an inkjet print head (hereinafter, print head) that is a representative embodiment of the present disclosure.

[0011] As shown in Figure 1, an inkjet recording device (hereinafter referred to as "recording device") 100 has an inkjet recording head (hereinafter referred to as "recording head") 103 mounted on a carriage 102, which performs recording by ejecting ink according to an inkjet method. Recording is performed by moving the carriage 102 back and forth in the direction of arrow A. A recording medium P, such as recording paper, is fed via a paper feed mechanism 105 and transported to a recording position, where ink is ejected from the recording head 103 onto the recording medium P, thereby performing recording.

[0012] The carriage 102 of the printing apparatus 100 not only carries the print head 103 but also has an ink tank 106 that stores ink to be supplied to the print head 103. The ink tank 106 is detachable from the carriage 102.

[0013] 1 is capable of color printing, and for that purpose, four ink cartridges containing magenta (M), cyan (C), yellow (Y), and black (K) ink are mounted on the carriage 102. Each of these four ink cartridges can be attached and detached independently.

[0014] The print head 103 of this embodiment employs an inkjet system that uses thermal energy to eject ink. To this end, it is equipped with printing elements (heaters). These printing elements are provided corresponding to each ejection port, and ink is ejected from the corresponding ejection port by applying a pulse voltage to the corresponding printing element in response to a print signal. The printing apparatus is not limited to the serial type printing apparatus described above, but can also be applied to a so-called full-line type printing apparatus in which a print head (line head) with ejection ports arranged in the width direction of the print medium is arranged in the print medium transport direction.

[0015] FIG. 2 is a block diagram showing the control configuration of the recording apparatus 100 shown in FIG.

[0016] As shown in FIG. 2, the controller 200 includes an MPU 201, a ROM 202, an application-specific integrated circuit (ASIC) 203, a RAM 204, a system bus 205, and an A / D converter 206. The ROM 202 stores programs, necessary tables, and other fixed data for controlling the entire printing apparatus 100 by the MPU 201. The ASIC 203 generates control signals for controlling the carriage motor M1, the transport motor M2, and the print head 103. The RAM 204 is used as an area for storing image data and as a working area for executing programs. The system bus 205 interconnects the MPU 201, the ASIC 203, and the RAM 204 to exchange data. The A / D converter 206 receives analog signals from a group of sensors (described below), A / D converts them, and supplies the digital signals to the MPU 201.

[0017] 2, reference numeral 210 denotes a host device such as a personal computer that serves as a supply source of image data. Image data, commands, status, etc. are transmitted and received by packet communication between the host device 210 and the recording device 1 via an interface (I / F) 211. Note that a USB interface may also be provided as the interface 211 in addition to the network interface, so that the recording device 100 can receive bit data and raster data serially transferred from the host device 210.

[0018] Furthermore, reference numeral 220 denotes a group of switches, which includes a power switch 221 , a print switch 222 , and a recovery switch 223 .

[0019] Reference numeral 230 denotes a group of sensors for detecting the device status, and includes a position sensor 231 and a temperature sensor 232. In this embodiment, a photosensor for detecting the remaining amount of ink may also be provided. Furthermore, reference numeral 240 denotes a carriage motor driver that drives a carriage motor M1 for causing the carriage 102 to scan back and forth in the direction of arrow A, and 242 denotes a transport motor driver that drives a transport motor M2 for transporting the recording medium P.

[0020] During print scanning by the print head 103, the ASIC 203 directly accesses the storage area of ​​the RAM 204 and transfers data for driving print elements (heaters for ejecting ink) to the print head 103. In addition, although not shown, the printing apparatus 100 is provided with a display unit configured with an LCD and LED as a user interface.

[0021] [First embodiment] Fig. 3 is a circuit configuration diagram of a recording element substrate according to the first embodiment. As shown in Fig. 3, a recording element substrate 300 is provided with LVDS receivers 301a and 301b, an operational amplifier (OP amp) 302, and a data development circuit 309. The recording element substrate 300 is also provided with a drive signal generation circuit 310, a drive signal selection circuit 311, and heater array circuits 320A and 320B.

[0022] The printing element substrate 300 receives serial signals from the controller of the printing apparatus 100 using the LVDS system. The LVDS receiver 301a receives serial signals (DATA+, DATA-) through input terminals 303 and 304 and outputs an internal data signal "data." The LVDS receiver 301b receives clock signals (CLK+, CLK-) through input terminals 305 and 306 and outputs an internal clock signal "clk." A latch signal (LT) is received as a normal serial signal through input terminal 307, which is amplified by operational amplifier 302 and output as a latch signal "lt."

[0023] The internal data signal data is supplied to the data expansion circuit 309. The internal clock signal clk is supplied to the data expansion circuit 309 and the drive signal generation circuit 310. The latch signal lt is supplied to the data expansion circuit 309, heater array circuits 320A and 320B, and the drive signal generation circuit 310.

[0024] The data expansion circuit 309 expands the internal clock signal clk and the internal data signal data by type and distributes and transfers them to the heater array circuits 320A and 320B, the drive signal generation circuit 310, and the drive signal selection circuit 311. Specifically, the data expansion circuit 309 transfers the signals hd_clk and hd_data to the serial-parallel conversion circuit 308 included in the heater array circuit 320A. The data expansion circuit 309 also transfers the signals hd_clk and hd_data to the serial-parallel conversion circuit 308 included in the heater array circuit 320B. Note that the data hd_data transferred to the serial-parallel conversion circuit 308 of the heater array circuit 320A is generally different from the data hd_data transferred to the serial-parallel conversion circuit 308 of the heater array circuit 320B. The data expansion circuit 309 also transfers the clock signal he_clk and the common pattern designation signal he_data to the drive signal generation circuit 310. Furthermore, the data development circuit 309 transfers the operation switching signal sel to the drive signal selection circuit 311 .

[0025] The drive signal generation circuit 310 generates two pre-selection drive signals he1 and he2 based on the supplied internal clock signal clk, clock signal he_clk, common pattern designation signal he_data, and latch signal lt. The drive signal generation circuit 310 is similar to the drive signal generation circuit described in Patent Document 2. Briefly, the drive signal generation circuit 310 performs serial-to-parallel conversion of the input common pattern designation signal he_data using the input clock signal he_clk, using an internal shift register. The drive signal generation circuit 310 generates the pre-selection drive signals he1 and he2 using multiple internal counters and combinational circuits based on the rising and falling edges of the pre-selection drive signals he1 and he2 designated by the common pattern designation signal he_data. The pre-selection drive signals he1 and he2 generated by the drive signal generation circuit 310 are, for example, as shown in FIG. 5. As shown in FIG. 5, the pre-selection drive signal he1 is a double-pulse signal that intermittently reaches a high level (active level) twice during the first portion of each block period 501. Furthermore, the pre-selection drive signal he2 is a double-pulse signal that intermittently reaches a high level (effective level) twice in the second portion following the first portion of each block period 501. As described in Patent Document 2, the drive signal generation circuit 310 repeats the same operation twice in one block period. Therefore, the shape of the double-pulse pattern of the pre-selection drive signal he1 and the shape of the double-pulse pattern of the pre-selection drive signal he2 are mutually identical.

[0026] The drive signal selection circuit 311 selects either the pre-selection drive signal he1 or the pre-selection drive signal he2 as the post-selection drive signal he_a in accordance with the operation mode specified by the operation switching signal sel. However, in the first embodiment, the drive signal selection circuit 311 may always select the pre-selection drive signal he1 as the post-selection drive signal he_a. Alternatively, the drive signal selection circuit 311 may select either the pre-selection drive signal he1 or the pre-selection drive signal he2 as the post-selection drive signal he_b in accordance with the operation mode specified by the operation switching signal sel. The drive signal selection circuit 311 then supplies the post-selection drive signal he_a to a plurality of control circuits 321 included in the heater array circuit 320A, and supplies the post-selection drive signal he_b to a plurality of control circuits 321 included in the heater array circuit 320B.

[0027] The heater array circuit 320 includes multiple printing elements (heaters) 323 that heat and eject ink in the nozzles they are responsible for, and multiple driving elements (driver transistors) 322 that drive each of the printing elements 323. The driving elements 322 are typically transistors such as MOSFETs. The heater array circuit 320 also includes a serial-to-parallel conversion circuit 308. The serial-to-parallel conversion circuit 308 includes a shift register (not shown) that includes multiple flip-flop circuits connected in series, and multiple latch circuits (not shown) that correspond to each of the multiple flip-flop circuits. The shift register shifts the signal hd_data in response to a clock signal hd_clk. Each of the multiple latch circuits latches the output of the corresponding flip-flop circuit in the shift register as an element selection signal in response to a signal lt. The heater array circuit 320 also includes multiple control circuits 321 that perform a logical AND operation on the element selection signal supplied from each of the multiple latches (not shown) in the serial-to-parallel conversion circuit 308 and the post-selection drive signal (described below) supplied from the drive signal selection circuit 311. Here, the control circuit 321 is a logic circuit, and in this case, an AND circuit. Therefore, when the input element selection signal becomes an active level and the input post-selection drive signal becomes an active level, the control circuit 321 activates the corresponding drive element 322, thereby driving the corresponding recording element 323. Here, if the control circuit 321 is an AND circuit, the active level is a HIGH level. Also, if the drive element 322 is a transistor, activating the drive element 322 means that it is in a conductive state.

[0028] In the example shown in FIG. 3, heater array circuits 320A and 320B are mounted on the printing element substrate 300 as the heater array circuit 320. The heater array circuit 320B has the same internal configuration as the heater array circuit 320A. Therefore, the printing element substrate 300 includes a plurality of printing elements 323 belonging to array A, a plurality of driving elements (driver transistors) 322, a plurality of control circuits 321, and a serial-parallel conversion circuit 308. The printing element substrate 300 also includes a plurality of printing elements 323 belonging to array B, a plurality of driving elements (driver transistors) 322, a plurality of control circuits 321, and a serial-parallel conversion circuit 308. The number of heater array circuits is not limited to two and may be more. For example, a heater array circuit 320C and a heater array circuit 320D may be added. In this case, the heater array circuits 320C and 320D may be supplied with individual signals hd_clk, hd_data, and lt from the data development circuit 309. Furthermore, the heater array circuit 320C may be supplied with a post-selection drive signal he_a, and the heater array circuit 320D may be supplied with a post-selection drive signal he_b.

[0029] 5 is a timing chart showing a first operation of the recording element substrate 300 according to the first embodiment. Here, an example is shown in which a plurality of driving elements 322 corresponding to a plurality of recording elements 323 are divided into 16 blocks (blocks 0 to 15), and the plurality of recording elements 323 are driven in a time-division manner by the divided driving elements 322.

[0030] As shown in FIG. 5, in time-division driving, data transfer for block_(n+1) and driving of the printing elements 323 of block_n are performed simultaneously within each block period 501. Specifically, during each block period 501, differential signals DATA+ and DATA- are transferred from the main body of the printing device 100 in synchronization with differential signals CLK+ and CLK-. These differential signals are converted by LVDS receivers 301a and 301b (FIG. 3) into single-ended internal clock signals clk and internal data signals data, respectively, and transferred to the data development circuit 309. The data development circuit 309 further develops the internal clock signals clk and internal data signals data by type and distributes and transfers them to the heater array circuits 320A and 320B, the drive signal generation circuit 310, and the drive signal selection circuit 311. Specifically, the data development circuit 309 transmits hd_clk and hd_data for column A to the shift register 308 of the heater array circuit 320A. The data expansion circuit 309 also transmits hd_clk and hd_data for column B to the shift register 308 of the heater array circuit 320B. Furthermore, the data expansion circuit 309 transmits a clock signal he_clk and a common pattern designation signal he_data to the shift register of the drive signal generation circuit 310. Furthermore, the data expansion circuit 309 transmits an operation switching signal sel to the drive signal selection circuit 311.

[0031] On the other hand, the latch signal LT307, which generates a latch pulse for each block period 501, is amplified by the operational amplifier 302 and transferred as an internal signal lt to a plurality of circuits provided on the recording element substrate 300. The plurality of circuits to which the signal is transferred include a data expansion circuit 309, a drive signal generation circuit 310, and a latch circuit in the serial-parallel conversion circuit 308 of the heater array circuit 320A, and a latch circuit in the serial-parallel conversion circuit 308 of the heater array circuit 320B.

[0032] A latch pulse for the lt signal is generated at the beginning of the next block period 501. At the rising edge of the latch pulse, the internal signal hd_data transferred to the serial-parallel conversion circuit 308 of the heater array circuit 320A during the previous block period 501 is stored as a first element selection signal in the latch circuit within the serial-parallel conversion circuit 308. This selects the printing element 323 in row A to be driven. There are the same number of printing elements 323, driving elements 322, control circuits 321, and latch circuits within the serial-parallel conversion circuit 308, and each printing element 323, driving element 322, control circuit 321, and latch circuit within the serial-parallel conversion circuit 308 is associated with each other. For example, only the element selection signal output by one latch circuit goes to a high level (effective level), and when the post-selection drive signal he_a goes to a high level (effective level), the corresponding driving element 322 drives the corresponding printing element 323.

[0033] The heater array circuit B operates in a similar manner. Therefore, for example, only the element selection signal output by one latch circuit in array B becomes a high level (effective level). Then, at the timing when the post-selection drive signal he_b becomes a high level (effective level), the corresponding drive element 322 drives the corresponding print element 323.

[0034] The element selection signal latched in the latch circuit is maintained until the next latch pulse is generated, and is updated by the next latch pulse.

[0035] Although the explanation will be partially redundant, the data transmitted from the outside includes an operation switching signal sel for specifying which pre-selection drive signal is to be selected as the post-selection drive signal. The operation switching signal sel is expanded by the data expansion circuit 309 and transmitted to the drive signal selection circuit 311.

[0036] Fig. 4 shows an example of the configuration of a drive signal selection circuit according to this embodiment. The drive signal selection circuit shown in Fig. 4 includes a logical AND gate 401 that takes the logical AND of he1 and sel, and a logical inversion gate 403 that logically inverts sel.

[0037] The drive signal selection circuit further includes a logical AND gate 402 which takes the logical AND of he2 and the logically inverted sel, and a logical OR gate 404 which takes the logical OR of the output of the logical AND gate 401 and the output of the logical AND gate 402.

[0038] From Figure 4, he_a = he1 he_b = sel·he1+!sel·he2 where: indicates logical inversion.

[0039] Therefore, the first pre-selection drive signal he1 (one of the first pre-selection drive signal he_1 and the second pre-selection drive signal he2) is always used as the first post-selection drive signal he_a. Furthermore, when the operation switching signal sel is at a LOW level and the first operation mode is specified, the second pre-selection drive signal he2 (the other of the first pre-selection drive signal he_1 and the second pre-selection drive signal he2) is used as the second post-selection drive signal he_b. Furthermore, when the operation switching signal sel is at a HIGH level and the second operation mode is specified, the first pre-selection drive signal he1 (one of the first pre-selection drive signal he_1 and the second pre-selection drive signal he2) is used as the second post-selection drive signal he_b.

[0040] Therefore, when the operation switching signal sel is at a low level and the first operating mode is specified, the relationship shown in FIG. 5 is satisfied. That is, the relationship between the first pre-selection drive signal he1, the second pre-selection drive signal he2, the first post-selection drive signal he_a, and the second post-selection drive signal he_b is as shown in FIG. 5. As is clear from FIG. 5, the first post-selection drive signal he_a has a double pulse in the initial portion of each block period 501, and the second post-selection drive signal he_b has a double pulse in the subsequent portion. This prevents overlap between the timing of driving the print elements 323 in row A and the timing of driving the print elements 323 in row B, thereby suppressing peak current and reducing voltage drops. This results in higher image quality. In particular, the first operating mode is suitable for the high-image-quality mode because the number of shots (e.g., the number of print elements to be driven) is large in the high-image-quality mode.

[0041] When the operation switching signal sel is at a HIGH level and the second operation mode is specified, the relationship between the first pre-selection drive signal he1, the second pre-selection drive signal he2, the first post-selection drive signal he_a, and the second post-selection drive signal he_b is as shown in Figure 6. As is clear from Figure 6, the first post-selection drive signal he_a has a double pulse in the initial part of each block period 501, and the second post-selection drive signal he_b has a double pulse in the same part (i.e., at the same timing). Note that the length of the block period 501 shown in Figure 5 is the same as the length of the block period 601 shown in Figure 6.

[0042] Fig. 7 is a timing diagram in which the block period is shorter than that shown in Fig. 6. The block period 701 shown in Fig. 7 is about half the length of the block period 601 shown in Fig. 6. Note that, also in the case shown in Fig. 7, the operation switching signal sel is at a HIGH level, and the second operation mode is specified.

[0043] As shown in FIG. 7, by specifying the second operating mode as the operating mode, the printing elements 323 in row A and the printing elements 323 in row B can be driven even if the block period is shortened. Therefore, printing time can be shortened. Compared to the case of FIG. 6, the length of the block period in the case of FIG. 7 is approximately half, so printing time can be shortened by approximately half. Note that the block period 701 is set so that the data transfer required for one block can be completed in each block period 701. Therefore, as long as the post-selection drive signals he_a and he_b are not dropped and the data transfer required for one block can be completed in each block period 701, the block period can be further shortened. Although the second operating mode may result in lower image quality compared to the first operating mode, it is suitable for shortening printing time. Printing time can be further shortened by changing the common pattern designation signal he_data to shorten the pulse length of the first pre-selection drive signal he1 (and therefore the first post-selection drive signal he_a and the second post-selection drive signal he_b).

[0044] According to this embodiment, the first operating mode and the second operating mode can be switched depending on whether high image quality or short printing time is prioritized. For example, if the user selects high-quality printing, the first operating mode can be selected, and if the user selects high-speed printing, the second operating mode can be selected. In addition, the first operating mode and the second operating mode can be switched depending on the type of recording medium to be printed on.

[0045] Furthermore, according to this embodiment, the drive signal generation circuit 310 that generates two drive signals with a small circuit scale can be used as is. Also, only one drive signal selection circuit 311 is required, and the number of gates is small. Therefore, according to this embodiment, the circuit scale can be reduced.

[0046] In the above-described configuration, the operation switching signal sel is supplied from the outside to the drive signal selection circuit 311 via the terminals 303 and 304, the receiver 301a, and the data expansion circuit 309. However, this is not limitative, and the operation switching signal sel may be supplied from the outside to the drive signal selection circuit 311 via a terminal and wiring (not shown).

[0047] The post-selection drive signal supplied to the heater array circuit 320 may be delayed for each drive element 322 within the heater array circuit 320. For this purpose, for example, if multiple print elements 323 are selected in the same heater array circuit 320, a delay element may be inserted in the drive signal wiring between the right-hand input terminals of the AND gates that function as two adjacent control circuits 321 in the heater array circuit 320. Furthermore, if a common post-selection drive signal is used by multiple heater array circuits 320, the post-selection drive signals may be time-shifted between the multiple heater array circuits 320. For this purpose, for example, a delay element may be added that delays the post-selection drive signal supplied to the heater array circuit 320A by a first delay time. Alternatively, a delay element may be added that delays the post-selection drive signal supplied to the heater array circuit 320B by a second delay time, or both delay elements may be added. Furthermore, for example, delaying the drive signal for each time division unit can prevent sudden voltage fluctuations caused by simultaneously turning on and off drive elements.

[0048] [Second embodiment] Fig. 8 is a circuit configuration diagram of a recording element substrate according to the second embodiment. In Fig. 8, the same components as those already explained with reference to the drawings are given the same reference numerals, and duplicate explanations will be omitted.

[0049] As shown in FIG. 8, the data development circuit 309 transmits 2-bit operation switching signals sel0 and sel1 to the drive signal selection circuit 311.

[0050] FIG. 9 shows an example configuration of a drive signal selection circuit according to the second embodiment. The drive signal selection circuit shown in FIG. 9 includes an AND gate 901 that takes the logical AND of he1 and sel1, and an inverting logic gate 903 that logically inverts sel1. The drive signal selection circuit shown in FIG. 9 also includes an AND gate 902 that takes the logical AND of he2 and the logically inverted sel1, and an OR gate 904 that takes the logical OR of the output of AND gate 901 and the output of AND gate 902. The drive signal selection circuit shown in FIG. 9 also includes an exclusive OR gate 905 that takes the exclusive OR of sel0 and sel1, and an AND gate 906 that takes the logical AND of he2 and the output of exclusive OR gate 905. The drive signal selection circuit shown in FIG. 9 also includes an inverting logic gate 908 that logically inverts the output of exclusive OR gate 905, and an AND gate 907 that takes the logical AND of he1 and the output of logic inverting gate 908. Furthermore, the drive signal selection circuit shown in FIG. 9 includes an OR gate 909 that takes the logical sum of the output of AND gate 906 and the output of AND gate 907 .

[0051] From Figure 9, he_a = !sel1·he1 + sel1·he2 he_b = (sel1*sel0)·he1 +!(sel1*sel0)·he2 where: indicates logical inversion, and * indicates logical exclusive or.

[0052] Therefore, if sel0=LOW, he_a = !sel1·he1+ sel1·he2 he_b = sel1·he1+!sel1·he2 Also, when sel0=HIGH, he_a = !sel1·he1+ sel1·he2 he_b = !sel1·he1+ sel1·he2 is.

[0053] Therefore, When sel0=LOW and sel1=LOW, he_a = he1 he_b = he2 which corresponds to the first operation mode of the first embodiment.

[0054] Also, if sel0=HIGH and sel1=LOW, he_a = he1 he_b = he1 which corresponds to the second operation mode of the first embodiment.

[0055] A duplicated description of the first and second operation modes will be omitted.

[0056] In the second embodiment, the following combinations are newly added.

[0057] When sel0=LOW and sel1=HIGH, he_a = he2 he_b = he1 This will be called the third operating mode.

[0058] If sel0=HIGH and sel1=HIGH, he_a = he2 he_b = he2 This will be called the fourth operating mode.

[0059] The first post-selection drive signal and the second post-selection drive signal in the third operation mode are obtained by swapping the first post-selection drive signal and the second drive signal compared to the first operation mode. Therefore, if the first operation mode and the third operation mode are alternately repeated for each block period as shown in Figure 10, the first post-selection drive signal and the second post-selection drive signal will be as follows: That is, block periods in which the first post-selection drive signal has a double pulse before the second post-selection drive signal, and block periods in which this order is reversed, are alternately repeated. However, as shown in the figure, this assumes that the first pre-selection drive signal has a double pulse in the initial part of each block period, and the second pre-selection drive signal has a double pulse in the subsequent part.

[0060] If only the first operating mode is selected and ink is continuously ejected using the same nozzles in the same block period, the voltage fluctuations may be dependent on the location of the nozzles, resulting in uneven printing.In contrast, if the operating mode is switched so that the first operating mode and the third operating mode are alternately repeated every block period, it is possible to suppress such uneven printing.

[0061] Next, the fourth operating mode will be described. The second pre-selection drive signal he2 is selected as the first post-selection drive signal he_a, and the second pre-selection drive signal he2 is also selected as the second post-selection drive signal he_b. Here, in each block period 1001, the double pulse of the second pre-selection drive signal he2 occurs later than the double pulse of the first pre-selection drive signal he1, as shown in FIG. 10. Therefore, the first post-selection drive signal he_a and the second post-selection drive signal he_b maintain a low level during the period in which the double pulse of the first pre-selection drive signal he1 occurs. Thereafter, the double pulses of the first post-selection drive signal he_a and the second post-selection drive signal he_b occur simultaneously. The fourth operating mode may be selected when, for example, it becomes necessary to avoid driving the recording elements in the first half of the block period due to noise or other considerations.

[0062] [Third embodiment] Fig. 11 is a circuit configuration diagram of a recording element substrate according to the third embodiment. In Fig. 11, the same components as those already explained with reference to the drawings are given the same reference numerals, and duplicate explanations will be omitted.

[0063] In this embodiment, two drive signal generation circuits 310-1 and 310-2 are arranged on the recording element substrate 300. In the configurations shown in FIG. 3 and FIG. 8, the drive signal generation circuit 310 generates two pre-selection drive signals he1 and he2. Therefore, the part that generates the pre-selection drive signal he1 and the part that generates the pre-selection drive signal he2 can be considered to be shared. In contrast, in the configuration of this embodiment shown in FIG. 11, the part that generates the pre-selection drive signal he1 and the part that generates the pre-selection drive signal he2 are provided separately as drive signal generation circuits 310-1 and 310-2.

[0064] The drive signal generation circuits 310-1 and 310-2 receive a common clock signal and a common latch signal lt. However, the drive signal generation circuits 310-1 and 310-2 receive separate clock signals he_clk and individual pattern designation signals he_data. The first individual pattern designation signal he_data supplied to the drive signal generation circuit 310-1 and the second individual pattern designation signal he_data supplied to the drive signal generation circuit 310-2 specify pre-selection drive signals with different double-pulse waveforms. The drive signal generation circuit 310-1 may generate two pre-selection drive signals, but uses the pre-selection drive signal with the earlier double pulse as the pre-selection drive signal he1 supplied to the drive signal selection circuit 311. The drive signal generation circuit 310-2 may also generate two pre-selection drive signals, but uses the pre-selection drive signal with the later double pulse as the pre-selection drive signal he2 supplied to the drive signal selection circuit 311. However, drive signal generation circuit 310-1 may generate one double pulse, and drive signal generation circuit 310-2 may also generate one double pulse. Here, the waveform of the double pulse of pre-selection drive signal he1 supplied to drive signal selection circuit 311 and the waveform of the double pulse of pre-selection drive signal he2 supplied to drive signal selection circuit 311 are different from each other.

[0065] Similar to the second embodiment, 2-bit operation switching signals sel0 and sel1 are supplied to the drive signal selection circuit 311. The drive signal selection circuit 311 of this embodiment operates in the same manner as the drive signal selection circuit 311 of the second embodiment. Note that the drive signal selection circuit 311 of this embodiment may be configured similarly to the drive signal selection circuit 311 of the first embodiment, and a 1-bit operation switching signal sel may be supplied to it, similar to the first embodiment.

[0066] 12 is a timing chart showing the operation of the recording element substrate according to the third embodiment in the first operating mode. As shown in the figure, the waveform of the double pulse of the first pre-selection drive signal he1 and the waveform of the double pulse of the second pre-selection drive signal he2 are different from each other. Because the recording element substrate is operating in the first operating mode, the first pre-selection drive signal he1 is selected as the first post-selection drive signal he_a, and as shown in the figure, this waveform is the same as the waveform of the first pre-selection drive signal he1. Similarly, the second pre-selection drive signal he2 is selected as the second post-selection drive signal he_b, and as shown in the figure, this waveform is the same as the waveform of the first pre-selection drive signal he2.

[0067] This embodiment can be applied, for example, to a case where it is necessary to drive the printing elements with different drive signals for each column.

[0068] [Other embodiments] A piezoelectric element may be used as the recording element instead of the heater.

[0069] The recording element substrate may operate in only any two operation modes selected from the group consisting of the first to fourth operation modes of the second embodiment, or may operate in only any three operation modes. In this case, as in the first and second embodiments, the pre-selection drive signal he1 and the pre-selection drive signal he2 may have the same pattern. As in the third embodiment, the pre-selection drive signal he1 and the pre-drive drive signal he2 may have mutually different patterns.

[0070] In the above embodiment, a double pulse pattern was used as an example of a pattern in which the drive signal intermittently reaches an effective level, but it may also be a pattern with more pulses or a single pulse pattern.

[0071] Depending on the application, the operation shown in Figure 6 may be modified to halve the block period so that a pulse is generated in the first post-selection drive signal and the second post-selection drive signal is always at an inactive level. Similarly, depending on the application, the operation shown in Figure 10 may be modified to halve the block period so that a period in which a pulse is generated in the first post-selection drive signal and the second post-selection drive signal is always inactive and a period in which "first" and "second" alternate may be repeated.

[0072] The printing apparatus in the above embodiment has a print head that prints by ejecting ink, but a liquid other than ink may be used instead of ink.

[0073] <Technical Features of the Present Disclosure> The present disclosure includes the following configurations.

[0074] [Configuration 1] a plurality of first recording elements; a plurality of second recording elements; a plurality of first drive elements for driving the plurality of first recording elements; a plurality of second drive elements for driving the plurality of second recording elements; a drive signal generating circuit that generates a first drive signal and a second drive signal; a drive signal selection circuit that selects both or either of the first drive signal and the second drive signal based on an operation switching signal supplied from an external device; Equipped with at least one first driving element and at least one second driving element operate based on the driving signal selected by the driving signal selection circuit; Recording element board.

[0075] [Configuration 2] when the operation switching signal indicates a first value, the drive signal selection circuit selects one of the first drive signal and the second drive signal for at least one of the first drive elements, and selects the other of the first drive signal and the second drive signal for at least one of the second drive elements; When the operation switching signal indicates a second value, the drive signal selection circuit commonly selects one or the other of the first drive signal and the second drive signal for at least one of the first drive element and at least one of the plurality of second drive elements. The recording element substrate according to configuration 1.

[0076] [Configuration 3] a blocking period when the operation switching signal indicates the second value is shorter than a blocking period when the operation switching signal indicates the first value; 3. The recording element substrate according to claim 2.

[0077] [Configuration 4] the at least one first driving element is a first driving element selected from the plurality of first printing elements based on a first element selection signal supplied from an external device; the at least one second driving element is a second driving element selected from the plurality of second printing elements based on a second element selection signal supplied from an external device; The recording element substrate according to configuration 2 or 3.

[0078] [Configuration 5] during a block period in which the operation switching signal indicates a first value, the drive signal selection circuit selects one of the first drive signal and the second drive signal for at least one of the first drive elements, and selects the other of the first drive signal and the second drive signal for at least one of the second drive elements; During a block period in which the operation switching signal indicates a third value, the drive signal selection circuit selects the other of the first drive signal and the second drive signal for at least one of the first drive elements, and selects the one of the first drive signal and the second drive signal for at least one of the second drive elements. 5. The recording element substrate according to any one of configurations 1 to 4.

[0079] [Configuration 6] the block period during which the drive signal indicates a first value and the block period during which the drive signal indicates a third value are repeated alternately; 6. The recording element substrate according to configuration 5.

[0080] [Configuration 7] the at least one first driving element is a driving element selected from the plurality of first printing elements based on a first element selection signal supplied from an external device; the at least one second driving element is a driving element selected from the plurality of second printing elements based on a second element selection signal supplied from an external device; 7. The recording element substrate according to any one of configurations 1 to 6.

[0081] [Configuration 8] further comprising a data expansion circuit that expands an externally supplied serial signal into the first element selection signal, the second element selection signal, the operation switching signal, and a common pattern designation signal that designates a pattern of the first drive signal and a pattern of the second drive signal, based on an externally supplied clock signal and an externally supplied latch signal; The recording element substrate according to configuration 4 or 7.

[0082] [Configuration 9] the first element selection signal, the second element selection signal, the operation switching signal, and the common pattern designation signal are updated for each block period based on the latch signal. The recording element substrate according to configuration 8.

[0083] [Configuration 10] a data expansion circuit that expands an externally supplied serial signal into the first element selection signal, the second element selection signal, a pattern of the first drive signal, and a common pattern designation signal that designates a pattern of the second drive signal, based on an externally supplied clock signal and an externally supplied latch signal; the operation switching signal is supplied from an external source separately from the serial signal; The recording element substrate according to configuration 4 or 7.

[0084] [Configuration 11] the first element selection signal, the second element selection signal, the operation switching signal, and the common pattern designation signal are updated for each block period based on the latch signal. 11. The recording element substrate according to configuration 10.

[0085] [Configuration 12] further comprising a data expansion circuit that expands an externally supplied serial signal into the first element selection signal, the second element selection signal, the operation switching signal, a first individual pattern designation signal that designates a pattern of the first drive signal, and a second individual pattern designation signal that designates a pattern of the second drive signal, based on an externally supplied clock signal and an externally supplied latch signal; The recording element substrate according to configuration 4 or 7.

[0086] [Configuration 13] the first element selection signal, the second element selection signal, the operation switching signal, the first individual pattern designation signal, and the second individual pattern designation signal are updated for each block period based on the latch signal. 13. The recording element substrate according to claim 12.

[0087] [Configuration 14] a data expansion circuit that expands an externally supplied serial signal into the first element selection signal, the second element selection signal, a first individual pattern designation signal that designates a pattern of the first drive signal, and a second individual pattern designation signal that designates a pattern of the second drive signal, based on an externally supplied clock signal and an externally supplied latch signal; the operation switching signal is supplied from an external source separately from the serial signal; The recording element substrate according to configuration 4 or 7.

[0088] [Configuration 15] the first element selection signal, the second element selection signal, the operation switching signal, the first individual pattern designation signal, and the second individual pattern designation signal are updated for each block period based on the latch signal. 15. The recording element substrate according to configuration 14.

[0089] [Configuration 16] a delay element for supplying the drive signal selected for at least one of the first drive elements by the drive signal selection circuit with a different delay time to different first drive elements selectable by the first element selection signal; a delay element for supplying the drive signal selected for at least one of the second drive elements by the drive signal selection circuit with a different delay time to different second drive elements selectable by the second element selection signal; Further comprising: The recording element substrate according to configuration 4 or 7.

[0090] [Configuration 17] a plurality of first control circuits for operating at least one of the first drive elements based on a selection signal selected for the at least one of the first drive elements by the drive signal selection circuit; a plurality of second control circuits for operating at least one of the second drive elements based on a selection signal selected for the at least one of the second drive elements by the drive signal selection circuit; Further comprising: 17. The recording element substrate according to any one of configurations 1 to 16.

[0091] [Configuration 18] a delay element that delays the drive signal selected by the drive signal selection circuit for at least one of the first drive elements and that is supplied to the plurality of first control circuits; and a delay element that delays the drive signal selected by the drive signal selection circuit for at least one of the second drive elements and that is supplied to the plurality of second control circuits; Equipped with one or both of the following: 18. The recording element substrate according to claim 17.

[0092] [Configuration 19] the first drive signal has a waveform for driving the first drive element or the second drive element to drive the recording element corresponding to the first drive element or the second drive element during a first portion of a block period; the second drive signal has a waveform for driving the first drive element or the second drive element to drive the recording element corresponding to the first drive element or the second drive element in a second portion that is temporally later than the first portion of the block period; 19. The recording element substrate according to any one of configurations 1 to 18.

[0093] [Configuration 20] a waveform of the first portion of the first drive signal and a waveform of the second portion of the second drive signal are identical; 20. The recording element substrate according to claim 19.

[0094] [Configuration 21] a waveform of the first portion of the first drive signal and a waveform of the second portion of the second drive signal are different from each other; 20. The recording element substrate according to claim 19.

[0095] [Configuration 22] the drive signal selection circuit shares a section for generating the first drive signal and a section for generating the second drive signal, and generates the first drive signal and the second drive signal based on a common pattern designation signal. 22. The recording element substrate according to any one of configurations 1 to 21.

[0096] [Configuration 23] The drive signal generating circuit a first drive signal generating circuit that generates the first drive signal based on a first individual pattern designation signal; a second drive signal generating circuit that generates the second drive signal based on a second individual pattern designation signal; Equipped with 22. The recording element substrate according to any one of configurations 1 to 21.

[0097] [Configuration 24] 24. A print head using the print element substrate according to any one of configurations 1 to 23, characterized in that the print head has a plurality of ejection ports for ejecting liquid.

[0098] [Configuration 25] A recording apparatus using the recording head according to Configuration 24 as a recording head that ejects ink as the liquid and performs recording on a recording medium, a recording device that ejects ink from ejection openings by driving the plurality of first recording elements and the plurality of second recording elements; [Explanation of symbols]

[0099] 300 recording element substrate 309 Data expansion circuit 310 Drive signal generation circuit 311 Drive signal selection circuit 320 Heater Array Circuit 321 Control circuit 322 Driver element (driver transistor) 323 Recording element (heater)

Claims

1. a plurality of first recording elements; a plurality of second recording elements; a plurality of first drive elements for driving the plurality of first recording elements; a plurality of second drive elements for driving the plurality of second recording elements; a drive signal generating circuit that generates a first drive signal and a second drive signal; a drive signal selection circuit that selects both or either of the first drive signal and the second drive signal based on an operation switching signal supplied from an external device; Equipped with at least one first driving element and at least one second driving element are operated based on the driving signal selected by the driving signal selection circuit; Recording element board.

2. when the operation switching signal indicates a first value, the drive signal selection circuit selects one of the first drive signal and the second drive signal for at least one of the first drive elements, and selects the other of the first drive signal and the second drive signal for at least one of the second drive elements; When the operation switching signal indicates a second value, the drive signal selection circuit commonly selects one or the other of the first drive signal and the second drive signal for at least one of the first drive element and at least one of the plurality of second drive elements. The recording element substrate according to claim 1 .

3. a blocking period when the operation switching signal indicates the second value is shorter than a blocking period when the operation switching signal indicates the first value; The recording element substrate according to claim 2 .

4. the at least one first driving element is a first driving element selected from the plurality of first printing elements based on a first element selection signal supplied from an external device; the at least one second driving element is a second driving element selected from the plurality of second printing elements based on a second element selection signal supplied from an external device; The recording element substrate according to claim 2 .

5. during a block period in which the operation switching signal indicates a first value, the drive signal selection circuit selects one of the first drive signal and the second drive signal for at least one of the first drive elements, and selects the other of the first drive signal and the second drive signal for at least one of the second drive elements; During a block period in which the operation switching signal indicates a third value, the drive signal selection circuit selects the other of the first drive signal and the second drive signal for at least one of the first drive elements, and selects the one of the first drive signal and the second drive signal for at least one of the second drive elements. The recording element substrate according to claim 1 .

6. the block period during which the drive signal indicates a first value and the block period during which the drive signal indicates a third value are alternately repeated; The recording element substrate according to claim 5 .

7. the at least one first driving element is a driving element selected from the plurality of first printing elements based on a first element selection signal supplied from an external device; the at least one second driving element is a driving element selected from the plurality of second printing elements based on a second element selection signal supplied from an external device; The recording element substrate according to claim 1 .

8. a data expansion circuit that expands an externally supplied serial signal into the first element selection signal, the second element selection signal, the operation switching signal, and a common pattern designation signal that designates a pattern of the first drive signal and a pattern of the second drive signal, based on an externally supplied clock signal and an externally supplied latch signal; 8. The recording element substrate according to claim 4 or 7.

9. the first element selection signal, the second element selection signal, the operation switching signal, and the common pattern designation signal are updated for each block period based on the latch signal; The recording element substrate according to claim 8 .

10. a data expansion circuit that expands an externally supplied serial signal into the first element selection signal, the second element selection signal, a pattern of the first drive signal, and a common pattern designation signal that designates a pattern of the second drive signal, based on an externally supplied clock signal and an externally supplied latch signal; the operation switching signal is supplied from an external source separately from the serial signal; 8. The recording element substrate according to claim 4 or 7.

11. the first element selection signal, the second element selection signal, the operation switching signal, and the common pattern designation signal are updated for each block period based on the latch signal; The recording element substrate according to claim 10.

12. a data expansion circuit that expands an externally supplied serial signal into the first element selection signal, the second element selection signal, the operation switching signal, a first individual pattern designation signal that designates a pattern of the first drive signal, and a second individual pattern designation signal that designates a pattern of the second drive signal, based on an externally supplied clock signal and an externally supplied latch signal; 8. The recording element substrate according to claim 4 or 7.

13. the first element selection signal, the second element selection signal, the operation switching signal, the first individual pattern designation signal, and the second individual pattern designation signal are updated for each block period based on the latch signal. The recording element substrate according to claim 12.

14. a data expansion circuit that expands an externally supplied serial signal into the first element selection signal, the second element selection signal, a first individual pattern designation signal that designates a pattern of the first drive signal, and a second individual pattern designation signal that designates a pattern of the second drive signal, based on an externally supplied clock signal and an externally supplied latch signal; the operation switching signal is supplied from an external source separately from the serial signal; 8. The recording element substrate according to claim 4 or 7.

15. the first element selection signal, the second element selection signal, the operation switching signal, the first individual pattern designation signal, and the second individual pattern designation signal are updated for each block period based on the latch signal. The recording element substrate according to claim 14.

16. a delay element for supplying the drive signal selected for at least one of the first drive elements by the drive signal selection circuit with a different delay time to different first drive elements selectable by the first element selection signal; a delay element for supplying the drive signal selected for at least one of the second drive elements by the drive signal selection circuit with a different delay time to different second drive elements selectable by the second element selection signal; Further comprising:

8. The recording element substrate according to claim 4 or 7.

17. a plurality of first control circuits for operating at least one of the first drive elements based on a selection signal selected for the at least one of the first drive elements by the drive signal selection circuit; a plurality of second control circuits for operating at least one of the second drive elements based on a selection signal selected for the at least one of the second drive elements by the drive signal selection circuit; Further comprising: The recording element substrate according to claim 1 .

18. a delay element that delays the drive signal selected by the drive signal selection circuit for at least one of the first drive elements and that is supplied to the plurality of first control circuits; and a delay element that delays the drive signal selected by the drive signal selection circuit for at least one of the second drive elements and that is supplied to the plurality of second control circuits; Equipped with one or both of the following: The recording element substrate according to claim 17.

19. the first drive signal has a waveform for driving the first drive element or the second drive element to drive the recording element corresponding to the first drive element or the second drive element in a first portion of a block period; the second drive signal has a waveform for driving the first drive element or the second drive element to drive the recording element corresponding to the first drive element or the second drive element in a second portion that is temporally later than the first portion of the block period; The recording element substrate according to claim 1 .

20. a waveform of the first portion of the first drive signal and a waveform of the second portion of the second drive signal are identical; 20. The recording element substrate according to claim 19.

21. a waveform of the first portion of the first drive signal and a waveform of the second portion of the second drive signal are different from each other; 20. The recording element substrate according to claim 19.

22. the drive signal selection circuit shares a section for generating the first drive signal and a section for generating the second drive signal, and generates the first drive signal and the second drive signal based on a common pattern designation signal; The recording element substrate according to claim 1 .

23. The drive signal generating circuit a first drive signal generating circuit that generates the first drive signal based on a first individual pattern designation signal; a second drive signal generating circuit that generates the second drive signal based on a second individual pattern designation signal; Equipped with The recording element substrate according to claim 1 .

24. 2. A printhead using the print element substrate according to claim 1, characterized in that it has a plurality of ejection ports for ejecting liquid.

25. A recording apparatus using the recording head according to claim 24 as a recording head that ejects ink as the liquid and performs recording on a recording medium, a recording device that ejects ink from ejection openings by driving the plurality of first recording elements and the plurality of second recording elements;

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