Voltage detection circuit

Abstract

To execute disconnection detection operation in parallel with detection operation of an object voltage.SOLUTION: A voltage detection circuit comprises: an A / D converter (50); an input chopper circuit (40) for switching a connection state between each input terminal of the A / D converter, and a first input wire and a second input wire at a first frequency fc1; an output chopper circuit (60) for alternately executing inverting operation and non-inverting operation to an output value of the A / D converter at the first frequency fc1; a digital low-pass filter (70) that operates at an output frequency fd and removes a high-frequency component from the output value of the output chopper circuit; and a current chopper circuit (34) for switching a connection state of a first current source, the first input wire, a second current source, and the second input wire at a second frequency fc2. When m and n are set to an integer of 0 or larger, fc1=fd*2m, fc2=fd*2n, and n≥m are satisfied.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a voltage detection circuit.

[0002] Patent Document 1 discloses a technique for detecting a disconnection on the analog circuit side of an AD converter (analog-digital converter) that converts an input voltage into a digital value. This technique pulls up or down the potential of the input terminal of the AD converter, and detects the disconnection based on the output value of the AD converter at that time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 1,135,3517 Summary of the Invention [Problem to be solved by the invention]

[0004] In the AD converter of Patent Document 1, the input voltage of the AD converter changes during the disconnection detection operation, so it is necessary to stop the detection operation of the target voltage during the disconnection detection operation. This specification proposes a technology that can detect a disconnection during the detection operation of the target voltage and can accurately detect the target voltage. [Means for solving the problem]

[0005] The voltage detection circuit disclosed in this specification includes an AD converter (50) that converts a voltage applied between a first input terminal (50a) and a second input terminal (50b) into a digital value, a first input wiring (20a), a second input wiring (20b), an input chopper circuit (40) that switches a connection state at a first frequency fc1 between a first connection state in which the first input wiring is connected to the first input terminal and the second input wiring is connected to the second input terminal and a second connection state in which the first input wiring is connected to the second input terminal and the second input wiring is connected to the first input terminal, and an inversion operation that inverts and outputs an output value of the AD converter and a pre-inverter circuit (40) that outputs ... The digital chopper circuit (60) includes an output chopper circuit (60) that alternately performs a non-inversion operation at the first frequency fc1 to output the output value without inverting it, a digital low-pass filter (70) that operates at an output frequency fd and removes high-frequency components from the output value of the output chopper circuit, a first current source (30a), a second current source (30b), and a current chopper circuit (34) that switches connection states at a second frequency fc2 between a third connection state in which the first current source is connected to the first input wiring and the second current source is connected to the second input wiring, and a fourth connection state in which the first current source is connected to the second input wiring and the second current source is connected to the first input wiring. fc1=fd·2 m fc2=fd·2 n n≧m is satisfied.

[0006] In this voltage detection circuit, the first input wire and the second input wire are connected to a device to be detected. The voltage between the first input wire and the second input wire is converted by the input chopper circuit into a voltage that fluctuates at a first frequency fc1 and then input to the AD converter. The AD converter outputs the input voltage (i.e., the voltage that fluctuates at the first frequency fc1) as a digital value. The output chopper circuit restores a waveform corresponding to the original voltage (i.e., the voltage between the first input wire and the second input wire) by inverting the output value of the AD converter (i.e., the voltage that fluctuates at the first frequency fc1) at predetermined intervals at the first frequency fc1. The digital low-pass filter removes high-frequency components from the output value of the output chopper circuit. With this configuration, low-frequency noise generated by the AD converter is modulated to a high frequency by the output chopper circuit, and the high-frequency voltage is removed by the digital low-pass filter, thereby suppressing errors caused by low-frequency noise. In addition, in this voltage detection circuit, current is supplied to the first input wire and the second input wire from the first current source and the second current source. Due to the operation of the current chopper circuit, the supply current of the first current source and the supply current of the second current source flow alternately through the first input wire and the second input wire. When there is no disconnection in the first input wire and the second input wire, an offset voltage occurs between the first input wire and the second input wire due to the difference between the current supplied from the first current source and the current supplied from the second current source. Because the current chopper circuit switches the connection state at the second frequency fc2, the offset voltage becomes a voltage that fluctuates at the second frequency fc2. The offset voltage is input to the digital low-pass filter via the input chopper circuit, AD converter, and output chopper circuit. The offset voltage, which fluctuates at high frequencies, is removed by the digital low-pass filter. Therefore, the voltage of the detection target can be accurately detected while suppressing the effects of the offset voltage. In particular, fc1=fd·2 m , fc2=fd·2 nWhen the relationship of n≥m is satisfied, the voltage having the first frequency fc1 and the voltage having the second frequency fc2 can be appropriately removed by the digital low-pass filter. Therefore, according to this voltage detection circuit, the voltage to be detected can be detected more accurately. Also, when a disconnection occurs in the first input wiring, the current supplied from the current chopper circuit to the first input wiring does not flow to the voltage detection target device side, so the potential of the first input wiring rises. When a disconnection occurs in the second input wiring, the current supplied from the current chopper circuit to the second input wiring does not flow to the voltage detection target device, so the potential of the second input wiring rises. Therefore, a disconnection can be detected from the potential of the first input wiring and the potential of the second input wiring. As described above, according to this voltage detection circuit, a disconnection detection operation can be executed in parallel with the detection operation of the target voltage, and the target voltage can be accurately detected.

Brief Description of Drawings

[0007] [Figure 1] Circuit diagram of the voltage detection circuit 10 of Example 1. [Figure 2] Graph showing each voltage during the operation of the voltage detection circuit 10 of Example 1. [Figure 3] Circuit diagram of the voltage detection circuit 100 of Example 2. [Figure 4] Graph showing each voltage during the operation of the voltage detection circuit 100 of Example 2.

Embodiments for Carrying Out the Invention

Examples

[0008] The voltage detection circuit 10 of Example 1 shown in FIG. 1 has a shunt resistor 12. The shunt resistor 12 is connected to an external circuit not shown. A current Is supplied from the external circuit flows through the shunt resistor 12. The voltage detection circuit 10 detects the current Is by detecting the voltage Vs between both ends of the shunt resistor 12.

[0009] The voltage detection circuit 10 has a first input wiring 20a, a second input wiring 20b, and an anti-aliasing filter 24 (hereinafter referred to as AAF 24). The first input wiring 20a and the second input wiring 20b are connected to the shunt resistor 12 via the AAF 24. The AAF 24 has a first resistor 24a, a second resistor 24b, and a capacitor 24c. The first input wiring 20a is connected to one terminal 12a (more specifically, the high-potential terminal) of the shunt resistor 12 via the first resistor 24a. The second input wiring 20b is connected to the other terminal 12b (more specifically, the low-potential terminal) of the shunt resistor 12 via the second resistor 24b. Therefore, the shunt resistor 12 is connected between the first input wiring 20a and the second input wiring 20b via the first resistor 24a and the second resistor 24b. The electrical resistance of the first resistor 24a is equal to the electrical resistance of the second resistor 24b. The capacitor 24c is connected between the first input wiring 20a and the second input wiring 20b.

[0010] The voltage detection circuit 10 has a frequency signal generation circuit 80. The frequency signal generation circuit 80 has a duty ratio of 50% and outputs a pulse signal 90 that oscillates at a frequency fc. The pulse signal 90 is input to each chopper circuit, which will be described later.

[0011] The voltage detection circuit 10 includes a first current source 30a, a second current source 30b, and a current chopper circuit 34. The first current source 30a generates a constant DC current Iwod1. The second current source 30b generates a constant DC current Iwod2. The output terminals of the first current source 30a and the second current source 30b are connected to the current chopper circuit 34.

[0012] The current chopper circuit 34 changes the mutual connection state among the first current source 30a, the second current source 30b, the first input wiring 20a, and the second input wiring 20b. The current chopper circuit 34 alternately switches the connection state between connection state A and connection state B. In connection state A, the output terminal of the first current source 30a is connected to the first input wiring 20a, and the output terminal of the second current source 30b is connected to the second input wiring 20b. Therefore, in connection state A, a current Iwod1 flows through the first input wiring 20a, and a current Iwod2 flows through the second input wiring 20b. In connection state B, the output terminal of the first current source 30a is connected to the second input wiring 20b, and the output terminal of the second current source 30b is connected to the first input wiring 20a. Therefore, in connection state B, a current Iwod1 flows through the second input wiring 20b, and a current Iwod2 flows through the first input wiring 20a. A pulse signal 90 output from the frequency signal generating circuit 80 is input to the current chopper circuit 34. The current chopper circuit 34 alternately switches the connection state between connection state A and connection state B in synchronization with the pulse signal 90. Therefore, the current chopper circuit 34 alternately switches the connection state between connection state A and connection state B at the frequency fc. Furthermore, because the duty ratio of the pulse signal 90 is 50%, the length of the period of connection state A and the length of the period of connection state B are equal in each cycle.

[0013] As shown in FIG. 1, the current I1 (i.e., the current Iwod1 or Iwod2) supplied from the current chopper circuit 34 to the first input wiring 20a flows to an external circuit via the first resistor 24a and the shunt resistor 12. The current I2 (i.e., the current Iwod1 or Iwod2) supplied from the current chopper circuit 34 to the second input wiring 20b flows to the external circuit via the second resistor 24b. As described above, the first resistor 24a and the second resistor 24b have the same electrical resistance. Hereinafter, the electrical resistances of the first resistor 24a and the second resistor 24b will be represented as electrical resistance R. The electrical resistance of the shunt resistor 12 is much smaller than the electrical resistance R of the first resistor 24a and the second resistor 24b. Because the current I1 flows through the first resistor 24a, the potential of the first input wiring 20a becomes higher than the potential of the terminal 12a of the shunt resistor 12 by a voltage Va (=R·I1). Furthermore, because a current I2 flows through the second resistor 24b, the potential of the second input wiring 20b becomes higher by a voltage Vb (=R·I2) than the potential of the terminal 12b of the shunt resistor 12. Therefore, a voltage V1, V1=Vs+ΔV (ΔV=Va-Vb), is applied between the first input wiring 20a and the second input wiring 20b. If Iwod1=Iwod2, then I1=I2, and therefore ΔV=0. However, in reality, an error occurs between the currents Iwod1 and Iwod2, and a voltage ΔV due to the difference between the currents Iwod1 and Iwod2 is applied between the first input wiring 20a and the second input wiring 20b. In this way, a voltage that is offset by ΔV from the voltage Vs to be detected is applied between the first input wiring 20a and the second input wiring 20b. Hereinafter, the voltage ΔV will be referred to as an offset voltage ΔV. The current chopper circuit 34 passes current through the first input wiring 20a and the second input wiring 20b while switching between the current Iwod1 and the current Iwod2, so the direction of the offset voltage ΔV generated in the connection state A is opposite to the direction of the offset voltage ΔV generated in the connection state B. Therefore, the offset voltage ΔV alternates between positive and negative.

[0014] The voltage detection circuit 10 includes an input chopper circuit 40, an AD converter 50 (hereinafter referred to as ADC 50), an output chopper circuit 60, and a digital low-pass filter 70 (hereinafter referred to as DLPF 70). A first input wiring 20a and a second input wiring 20b are connected to the input chopper circuit 40. The ADC 50 includes a first input terminal 50a and a second input terminal 50b. The first input terminal 50a and the second input terminal 50b are connected to the input chopper circuit 40. The input chopper circuit 40 changes the mutual connection states of the first input wiring 20a, the second input wiring 20b, the first input terminal 50a, and the second input terminal 50b. The input chopper circuit 40 alternately switches the connection state between connection state C and connection state D. In connection state C, the first input wiring 20a is connected to the first input terminal 50a, and the second input wiring 20b is connected to the second input terminal 50b. In connection state D, the first input wiring 20a is connected to the second input terminal 50b, and the second input wiring 20b is connected to the first input terminal 50a. Therefore, in connection state C, the voltage V2 applied between the first input terminal 50a and the second input terminal 50b is equal to the voltage V1 between the first input wiring 20a and the second input wiring 20b. Also, in connection state D, the voltage V2 applied between the first input terminal 50a and the second input terminal 50b is equal to the voltage obtained by inverting the voltage V1 between the first input wiring 20a and the second input wiring 20b. The input chopper circuit 40 alternately switches the connection state between connection state C and connection state D in synchronization with the pulse signal 90 input from the frequency signal generation circuit 80. Therefore, the input chopper circuit 40 alternately switches the connection state between connection state C and connection state D at the frequency fc. Furthermore, since the duty ratio of the pulse signal 90 is 50%, the length of the period of connection state C and the length of the period of connection state D are equal in each cycle.

[0015] The ADC 50 outputs a signal obtained by converting the voltage V2 applied between the first input terminal 50a and the second input terminal 50b into a digital value. Hereinafter, the voltage indicated by the digital signal output by the ADC 50 will be referred to as voltage V3. Voltage V3 includes voltage V2 and an error component generated by the ADC 50.

[0016] The output chopper circuit 60 processes the voltage V3 output as a digital value by the ADC 50. The output chopper circuit 60 alternates between a non-inverting operation, in which the voltage V3 is output as is, and an inverting operation, in which a voltage obtained by inverting the voltage V3 is output. The output chopper circuit 60 alternates between the non-inverting operation and the inverting operation in synchronization with the pulse signal 90 input from the frequency signal generation circuit 80. Therefore, the output chopper circuit 60 alternates between the non-inverting operation and the inverting operation at a frequency fc. Furthermore, since the duty ratio of the pulse signal 90 is 50%, the length of the non-inverting operation period and the length of the inverting operation period are equal in each cycle. Hereinafter, the voltage indicated by the digital signal output by the output chopper circuit 60 will be referred to as voltage V4.

[0017] The DLPF 70 removes high-frequency components from the voltage V4 output by the output chopper circuit 60. Specifically, the DLPF 70 calculates the average value of the voltage V4 within one cycle of the output frequency fd and outputs the average value as the voltage V5. Therefore, the DLPF 70 repeatedly outputs the voltage V5 at the output frequency fd. In this way, the DLPF 70 repeatedly calculates the average value of the voltage V4, thereby outputting the voltage V5 from which the high-frequency components have been removed from the voltage V4. The output frequency fd is a value obtained by dividing the sampling frequency fs of the ADC 50 by a predetermined decimation ratio. In other words, the output frequency fd is lower than the sampling frequency fs. Furthermore, the above-mentioned frequency fc is lower than the sampling frequency fs and equal to or higher than the output frequency fd. In the first embodiment, fc=fd.

[0018] FIG. 2 shows the changes in voltages V1 to V5 during normal operation of the voltage detection circuit 10. Because the rate of change of voltage Vs is much lower than the rates of change of voltages V1 to V4, voltage Vs is shown as a constant value in FIG. 2. In FIG. 2, period Td represents one cycle of frequency fd. That is, Td = 1 / fd. Also, period T1 in FIG. 2 is the first half of period Td, and period T2 is the second half of period Td. Periods T1 and T2 are equal in length. As described above, voltage V1 applied between input wirings 20a and 20b is V1 = Vs + ΔV. As described above, current chopper circuit 34 switches the current path at frequency fc, so offset voltage ΔV alternates between positive and negative at frequency fc. Therefore, voltage V1 fluctuates at frequency fc, centered on voltage Vs.

[0019] As described above, the input chopper circuit 40 switches the connection state between connection state C and connection state D at the frequency fc. In period T1, the connection state is connection state C, and in period T2, the connection state is connection state D. As described above, in connection state C (i.e., period T1), voltage V2 matches voltage V1. Also, in connection state D (i.e., period T2), voltage V2 matches a voltage obtained by inverting voltage V1.

[0020] As described above, the ADC 50 converts the voltage V2 into a digital value and outputs the converted signal. However, a certain error voltage Verr occurs in the output value of the ADC 50. The error voltage Verr is almost a DC component. Therefore, the voltage V3 indicated by the output value of the ADC 50 is a voltage obtained by shifting the voltage V2 by the error voltage Verr (i.e., V3 = V2 + Verr).

[0021] As described above, the output chopper circuit 60 alternately performs non-inverting and inverting operations at a frequency fc. The output chopper circuit 60 performs the non-inverting operation during the period T1 and the inverting operation during the period T2. During the non-inverting operation (i.e., during the period T1), the voltage V4 is equal to the voltage V3. During the inverting operation (i.e., during the period T2), the voltage V4 is equal to the voltage obtained by inverting the voltage V3. FIG. 2 also shows the voltage V1c and the error voltage Verrc that constitute the voltage V4. That is, V4 = V1c + Verrc. The voltage V1c is a component equivalent to the voltage V1, and the error voltage Verrc is a voltage equivalent to the error voltage Verr. As shown in FIG. 2, the error voltage Verr, which is a direct current, is converted by the output chopper circuit 60 into a high-frequency error voltage Verrc that fluctuates at a frequency fc. The output chopper circuit 60 performs the non-inverting and inverting operations in synchronization with the pulse signal 90, thereby restoring the voltage V1c equivalent to the voltage V1. The voltage V1c is a voltage that fluctuates by the amount of the offset voltage ΔV around the voltage Vs, and is approximately equal to the voltage V1.

[0022] The DLPF 70 outputs voltage V5 as the average value of voltage V4 within period Td. That is, the DLPF 70 repeatedly outputs voltage V5 for each period Td. By repeatedly calculating voltage V5 in this manner, voltage V5 is obtained by removing high-frequency components from voltage V4. Since error voltage Verrc of voltage V4 is a high-frequency component, it is removed by the DLPF 70. Furthermore, voltage V1c of voltage V4 is a voltage that matches the above-mentioned voltage V1 (note that V1 = Vs + ΔV). Since offset voltage ΔV that constitutes voltage V1c is a high-frequency component, it is removed by the DLPF 70. Since voltage Vs that constitutes voltage V1c is a DC component, it is not removed by the DLPF 70. Therefore, voltage V5 output by the DLPF 70 matches voltage Vs.

[0023] As described above, the voltage detection circuit 10 can output a voltage V5 that matches the voltage Vs. In particular, the error voltage Verr can be removed by the output chopper circuit 60 and the DLPC 70. Furthermore, because the offset voltage ΔV is modulated to a high-frequency component by the operation of the current chopper circuit 34, the offset voltage ΔV can be removed by the DLPC 70. Furthermore, because the frequency fc of the offset voltage ΔV and the frequency fc of the error voltage Verrc are both equal to the output frequency fd of the DLPC 70, no error due to frequency deviation occurs in the DLPC 70. Therefore, the voltage detection circuit 10 can accurately detect the voltage Vs.

[0024] In addition, in the first embodiment, the current chopper circuit 34 is operated at the same frequency fc as the input chopper circuit 40 and the output chopper circuit 60, so that a common pulse signal 90 can be input to these chopper circuits. Since the frequency signal generating circuit 80 can be made common to each chopper circuit, the voltage detection circuit 10 can be made smaller.

[0025] Next, we will explain how the voltage detection circuit 10 detects an open circuit. If an open circuit occurs at point X in FIG. 1 during the detection of the voltage Vs, the first input wiring 20a is disconnected from the terminal 12a, and the current I1 stops flowing from the first input wiring 20a to the terminal 12a. This causes the current I1 to charge the first input wiring 20a, resulting in a sudden increase in the potential of the first input wiring 20a. For example, the current I1 charges the capacitor 24c, causing a sudden increase in the potential of the first input wiring 20a. For example, the voltage V1 increases to an excessively high positive voltage. Furthermore, although not shown, if the second input wiring 20b is disconnected from the terminal 12b, the current I2 stops flowing from the second input wiring 20b to the terminal 12b, causing a sudden decrease in the voltage V1. For example, the voltage V1 decreases to an excessively large negative voltage. Therefore, whether or not an open circuit has occurred can be detected based on the absolute value or rate of change of the voltage V1. For example, it is possible to detect whether a disconnection has occurred based on the absolute value or rate of change of voltage V5, which changes in response to voltage V1. In this way, the voltage detection circuit 10 can perform a disconnection detection operation in parallel with the detection operation of voltage Vs. This prevents erroneous detection of voltage Vs when a disconnection has occurred.

[0026] As described above, the voltage detection circuit 10 of the first embodiment can accurately detect the voltage Vs and can detect a disconnection during the operation of detecting the voltage Vs. [Example]

[0027] The voltage detection circuit 100 of the second embodiment shown in FIG. 3 has two frequency signal generation circuits 81 and 82. The frequency signal generation circuit 81 outputs a pulse signal 91 that oscillates at a frequency fc1. The frequency fc1 is equal to the output frequency fd of the DLPF 70. The duty ratio of the pulse signal 91 is 50%. The frequency signal generation circuit 82 outputs a pulse signal 92 that oscillates at a frequency fc2. The frequency fc2 is four times (i.e., 2 times) the output frequency fd of the DLPF 70. 2The duty ratio of the pulse signal 92 is 50%. The pulse signal 91 is input to the input chopper circuit 40 and the output chopper circuit 60. The input chopper circuit 40 and the output chopper circuit 60 operate in synchronization with the pulse signal 91. The pulse signal 92 is input to the current chopper circuit 34. The current chopper circuit 34 operates in synchronization with the pulse signal 92. The other configurations of the voltage detection circuit 100 of the second embodiment are the same as those of the first embodiment.

[0028] FIG. 4 shows the changes in voltages V1 to V5 during normal operation of the voltage detection circuit 100 of the second embodiment. In the second embodiment, the current chopper circuit 34 switches its connection state at a frequency fc2 that is four times the output frequency fd. Therefore, the offset voltage ΔV oscillates four times during the period Td. Furthermore, since the operating frequency fc1 of the input chopper circuit 40 is equal to the output frequency fd of the DLPF, the input chopper circuit 40 operates in the same manner as in the first embodiment. Therefore, the voltage V2 is equal to the voltage V1 during the period T1 and becomes the inverted voltage of the voltage V1 during the period T2. Since the ADC 50 converts the voltage V2 into a digital value, as in the first embodiment, the voltage V3 is the sum of the error voltage Verr and the voltage V2. Since the operating frequency fc1 of the output chopper circuit 60 is equal to the output frequency fd of the DLPF, the output chopper circuit 60 operates in the same manner as in the first embodiment. Therefore, the voltage V4 output by the output chopper circuit 60 contains a voltage V1c obtained by restoring the voltage V1 and an error voltage Verrc obtained by modulating the error voltage Verr to a high frequency. As in the first embodiment, the DLPF 70 operates at the output frequency fd and removes high-frequency components from the voltage V4. The error voltage Verrc is removed by the DLPF 70. The high-frequency components (i.e., the offset voltage ΔV) included in the voltage V1c are also removed by the DLPF 70. Therefore, a voltage substantially equal to the voltage Vs is output as the voltage V5.

[0029] As described above, the voltage detection circuit 100 of the second embodiment can output the voltage V5 that is equal to the voltage Vs, similar to the first embodiment. Furthermore, in the second embodiment, the offset voltage ΔV is modulated to a higher frequency fc2 than in the first embodiment, so that the offset voltage ΔV can be more effectively removed by the DLPF 70, thereby reducing noise. Furthermore, in the second embodiment, similar to the first embodiment, a wire break can be detected during the operation of detecting the voltage Vs. Thus, the voltage detection circuit 100 of the second embodiment can accurately detect the voltage Vs and can detect a wire break during the operation of detecting the voltage Vs.

[0030] When m and n are integers equal to or greater than 0, if the frequencies fd, fc1, and fc2 satisfy the following relationship, the voltage Vs can be accurately detected. fc1=fd·2 m fc2=fd·2 n n≧m Note that Example 1 is an example where m=0, n=0, and Example 2 is an example where m=0, n=2. Note that in Examples 1 and 2, m is 0, but m may be an integer equal to or greater than 1. In this way, when frequencies fc1 and fc2 are equal to or greater than frequency fd, the offset voltage ΔV and error voltage Verr can be modulated to a high frequency band that can be removed by the DLPF 70. Therefore, the offset voltage ΔV and error voltage Verr can be appropriately removed. In addition, when frequencies fc1 and fc2 are 2 times the frequency fd, m Double or 2 n If the offset voltage ΔV and the error voltage Verr are doubled, it is possible to prevent the processing of the DLPF 70 from becoming out of synchronization with each other, and to suppress the occurrence of errors in the DLPF 70. Therefore, if the above relationship is satisfied, the voltage Vs can be accurately detected.

[0031] Connection state A is an example of a third connection state. Connection state B is an example of a fourth connection state. Connection state C is an example of a first connection state. Connection state D is an example of a second connection state.

[0032] (Configuration 1) A voltage detection circuit, an AD converter (50) that converts a voltage applied between a first input terminal (50a) and a second input terminal (50b) into a digital value; a first input wiring (20a); a second input wiring (20b); an input chopper circuit (40) that switches a connection state between a first connection state in which the first input wiring is connected to the first input terminal and the second input wiring is connected to the second input terminal, and a second connection state in which the first input wiring is connected to the second input terminal and the second input wiring is connected to the first input terminal, at a first frequency fc1; an output chopper circuit (60) that alternately performs, at the first frequency fc1, an inversion operation of inverting and outputting an output value of the AD converter and a non-inversion operation of outputting the output value of the AD converter without inverting it; a digital low-pass filter (70) that operates at an output frequency fd and removes high-frequency components from the output value of the output chopper circuit; a first current source (30a); a second current source (30b); a current chopper circuit (34) that switches a connection state between a third connection state in which the first current source is connected to the first input wiring and the second current source is connected to the second input wiring, and a fourth connection state in which the first current source is connected to the second input wiring and the second current source is connected to the first input wiring, at a second frequency fc2; and When m and n are integers greater than or equal to 0, fc1=fd·2 m fc2=fd·2 n n≧m is satisfied, Voltage detection circuit. (Configuration 2) 2. The voltage detection circuit of configuration 1, wherein n=m. (Configuration 3) 2. The voltage detection circuit of configuration 1, wherein n>m. (Configuration 4) the first input wiring is connected to a voltage detection target device (12) via a first resistor (24a); the second input wiring is connected to the voltage detection target device via a second resistor (24b); 4. The voltage detection circuit according to any one of configurations 1 to 3. (Configuration 5) 5. The voltage detection circuit according to any one of configurations 1 to 4, wherein a shunt resistor (12) is connected between the first input wiring and the second input wiring.

[0033] According to configuration 2, the input chopper circuit, the output chopper circuit, and the current chopper circuit can be operated at a common frequency, and the structure of the voltage detection circuit can be simplified.

[0034] According to configuration 3, the offset voltage can be modulated to a higher frequency, so that the offset voltage can be more effectively removed by the digital low-pass filter.

[0035] According to the fourth configuration, even if an offset voltage occurs due to an error between the first current source and the second current source, the voltage of the detection target can be accurately detected.

[0036] According to the fifth configuration, the current flowing through the shunt resistor can be detected.

[0037] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0038] 10: voltage detection circuit, 12: shunt resistor, 24: anti-aliasing filter, 30a: first current source, 30b: second current source, 34: current chopper circuit, 40: input chopper circuit, 50: AD converter, 60: output chopper circuit, 70: digital low-pass filter

Claims

1. A voltage detection circuit, an AD converter (50) that converts a voltage applied between a first input terminal (50a) and a second input terminal (50b) into a digital value; A first input wiring (20a), A second input wiring (20b); an input chopper circuit (40) that switches a connection state between a first connection state in which the first input wiring is connected to the first input terminal and the second input wiring is connected to the second input terminal, and a second connection state in which the first input wiring is connected to the second input terminal and the second input wiring is connected to the first input terminal, at a first frequency fc1; an output chopper circuit (60) that alternately performs an inversion operation of inverting and outputting an output value of the AD converter and a non-inversion operation of outputting the output value of the AD converter without inverting it, at the first frequency fc1; a digital low-pass filter (70) that operates at an output frequency fd and removes high-frequency components from the output value of the output chopper circuit; a first current source (30a); a second current source (30b); a current chopper circuit (34) that switches a connection state between a third connection state in which the first current source is connected to the first input wiring and the second current source is connected to the second input wiring, and a fourth connection state in which the first current source is connected to the second input wiring and the second current source is connected to the first input wiring, at a second frequency fc2; and When m and n are integers of 0 or more, fc1=fd・2 ｍ fc2=fd・2 ｎ n≧m is satisfied, Voltage detection circuit.

2. 2. The voltage detection circuit of claim 1, wherein n=m.

3. 2. The voltage detection circuit according to claim 1, wherein n>m.

4. the first input wiring is connected to a voltage detection target device (12) via a first resistor (24a); the second input wiring is connected to the voltage detection target device via a second resistor (24b); The voltage detection circuit according to any one of claims 1 to 3.

5. 4. The voltage detection circuit according to claim 1, wherein a shunt resistor (12) is connected between the first input wiring and the second input wiring.

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