Voltage generation circuit and writing device

Abstract

To provide a voltage generation circuit capable of setting an output voltage with high resolution.SOLUTION: A voltage generation circuit comprises: a smoothing circuit for receiving an input of a pulse-width modulated signal and outputting voltage obtained by smoothing the pulse-width modulated signal to a first node; a first resistor connected between an output node and a second node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a ground node; and a voltage control circuit for generating a second voltage based on a first voltage input to an input node, outputting the second voltage to the output node, and controlling the second voltage so that the voltage of the second node becomes a prescribed voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a voltage generating circuit and a writing device. [Background technology]

[0002] Patent Document 1 describes a power supply circuit equipped with a variable output regulator that can be easily and accurately set by the user. The power supply circuit described in Patent Document 1 converts the output from a microcomputer into a pulse-width modulated signal, smooths this pulse-width modulated signal, and inputs it to one end of a resistor whose other end is connected to the output terminal of the variable output regulator. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-034568 Summary of the Invention [Problem to be solved by the invention]

[0004] In the power supply circuit described in Patent Document 1, it is difficult to widen the setting range of the pulse width of the pulse width modulation signal that can change the output voltage, and as a result, the resolution for changing the output voltage is low. [Means for solving the problem]

[0005] One aspect of the voltage generating circuit according to the present invention is a smoothing circuit that receives a pulse width modulated signal and smooths the pulse width modulated signal to output a voltage to a first node; a first resistor connected between the output node and a second node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a ground node; and a voltage control circuit that generates a second voltage based on a first voltage input to an input node, outputs the second voltage to the output node, and controls the second voltage so that the voltage of the second node becomes a predetermined voltage.

[0006] One aspect of the writing device according to the present invention is One aspect of the voltage generating circuit; a pulse width modulation circuit that generates the pulse width modulation signal and outputs it to the voltage generation circuit; The second voltage generated by the voltage generating circuit is supplied to an electronic component. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a diagram showing the configuration of a voltage generating circuit according to the first embodiment. [Figure 2] FIG. 1 is a diagram showing an example of the configuration of a regulator. [Figure 3] FIG. 3 is a diagram showing an example of the relationship between a pulse width modulation signal and a voltage in the voltage generating circuit of the first embodiment. [Figure 4] FIG. 10 is a diagram showing the configuration of a voltage generating circuit of a comparative example. [Figure 5] FIG. 10 is a diagram showing an example of the relationship between a pulse width modulation signal and a voltage in a voltage generating circuit of a comparative example. [Figure 6] FIG. 10 is a diagram showing the configuration of a voltage generating circuit according to a second embodiment. [Figure 7] FIG. 1 is a diagram showing an example of the configuration of a DC-DC converter. [Figure 8] FIG. 2 is a functional block diagram of the writing device of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Voltage generation circuit 1-1. First embodiment The voltage generating circuit of the first embodiment is a linear regulator that steps down an input voltage and outputs it. Fig. 1 is a diagram showing the configuration of the voltage generating circuit of the first embodiment. As shown in Fig. 1, the voltage generating circuit 1 of the first embodiment includes a voltage control circuit 10, a logic buffer 20, a smoothing circuit 30, resistors 41, 42, and 43, and capacitors 44 and 45.

[0010] The logic buffer 20 buffers the pulse-width modulated signal PWMIN input from outside the voltage generating circuit 1, and outputs a pulse-width modulated signal PWMX with the power supply voltage VCC at its high level and the ground voltage VSS at its low level. The power supply voltage VCC is supplied from outside the voltage generating circuit 1 and is, for example, 3.3 V. Note that the logic buffer 20 may be replaced with a logic inverter that outputs a pulse-width modulated signal PWMX that is the logical inversion of the pulse-width modulated signal PWMIN.

[0011] The smoothing circuit 30 receives the pulse-width modulated signal PWMX and outputs a voltage V1 obtained by smoothing the pulse-width modulated signal PWMX to a node N1. Specifically, the smoothing circuit 30 is a low-pass filter configured by a resistor 31 and a capacitor 32 connected in series between the output terminal of the logic buffer 20 and the ground, and the node where the resistor 31 and the capacitor 32 are connected is the node N1.

[0012] Voltage V1 at node N1 is an averaged voltage of pulse width modulation signal PWMX, and is expressed by equation (1) where tPeriod is the period of pulse width modulation signal PWMX and tWHigh is the high level pulse width.

[0013]

number

[0014] The resistor 41 is connected between the output node NO and a node N2. The resistor 42 is connected between the node N1 and a node N2. The resistor 43 is connected between the node N2 and a ground node NG.

[0015] The capacitor 44 is connected between the input node NI and the ground node NG, and the capacitor 45 is connected between the output node NO and the ground node NG.

[0016] The voltage control circuit 10 includes a regulator 11. The regulator 11 has an input terminal IN, an output terminal OUT, a feedback terminal FB, and a ground terminal GND, and outputs a voltage from the output terminal OUT that is obtained by stepping down the voltage input from the input terminal IN based on the voltage supplied to the ground terminal GND. The regulator 11 also outputs a constant voltage from the output terminal OUT by controlling the voltage input to the feedback terminal FB so that it coincides with a predetermined voltage.

[0017] Fig. 2 is a diagram showing an example configuration of the regulator 11. As shown in Fig. 2, the regulator 11 includes a reference voltage generating circuit 12, an error amplifier 13, and a P-channel MOSFET 14. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0018] The reference voltage generation circuit 12 generates a constant reference voltage VREF and outputs it to the inverting input terminal of the error amplifier 13. For example, the reference voltage generation circuit 12 uses the bandgap voltage of silicon to generate a constant reference voltage VREF regardless of the power supply voltage or temperature.

[0019] The non-inverting input terminal of the error amplifier 13 is connected to the feedback terminal FB. Therefore, the error amplifier 13 compares the voltage at the feedback terminal FB with the reference voltage VREF, and controls the gate voltage of the MOSFET 14 so that the voltage at the feedback terminal FB matches the reference voltage VREF.

[0020] The gate of the MOSFET 14 is connected to the output terminal of the error amplifier 13, its source is connected to the input terminal IN, and its drain is connected to the output terminal OUT. The voltage VFB at the feedback terminal FB is the voltage obtained by dividing the output voltage VOUT by two resistors 41 and 42. If this divided voltage is smaller than the reference voltage VREF, the gate voltage of the MOSFET 14 decreases, the current supply capacity of the MOSFET 14 increases, and the output voltage VOUT rises. An equilibrium state is reached when the divided voltage VFB matches the reference voltage VREF. The same operation occurs in the reverse case, where the current supply capacity of the MOSFET 14 is controlled so that the reference voltage VREF and the divided voltage VFB match, thereby maintaining the output voltage VOUT constant.

[0021] As shown in FIG. 1, regulator 11 has an input terminal IN connected to input node NI, an output terminal OUT connected to output node NO, a feedback terminal FB connected to node N2, and a ground terminal GND connected to ground node NG. A voltage VIN is input to input node NI from outside voltage generating circuit 1, and a ground voltage VSS is supplied to ground node NG. Therefore, regulator 11 compares the voltage at node N2 with a predetermined reference voltage VREF and controls the current supply capacity from input terminal IN to output terminal OUT based on the comparison result. Note that voltage VIN is higher than output voltage VOUT, e.g., 5V. Let VFB be the feedback voltage based on voltage VOUT at NO, and let R1, R2, R3, and R4 be the resistances of resistors 41, 42, 43, and 31, respectively. Then, currents I1, I2, and I3 flowing through resistors 41, 42, and 43, respectively, be expressed by equations (2), (3), and (4).

[0022]

number

[0023]

number

[0024]

number

[0025] From equation (2), the voltage VOUT of the output node NO is expressed by equation (5), and by substituting equations (3) and (4) into equation (5), equation (6) is obtained.

[0026]

number

[0027]

number

[0028] The voltage control circuit 10 generates a voltage VOUT based on a voltage VIN input to an input node NI and outputs it to an output node NO. The voltage control circuit controls the voltage VOUT so that the feedback voltage VFB, which is the voltage at node N2, becomes equal to a predetermined reference voltage VREF. In equation (6), since the feedback voltage VFB is a constant reference voltage VREF, the higher the voltage V1, the lower the voltage VOUT. However, if the voltage VOUT becomes lower than the feedback voltage VFB, i.e., the reference voltage VREF, current flows from node N2 through output node NO to a downstream circuit connected to output node NO. Therefore, the range in which the voltage VOUT is lower than the reference voltage VREF is prohibited. In other words, the voltage generation circuit 1 cannot output a voltage VOUT lower than the feedback voltage VFB unless a downstream circuit connected to output node NO is connected. Therefore, based on equation (6), the voltage generation circuit 1 can be used within a range in which the voltage V1 satisfies equation (7).

[0029]

number

[0030] FIG. 3 shows an example of the relationship between the pulse-width modulation signal PWMX and the voltage VOUT in the voltage generating circuit 1 of the first embodiment. FIG. 3 graphically illustrates the calculated values ​​of the voltage VOUT when the high-level pulse width of the pulse-width modulation signal PWMX is changed linearly in 256 steps from 0 to 255, assuming VCC=3.3V, VREF=1.2V, R1=22 kΩ, R2=R3=15 kΩ, and R4=20 kΩ. In the example of FIG. 3, where tWHigh / tPeriod is 232 / 256, where tWHigh is the period tPeriod and tWHigh is the high-level pulse width of the pulse-width modulation signal PWMX, the voltage VOUT is 1.207 V, which is approximately equal to the reference voltage VREF=1.2 V. Therefore, the voltage VOUT can be adjusted in 233 steps from 0 to 232 / 256 for tWHigh / tPeriod. When tWHigh / tPeriod=0, the voltage VOUT is 3.4V, and when tWHigh / tPeriod=233 / 256, the voltage VOUT is 1.2V, so (3.4V-1.2V) / (233-1) ≈ 9mV per step. In other words, the voltage VOUT can be adjusted in 9mV steps.

[0031] The voltage generating circuit 1 of this embodiment is characterized in that a resistor 43 is provided between the node N2 and the ground node NG. Therefore, as shown in Fig. 4, a voltage generating circuit 2 of a comparative example in which the resistor 43 is not provided between the node N2 and the ground node NG is assumed and compared in terms of effect. In the voltage generating circuit 2 of the comparative example shown in Fig. 4, the current I1 flowing through the resistor 41 is expressed by equation (8), and the current I2 flowing through the resistor 42 is expressed by the above-mentioned equation (3).

[0032]

number

[0033] From equation (8), the voltage VOUT of the output node NO is expressed by equation (9), and by substituting equation (3) into equation (9), equation (10) is obtained.

[0034]

number

[0035]

number

[0036] From equation (10), the voltage generating circuit 2 can be used within a range in which the voltage V1 satisfies equation (11).

[0037]

number

[0038] FIG. 5 shows an example of the relationship between the pulse-width modulation signal PWMX and the voltage VOUT in the voltage generating circuit 2 of the comparative example. FIG. 5 graphically illustrates the calculated values ​​of the voltage VOUT when the high-level pulse width of the pulse-width modulation signal PWMX is changed linearly in 256 steps from 0 to 255, assuming VCC=3.3V, VREF=1.2V, R1=20kΩ, R2=5.6kΩ, and R4=5.6kΩ. In the example of FIG. 5, where tWHigh / tPeriod is the period tPeriod and the high-level pulse width tWHigh of the pulse-width modulation signal PWMX, the voltage VOUT is 1.202V when tWHigh / tPeriod is 93 / 256, which is nearly equal to the reference voltage VREF=1.2V. Therefore, the voltage VOUT can be adjusted in 94 steps from 0 to 93 / 256 for tWHigh / tPeriod. When tWHigh / tPeriod=0, the voltage VOUT is 3.343V, and when tWHigh / tPeriod=93 / 256, the voltage VOUT is 1.202V, so (3.343V-1.202V) / (94-1) ≈ 23mV per step. In other words, the voltage VOUT can be adjusted in 23mV steps.

[0039] As described above, in the voltage generating circuit 1 of this embodiment, the resistor 43 is provided between the node N2 and the ground node NG, so that the voltage VOUT can be adjusted in steps of 9 mV, which is significantly smaller than in the voltage generating circuit 2 of the comparative example.

[0040] In the first embodiment, node N1 is an example of a "first node," and node N2 is an example of a "second node." Furthermore, resistor 41 is an example of a "first resistor," resistor 42 is an example of a "second resistor," and resistor 43 is an example of a "third resistor." Furthermore, voltage VIN is an example of a "first voltage," and voltage VOUT is an example of a "second voltage."

[0041] As described above, in the voltage generating circuit 1 of the first embodiment, not only is there a current path from output node NO through resistors 41 and 42, but there is also a current path from output node NO through resistors 41 and 43. This means that a larger current flows through resistor 41 than in the absence of the latter current path. Therefore, even if the high-level pulse width of pulse-width modulation signal PWMIN is increased to raise voltage V1 output to node N1, voltage VOUT at output node NO does not drop significantly, and voltage VOUT is unlikely to become smaller than reference voltage VREF, which is the voltage at node N2. Therefore, with the voltage generating circuit 1 of the first embodiment, the setting range of the pulse width of pulse-width modulation signal PWMIN that changes voltage VOUT can be widened, allowing the output voltage VOUT to be set with high resolution.

[0042] 1-2. Second embodiment In the following, in the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and explanations of the same components as those in the first embodiment are omitted or simplified, and differences from the first embodiment will be mainly described.

[0043] The voltage generating circuit of the second embodiment is a switching regulator that boosts an input voltage and outputs it. Fig. 6 is a diagram showing the configuration of the voltage generating circuit of the second embodiment. As shown in Fig. 6, in the voltage generating circuit 1A of the second embodiment, the voltage control circuit 10 of the voltage generating circuit 1 of the first embodiment is replaced with a voltage control circuit 50.

[0044] The voltage control circuit 50 includes a DC-DC converter 51, an inductor 52, and a diode 53. The inductor 52 is connected between an input node NI and a node N3. The diode 53 is connected between the node N3 and an output node NO. The DC-DC converter 51 has a power supply terminal VDD, a switch terminal SW, a feedback terminal FB, and a ground terminal GND, and controls the voltage input to the feedback terminal FB to match a predetermined voltage, thereby switching whether or not the switch terminal SW and the ground terminal GND are connected.

[0045] 7 is a diagram showing an example of the configuration of a DC-DC converter 51. As shown in Fig. 7, the DC-DC converter 51 includes a reference voltage generating circuit 54, an error amplifier 55, a pulse width modulation circuit 56, and an N-channel MOSFET 57.

[0046] The reference voltage generation circuit 54 generates a constant reference voltage VREF and outputs it to the inverting input terminal of the error amplifier 55. For example, the reference voltage generation circuit 54 uses the bandgap voltage of silicon to generate a constant reference voltage VREF regardless of the power supply voltage or temperature.

[0047] The non-inverting input terminal of the error amplifier 55 is connected to the feedback terminal FB. Therefore, the error amplifier 55 compares the voltage at the feedback terminal FB with a reference voltage VREF, and outputs a high-level voltage when the voltage at the feedback terminal FB is higher than the reference voltage VREF, and outputs a low-level voltage when the voltage at the feedback terminal FB is lower than the reference voltage VREF. The high-level voltage is the voltage input from the power supply terminal VDD, and the low-level voltage is the voltage supplied to the ground terminal GND.

[0048] The pulse width modulation circuit 56 generates a control signal DRV that controls the on / off of the MOSFET 57 based on the output voltage of the error amplifier 55, and outputs the control signal DRV to the gate of the MOSFET 57. For example, the pulse width modulation circuit 56 compares the output voltage of the error amplifier 55 with a triangular wave to generate, as the control signal DRV, a pulse width modulated signal having a pulse width according to the output voltage of the error amplifier 55, and outputs the control signal DRV to the gate of the MOSFET 57.

[0049] The MOSFET 57 has a gate that receives the control signal DRV output from the pulse width modulation circuit 56, a source that is connected to the switch terminal SW, and a drain that is connected to the ground terminal GND. Therefore, when the control signal DRV is at a high level, the switch terminal SW and the ground terminal GND are electrically connected, and when the control signal DRV is at a low level, the switch terminal SW and the ground terminal GND are electrically disconnected. That is, the MOSFET 57 switches whether or not to connect the switch terminal SW and the ground terminal GND, depending on the output voltage of the error amplifier 55.

[0050] 6, the power supply terminal VDD of DC-DC converter 51 is connected to input node NI, switch terminal SW is connected to node N3, feedback terminal FB is connected to node N2, and ground terminal GND is connected to ground node NG. A voltage VIN is input to input node NI from outside voltage generating circuit 1, and a ground voltage VSS is supplied to ground node NG. Therefore, DC-DC converter 51 operates using voltage VIN supplied to power supply terminal VDD as its power supply voltage, and switches whether or not to connect the voltage at node N3 to ground node NG.

[0051] In the voltage control circuit 50 configured as described above, when the MOSFET 57 of the DC-DC converter 51 is on, a current flows from the input node NI to the ground node via the inductor 52 and the MOSFET 57, and this current stores energy in the inductor 52. When the MOSFET 57 is off, a current corresponding to the voltage VIN input to the input node NI and the energy stored in the inductor 52 flows to the output node NO via the diode 53, and this current charges the capacitor 45, increasing the voltage VOUT at the output node NO. The diode 53 may be, for example, a Schottky barrier diode. A Schottky barrier diode has a low forward voltage, resulting in low loss and enabling high-speed switching.

[0052] In the voltage generating circuit 1A of the second embodiment, the circuit configuration except for the voltage control circuit 50 is the same as that of the voltage generating circuit 1 of the first embodiment, and therefore a description thereof will be omitted. In the voltage generating circuit 1A of the second embodiment, the voltage VOUT at the output node NO is also expressed by the above-described equation (6), and the higher the voltage V1, the lower the voltage VOUT. That is, the voltage control circuit 50 generates the voltage VOUT based on the voltage VIN input to the input node NI, outputs the voltage VOUT to the output node NO, and controls the voltage VOUT so that the feedback voltage VFB, which is the voltage of the node N2, becomes the reference voltage VREF, which is a predetermined voltage. Furthermore, in the voltage generating circuit 1A of the second embodiment, the resistor 43 is provided between the node N2 and the ground node NG, thereby enabling the voltage VOUT to be adjusted in significantly smaller steps than when the resistor 43 is not provided.

[0053] In the second embodiment, node N1 is an example of a "first node," node N2 is an example of a "second node," and node N3 is an example of a "third node." Furthermore, resistor 41 is an example of a "first resistor," resistor 42 is an example of a "second resistor," and resistor 43 is an example of a "third resistor." Furthermore, voltage VIN is an example of a "first voltage," and voltage VOUT is an example of a "second voltage."

[0054] According to the voltage generating circuit 1A of the second embodiment described above, similarly to the voltage generating circuit 1 of the first embodiment, the setting range of the pulse width of the pulse width modulation signal PWMIN that can change the voltage VOUT can be widened, and therefore the output voltage VOUT can be set with high resolution.

[0055] 2. Writing device 8 is a functional block diagram of a writing device of this embodiment. As shown in FIG. 8, the writing device 100 of this embodiment includes the voltage generating circuit 1 of the first embodiment and the voltage generating circuit 1A of the second embodiment. The writing device 100 also includes a microcontrol unit 110, a reference voltage generating circuit 120, a switch circuit 130, and digital input / output circuits 140, 141, 142, and 143.

[0056] The microcontrol unit 110 includes a control circuit 111, an A / D conversion circuit 112, a pulse width modulation circuit 113, and general-purpose input / output circuits 114 and 115.

[0057] Based on the reference voltage generated by the reference voltage generation circuit 120, the A / D conversion circuit 112 converts the voltage fed back from the output node of the voltage generation circuit 1A into a first digital signal and outputs it to the pulse width modulation circuit 113. Also, based on the reference voltage, the A / D conversion circuit 112 converts the voltage fed back from the output node of the voltage generation circuit 1A into a second digital signal and outputs it to the pulse width modulation circuit 113.

[0058] The pulse width modulation circuit 113 outputs a pulse width modulated signal based on a voltage fed back from the output nodes of the voltage generation circuits 1 and 1A. Specifically, the pulse width modulation circuit 113 generates a first pulse width modulated signal based on a first digital signal and outputs the first pulse width modulated signal to the voltage generation circuit 1 via the general-purpose input / output circuit 114. The pulse width modulation circuit 113 also generates a second pulse width modulated signal based on a second digital signal and outputs the second pulse width modulated signal to the voltage generation circuit 1A via the general-purpose input / output circuit 115.

[0059] The control circuit 111 communicates with a personal computer 200 connected to the writing device 100, and receives from the personal computer 200 setting data for the output voltage of the voltage generating circuits 1, 1A and data to be written to the electronic component 300. Based on the setting data for the output voltage of the voltage generating circuits 1, 1A, the control circuit 111 sets the pulse width of the pulse width modulation signal output by the pulse width modulation circuit 113. Based on the digital signal output from the A / D conversion circuit 112, the pulse width modulation circuit 113 generates a pulse width modulation signal having the set pulse width.

[0060] The control circuit 111 also communicates with the electronic component 300 via the digital input / output circuits 140, 141, 142, and 143. That is, the digital signals DIO0, DIO1, DIO2, and DIO3 input and output from the digital input / output circuits 140, 141, 142, and 143 are communication signals conforming to a predetermined communication standard. The predetermined communication standard may be, for example, SPI. SPI is an abbreviation for Serial Peripheral Interface. The control circuit 111 writes write data received from the personal computer 200 to the nonvolatile memory of the electronic component 300 via the digital signals DIO0, DIO1, DIO2, and DIO3, and reads the written data. The nonvolatile memory may be, for example, a MONOS memory or an EEPROM. MONOS is an abbreviation for Metal Oxide Nitride Oxide Silicon, and EEPROM is an abbreviation for Electrically Erasable Programmable Read-Only Memory.

[0061] The voltage generating circuit 1 generates a voltage VOUT using the first pulse-width modulated signal as the aforementioned pulse-width modulated signal PWMIN and outputs the generated voltage VOUT as a power supply voltage VCC. The power supply voltage VCC is supplied to digital input / output circuits 140, 141, 142, and 143, and the digital input / output circuits 140, 141, 142, and 143 operate by being supplied with the power supply voltage VCC.

[0062] The switch circuit 130 turns on / off in response to a control signal output from the control circuit 111. When the switch circuit 130 is on, the power supply voltage VCC output from the voltage generating circuit 1 is output from the writing device 100 and supplied to the electronic component 300.

[0063] The voltage generating circuit 1A generates a voltage VOUT using the second pulse-width modulated signal as the pulse-width modulated signal PWMIN and outputs the generated voltage VOUT as a write voltage VPP. When writing data to the electronic component 300, the write voltage VPP is supplied to the electronic component 300 via the digital input / output circuit 140.

[0064] According to the writing device 100 of this embodiment, the voltage generating circuits 1, 1A, which can set the output voltage with high resolution, can supply the electronic component 300 with an optimum power supply voltage VCC and write voltage VPP, thereby increasing the reliability of writing data to the electronic component 300. Furthermore, according to the writing device 100 of this embodiment, the microcontrol unit 110 generates a pulse width modulation signal to be supplied to the voltage generating circuits 1, 1A based on the fed-back power supply voltage VCC and write voltage VPP, thereby stabilizing the power supply voltage VCC and write voltage VPP, thereby increasing the reliability of writing data to the electronic component 300.

[0065] The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0066] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0067] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0068] The following can be derived from the above-described embodiment and modifications.

[0069] One aspect of the voltage generating circuit is a smoothing circuit that receives a pulse width modulated signal and smooths the pulse width modulated signal to output a voltage to a first node; a first resistor connected between the output node and a second node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a ground node; and a voltage control circuit that generates a second voltage based on a first voltage input to an input node, outputs the second voltage to the output node, and controls the second voltage so that the voltage of the second node becomes a predetermined voltage.

[0070] In this voltage generating circuit, not only is there a current path from the output node through the first and second resistors, but there is also a current path from the output node through the first and third resistors. Therefore, compared to when the latter current path does not exist, a larger current flows through the first resistor connected between the output node and the second node. Therefore, even if the high-level pulse width of the pulse-width modulated signal is increased to raise the voltage output to the first node, the voltage at the output node does not drop significantly, and the voltage at the output node is unlikely to become lower than the predetermined voltage at the second node. Therefore, with this voltage generating circuit, the setting range of the pulse width of the pulse-width modulated signal that changes the output voltage can be widened, allowing the output voltage to be set with high resolution.

[0071] One aspect of the voltage generating circuit is a capacitor connected between the output node and the ground node; The voltage control circuit The power supply may further include a regulator that compares the voltage at the second node with the predetermined voltage and switches whether or not to output the first voltage to the output node based on the comparison result.

[0072] This voltage generating circuit allows the output voltage obtained by stepping down the input voltage to be set with high resolution.

[0073] One aspect of the voltage generating circuit is an inductor connected between the input node and a third node; a diode connected between the third node and the output node; a capacitor connected between the output node and the ground node, The voltage control circuit The voltage of the second node may be compared with the predetermined voltage, and whether or not to connect the third node to the ground node may be switched based on the comparison result.

[0074] This voltage generating circuit allows the output voltage, which is obtained by boosting the input voltage, to be set with high resolution.

[0075] One aspect of the writing device is One aspect of the voltage generating circuit; a pulse width modulation circuit that generates the pulse width modulation signal and outputs it to the voltage generation circuit; The second voltage generated by the voltage generating circuit is supplied to an electronic component.

[0076] According to this writing device, the voltage generating circuit that can set the output voltage with high resolution can supply the optimum voltage to the electronic component, thereby increasing the reliability of writing data to the electronic component.

[0077] In one aspect of the writing device, The pulse width modulation circuit may generate the pulse width modulation signal based on a voltage fed back from the output node.

[0078] According to this writing device, the output voltage of the voltage generating circuit can be stabilized, thereby increasing the reliability of writing data to electronic components.

[0079] One aspect of the writing device is an A / D conversion circuit that converts the voltage fed back from the output node into a digital signal; a control circuit that sets the pulse width of the pulse width modulated signal; The pulse width modulation circuit may generate the pulse width modulation signal having the set pulse width based on the digital signal. [Explanation of symbols]

[0080] 1,1A...voltage generation circuit, 10...voltage control circuit, 11...regulator, 12...reference voltage generation circuit, 13...error amplifier, 14...MOSFET, 20...logic buffer, 30...smoothing circuit, 31...resistor, 32...capacitor, 41,42,43...resistor, 44,45...capacitor, 50...voltage control circuit, 51...DC-DC converter, 52...inductor, 53...diode, 54...reference voltage generation circuit, 55...error amplifier, 56...pulse width modulation circuit, 57...MOSFET, 100...writing device, 110...microcontroller unit, 111...control circuit, 112...A / D conversion circuit, 113...pulse width modulation circuit, 114,115...general-purpose input / output circuit, 120...reference voltage generation circuit, 130...switch circuit, 140,141,142,143...digital input / output circuit, 200...personal computer, 300...electronic component

Claims

1. a smoothing circuit that receives a pulse width modulated signal and smooths the pulse width modulated signal to output a voltage to a first node; a first resistor connected between the output node and a second node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a ground node; a voltage control circuit that generates a second voltage based on a first voltage input to an input node, outputs the second voltage to the output node, and controls the second voltage so that the voltage of the second node becomes a predetermined voltage.

2. In claim 1, a capacitor connected between the output node and the ground node; The voltage control circuit a regulator that compares the voltage of the second node with the predetermined voltage and switches whether or not to output the first voltage to the output node based on a comparison result;

3. In claim 1, an inductor connected between the input node and a third node; a diode connected between the third node and the output node; a capacitor connected between the output node and the ground node, The voltage control circuit a voltage generating circuit that compares the voltage of the second node with the predetermined voltage and switches whether or not to connect the third node to the ground node based on the comparison result;

4. a voltage generating circuit according to any one of claims 1 to 3; a pulse width modulation circuit that generates the pulse width modulation signal and outputs it to the voltage generation circuit; A writing device that supplies the second voltage generated by the voltage generating circuit to an electronic component.

5. In claim 4, The pulse width modulation circuit generates the pulse width modulation signal based on a voltage fed back from the output node.

6. In claim 5, an A / D conversion circuit that converts the voltage fed back from the output node into a digital signal; a control circuit that sets the pulse width of the pulse width modulated signal; The pulse width modulation circuit generates the pulse width modulation signal having the set pulse width based on the digital signal.

Images