Wiring board

Abstract

To improve a quality of a wiring board.SOLUTION: A wiring board 1 of an embodiment includes: a first build-up part 10; a solder resist layer 81 in contact with a first surface 10a of the first build-up part 10; and a metal post 7 protruding from the solder resist layer 81 in a direction opposite to the first surface 10a. The first build-up part 10 includes: a first insulating layer 51 constituting the first surface 10a; and a first conductor layer 41 formed on a contact surface of the solder resist layer 81 with the first surface 10a and including a first conductor pad 411. The metal post 7 includes a base plating layer 71 connected to the first conductor pad 411, and the base plating layer 71 includes: a penetrating part 711 formed in an opening 81h of the solder resist layer 81; and a pad part 712 protruding from the solder resist layer 81.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses a build-up wiring board without a core substrate, which is manufactured by alternately forming conductor layers and insulating layers on the surface of a support substrate. A metal film is provided on the surface of the support substrate, and the outermost conductor layer is formed by electrolytic plating using the metal film as a seed layer. The surface (component mounting surface) exposed by removing the support substrate is composed of an insulating layer and conductor pads embedded in the insulating layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-15869 Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board disclosed in Patent Document 1, the outermost conductor layer is formed on a metal film on the surface of a support substrate. Therefore, the desired number of conductor layers and insulating layers are sequentially formed while the individual conductor patterns in the outermost conductor layer are short-circuited. Therefore, it is considered impossible to perform electrical inspection (short-circuit check) for shorts between conductor patterns included in the outermost conductor layer that are separated by design until the support substrate and metal film are removed after the desired number of conductor layers and insulating layers are formed. Furthermore, it may not be possible to check for shorts between conductor patterns in inner conductor layers connected to conductor patterns in such outermost conductor layers. This may require visual inspection, or even if wiring boards are formed in multiple product areas on the support substrate, short-circuit checks may only be performed after the support substrate is removed and the board is separated into individual pieces. As a result, quality inspections may not be performed efficiently. Furthermore, in the wiring board of Patent Document 1, if the conductor pads exposed on the component mounting surface are arranged at a narrow pitch, it may be difficult to ensure high connection reliability between the conductor pads and the mounted components. [Means for solving the problem]

[0005] The wiring board of the present invention includes a first buildup section formed of laminated conductor layers and insulating layers and having a first surface and a second surface facing opposite each other, a solder resist layer in contact with the first surface of the first buildup section, and a metal post protruding from the solder resist layer in a direction opposite to the first surface. The first buildup section includes a first insulating layer constituting the first surface, and a first conductor layer formed on a contact surface of the solder resist layer with the first surface and including a first conductor pad, the metal post including a base plating layer connected to the first conductor pad, and the base plating layer including a penetration portion formed in an opening of the solder resist layer and a pad portion protruding from the solder resist layer.

[0006] According to the embodiment of the present invention, efficient and sufficient short-circuit checks can be performed, which is presumably contributing to improving the quality of the wiring board. In addition, the metal posts and solder resist layer can ensure good connection reliability between the conductor pads arranged at a narrow pitch and the mounted components. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring substrate according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of part II of the wiring board of FIG. [Figure 3] 1 is a plan view showing an example of an overlapping state of a metal post, a conductor pad, and a via conductor in a wiring board according to an embodiment. [Figure 4] 1. FIG. 4 is an enlarged cross-sectional view showing a modified example of a metal post in the wiring board of FIG. [Figure 5A] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5B] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5C] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5D] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5E] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5F] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5G] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5H] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5I] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5J] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5K] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 5L]1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 6] FIG. 10 is a cross-sectional view showing an example of a wiring board according to a second embodiment. [Figure 7A] FIG. 10 is a cross-sectional view showing an example of a wiring substrate according to a second embodiment during a manufacturing process. [Figure 7B] FIG. 10 is a cross-sectional view showing an example of a wiring substrate according to a second embodiment during a manufacturing process. DETAILED DESCRIPTION OF THE INVENTION

[0008] <Basic configuration of wiring board according to embodiment> Wiring boards according to embodiments of the present invention will be described with reference to the drawings. FIG. 1 illustrates a wiring board 1, which is an example of a wiring board according to an embodiment, and FIG. 2 illustrates an enlarged view of part II of the wiring board 1 in FIG. 1. Note that the wiring boards illustrated in the drawings referred to in the following description are merely examples of wiring boards according to an embodiment. The layered structure of the wiring board according to the embodiment is not limited to the layered structure of the wiring board illustrated in the drawings, and the number of conductor layers and insulating layers included in the wiring board according to the embodiment is not limited to the number of conductor layers and insulating layers included in the wiring board according to the embodiment. The wiring board according to the embodiment may include any number of insulating layers and conductor layers in addition to the insulating layers and conductor layers included in the wiring board illustrated in the drawings, and may not include all of the insulating layers and conductor layers included in the wiring board illustrated in the drawings. Note that in the drawings referred to in the following description, certain portions may be enlarged to facilitate understanding of the disclosed embodiments. Therefore, the components may not be drawn to exact proportions relative to each other in terms of size or length.

[0009] As shown in FIG. 1, the wiring board 1 includes a buildup section 10 (first buildup section) having a first surface 10a and a second surface 10b facing opposite directions, a solder resist layer 81, and metal posts 7 protruding from the solder resist layer 81 in a direction opposite to the first surface 10a of the buildup section 10. The metal posts 7 include a base plating layer 71. The solder resist layer 81 is in contact with the first surface 10a of the buildup section 10. The first surface 10a and the second surface 10b of the buildup section 10 are two main surfaces of the buildup section 10 that are perpendicular to the thickness direction of the buildup section 10 and are two surfaces of the buildup section 10 facing in opposite directions. The wiring board 1 of FIG. 1 further includes a solder resist layer 82. The surface of the wiring board 1 on which the solder resist layer 81 is provided is a component mounting surface on which components (not shown), such as semiconductor integrated circuit devices, are mounted.

[0010] The buildup section 10 is composed of conductor layers and insulating layers that are alternately stacked. In the wiring board 1 of FIG. 1, the buildup section 10 includes insulating layers 51 and 52, conductor layers 41 and 43, and via conductors 61 and 62. In the buildup section 10, a conductor layer 41 (first conductor layer), an insulating layer 51 (first insulating layer), and a conductor layer 42 (second conductor layer) are formed in this order from the first surface 10a that is in contact with the solder resist layer 81 toward the second surface 10b. Furthermore, insulating layers 52 and conductor layers 43 are alternately formed on the conductor layer 42 and on the second surface 10b side of the insulating layer 51, resulting in a total of four pairs of insulating layers 52 and conductor layers 43 being stacked. The via conductor 61 (first via conductor) of the via conductors 61 and 62 penetrates the insulating layer 51 to connect the conductor layer 41 and the conductor layer 42. Furthermore, the via conductors 62 each penetrate the insulating layer 52 to connect the conductor layer 42 to the conductor layer 43 or to connect the conductor layers 43 to each other.

[0011] Of the insulating layers 51 and 52, the insulating layer 51 constitutes the first surface 10a of the buildup section 10. Specifically, the surfaces of the insulating layer 51 and the conductor layer 41 facing the solder resist layer 81 constitute the first surface 10a. Meanwhile, the surfaces of the insulating layer 52 and the conductor layer 43, which are farthest from the first surface 10a, facing away from the first surface 10a constitute the second surface 10b of the buildup section 10.

[0012] The conductor layer 41 is embedded in the insulating layer 51. The surface of the conductor layer 41 facing the solder resist layer 81 is exposed on the first surface 10a and is in contact with the surface 81b of the solder resist layer 81. The surface 81b of the solder resist layer 81 is in contact with the first surface 10a of the buildup section 10. In other words, the surface 81b is the contact surface of the solder resist layer 81 with the first surface 10a. The insulating layer 51 and the conductor layer 41 are formed on the surface 81b of the solder resist layer 81. On the other hand, the solder resist layer 82 covers the second surface 10b of the buildup section 10.

[0013] Each of the conductor layers 41 to 43 includes an arbitrary conductor pattern. The conductor layer 41 includes a conductor pad 411 (first conductor pad). The conductor layer 42 includes conductor pads 421 and 422. The conductor pad 411 is a conductor pad known as a mounting pad or a mounting pad, which is used to connect to a component (not shown) such as a semiconductor integrated circuit device mounted on the wiring board 1. The via conductor 61 is connected to the conductor pad 411. That is, the conductor pad 411 also serves as a so-called via receiving pad for the via conductor 61.

[0014] The via conductor 61 connects the conductor pad 411 and the second conductor pads 421 and 422. The conductor pads 421 and 422 are via pads of the via conductor 61 and are each formed integrally with the via conductor 61. That is, the conductor pads 421 and 422 are formed on the surface of the insulating layer 51 facing the second surface 10b of the buildup portion 10 and are connected to the via conductor 61. The conductor pad 421 also serves as a via receiving pad for the via conductor 62.

[0015] 1 is tapered toward the conductor pad 411. That is, the via conductor 61 has a cone-like shape in which the width of the via conductor 61 gradually decreases toward the conductor pad 411. Therefore, the width of the via conductor 61 gradually decreases toward the first surface 10a of the buildup section 10. Similar to the via conductor 61, the via conductor 62 is also tapered so that the width of the via conductor 62 gradually decreases toward the first surface 10a. Therefore, the width of the via conductor 62 gradually decreases toward the first surface 10a of the buildup section 10.

[0016] The "width" of the via conductor 61 and the "width" of the via conductor 62 are the maximum distances between any two points on the periphery of each via conductor in a cross section or end face perpendicular to the axial direction. The via conductors 61 and 62 may have any planar shape. When the via conductors 61 and 62 have a substantially circular planar shape, the tapered via conductors 61 and 62 may gradually decrease in diameter toward the first surface 10a. The "planar shape" refers to the shape of an object in a planar view, and "planar view" refers to viewing the object from a line of sight along the stacking direction of the conductor layers and insulating layers of the build-up section 10.

[0017] The build-up section 10, including the via conductors 61 tapered so that their widths decrease toward the first surface 10a, is formed by sequentially forming individual conductor layers and individual insulating layers starting from the first surface 10a side in contact with the solder resist layer 81. That is, after each insulating layer is formed, through holes for forming the via conductors 61 or 62 are formed in the surface of each insulating layer opposite the first surface 10a by processing means such as laser light irradiation. Because the power of the irradiated laser light decreases with increasing distance from the light source, through holes with a smaller width are formed toward the first surface 10a. The via conductors 61 or 62 are formed by filling these through holes with a conductor. In this way, the build-up section 10 is formed by forming conductor layers and insulating layers on the surface 81b of the solder resist layer 81 from the first surface 10a side. As shown in FIG. 1 , the via conductors 61 and 62 included in the build-up section 10 thus formed have widths that decrease toward the first surface 10a side.

[0018] In the wiring board 1 of the embodiment, the conductor layer 41 is formed on the surface 81b of the solder resist layer 81 as described above. That is, the conductor layer 41 is not formed on a metal film called a seed layer, which is provided separately from the conductor layer 41 and used as a power supply layer when the conductor layer 41 is formed. Therefore, the conductor patterns, such as the conductor pads 411 of the conductor layer 41, are already insulated from each other at the time of completing the formation of the conductor layer 41 during the manufacturing process of the wiring board 1. Therefore, after the formation of the conductor layer 41, it is possible to perform an electrical inspection (short check) for shorts between individual conductor patterns, such as the conductor pads 411. Furthermore, at the time of completing the formation of the conductor layer 42, it may be possible to perform a short check between the conductor patterns of the conductor layer 42, such as the conductor pads 421, which are connected to the conductor patterns of the conductor layer 41 by the via conductors 61.

[0019] Similarly, when the formation of each conductor layer 43 is completed, it may be possible to perform a short-circuit check between the conductor patterns of each conductor layer 43 that are connected to the conductor patterns of the conductor layer 41 via the via conductors 62 and 61. Furthermore, when the formation of the build-up section 10 is completed, it may be possible to perform a short-circuit check between the conductor patterns of the conductor layer 43 exposed on the second surface 10b that are electrically connected to the conductor patterns of the conductor layer 41. Therefore, it is believed that sufficient short-circuit checks can be performed efficiently in the manufacture of the wiring board of the embodiment. It is presumed that the wiring board of the embodiment, in which sufficient short-circuit checks can be performed efficiently, has higher and better quality than conventional wiring boards.

[0020] The insulating layers 51-52 are mainly formed of any insulating resin. Examples of insulating resins used to form the insulating layers 51-52 include thermosetting resins such as epoxy resin, bismaleimide triazine resin (BT resin), and phenolic resin, as well as thermoplastic resins such as fluororesin, liquid crystal polymer (LCP), fluoroethylene (PTFE) resin, polyester (PE) resin, and modified polyimide (MPI) resin. Each of the insulating layers 51-52 may contain a filler such as silicon oxide, alumina, or mullite. The resins listed as materials for the insulating layers 51-52 are merely examples of materials that can form the insulating layers. Each insulating layer can be formed of any material that provides insulation to and supports the conductor layers 41-43.

[0021] Examples of materials for the solder resist layer 81 include polyimide resin, epoxy resin, and phenol resin. Epoxy resin is typically used as the material for the solder resist layer 81. The solder resist layer 82 may also be formed using a polyimide resin, epoxy resin, or phenol resin of the same or a different system as the resin used for the solder resist layer 81. The resin forming the solder resist layer 81 or the solder resist layer 82 may be photosensitive or thermosetting. An opening 82h is formed in the solder resist layer 82, and the conductor pads of the conductor layer 43 are exposed in the opening 82h.

[0022] The conductor layers 41-43, the via conductors 61-62, and the base plating layer 71 of the metal post 7 are each formed of any metal having appropriate conductivity. For example, copper is an example of a material that can be used to form these layers. However, the material for the conductor layers 41-43, the via conductors 61-62, and the base plating layer 71 of the metal post 7 is not limited to copper. The conductor layers 41-43, the via conductors 61-62, and the base plating layer 71 of the metal post 7 are each formed of, for example, an electroless plating film, a sputtering film, or an electrolytic plating film. Although the conductor layers 41-43, the via conductors 61-62, and the base plating layer 71 of the metal post 7 are each depicted in FIG. 1 as a simplified single layer, they may have a multilayer structure formed of two or more metal films, as shown in FIG. 2. However, the conductor layers 41-43, the via conductors 61-62, and the base plating layer 71 of the metal post 7 may each be formed of, for example, a single metal film, such as an electroless plating film.

[0023] As shown in FIG. 2, the conductor layer 41 includes a first metal film 4a located on the first surface 10a of the buildup portion 10 and a second metal film 4b formed on the surface of the first metal film 4a facing the second surface 10b (see FIG. 1) of the buildup portion 10. The first metal film 4a of the conductor layer 41 is in contact with the surface 81b of the solder resist layer 81. However, the surface 81b of the solder resist layer 81 is not in contact with the second metal film 4b of the conductor layer 41. The conductor layers 42 and 43, as well as the via conductors 61 and 61, also include the first metal film 4a located on the first surface 10a of the buildup portion 10 and the second metal film 4b formed on the surface of the first metal film 4a facing the second surface 10b of the buildup portion 10. The first metal film 4a may be an electroless plated film or a sputtered film, and the second metal film 4b may be an electrolytic plated film. Each conductor layer, such as conductor layer 41, and each via conductor, which are composed of two such metal films, can be efficiently formed to the desired thickness, and good adhesion can be obtained between each conductor layer and each via conductor and the underlying insulating layer.

[0024] An opening 81h is formed in the solder resist layer 81. The opening 81h exposes the conductor pad 411 of the conductor layer 41 from the solder resist layer 81. A metal post 7 is formed on the conductor pad 411 exposed in the opening 81h. The base plating layer 71 of the metal post 7 is connected to the conductor pad 411. In the example of FIGS. 1 and 2, the metal post 7 includes a top plating layer 72 in addition to the base plating layer. The top plating layer 72 is formed on the surface of the base plating layer 71 opposite to the solder resist layer 81 side. The base plating layer 71 includes a through portion 711 formed in the opening 81h of the solder resist layer 81 and a pad portion 712 protruding from the surface 81a of the solder resist layer 81. The surface 81a of the solder resist layer 81 is the surface of the solder resist layer 81 opposite to the build-up portion 10 side.

[0025] The through-holes 711 of the base plating layer 71 fill the openings 81h of the solder resist layer 81. The pad portions 712 of the base plating layer 71 cover the through-holes 711 and extend a predetermined distance outside the openings 81h on the surface 81a of the solder resist layer 81 beyond the outer edge of the openings 81h in a plan view. Therefore, the surface (top surface) of the pad portions 712 opposite the solder resist layer 81 and the side surfaces of the pad portions 712 are exposed and protrude from the surface 81a of the solder resist layer 81. The base plating layer 71 is composed of a third metal film 71a formed on the wall surfaces of the openings 81h and on the surface 81a of the solder resist layer 81, and a fourth metal film 71b formed on the third metal film 71a. The third metal film 71a may be an electroless plated film or a sputtered film, and the fourth metal film 71b may be an electrolytic plated film.

[0026] In the wiring board 1 of the embodiment, the metal posts 7 protruding from the surface 81a of the solder resist layer 81 are formed on the conductor pads 411, which is believed to facilitate mounting components on the wiring board 1. That is, electronic components such as semiconductor integrated circuit devices can be connected to the conductor pads 411 via the metal posts 7 protruding from the solder resist layer 81. Specifically, components to be mounted on the wiring board 1 can be placed on the top plating layer 72 of the metal posts 7. By mounting components via the metal posts 7, components can be easily mounted on the wiring board 1 while preventing short circuits caused by bonding materials such as solder between adjacent conductor pads 411.

[0027] As described above, the base plating layer 71 of the metal post 7 is formed of a metal such as copper. The base plating layer 71 is preferably formed of a metal having a melting point higher than that of a bonding material, such as solder, used to connect a component (not shown) mounted on the metal post 7. It is believed that this allows components to be mounted more stably on the wiring board 1 than metal posts formed by filling openings in a solder resist with solder balls or solder paste. In other words, it is believed that components mounted on the wiring board 1 can be stably connected to the conductor pads 411 with little tilt and little variation in height.

[0028] The top plating layer 72 includes a lower layer 721 and an upper layer 722. The lower layer 721 is formed on the pad portion 712 of the base plating layer 71 and covers the upper surface of the pad portion 712. The upper layer 722 is formed on the lower layer 721 and covers the upper surface of the lower layer 721. The lower layer 721 is formed of a metal such as nickel, but the material of the lower layer is not limited to nickel. Preferably, the lower layer 721 is formed of a metal different from the metal and material that constitute the base plating layer 71.

[0029] On the other hand, upper layer 722 may be formed of a metal such as solder that can function as a connecting material between metal post 7 and a component (not shown) mounted on wiring board 1. It is presumed that if metal post 7 contains a plating film made of a material that functions as a connecting material with the component, the amount of connecting material will be stable, allowing the component to be mounted easily and stably. Note that the material of upper layer 722 is not limited to solder, and may be gold or an alloy of gold and another metal such as palladium.

[0030] 1 and 2, the surface (top surface) of the conductor pad 411 facing the solder resist layer 81 and the surface (top surface) of the insulating layer 51 facing the solder resist layer 81 are substantially flush with each other. That is, because both the conductor layer 41 and the insulating layer 51 are formed on the surface 81b of the solder resist layer 81, a step is unlikely to occur between the top surface of the conductor pad 411 and the top surface of the insulating layer 51, and the top surfaces of the conductor layer 41 and the insulating layer 51 tend to be flush with each other. Because the top surfaces of the conductor layer 41 and the insulating layer 51 are substantially flush with each other, it is thought that voids are unlikely to occur at the interface between the conductor layer 41 or the insulating layer 51 and the solder resist layer 81. Note that "substantially flush" means that the step between the two surfaces being compared is 0.5 μm or less.

[0031] The solder resist layer 81 may have any thickness. For example, the thickness of the solder resist layer 81 is approximately 15 μm to 30 μm. On the other hand, the thickness of each of the insulating layers 51 and 52 may be approximately 7.5 μm to 15 μm. The thickness of the solder resist layer 81 may therefore be thicker than the thickness of the insulating layers 51 and 52. Even if a connecting material such as solder supplied onto the metal post 7 adheres to the solder resist layer 81, it is believed that short-circuiting between the connecting material and the conductor layer 41 can be more reliably prevented. The thickness of the insulating layer 51 is the distance from the surface of the conductor layer 41 facing the second surface 10b of the buildup portion 10 to the surface of the insulating layer 51 facing the second surface 10b.

[0032] When the thickness of the solder resist layer 81 is thicker than the thickness of the insulating layer 51, the length L7 of the through portion 711 of the base plating layer 71 is longer than the length L6 of the via conductor 61 in the stacking direction of the conductor layer 41 and the insulating layer 51. It is believed that when the length L7 of the through portion 711 is long, the through portion 711 can absorb more of the stress generated by, for example, the difference in the thermal expansion coefficient between the wiring board 1 and a component (not shown) connected to the conductor pad 411 via the metal post 7. It is also believed that when the length L6 of the via conductor 61 is short, the conductor pad 411 can be connected to the conductor pad 421 or the conductor pad 422 with smaller conductor resistance.

[0033] It is preferable that the conductive pad 411, the metal post 7, and the via conductor 61 have an appropriate size relationship with respect to the sizes of their respective parts. In the example of FIG. 2, the width (bottom width) W7b of the through portion 711 of the base plating layer 71 at the interface with the conductive pad 411 is smaller than the width (top width) W7t of the through portion 711 at the surface 81a of the solder resist layer 81. In particular, the through portion 711 in the example of FIG. 2 is tapered so that the width of the through portion 711 gradually decreases toward the conductive pad 411. On the other hand, the width (bottom width) W6b of the via conductor 61 at the interface with the conductive pad 411 is smaller than the width (top width) W6t of the via conductor 61 at the interface with the conductive pad 421 or the conductive pad 422. In particular, the via conductor 61 in the example of FIG. 2 is tapered so that the width of the via conductor 61 gradually decreases toward the conductive pad 411.

[0034] That is, the through portion 711 and the via conductor 61 of the base plating layer 71 in the example of FIG. 2 are tapered in opposite directions. It is believed that a wide contact area between the component mounted on the wiring board 1 and the metal post 7 can be ensured, while the entire surface of the through portion 711 facing the conductor pad 411 can be more reliably in contact with the conductor pad 411. It is also believed that a wide contact area with the conductor pad 421 or the conductor pad 422 can be ensured, while the entire surface of the via conductor 61 facing the conductor pad 411 can be more reliably in contact with the conductor pad 411. The "width" of the through portion 711 is the maximum distance between any two points on the periphery of the cross section or end face of the through portion 711 perpendicular to the stacking direction of the buildup section 10. The "width" of each of the conductor pads 411 and 421, which will be described later, is the maximum distance between any two points on the periphery of each conductor pad in a plan view.

[0035] Furthermore, the width W7t of the through portion 711 of the base plating layer 71 at the surface 81a of the solder resist layer 81 is larger than the width W6t of the via conductor 61 at the interface with the conductor pad 421 or the conductor pad 422. The small width W6t of the via conductor 61 at the interface with the conductor pad 421 or the conductor pad 422 may allow for high-density arrangement of wiring patterns on the conductor layer 42. On the other hand, a large connection area may be secured between the metal post 7 and a component (not shown) mounted on the wiring board 1.

[0036] 2, the width W41 of the conductor pad 411 is larger than the width W72 of the pad portion 712 of the base plating layer 71, and the width W72 of the pad portion 712 of the base plating layer 71 is larger than the width W42 of the conductor pad 421 and the conductor pad 422. Note that the "width" of each of the conductor pads 411 and 421 and the pad portion 712 is the maximum distance between any two points on the periphery of each conductor pad or pad portion 712 in a plan view.

[0037] In particular, in the wiring board 1 of the embodiment shown in FIGS. 1 and 2, as shown in FIG. 3, the entire conductor pad 421 overlaps the pad portion 712 of the base plating layer in a plan view, and the entire pad portion 712 overlaps the conductor pad 411 in a plan view. Furthermore, the entire via conductor 61 overlaps the conductor pad 411 in a plan view, and the entire through portion 711 of the base plating layer 71 overlaps the conductor pad 411 in a plan view. Note that FIG. 3 schematically shows, in a plan view, an example of the overlapping state in a plan view between the base plating layer 71 of the metal post 7, the conductor pads 411 and 421, and the via conductor 61 in the wiring board 1 of FIGS. 1 and 2. In the wiring board 1, the area of ​​the conductor pad 411 is larger than the area of ​​the pad portion 712 of the base plating layer 71 of the metal post 7. Furthermore, the area of ​​the pad portion 712 is larger than the areas of the conductor pads 421 and 422.

[0038] Because the width W41 of the conductor pad 411 is larger than the width W72 of the pad portion 712, even if there is some misalignment of the metal post 7, the metal post 7 and the conductor pad 411 can be in reliable contact with each other. Furthermore, because the width W41 of the conductor pad 411 is small, short-circuiting between the metal posts 7 to which a connecting material such as solder may be supplied can be avoided. Furthermore, because the width W72 of the pad portion 712 is larger than the width W42 of the conductor pads 421, 422, that is, because the conductor pads 421, 422 are small, it may be possible to arrange wiring patterns on the conductor layer 42 with high density.

[0039] The minimum wiring width in the conductor layers 42-43 included in the build-up section 10 may be 1 μm or more and 3 μm or less, and the minimum wiring spacing in the conductor layers 42-43 may be 1 μm or more and 3 μm or less. Wiring patterns can be arranged at high density on the conductor layers 42-43. The aspect ratio of the wiring included in the conductor layers 42-43 may be 2.0 or more and 4.0 or less. The aspect ratio of the via conductor 61 (spacing between the conductor pad 411 and the conductor pad 421 / width of the via conductor 61 at the interface with the conductor pad 421) may be 0.5 or more and 1.0 or less.

[0040] The minimum pitch of the metal posts 7 is, for example, 40 μm or more and 75 μm or less. In this case, an example of the width of each portion of the metal post 7, the width of each conductive pad, and the width of the via conductor 61 is shown below. The width W42 of the conductive pads 421, 422 is 12 μm or more and 30 μm or less, and the top width W6t of the via conductor 61 is 6 μm or more and 12 μm or less. The width W41 of the conductive pad 411 is 32 μm or more and 45 μm or less. The top width W7t of the penetrating portion 711 of the base plating layer 71 of the metal post 7 is 13 μm or more and 27 μm or less, and the width W72 of the pad portion 712 is 25 μm or more and 40 μm or less.

[0041] <Modification> 4 shows a portion of a wiring board 1a, which is a modified example of the wiring board 1 of the embodiment, corresponding to the portion shown in FIG. 2. The wiring board 1a differs from the wiring board 1 shown in FIG. 2 only in that the pad portion 712 of the base plating layer 71 of the metal post 7 is composed of a fifth metal film 71c in addition to the third metal film 71a and the fourth metal film 71b. Except for the fifth metal film 71c, the structure and components of the wiring board 1a are similar to those of the wiring board 1 of FIG. 2. Therefore, components similar to those of the wiring board 1 are assigned the same reference numerals in FIG. 2 or omitted as appropriate, and repeated explanations thereof will be omitted.

[0042] In the wiring board of the embodiment, the base plating layer 71 of the metal post 7 may have a pad portion 712 including a fifth metal film 71c, as in the wiring board 1a. Examples of the fifth metal film 71c include a sputtered film made of copper, titanium, or the like. However, a metal film made of a metal other than copper or titanium and formed by a method other than sputtering may also be used as the fifth metal film 71c. The fifth metal film 71c is bonded to a surface 81a of the solder resist layer 81, and a third metal film 71a is formed on the surface of the fifth metal film 71c opposite the solder resist layer 81. Because the fifth metal film 71c is interposed between the third metal film 71a and the solder resist layer 81, adhesion between the metal post 7 and the surface 81a of the solder resist layer 81 may be high.

[0043] <Method for manufacturing wiring board according to embodiment> With reference to FIGS. 5A to 5L, an example of a method for manufacturing a wiring board according to an embodiment will be described using wiring board 1 shown in FIG. 1 as an example.

[0044] As shown in Figure 5A, a support substrate SP is prepared, which includes a core layer GS and metal film layers ML1 and ML2 laminated on both sides of the core layer GS. The core layer GS is made of, for example, glass or glass epoxy material. The metal film layers ML1 and ML2 are single-layer or multi-layer metal films formed by electroless plating or sputtering using materials such as copper and titanium. The metal film layers ML1 and ML2 are joined together by an adhesive layer AL, which is made of, for example, an adhesive whose adhesiveness changes depending on the light received.

[0045] In the following description, the side of the support substrate SP closer to the core layer GS is also referred to as the "bottom" or "lower side," and the side farther from the core layer GS is also referred to as the "top" or "upper side." Therefore, the surface of each element constituting the wiring board that faces the support substrate SP is also referred to as the "bottom surface," and the surface that faces away from the support substrate SP is also referred to as the "upper surface."

[0046] 5A, a solder resist layer 81 is formed on the surface of the metal film layer ML2 of the prepared support substrate SP. For example, a resin film made of polyimide resin, epoxy resin, or the like is formed by supplying a photosensitive epoxy resin or polyimide resin onto the surface of the metal film layer ML2 by a method such as spraying, coating, or laminating. The solder resist layer 81 is formed by curing the resin film by irradiating it with ultraviolet light or by heat treatment.

[0047] As shown in FIG. 5B, a first metal film 4a and a second metal film 4b are formed on a surface 81b of the solder resist layer 81 opposite to the support substrate SP side. First, a first metal film 4a made of a metal such as copper is formed on the entire surface 81b of the solder resist layer 81 by electroless plating, sputtering, or the like. Then, a resist film RF is formed on the first metal film 4a by laminating a dry film. In the resist film RF, openings RF0 are formed by photolithography or the like, corresponding to formation areas of conductor patterns such as conductor pads 411 (see FIG. 5C) included in the conductor layer 41 (see FIG. 5C). Then, a second metal film 4b is formed in the openings RF0 by electrolytic plating using the first metal film 4a as a power supply layer. After the second metal film 4b is formed, the resist film RF is removed. Furthermore, portions of the first metal film 4a exposed by removing the resist film RF are removed.

[0048] As a result, as shown in FIG. 5C, a conductor layer 41 including electrically isolated conductor pads 411 is obtained at desired positions. In the manufacturing process of a wiring board according to an embodiment, such as the wiring board 1 shown in FIG. 1, a short check can be performed between conductor patterns, such as the conductor pads 411, included in the conductor layer 41 upon completion of the formation of the conductor layer 41, as shown in FIG. 5C. Specifically, in the formation of the conductor layer 41, for example, the metal film layer ML2 of the support substrate SP is not used as the power supply layer, but the first metal film 4a formed on the solder resist layer 81 is used as the power supply layer. Furthermore, portions of the first metal film 4a that do not constitute the conductor patterns of the conductor layer 41 have already been removed upon completion of the formation of the conductor layer 41. In other words, the individual conductor patterns of the conductor layer 41 are already electrically isolated from one another upon completion of the formation of the conductor layer 41. Therefore, a short check can be performed between the conductor patterns of the conductor layer 41 upon completion of the formation of the conductor layer 41, i.e., before proceeding to the next process, such as the formation of the insulating layer 51 (see FIG. 5D). Therefore, short-circuit defects can be detected early. This can reduce the man-hours and costs that would otherwise be incurred by continuing to transport in-process products containing short-circuit defects through the process, and can produce high-quality wiring boards.

[0049] As shown in FIG. 5D, an insulating layer 51 is formed to cover the conductor layer 41. The insulating layer 51 is formed of, for example, a thermosetting resin such as epoxy resin, BT resin, or phenolic resin, or a thermoplastic resin such as fluororesin or LCP. The insulating layer 51 is formed by thermocompression bonding these resins formed into a film shape. In the insulating layer 51, through holes 61a are formed at the positions where via conductors 61 (see FIG. 5G) will be formed by irradiation with, for example, a carbon dioxide laser beam or an excimer laser beam. Although not shown, the formation of the through holes 61a may be performed while protecting the upper surface of the insulating layer 51 with a protective film such as a polyethylene terephthalate (PET) film. Preferably, after the formation of the through holes 61a, resin residues (smears) that tend to form in the through holes 61a are removed by dry desmearing using plasma gas or wet desmearing using a permanganate solution.

[0050] 5D, as well as Figures 5E to 5I, 7A, and 7B, which will be referred to below, show only one surface side of the support substrate SP after each process, and the state of the other side is not shown. However, on the surface of the support substrate SP on the side not shown, each insulating layer and each conductor layer may be formed, as on the side shown in the drawings, or such conductor layers and insulating layers may not be formed.

[0051] As shown in FIG. 5E, after the through-hole 61a is formed, a first metal film 4a constituting the conductor layer 42 (see FIG. 5G) is formed on the inner wall of the through-hole 61a and on the surface of the insulating layer 51 by electroless plating, sputtering, or the like. Then, a dry film DF containing, for example, a photosensitive resin is laminated on the first metal film 4a. The dry film DF is subjected to exposure and development processes. The exposure of the dry film DF is performed, for example, by direct imaging, in which laser light LZ is irradiated along a pattern corresponding to the conductor pattern to be provided on the conductor layer 42. The exposure of the dry film DF may be performed using an exposure mask having openings corresponding to the conductor pattern to be provided on the conductor layer 42.

[0052] As a result of the development process on the exposed dry film DF, as shown in FIG. 5F, a plating resist RL having openings RO corresponding to the conductor pattern to be provided on the conductor layer 42 (see FIG. 5G) is formed.

[0053] After the plating resist RL is formed, a second metal film 4b (see FIG. 5G) made of an electrolytic plated film is formed inside the opening RO of the plating resist RL by electrolytic plating using the first metal film 4a as a power supply layer. Thereafter, the plating resist RL is removed using, for example, an alkaline stripping solution. Furthermore, the portion of the first metal film 4a exposed by the removal of the plating resist RL is removed by, for example, etching.

[0054] As a result of the partial etching of the first metal film 4a, a conductor layer 42 is obtained, which is made up of the first metal film 4a and the second metal film 4b and includes conductor pads 421 and 422, as shown in FIG. 5G. A via conductor 61 is formed inside the through hole 61a. In the manufacturing process for the wiring board of the embodiment, even after the conductor layer 42 is formed, a short check can be performed between the conductor patterns of the conductor layer 42 that are connected to the conductor patterns of the conductor layer 41, such as the conductor pad 411.

[0055] As shown in FIG. 5H, a desired number of insulating layers 52 and conductor layers 43 (four layers each in FIG. 5D) are formed, as well as via conductors 62 penetrating each insulating layer, using a method similar to that for forming insulating layers 51, conductor layers 42, and via conductors 61 described above. The formation of build-up section 10 is then completed. In the manufacturing process for the wiring board of the embodiment, even after the formation of each conductor layer 43, a short check can be performed between the conductor patterns of conductor layer 43 connected to the conductor patterns of conductor layer 41. Therefore, short-circuit defects can be detected early. This can potentially reduce the man-hours and costs that would otherwise be incurred by continuing to transport work-in-process containing short-circuit defects through the process. This also contributes to the manufacture of high-quality wiring boards.

[0056] After the desired number of conductor layers 43 are formed, a solder resist layer 82 is formed on the uppermost conductor layer 43 and the insulating layer 52. The solder resist layer 82 is formed by any method, such as spraying, laminating, or coating, using, for example, a photosensitive polyimide resin or epoxy resin. Note that the solder resist layer 82 may be formed after removing the core layer GS of the support substrate SP, which will be described below with reference to FIG. 5I, rather than immediately after forming the desired number of conductor layers 43.

[0057] As shown in FIG. 5I, the core layer GS of the support substrate SP is removed. The lower surface of the metal film layer ML2 of the support substrate SP is exposed. The core layer GS is removed, for example, by softening the adhesive layer AL by irradiation with laser light, and then peeling the metal film layer ML2 from the adhesive layer AL. Then, the metal film layer ML2 is removed by etching, and the surface 81a of the solder resist layer 81 is exposed.

[0058] As shown in FIG. 5J, an opening 81h is formed in the solder resist layer 81, and an opening 82h is formed in the solder resist layer 82. Note that FIG. 5J, as well as FIGS. 5K and 5L, are drawn so that the solder resist layer 81 is positioned on the upper side and the solder resist layer 82 is positioned on the lower side. The openings 81h and 82h are formed, for example, by photolithography including exposure and development processes, or by irradiation with laser light. The openings 81h are formed in areas where metal pads 7 (see FIG. 5L) will be formed in a later process. The openings 82h are formed in areas that expose desired areas of the conductor pads of the conductor layer 43 covered by the solder resist layer 82.

[0059] As shown in FIG. 5K, a base plating layer 71 of the metal post 7 (see FIG. 5L) is formed. The base plating layer 71 is formed, for example, by a method similar to the method for forming the conductor layer 42 described above. That is, a third metal film 71a made of, for example, copper is formed on the inner wall of the opening 81h and the entire surface 81a of the solder resist layer 81 by electroless plating, sputtering, or the like. A dry film (not shown) is then laminated on the third metal film 71a, and a plating resist is formed by forming an opening in the dry film by exposure and development in a region above the opening 81h corresponding to the region where the base plating layer 71 is to be formed. A fourth metal film 71b made of, for example, copper is formed within the opening in the plating resist by electrolytic plating using the third metal film 71a as a power supply layer. The plating resist is then removed, and the portion of the third metal film 71a exposed by the removal of the plating resist is then removed by, for example, etching. As a result, as shown in FIG. 5K, a base plating layer 71 is formed that includes the third metal film 71a and the fourth metal film 71b and fills the opening 81h.

[0060] As shown in FIG. 5L, a top plating layer 72 of a metal post 7 is formed on a base plating layer 71. For example, a lower layer 721 of the top plating layer 72 is formed on the exposed surface of the base plating layer 71 by electroless plating of a metal such as nickel. Then, an upper layer 722 of the top plating layer 72 made of a metal such as solder is formed on the lower layer 721 by electroless plating, for example. As a result, as shown in FIG. 5L, a metal post 7 is formed that includes the base plating layer 71 and the top plating layer 72 and protrudes from the solder resist layer 81. Through the above steps, the wiring board 1 of the exemplary embodiment shown in FIG. 1 is completed.

[0061] 4 is manufactured, the steps described with reference to FIGS. 5J to 5L are carried out without removing the metal film layer ML2 after removing the core layer GS of the support substrate SP as described with reference to FIG. 5I. As a result, the base plating layer 71 of the metal post 7 is formed, including a portion of the metal film layer ML2 as the fifth metal film 71c, and the wiring board 1a including such a metal post 7 is manufactured. Note that the unnecessary portion of the metal film layer ML2 may be removed, for example, by etching, together with the exposed portion of the third metal film 71a that is not covered by the fourth metal film 71b, in the step described with reference to FIG.

[0062] Second Embodiment Fig. 6 shows a cross-sectional view of a wiring board 1b of the second embodiment. As shown in Fig. 6, wiring board 1b includes buildup section 20 (second buildup section) and buildup section 30 (third buildup section) in addition to buildup section 10 (first buildup section), solder resist 81, and metal posts 7 included in wiring board 1 of Fig. 1. Buildup section 20 is composed of insulating layers 21 and conductor layers 22 that are alternately stacked. Buildup section 30 is composed of insulating layers 31 and conductor layers 32.

[0063] A buildup section 20 is laminated on the second surface 10b of the buildup section 10. A buildup section 30 is laminated on the surface of the buildup section 20 opposite the buildup section 10 side. The solder resist layer 82 is formed not on the second surface 10b of the buildup section 10 but on the surface of the buildup section 30 opposite the buildup section 10 side.

[0064] Via conductors 23 are formed in the insulating layers 21 of the buildup section 20, penetrating each insulating layer 21 and connecting opposing conductor layers via each insulating layer 21. Each conductor layer 22 may include a desired conductor pattern. Via conductors 33 are formed in the insulating layer 31 of the buildup section 30, penetrating the insulating layer 31 and connecting conductor layer 32 and conductor layer 22 of the buildup section 20. The conductor layer 32 may include a desired conductor pattern. The conductor layer 32 in the example of FIG. 6 includes a conductor pad 32p. The conductor pad 32p is exposed from an opening 82h in the solder resist layer 82.

[0065] The surface of the wiring board 1b on the build-up portion 30 side is the surface that is connected to an external member such as a motherboard of an electronic device in which the wiring board 1b is used. The conductor pads 32p may be connected to any substrate, electrical component, or mechanical component.

[0066] The insulating layer 21 constituting the buildup section 20 and the insulating layer 31 constituting the buildup section 30 may be formed using the same insulating resin as the insulating layers 51 and 52 of the buildup section 10. Although not shown, the insulating layer 21 may include a core material (reinforcing material) made of glass fiber or aramid fiber. In the example of FIG. 6, the insulating layer 31 of the buildup section 30 includes a core material 31a made of glass fiber. The insulating layer 21 and the insulating layer 31 may further include an inorganic filler (not shown) made of fine particles such as silica (SiO), alumina, or mullite. In the wiring board 1b, the thickness of the insulating layer 21 may be thicker than the thicknesses of the insulating layers 51 and 52, and the thickness of the insulating layer 31 may be thicker than the thickness of the insulating layer 21.

[0067] The conductor layers 22 and 32 and the via conductors 23 and 33 may be formed using any metal, such as copper, similar to the conductor layers of the buildup section 10, such as the conductor layer 41, and the via conductors 61 and 62. The conductor layers 22 and 32 and the via conductors 23 and 33 may each have a single layer, such as a plated film, or a multilayer structure including two or more metal films formed by any method, such as sputtering or various plating processes. For example, the conductor layers 22 and 32 may each include an electroless plated film and an electrolytic plated film on the electroless plated film. In this case, each conductor layer of the buildup section 10, such as the conductor layer 41, may include a first metal film 4a, which is a sputtered film, and a second metal film 4b, which is an electrolytic plated film formed on the first metal film 4a, as described with reference to FIG. 2.

[0068] In wiring board 1b, conductor layer 22 may be thicker than the thickness of each conductor layer in buildup section 10, such as conductor layer 41. That is, the thickness of the wiring in each conductor layer included in buildup section 10 may be smaller than the thickness of the wiring in conductor layer 22. The thickness of each conductor layer included in buildup section 10 is, for example, about 7 μm or less. The thickness of conductor layer 22 is, for example, 10 μm or more. The thickness of conductor layer 32 may be thicker than the thickness of conductor layer 22, and therefore the thickness of the wiring in conductor layer 32 may be greater than the thickness of the wiring in conductor layer 22. The thickness of conductor layer 32 is, for example, about 20 μm.

[0069] In wiring board 1b, the minimum wiring width of the wiring patterns in each conductor layer included in buildup section 10, such as conductor layer 42, may be smaller than the minimum wiring width of the wiring patterns included in conductor layer 22. Furthermore, the minimum wiring spacing between the wiring patterns included in each conductor layer included in buildup section 10 may be smaller than the minimum wiring spacing between the wiring patterns included in conductor layer 22. Therefore, wiring that requires high-density arrangement can be concentrated in conductor layer 42 of buildup section 10, and wiring can be provided in conductor layer 22 according to a more relaxed wiring rule. This may allow buildup section 20 to be formed easily and inexpensively. The minimum wiring width of the wiring patterns included in conductor layer 22 is approximately 4 μm, and the minimum wiring spacing between the wiring patterns is approximately 6 μm.

[0070] The minimum wiring width of the wiring pattern included in the conductor layer 32 of the build-up section 30 may be larger than the minimum wiring width of the wiring pattern included in the conductor layer 22 of the build-up section 20. Furthermore, the minimum wiring spacing between the wiring patterns included in the conductor layer 32 may be larger than the minimum wiring spacing between the wiring patterns included in the conductor layer 22. This may allow a large current to flow through the wiring pattern of the conductor layer 32, and may also enable the conductor layer 32 to be formed more easily and inexpensively.

[0071] In wiring board 1b, conductor layer 41 of buildup section 10 is also formed on surface 81b of solder resist layer 81. Therefore, it is possible to check for shorts between conductor pads 411 immediately after the formation of each conductor layer in buildup section 10. Also, it is possible to check for shorts between the conductor patterns of conductor layers 42 and 43 connected to each conductor pattern of conductor layer 41, such as conductor pad 411. Furthermore, in the manufacturing process of wiring board 1b, it is sometimes possible to check for shorts between the conductor patterns of conductor layer 22 or conductor layer 32 connected to each conductor pattern of conductor layer 41 immediately after the formation of each conductor layer in buildup sections 20 and 30. Therefore, it is presumed that wiring board 1b can also have higher and better quality than conventional wiring boards.

[0072] When manufacturing the wiring board 1b of the second embodiment shown in FIG. 6, after the buildup section 10 is formed to the state shown in FIG. 5H, the buildup section 20 is formed without forming the solder resist layer 82 and with the support substrate SP still attached, as shown in FIG. 7A. That is, a desired number of insulating layers 21 and conductor layers 22 are alternately stacked on the conductor layer 43 and insulating layer 52 exposed on the second surface 10b of the buildup section 10 formed to the state shown in FIG. 5H. In FIG. 7A, three pairs of insulating layers 21 and conductor layers 22 are stacked. Each insulating layer 22 has via conductors 23 formed therein, connecting the upper and lower conductor layers. The insulating layer 21 is formed, for example, by a method similar to the method for forming the insulating layer 51 described above. When forming the insulating layer 21, a resin containing a core material molded into a sheet shape, such as a prepreg, may be used instead of a film-like resin. The conductor layer 22 and the via conductors 23 are formed by any method, for example, a semi-additive method.

[0073] In the manufacturing process of the wiring board 1b, a short check may be performed between the conductor patterns of each conductor layer 22 connected to each conductor pattern of the conductor layer 41 immediately after forming the build-up portion 20 shown in FIG. 7A and / or immediately after forming each conductor layer 22.

[0074] As shown in FIG. 7B , a buildup section 30 is formed on an insulating layer 21 and a conductor layer 22 that form the surface of the buildup section 20 opposite the buildup section 10 side. First, an insulating layer 31 is formed using a method similar to that for the insulating layer 21. In the example of FIG. 7B , the insulating layer 31 is formed using a prepreg including a core material 31a made of, for example, glass fiber. A prepreg with copper foil may also be used. Through holes 33a are formed in the insulating layer 31 by irradiation with laser light or drilling at positions where via conductors 33 will be formed. Then, a conductor layer 32 is formed on the surface of the insulating layer 31, and the via conductors 33 are formed in the through holes 33a. The conductor layer 32 and the via conductors 33 are formed using an appropriate method, such as a semi-additive method or a subtractive method.

[0075] In the manufacturing process of the wiring board 1b, immediately after forming the conductor layer 32 of the build-up portion 30, a short check may be performed between the conductor patterns of the conductor layer 32 that are connected to each conductor pattern of the conductor layer 41, such as the conductor pad 411.

[0076] After the build-up portion 30 is formed, a solder resist layer 82 is formed on the surfaces of the insulating layer 31 and the conductor layer 32 using a photosensitive epoxy resin or polyimide resin. Thereafter, the core layer GS of the support substrate SP is removed, and then the metal film layer ML2 is removed, in the same manner as described with reference to Fig. 5I. Thereafter, the wiring board 1b shown in Fig. 6 is completed through the steps described with reference to Figs. 5J to 5L.

[0077] The wiring board of the embodiment is not limited to those having the structures illustrated in the drawings and the structures, shapes, and materials illustrated in this specification. As described above, the wiring board of the embodiment may have any laminated structure. The wiring board of the embodiment may have any number of conductor layers and insulating layers. The width of the conductor pad 411 may be smaller than the width of the conductor pads 421 and 422, and may be smaller than the width of the pad portion 712 of the base plating layer 71 of the metal post 7. The width of the through portion 711 of the base plating layer 71 may be smaller than the width of the via conductor 61. The through portion 711 does not have to be tapered toward the conductor pad 411. [Explanation of symbols]

[0078] 1, 1a, 1b Wiring board 10, 20, 30 Build-up section 10a First side of the build-up section 10b Second side of the build-up section 41 Conductor layer (first conductor layer) 411 Conductor pad (first conductive pad) 4a First metal film 4b Second metal film 42, 43 Conductor layer 421, 422 conductor pads (second conductor pads) 51 Insulating layer (first insulating layer) 52 Insulating layer 61, 62 Via conductor 7 metal posts 71 Base plating layer 711 Penetration 712 Pad section 72 Top plating layer 81 Solder resist layer 81a Surface of the solder resist layer opposite to the build-up portion 81b: Contact surface of the solder resist layer with the first surface of the build-up portion 81h Opening in solder resist layer L6 Via conductor length L7 Length of penetration of base plating layer of metal post W41 Width of first contact pad W42 Width of second contact pad W6b Width of the via conductor at the interface with the first conductor pad W6t Width of the via conductor at the interface with the second contact pad W7b Width of the penetration at the interface with the first conductive pad W7t Width of the penetration on the surface opposite to the build-up part in the solder resist layer W72 Width of the pad part of the base plating layer of the metal post

Claims

1. a first buildup section including laminated conductive layers and insulating layers, the first buildup section having a first surface and a second surface facing in opposite directions; a solder resist layer in contact with the first surface of the first buildup portion; a metal post protruding from the solder resist layer in a direction opposite to the first surface; A wiring board including: The first buildup portion is a first insulating layer constituting the first surface; a first conductor layer formed on a contact surface of the solder resist layer that contacts the first surface and includes a first conductor pad; Including, the metal post includes a base plating layer connected to the first contact pad; The base plating layer includes a through portion formed in an opening of the solder resist layer and a pad portion protruding from the solder resist layer.

2. 2. The wiring board according to claim 1, The first buildup portion is a second conductive pad formed on the surface of the first insulating layer on the second surface side; a via conductor passing through the first insulating layer and connecting the first conductive pad and the second conductive pad; further comprising a width of the through portion of the base plating layer at the interface with the first conductive pad is smaller than a width of the through portion of the solder resist layer at a surface opposite to the first buildup portion side; The width of the via conductor at the interface with the first conductive pad is smaller than the width of the via conductor at the interface with the second conductive pad.

3. 3. The wiring board according to claim 2, The through portion of the base plating layer and the via conductor are tapered in opposite directions.

4. 3. The wiring board according to claim 2, wherein the width of the through portion of the base plating layer at the surface of the solder resist layer is greater than the width of the via conductor at the interface with the second conductive pad.

5. 3. The wiring board according to claim 2, the width of the first conductive pad is greater than the width of the pad portion of the base plating layer; The width of the pad portion of the base plating layer is greater than the width of the second conductive pad.

6. 6. The wiring board according to claim 5, wherein the second conductive pad entirely overlaps the pad portion of the base plating layer in plan view, and the pad portion entirely overlaps the first conductive pad in plan view.

7. 3. The wiring board according to claim 2, wherein the length of the through portion of the base plating layer is longer than the length of the via conductor in the stacking direction of the first conductor layer and the first insulating layer.

8. 2. The wiring board according to claim 1, wherein the metal post further includes a top plating layer formed on the base plating layer.

9. 2. A wiring board according to claim 1, wherein the first conductor layer includes a first metal film in contact with the solder resist layer and a second metal film formed on the surface of the first metal film on the second side.

10. 2. The wiring board according to claim 1, wherein a surface of the first conductor pad facing the solder resist layer and a surface of the first insulating layer facing the solder resist layer are substantially flush with each other.

11. 2. The wiring board according to claim 1, wherein the minimum width of the wiring in the conductor layer included in the first buildup portion is 3 [mu]m or less, and the minimum spacing between the wirings is 3 [mu]m or less.

12. 2. The wiring board according to claim 1, further comprising a second buildup section including a conductor layer and an insulating layer and laminated on the second surface of the first buildup section, a minimum value of the wiring width in the conductor layer included in the first buildup portion is smaller than a minimum value of the wiring width in the conductor layer included in the second buildup portion; a minimum value of the wiring spacing in the conductor layer included in the first buildup portion is smaller than a minimum value of the wiring spacing in the conductor layer included in the second buildup portion; The thickness of the wiring in the conductor layer included in the first buildup portion is smaller than the thickness of the wiring in the conductor layer included in the second buildup portion.

13. 13. A wiring board according to claim 12, wherein the conductor layer included in the first build-up portion includes a sputtering film and an electrolytic plating film on the sputtering film, and the conductor layer included in the second build-up portion includes an electroless plating film and an electrolytic plating film on the electroless plating film.

14. 13. The wiring board according to claim 12, further comprising a third buildup section including a conductor layer and an insulating layer and laminated on a surface of the second buildup section opposite to the first buildup section side, a thickness of the wiring in the conductor layer included in the third buildup portion is greater than a thickness of the wiring in the conductor layer included in the second buildup portion; The insulating layer included in the third buildup section includes a core material.

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