Method for manufacturing nitride semiconductor laminate, and nitride semiconductor laminate

Abstract

To provide a method for manufacturing a nitride semiconductor laminate having high electrical properties, and the nitride semiconductor laminate.SOLUTION: A method for manufacturing a nitride semiconductor laminate comprises the steps of: forming a ground layer formed of AlxGa(1-x)N(0.5≤x≤1) on an Al containing nitride semiconductor substrate while supplying silicon gas as material gas using an organic metal vapor phase deposition method; and forming a GaN layer on the ground layer at a growth rate of 0.5 μm / hr or more and 2.0 μm / hr or less in the environment of a temperature of 600°C or more and 900°C or less and a pressure of 20 mbar or more and 200 mbar or less while supplying trimethyl gallium gas as material gas using the organic metal vapor phase deposition method. Thereby, the ground layer formed on the nitride semiconductor substrate and formed of AlxGa(1-x) N (0.5≤x≤1) containing Si of 1×1019 cm-3 or more and 1×1020 cm-3 or less improves electrical properties.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a nitride semiconductor stack and the nitride semiconductor stack. [Background technology]

[0002] In general power devices using nitride semiconductor laminates, an AlGaN barrier layer is provided on a GaN substrate (for example, Patent Document 1). Also, in order to increase the breakdown voltage of power devices, a method has been disclosed in which a nitride semiconductor laminate is grown on an AlN substrate with a wider band gap to create a power device (for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-49121 [Non-patent literature]

[0004] [Non-Patent Document 1] Sumitomo Electric Technical Review No. 180, Page 83 (2012) Summary of the Invention [Problem to be solved by the invention]

[0005] In nitride semiconductor laminates, when the miscut angle of the substrate is large, at 0.1 degrees or more, each layer of the semiconductor laminate formed on the substrate tends to relax, which can sometimes introduce new threading dislocations into the nitride semiconductor laminate. On the other hand, even when the miscut angle of the substrate is small, at less than 0.1 degrees, relaxation of the layers formed on the substrate is less likely to occur, but the problem still arises that the electrical properties of the nitride semiconductor laminate fall short of the required level. An object of the present disclosure is to provide a method for manufacturing a nitride semiconductor stack having excellent electrical properties, and a nitride semiconductor stack. [Means for solving the problem]

[0006] In order to solve the above-described problems, in a method for manufacturing a nitride semiconductor laminate according to one aspect of the present disclosure, an Al layer is deposited on a nitride semiconductor substrate containing Al by metal organic chemical vapor deposition while supplying silicon gas as a source gas. x Ga (1-x) The method includes the steps of forming an underlayer made of N (0.5≦x≦1), and forming a GaN layer on the underlayer at a growth rate of 0.5 μm / hr to 2.0 μm / hr using metal organic chemical vapor deposition in an environment where the temperature is 600°C to 900°C and the pressure is 20 mbar to 200 mbar, while supplying trimethylgallium gas as a source gas.

[0007] Furthermore, a nitride semiconductor stack according to another aspect of the present disclosure includes a nitride semiconductor substrate containing Al; It is placed on a nitride semiconductor substrate and Si is 1×10 19 cm -3 More than 1×10 20 cm -3 Al including x Ga (1-x) The semiconductor device includes an underlayer made of N (0.5≦x≦1) and a GaN layer disposed on the underlayer. It should be noted that the above summary of the invention does not list all of the features of the invention according to the present disclosure. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a method for manufacturing a nitride semiconductor stack having excellent electrical properties, and a nitride semiconductor stack having excellent electrical properties. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to an embodiment of the present invention. [Figure 2A] 1 is a TEM image of a vertical cross section of a conventional nitride semiconductor stack. [Figure 2B]1 is a TEM image of a vertical cross section of a nitride semiconductor stack according to an embodiment of the present invention. [Figure 3A] FIG. 2 is a perspective view illustrating a step-terrace structure formed on the surface of the underlayer of the nitride semiconductor stack according to the embodiment. [Figure 3B] 3 is a top view for schematically explaining a step-terrace structure formed on the surface of the underlayer of the nitride semiconductor laminate according to the embodiment. FIG. [Figure 4] 3 is a cross-sectional view schematically illustrating a step-terrace structure formed on the surface of the underlayer of the nitride semiconductor stack according to the embodiment. FIG. [Figure 5A] 1 is an AFM image showing an example of a step-terrace structure on the surface of an underlayer of a nitride semiconductor laminate according to an embodiment of the present invention. [Figure 5B] 10 is an AFM image showing another example of a step-terrace structure on the surface of the underlayer of the nitride semiconductor stack according to the embodiment. [Figure 6] 1 is an AFM image showing the structure of the surface (GaN layer surface) of the nitride semiconductor laminate according to this embodiment. [Figure 7] FIG. 10 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 8] 10 is an AFM image showing a step-terrace structure on the surface (surface of the electron barrier layer) of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 9A] FIG. 1 is an energy band diagram of a conduction band and a valence band in a conventional nitride semiconductor stack. [Figure 9B] FIG. 2 is an energy band diagram of the conduction band and the valence band in the nitride semiconductor stack according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 11] FIG. 10 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 12] FIG. 10 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 13]1 is a cross-sectional view showing an example of the configuration of a high electron mobility transistor (HEMT), which is an example of a power device using the nitride semiconductor stack according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The nitride semiconductor stack according to the present disclosure will be described below through embodiments, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. Furthermore, in the following description, "up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship of surfaces, films, substrates, etc., and do not limit the technical idea of ​​the present disclosure. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up."

[0011] 1. First embodiment A nitride semiconductor stack according to a first embodiment of the present disclosure will be described with reference to Fig. 1 to Fig. 6. The nitride semiconductor stack according to the first embodiment is used in a power device such as a high electron mobility transistor (HEMT) device. The nitride semiconductor stack according to the first embodiment will be described below.

[0012] (1.1) Structure of nitride semiconductor laminate A nitride semiconductor stack 1 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view schematically showing the configuration of a vertical cross section of the nitride semiconductor stack 1 according to this embodiment. The nitride semiconductor laminate 1 includes a nitride semiconductor substrate (hereinafter referred to as substrate) 11 containing Al, an underlayer 12 disposed on the substrate 11, and a GaN layer 13 disposed on the underlayer 12. The underlayer 12 contains Si at a concentration of 1×10 19 cm -3More than 1×10 20 cm -3 Al including x Ga (1-x) It is formed by N (0.5≦x≦1). Hereinafter, each layer of the nitride semiconductor laminate 1 (substrate 11, and underlying layer 12 and GaN layer 13, which are semiconductor laminate portions formed thereon) will be described in detail.

[0013] <Nitride semiconductor substrate> Substrate 11 includes an Al-containing nitride semiconductor. The Al-containing nitride semiconductor is, for example, an Al-containing nitride semiconductor such as AlGaN or AlN, and is preferably AlN. When substrate 11 is a nitride semiconductor single crystal substrate such as AlN or AlGaN, the difference in lattice constant with the nitride semiconductor layer formed on the substrate 11 is small, and threading dislocations can be reduced by growing the nitride semiconductor layer in a lattice-matched system, which is preferable, and an aluminum nitride single crystal substrate is more preferable.

[0014] Here, the "comprises" in the expression "substrate 11 comprises a nitride semiconductor" means that the nitride semiconductor is mainly contained in the layer, but this expression also includes cases where other elements are contained. Specifically, this expression also includes cases where the composition of this layer is slightly modified by adding small amounts of other elements (for example, elements such as Ga (when Ga is not the main element), In, As, P, or Sb in a few percent or less). The wording "comprises" has a similar meaning when describing the composition of other layers. Furthermore, the small amounts of elements contained are not limited to those described above.

[0015] The substrate 11 may be doped n-type or p-type with donor impurities or acceptor impurities, and may be a mixed crystal of a nitride semiconductor such as AlN and sapphire (Al2O3), Si, SiC, MgO, Ga2O3, ZnO, GaN, or InN.

[0016] For example, the substrate 11 preferably has a film thickness of 100 μm or more and 600 μm or less. The plane orientation may be c-plane (0001), a-plane (11-20), m-plane (10-10), etc., with the c-plane substrate being more preferred.

[0017] The miscut angle of the substrate 11 is preferably 0.1 to 0.4 degrees. By providing the underlayer 12 described below, it becomes possible to form each layer of the lattice-matched semiconductor laminate on the upper layer of the substrate 11, even when the substrate 11 has a large miscut angle of 0.1 degrees or more. This improves the electrical characteristics of a device formed using the nitride semiconductor laminate 1. The miscut direction of the substrate 11 is preferably the <10-10> direction, which allows a step-terrace structure, in which steps, which are level differences in the <10-10> direction, and flat terraces are repeated, to be exposed on the surface of the uppermost layer of the nitride semiconductor stack 1.

[0018] <Underlayer> The underlayer 12 is Al x Ga (1-x) N (0.5≦x≦1), that is, Al with an Al composition of 50% or more and 100% or less x Ga (1-x) The base layer 12 is a nitride semiconductor layer formed of N and contains a predetermined amount of Si as an impurity. The base layer 12 is formed on the entire surface of the substrate 11. That is, the base layer 12 is provided between the substrate 11 and a GaN layer 13, which will be described later. Here, for example, the word "on" in the expression "underlayer 12 is formed on substrate 11" means that underlayer 12 is formed on one surface of substrate 11. The above expression also includes the case where another layer exists between substrate 11 and underlayer 12. The word "on" has a similar meaning in the relationship between other layers. For example, the case where another layer is formed between substrate 11 and underlayer 12 is also included in the expression "underlayer 12 is formed on substrate 11."

[0019] Underlayer 12 can recover pits and polishing marks formed on the surface of the substrate. Also, the difference in lattice constant and thermal expansion coefficient between underlayer 12 and GaN layer 13 is small, allowing a nitride semiconductor layer with few defects to be grown on underlayer 12. Underlayer 12 also allows GaN layer 13 to be grown under compressive stress, suppressing the occurrence of cracks in GaN layer 13. Therefore, even when substrate 11 is formed of a nitride semiconductor such as AlN or AlGaN, a nitride semiconductor layer with few defects can be grown above substrate 11 via underlayer 12.

[0020] The underlayer 12 is formed by depositing Si at 1×10 19 cm -3 More than 1×10 20 cm -3 Contains the following: 3 x 10 19 cm -3 More than 6 x 10 19 cm -3 It is preferable that the underlayer 12 contains Si in an amount of 1×10 19 cm -3 More than 1×10 20 cm -3 By including the following, the electrical properties of the nitride semiconductor stack 1 are improved. Al x Ga (1-x) When a GaN layer 13 is formed on an underlayer 12 made of N (0.5≦x≦1) (see FIG. 1), a two-dimensional hole gas (2DHG), which is a two-dimensional carrier gas, is formed at the interface between the underlayer 12 and the GaN layer 13. Two-dimensional carrier gases such as two-dimensional hole gas (2DHG) have high saturated mobility, which allows for high-frequency characteristics. Furthermore, power devices can be obtained that combine low on-resistance due to high mobility with high breakdown voltage characteristics due to a wide band gap. Here, the on-resistance is determined by the mobility and carrier concentration of the two-dimensional carrier gas. A lower sheet resistance, which includes both the mobility and carrier concentration parameters mentioned above, is advantageous for reducing the on-resistance. Furthermore, the breakdown voltage is determined by the band gap of the nitride semiconductors that make up the HEMT, a device using a nitride semiconductor stack. By including a predetermined amount of Si in underlayer 12, the interface between underlayer 12 and GaN layer 13 formed on underlayer 12 becomes steep. This improves the carrier mobility of the two-dimensional hole gas (2DHG) formed at the interface between underlayer 12 and GaN layer 13, thereby improving the electrical characteristics.

[0021] The underlayer 12 is formed by metal organic chemical vapor deposition while supplying silicon gas as a source gas. 19 cm -3 More than 1×10 20 cm -3 It is formed by adjusting it so that it includes the following. 2A is a TEM (Transmission Electron Microscope) image of a vertical cross section of the nitride semiconductor stack 1 including the thus formed underlayer 12. Fig. 2 also shows a TEM image in the case where an electron barrier layer (described in detail in Modification 1 below) is formed on the GaN layer 13. As shown in FIG. 2A, the interface between the underlayer 12 and the GaN layer is clearly visible because the underlayer 12 contains a predetermined amount of Si. That is, it can be seen that a diffusion layer containing Al and Ga is not formed at the interface between the underlayer 12 and the GaN layer 13, which would be formed by Al from the underlayer 12 diffusing into the GaN layer 13 and Ga from the GaN layer 13 diffusing into the underlayer 12. Note that this does not mean that no diffusion layer is formed at all; rather, a trace amount of Al or Ga may be diffused. In this embodiment, a diffusion layer containing Al and Ga with a thickness of 1 nm or less is considered to be "no diffusion layer formed." Note that the diffusion layer containing Al and Ga is preferably 1 nm or less, but is preferably thinner, e.g., 0.5 nm or less. This reduces the number of misfit dislocations present at the interface between the underlayer 12 and the GaN layer 13. The reduction in misfit dislocations increases the mobility of two-dimensional hole gas (2DHG) generated at the interface between the underlayer 12 and the GaN layer 13, further improving the electrical characteristics. From the viewpoint of electrical properties, it is preferable that the interface between GaN layer 13 and underlayer 12 does not have misfit dislocations in the same direction as the miscut direction of substrate 11 .

[0022] For comparison, Figure 2B shows a TEM image of a longitudinal section of a nitride semiconductor stack including a Si-free underlayer. Between the Si-free underlayer and the GaN layer shown in Figure 2B, an unintended diffusion layer containing Al and Ga is formed. This is due to the diffusion of Al from the underlayer into the GaN layer and Ga from the GaN layer into the underlayer. The boundary between the underlayer and the GaN layer is therefore not as clearly defined as in Figure 2A. In such a nitride semiconductor stack, many misfit dislocations occur between the underlayer and the GaN layer, which can lead to degraded electrical properties.

[0023] Alternatively, underlayer 12 may be formed in an environment with a temperature lower than conventional levels, between 600°C and 1000°C, and a pressure lower than conventional levels, between 50 mbar and 500 mbar. As a result, as shown in Fig. 3A , a step-terrace structure is revealed on the surface of underlayer 12, in which steps ST, which are stepped portions, and flat terraces TE are repeated in the miscut direction (<10-10> direction) of substrate 11, and in which terrace ends ETE, which are the ends of terraces TE, have amplitude in the miscut direction (<10-10> direction) of substrate 11 and are wavy extending in the direction (<11-20> direction) perpendicular to the miscut direction (<10-10> direction) of substrate 11. When underlayer 12 is formed in an environment of a temperature of 600°C to 1000°C and a pressure of 50 mbar to 500 mbar, and has a step-terrace structure on its surface with wavy terrace edges, even when substrate 11 has a large miscut angle of 0.1 degree or more, the layers of the semiconductor laminate formed on substrate 11 are less likely to relax, and new threading dislocations are less likely to be introduced into nitride semiconductor laminate 1. Therefore, by having such underlayer 12, it is possible to improve the electrical characteristics even when using a substrate 11 with a large miscut angle, which is prone to degraded electrical characteristics.

[0024] The following describes the step-terrace structure formed on the underlayer 12, which is formed under an environment of a temperature of 600°C to 1000°C and a pressure of 50 mbar to 500 mbar. FIG. 3A is a perspective view schematically showing the step-terrace structure formed on the surface of the underlayer 12, and FIG. 3B is a top view of the step-terrace structure shown in FIG. 3A. FIG. 4 is a cross-sectional view showing the AA cross section shown in FIG. 3B, which schematically shows a longitudinal cross section of the step-terrace structure in the miscut direction of the substrate 11. Here, atoms are schematically shown as circles in FIG. 4. A step ST is a step portion of one or more atoms, and a terrace TE is an atomic alignment site. In the step-terrace structure, for example, two terraces TE are connected by a step ST. In this embodiment, a terrace end ETE is a convex end portion formed by the terrace TE and the step ST connected to the terrace TE. The step-terrace structure formed on the surface of the underlayer 12 can be confirmed from an image formed by, for example, an atomic force microscope (AFM) or a scanning probe microscope (SPM) such as a scanning tunneling microscope (STM). Furthermore, the height of the steps ST and the width of the terraces TE of the step-terrace structure can be confirmed from, for example, the cross-sectional profile of the AFM image or the STM image. It should be noted that the step-terrace structures shown in FIGS. 3A and 3B and FIG. 4 are diagrammatically illustrated structures, and the step-terrace structures that are actually formed do not necessarily conform to the diagrams.

[0025] 5A, the step-terrace structure on the surface of the underlayer 12 when the underlayer 12 is formed in an environment of, for example, 1100° C. or higher and 1250° C. or lower will be described. Fig. 5A is an AFM (Atomic Force Microscopy) image of the surface of the underlayer 12 formed at a temperature of 1100° C. or higher and 1250° C. or lower during the formation of the underlayer 12. 5A, a step-terrace structure is exposed on the surface of the underlayer 12 formed in an environment at a temperature of 1100° C. or higher and 1250° C. or lower, in which steps ST, which are level differences, and flat terraces TE are repeated in the miscut direction (<10-10> direction) of the substrate 11. In this case, the terrace edges of the step-terrace structure are substantially linear. 5B is an AFM image of the surface of underlayer 12 formed on a substrate with a miscut angle of 0.2 degrees under an environment with a temperature of 600° C. to 1000° C. and a pressure of 50 mbar to 500 mbar. As described above, underlayer 12 formed under an environment with a temperature of 600° C. to 1000° C. and a pressure of 50 mbar to 500 mbar has a wavy terrace edge in the step-terrace structure.

[0026] As described above, the terrace width WTE (the width between steps ST in the miscut direction (<10-10> direction) of substrate 11 in FIGS. 3B and 4) of the step-terrace structure having wavy terrace edges ETE exposed on the surface of underlayer 12 is preferably 50 nm or more and 150 nm or less. This makes it possible to form underlayer 12 and each nitride semiconductor layer formed above underlayer 12 that are pseudo-lattice matched to substrate 11, i.e., have a lattice constant that is approximately equal to that of substrate 11, even when using a substrate 11 with a large miscut angle of 0.1 degree or more.

[0027] Furthermore, the distance W1 between adjacent peaks (for example, P1 and P2 shown in FIG. 3B) of the wavy terrace edge ETE is preferably 300 nm or more and 800 nm or less. Furthermore, it is preferable that the distance W2 of a perpendicular line L3 drawn between a first straight line L1 connecting two peaks (e.g., P1 and P2 shown in FIG. 3B) of the wavy terrace end ETE and a second straight line L2 connecting two valleys (e.g., P3 and P4 shown in FIG. 3B) of the wavy terrace end ETE is not less than 50 nm and not more than 150 nm. Further, it is preferable that the angle θ formed by one peak (e.g., P2 shown in FIG. 3B) of the wavy terrace edge ETE and two adjacent valleys (e.g., P3 and P4 shown in FIG. 3B) sandwiching this peak is 60 degrees or more and 120 degrees or less. Thereby, even when the misalignment angle of the substrate 11 is as large as 0.1 degrees or more, it becomes possible to form the underlying layer 12 having a lattice constant that is pseudo-lattice-matched with the substrate 11, that is, substantially the same as the lattice constant of the substrate 11, and each nitride semiconductor layer formed on the upper layer of the underlying layer 12, and further improvement in electrical characteristics can be obtained.

[0028] The underlying layer 12 may contain impurities such as C, B, O, H, Si, Fe, and Mg. When AlN is used as the formation material of the substrate 11, since the underlying layer 12 and the substrate 11 are formed of the same material, the boundary between the underlying layer 12 and the substrate 11 becomes unclear. When the substrate 11 is formed of AlN, the substrate 11 may be regarded as constituting the substrate 11 and the underlying layer 12.

[0029] The underlying layer 12 has a thickness of, for example, several μm or less. Specifically, the thickness of the underlying layer 12 is preferably greater than 10 nm and less than 1 μm, and more preferably 50 nm or more and 200 nm or less. When the thickness of the underlying layer 12 is greater than 10 nm, the recovery of the substrate surface progresses and the crystallinity of AlN increases. Also, when the thickness of the underlying layer 12 is 50 nm or more, the effect of forming a nitride semiconductor layer having a lattice constant substantially the same as the lattice constant of the substrate 11 becomes higher. Further, from the viewpoint of raw material cost, it is preferable that the thickness of the underlying layer 12 is less than 1 μm, and more preferably 200 nm or less.

[0030] <GaN layer> GaN layer 13 is formed on underlayer 12. GaN layer 13 is formed by metal-organic vapor phase epitaxy at a growth rate of 0.5 μm / hr to 2.0 μm / hr while supplying trimethylgallium gas as a source gas in an environment of a temperature of 600°C to 900°C, which is lower than conventional temperatures (for example, about 1000°C), and a pressure of 20 mbar to 200 mbar. In the nitride semiconductor stack 1 of this embodiment, GaN layer 13 is the uppermost layer, forming the surface of nitride semiconductor stack 1. By forming the GaN layer 13 in this manner, the energy of Ga adsorbed on the step edges changes, and the amount of impurities contained changes, improving the crystal quality, and therefore the electrical characteristics.

[0031] The step-terrace structure exposed on the upper surface of GaN layer 13 is formed when GaN layer 13 is formed on underlayer 12 having a step-terrace structure, and the step-terrace structure of underlayer 12 is maintained up to the upper surface of GaN layer 13. For example, if a step-terrace structure with linear terrace edges ETE is formed on the surface of underlayer 12, a step-terrace structure with linear terrace edges ETE will also be exposed on the upper surface of GaN layer 13. Furthermore, if a step-terrace structure with corrugated terrace edges ETE is formed on the surface of underlayer 12, a step-terrace structure with corrugated terrace edges ETE will also be exposed on the upper surface of GaN layer 13.

[0032] As an example, Fig. 6 shows an AFM image of the surface of GaN layer 13, which is the surface of nitride semiconductor stack 1 in which GaN layer 13 formed under the above-mentioned conditions is provided on underlayer 12 formed under an environment with a temperature of 600°C to 1000°C and a pressure of 50 mbar to 500 mbar. As shown in Fig. 6, a step-terrace structure with wavy terrace edges is formed on the surface of GaN layer 13, similar to underlayer 12. Note that the step-terrace structure formed on the surface of GaN layer 13 and the step-terrace structure formed on the surface of underlayer 12 may not completely match.

[0033] That is, the step-terrace structure formed on the surface of the GaN layer 13, like the underlayer 12, has a repeating pattern of step STs and flat terraces TEs in the miscut direction (<10-10> direction) of the substrate 11, and the end of the terrace TE, the terrace end ETE (the boundary between the terrace TE and the step ST in top view), has an amplitude in the miscut direction (<10-10> direction) of the substrate 11 and forms a wave-like step-terrace structure extending in a direction (<11-20> direction) perpendicular to the miscut direction (<10-10> direction) of the substrate 11. In this way, in the nitride semiconductor stack 1 in which a step-terrace structure of a predetermined structure is exposed on the surface of the GaN layer 13, which is the surface of the nitride semiconductor stack 1, the mobility and carrier concentration are improved, thereby reducing the sheet resistance and resulting in further improved electrical characteristics.

[0034] Al constituting the underlayer 12 x Ga (1-x) N (0.5≦x≦1) and the GaN that makes up the GaN layer 13 each have spontaneous polarization, which is polarized in the c-axis direction. When layers with different polarizations are stacked, a charge equal to the difference in polarization is generated at the interface. In addition, piezoelectric polarization occurs due to lattice distortion. This piezoelectric polarization and spontaneous polarization induce carriers in the semiconductor layer, forming a highly concentrated sheet-like two-dimensional carrier layer at the interface.

[0035] AlN (Al composition is 100% x Ga (1-x) When GaN layer 13 is formed on underlayer 12 formed of N, a two-dimensional hole gas (2DHG) which is a two-dimensional carrier gas is formed at the interface between underlayer 12 and GaN layer 13. Two-dimensional carrier gases have high saturated mobility, which allows for high-frequency characteristics. Furthermore, power devices can be obtained that combine low on-resistance due to high mobility with high breakdown voltage characteristics due to a wide band gap. Here, the on-resistance is determined by the mobility and carrier concentration of the two-dimensional carrier gas. Lower sheet resistance, which includes both the mobility and carrier concentration parameters mentioned above, is advantageous for reducing on-resistance. Furthermore, breakdown voltage is determined by the band gap of the nitride semiconductors that make up the HEMT, a device using a nitride semiconductor stack.

[0036] The generation of such two-dimensional carrier gas is affected by polarization, i.e., strain. To form this two-dimensional hole gas (2DHG) with higher concentration and higher mobility, the influence of alloy scattering must be taken into consideration. s Ga (1-s) When an N layer is used, if the Al composition is too high, the mobility will be significantly reduced due to alloy scattering. Furthermore, when the nitride semiconductor laminate 1 is used to form a power device, it is preferable that the layer provided on the underlayer 12 does not contain Al, from the viewpoint of achieving both a high two-dimensional hole gas (2DHG) concentration and high mobility. For this reason, it is preferable to provide a GaN layer 13 on the underlayer 12.

[0037] In order to increase the concentration of the two-dimensional hole gas (2DHG), the abruptness of the interface is important, and from that viewpoint, the thickness of the GaN layer 13 is preferably 0.5 nm or more and 30 nm or less. The relaxation rate of GaN layer 13 is preferably 0% or more and 5% or less.

[0038] From the viewpoint of improving carrier mobility, it is preferable that there are no misfit dislocations in the miscut direction (e.g., the <10-10> direction) of substrate 11 at the interface between GaN layer 13 and underlayer 12. Here, in this disclosure, "there are no misfit dislocations" means that the dislocation density measured by the method described below is less than 1 / μm. The presence of misfit dislocations has the effect of alleviating strain, but they also impair the quality of the crystal, resulting in a decrease in the quality of the two-dimensional hole gas (2DHG). Therefore, it is preferable that misfit dislocations do not exist in horizontal planes. The two-dimensional hole gas (2DHG) has high mobility, which allows a power device such as a HEMT using the nitride semiconductor laminate 1 to obtain high frequency characteristics. For this reason, high-quality crystallinity and interface abruptness are desired in the nitride semiconductor laminate 1.

[0039] From the viewpoint of increasing the mobility of the two-dimensional hole gas (2DHG), the coverage of the GaN layer 13 with respect to the layer immediately below is preferably 80% or more and 100% or less. From the viewpoint of high crystal quality, the dislocation density in the GaN layer 13 is 1×10 4 cm -3 It is preferable that: From the viewpoint of interface abruptness, the surface root-square roughness of the surface of GaN layer 13 is preferably 0.9 nm or less. Here, the surface root-square roughness of GaN layer 13 is the surface root-square roughness of the surface of GaN layer 13 opposite to substrate 11. This allows the realization of a high-concentration, high-mobility two-dimensional hole gas (2DHG).

[0040] The GaN layer 13 may contain impurities such as group V elements other than N, such as P, As, and Sb, and C, H, F, O, Be, Mg, Zn, and Si, but the types of impurity elements are not limited to these.

[0041] (1.2) Variations (1.2.1) Variation 1 A nitride semiconductor stack 1A of Modification 1 will be described with reference to Fig. 7 to Fig. 9B. Fig. 7 is a cross-sectional schematic diagram showing a cross section of the nitride semiconductor stack 1A, and Fig. 8 is an AFM image showing the surface shape of the nitride semiconductor stack 1A. Fig. 9A is an energy band diagram of the conduction band and valence band in a nitride semiconductor stack using an underlayer that does not contain Si, and Fig. 9B is an energy band diagram of the conduction band and valence band in the nitride semiconductor stack 1 using the underlayer 12 that contains the above-mentioned predetermined amount of Si.

[0042] 7, the nitride semiconductor stack 1A includes a substrate 11, an underlayer 12, a GaN layer 13, and an electron barrier layer 14 provided on the GaN layer 13. That is, the nitride semiconductor stack 1A differs from the nitride semiconductor stack 1 according to the first embodiment in that the nitride semiconductor stack 1A further includes the electron barrier layer 14 on the GaN layer 13. The following describes in detail the electron barrier layer 14. Note that, in the nitride semiconductor stack 1A, the substrate 11, the underlayer 12, and the GaN layer 13 are the same as the layers constituting the nitride semiconductor stack 1, and therefore descriptions thereof will be omitted.

[0043] <Electron barrier layer> The electron barrier layer 14 is a layer provided for forming a two-dimensional electron gas (2DEG) that serves as a two-dimensional carrier layer at the interface with, for example, the GaN layer 13. In the nitride semiconductor stack 1A of Modification 1, the electron barrier layer 14 is the uppermost layer, which forms the surface of the nitride semiconductor stack 1A. Fig. 8 shows an AFM image of the surface of the electron barrier layer 14, which is the surface of the nitride semiconductor laminate 1A. As shown in Fig. 8, the surface of the electron barrier layer 14, like the underlayer 12, has a stepped portion, that is, a step ST, and a flat terrace TE repeated in the miscut direction (<10-10> direction) of the substrate 11, and the end of the terrace TE, that is, the terrace end ETE (the boundary between the terrace TE and the step ST in the top view), has an amplitude in the miscut direction (<10-10> direction) of the substrate 11 and forms a wave-like step-terrace structure extending in the direction (<11-20> direction) perpendicular to the miscut direction (<10-10> direction) of the substrate 11. The step-terrace structure formed on the surface of the electron barrier layer 14 and the step-terrace structure formed on the surface of the underlayer 12 may not be completely identical to each other.

[0044] The electron barrier layer 14 is a layer of a nitride semiconductor containing Al and Ga or Al. From the viewpoint of increasing the carrier concentration, the electron barrier layer 14 is made of Al. y Ga (1-y) Al formed with N (0.7≦y≦1) y Ga (1-y) Preferably, the electron barrier layer 14 is an N layer. The electron barrier layer 14 may also contain impurities such as Group III atoms other than Al and Ga, such as In, Group V elements other than N, such as P, As, and Sb, and C, H, F, O, Be, Mg, Zn, and Si, but the types of impurity elements are not limited to these.

[0045] On the GaN layer 13, an Al is formed as an electron barrier layer 14. y Ga (1-y) When an N layer (0.7≦y≦1, for example, an AlN layer) is stacked, a two-dimensional electron gas (2DEG) is formed at the interface between the GaN layer 13 and the electron barrier layer 14. From the viewpoint of two-dimensional electron gas (2DEG) formation, it is preferable that the Al composition y in the electron barrier layer 14 is larger than the Al composition x in the GaN layer 13 (y>x). Furthermore, if the difference between the Al composition x in the GaN layer 13 and the Al composition y in the electron barrier layer 14 is smaller than 0.5, cracks may occur in the GaN layer 13 and the electron barrier layer 14. For this reason, it is preferable that the difference between the Al composition x in the GaN layer 13 and the Al composition y in the electron barrier layer 14 is larger than 0.5.

[0046] The thickness of the electron barrier layer 14 is preferably, for example, 2 nm or more and 30 nm or less. When the thickness of the electron barrier layer 14 is 2 nm or more, a sufficient two-dimensional electron gas (2DEG) layer can be formed between the GaN layer 13 and the electron barrier layer 14, further improving the electrical characteristics of the nitride semiconductor stack 1A. When the thickness of the electron barrier layer 14 is 30 nm or more, the resistance of the electron barrier layer 14 is high, making it difficult to make sufficient contact with the two-dimensional electron gas (2DEG).

[0047] The characteristics of nitride semiconductor stack 1A, which uses an aluminum nitride single crystal substrate as substrate 11 and includes underlayer 12 formed of AlN to a thickness of 900 nm under the conditions of this embodiment, GaN layer 13 to a thickness of 15 nm, and electron barrier layer 14 formed of AlN to a thickness of 7.5 nm, are compared with the characteristics of a conventional nitride semiconductor stack in which the underlayer is formed in a conventional high-temperature environment. In the nitride semiconductor stack 1A, the mobility was improved by more than 200%, the carrier concentration was improved by more than 110%, and the sheet resistance was reduced to about 40% compared to the conventional nitride semiconductor stack.

[0048] In the nitride semiconductor stack 1A having the electron barrier layer 14, by providing the underlayer 12 containing a predetermined amount of Si, the characteristics of the two-dimensional electron gas (2DEG) formed at the interface between the electron barrier layer 14 and the GaN layer 13 can be improved. When such an electron barrier layer 14 is provided, the two-dimensional hole gas (2DHG) formed at the interface between the underlayer 12 and the GaN layer 13 may adversely affect the two-dimensional electron gas (2DEG) formed at the interface between the GaN layer 13 and the electron barrier layer 14, since the thickness of the GaN layer 13 is thin, at 0.5 nm or more and 30 nm or less, and may result in degradation of electrical characteristics. However, in the nitride semiconductor stack 1A having the electron barrier layer 14 and in which a two-dimensional electron gas (2DEG) is formed, by providing the underlayer 12 containing a predetermined amount of Si, the generation of the two-dimensional hole gas (2DHG) can be suppressed, and the influence on the two-dimensional electron gas (2DEG) can be suppressed.

[0049] For example, Figure 9A is an energy band diagram of the conduction band and valence band of a nitride semiconductor stack using a Si-free underlayer and provided with an electron barrier layer. In Figure 9A, the valence band energy is shown by a solid line, the conduction band energy by a bold line, and the Fermi level by a dashed line. Note that Figure 9A shows the energy of each of the Si-free underlayer, GaN layer, and electron barrier layer. 9A, when the energy depression in the valence band indicated by the dashed line overlaps with the Fermi level, two-dimensional hole gas (2DHG) accumulates in the energy depression in the valence band. As a result, two-dimensional hole gas (2DHG) is generated at the interface between the underlayer 12 and the GaN layer 13, and this two-dimensional hole gas (2DHG) affects the two-dimensional electron gas (2DEG), affecting the carrier mobility of the two-dimensional electron gas (2DEG) and degrading the electrical characteristics.

[0050] In contrast, FIG. 9B shows the underlayer 12 containing the above-mentioned predetermined amount of Si (in FIG. 9B, the Si concentration is 4.5×10 19 cm -3 9B is an energy band diagram of the conduction band and valence band of the nitride semiconductor stack 1A provided with the electron barrier layer 14, using a graphene-based material. In FIG. 9B, the valence band energy is indicated by a solid line, the conduction band energy is indicated by a thick line, and the Fermi level is indicated by a dashed line. Note that FIG. 9B also shows the energy of each layer when an electron barrier layer (described in detail in Modification 1 below) is provided on the GaN layer 13. In the nitride semiconductor stack 1A having the underlayer 12 containing a predetermined amount of Si shown in this embodiment, the valence band energy in the underlayer 12 is lower than that of the nitride semiconductor stack having the underlayer not containing a predetermined amount of Si shown in FIG. 9A, and the valence band energy dip does not overlap with the Fermi level. This prevents two-dimensional hole gas (2DHG) from accumulating in the valence band energy dip indicated by the dashed line in FIG. 9B, and suppresses the generation of two-dimensional hole gas (2DHG) that affects the two-dimensional electron gas (2DEG) at the interface between the underlayer 12 and the GaN layer 13. This suppresses a decrease in carrier mobility in the two-dimensional electron gas (2DEG), improving electrical characteristics.

[0051] (1.2.2) Variant Example 2 Referring to FIG. 10, the nitride semiconductor laminate 1B of the variant example 2 will be described. Here, FIG. 10 is a schematic cross-sectional view showing a cross-section of the nitride semiconductor laminate 1B.

[0052] As shown in FIG. 10, the nitride semiconductor laminate 1B includes a substrate 11, an underlayer 12, a GaN layer 13, and an AlN layer 15 provided between the substrate 11 and the underlayer 12. That is, the nitride semiconductor laminate 1B is different from the nitride semiconductor laminate 1 according to the first embodiment in that it further includes an AlN layer 15. Hereinafter, the AlN layer 15 will be described in detail. Since the substrate 11, the underlayer 12, and the GaN layer 13 of the nitride semiconductor laminate 1B are the same as the respective layers constituting the nitride semiconductor laminate 1, the description thereof will be omitted.

[0053] <AlN Layer> The AlN layer 15 is preferably formed over the entire surface of the substrate. Similar to the underlayer 12, the AlN layer 15 is a layer for forming a nitride semiconductor layer with a small lattice constant difference and a small coefficient of thermal expansion difference in the upper layer and with few defects. The AlN layer 15 is formed, for example, in an environment where the temperature is 1100°C or higher and 1250°C or lower. That is, the AlN layer 15 is formed at a higher temperature than the underlayer 12. The AlN layer 15 is preferably a nitride semiconductor layer containing Al, and is formed of a nitride semiconductor such as AlN or AlGaN, for example. The AlN layer 16 may also contain impurities such as C, Si, Fe, and Mg, etc.

[0054] The AlN layer 15 has a thickness of, for example, several μm. Specifically, the thickness of the AlN layer 15 is preferably greater than 10 nm and less than 10 μm, and is, for example, 900 nm. When the thickness of the AlN layer 15 is greater than 10 nm, the crystallinity of the nitride semiconductor such as AlN becomes higher. When the thickness of the AlN layer 15 is less than 10 μm, cracks are less likely to occur in the AlN layer 15 formed by crystal growth over the entire surface of the wafer.

[0055] (1.2.3) Variation 3 A nitride semiconductor stack 1C of Modification 3 will be described with reference to Fig. 11. Fig. 11 is a schematic cross-sectional view showing a cross section of the nitride semiconductor stack 1C of Modification 3.

[0056] 11, the nitride semiconductor stack 1C includes a substrate 11, an underlayer 12, a low Al layer 16, and a GaN layer 13. That is, the nitride semiconductor stack 1C differs from the nitride semiconductor stack 1 according to the first embodiment in that it further includes a low Al layer 16 (an example of a first low Al layer). The following describes in detail the low Al layer 16. Note that the substrate 11, underlayer 12, and GaN layer 13 of the nitride semiconductor stack 1C are similar to the layers constituting the nitride semiconductor stack 1, and therefore descriptions thereof will be omitted.

[0057] <Low Al layer> The low Al layer 16 is a layer for increasing the concentration of two-dimensional hole gas (2DHG), which is a two-dimensional carrier gas generated between the underlayer 12 and the GaN layer 13. AlN (Al composition is 100% x Ga (1-x) When GaN layer 13 is formed on underlayer 12 formed of N, a two-dimensional hole gas (2DHG) which is a two-dimensional carrier gas is formed at the interface between underlayer 12 and GaN layer 13. Two-dimensional carrier gases have high saturated mobility, which allows for high-frequency characteristics. Furthermore, power devices can be obtained that combine low on-resistance due to high mobility with high breakdown voltage characteristics due to a wide band gap. Here, the on-resistance is determined by the mobility and carrier concentration of the two-dimensional carrier gas. Lower sheet resistance, which includes both the mobility and carrier concentration parameters mentioned above, is advantageous for reducing on-resistance. Furthermore, breakdown voltage is determined by the band gap of the nitride semiconductors that make up the HEMT, a device using a nitride semiconductor stack.

[0058] The generation of such a two-dimensional carrier gas is affected by polarization, i.e., strain. When forming this two-dimensional hole gas (2DHG) at a higher concentration and with a higher mobility, it is necessary to consider the influence of alloy scattering. When using an AlsGa1-sN layer instead of the GaN layer 13, if the Al composition is too high, the mobility will be significantly reduced due to alloy scattering. Also, when using the nitride semiconductor stack 1 as a power device, from the perspective of achieving both a two-dimensional hole gas (2DHG) concentration and mobility, the Al composition ratio of the layer provided on the underlying layer 12 is preferably sufficiently smaller than the Al composition x of the underlying layer 12, and it is preferably Al-free. For this reason, a low-Al layer 16 formed of an Alz1Ga1-z1N layer (0 ≤ z1 < x) is preferably provided in the upper layer of the underlying layer 12 (between the underlying layer 12 and the GaN layer 13). That is, the Al composition z1 in the low-Al layer 16 is smaller than the Al composition x of the underlying layer 12. z1 Ga (1-z1) N layer (0 ≤ z1 < x). That is, the Al composition z1 in the low-Al layer 16 is smaller than the Al composition x of the underlying layer 12. Also, to increase the concentration of the two-dimensional hole gas (2DHG), the abruptness of the interface is important. From this perspective, the film thickness of the low-Al layer 16 provided in the upper layer of the underlying layer 12 is preferably more than 0 nm and 0.5 nm or less. Also, when the low-Al layer 16 is formed of AlN (Al composition z1 = 0, Alz1Ga1-z1N), the GaN layer 13 may also serve as the low-Al layer 16. z1 Ga (1-z1) N), the GaN layer 13 may also serve as the low-Al layer 16.

[0059] (1.2.4) Modified Example 4 Referring to FIG. 12, the nitride semiconductor stack 1D of Modified Example 5 will be described. Here, FIG. 12 is a cross-sectional schematic view showing the cross-section of the nitride semiconductor stack 1D which is Modified Example 5.

[0060] As shown in FIG. 12, the nitride semiconductor stack 1D includes a substrate 11, an underlying layer 12, a GaN layer 13, a low-Al layer 17, and an electron barrier layer 14. That is, the nitride semiconductor stack 1D is different from the nitride semiconductor stack 1A according to Modified Example 1 of the first embodiment in that it further includes a low-Al layer (an example of a second low-Al layer) 17. Hereinafter, the low-Al layer 17 will be described in detail. Note that since the substrate 11, the underlying layer 12, the GaN layer 13, and the electron barrier layer 14 in the nitride semiconductor laminate 1D are the same as the respective layers constituting the nitride semiconductor laminate 1A, the description thereof will be omitted.

[0061] <Low-Al layer> The low-Al layer 17 is a layer for increasing the concentration of the two-dimensional electron gas (2DEG), which is a two-dimensional carrier gas generated between the GaN layer 13 and the electron barrier layer 14. On the GaN layer 13, Al y Ga (1-y) When forming the electron barrier layer 14 formed of N(0.7 ≦ y ≦ 1), as described above, a two-dimensional electron gas (2DEG), which is a two-dimensional carrier gas, is formed at the interface between the GaN layer 13 and the electron barrier layer 14. When using the nitride semiconductor laminate 1A as a power device, from the viewpoint of achieving both the two-dimensional electron gas (2DEG) concentration and mobility, the Al composition ratio of the layer provided on the GaN 13 is preferably sufficiently smaller than the Al composition y of the electron barrier layer 14, and preferably does not contain Al. For this reason, in the upper layer of the GaN layer 13 (between the GaN layer 13 and the electron barrier layer 14), an Al z2 Ga (1-z2) N layer (0 ≦ z2 < y) is preferably provided as the low-Al layer 17. That is, the Al composition z2 in the low-Al layer 17 is smaller than the Al composition y of the electron barrier layer 14. In addition, to increase the concentration of the two-dimensional electron gas (2DEG), the steepness of the interface is important. From this viewpoint, the film thickness of the low-Al layer 17 provided in the upper layer of the GaN layer 13 is preferably more than 0 nm and 0.5 nm or less. In addition, when the low-Al layer 17 is formed of AlN (Al composition z2 = 0, Al z2 )]]Ga (1-z2) N), the GaN layer 13 may also serve as the low-Al layer 17.

[0062] (1.3) Method for manufacturing a nitride semiconductor laminate The method for manufacturing the nitride semiconductor laminate 1 of the present embodiment will be described. The nitride semiconductor laminate 1 is manufactured through the following steps. (A) Al is grown on a substrate 11, which is a nitride semiconductor substrate containing Al, by metal organic chemical vapor deposition while supplying silicon gas as a raw material gas. x Ga (1-x) Forming the underlayer 12 made of N (0.5≦x≦1) (B) On the underlayer 12, a GaN layer 13 is formed at a growth rate of 0.5 μm / hr to 2.0 μm / hr using metal organic chemical vapor deposition while supplying trimethylgallium gas as a source gas in an environment of a temperature of 600° C. to 900° C. and a pressure of 20 mbar to 200 mbar.

[0063] Substrate 11 is formed by a common substrate growth method, such as a vapor phase growth method such as sublimation or hydride vapor phase epitaxy (HVPE), or a liquid phase growth method. The miscut angle of substrate 11 is not particularly limited, but a miscut angle of 0.1 degrees or more and 0.4 degrees or less is preferable because the effect of underlayer 12 is significant. In addition, the miscut direction of substrate 11 is preferably the <10-10> direction.

[0064] The step of forming the underlayer 12 on the substrate 11 can be performed by using a metal organic chemical vapor deposition (MOCVD) method while supplying silicon gas as a source gas. Here, the underlayer 12 formed on the substrate 11 can be formed using, for example, an Al raw material containing trimethylaluminum (TMAl), a Ga raw material containing, for example, trimethylgallium (TMGa) or triethylgallium (TEGa), or an N raw material containing, for example, ammonia (NH3).

[0065] Specifically, the underlayer 12 is formed by depositing Si at a density of 1×10 19 cm -3 More than 1×10 20 cm -3 Al including x Ga (1-x) It is sufficient that the material is formed of N (0.5≦x≦1), and other conditions are not particularly limited. This prevents two-dimensional hole gas (2DHG) from accumulating in the energy depression of the valence band and reduces misfit dislocations present at the interface between the underlayer and the GaN layer, resulting in a nitride semiconductor stack with excellent electrical properties. Furthermore, the GaN layer 13 may be formed by metal organic chemical vapor deposition at a growth rate of 0.5 μm / hr to 2.0 μm / hr while supplying trimethylgallium gas as a source gas in an environment of a temperature of 600°C to 900°C and a pressure of 20 mbar to 200 mbar. This allows the step-terrace structure formed in the underlayer 12 to be exposed on the surface of the GaN layer 13, thereby obtaining a nitride semiconductor laminate with excellent electrical properties.

[0066] Furthermore, the underlayer 12 is preferably formed in an environment where the temperature is 600° C. or higher and 1000° C. or lower and the pressure is 50 mbar or higher and 500 mbar or lower. As a result, on the surface of the underlayer 12, steps ST, which are stepped portions, and flat terraces TE are repeated in the miscut direction (<10-10> direction) of the substrate 11, and the ends of the terraces TE, which are the terrace ends ETE (the boundary between the terraces TE and the steps ST in top view), have amplitude in the miscut direction (<10-10> direction) of the substrate 11, resulting in a step-terrace structure with a wave shape extending in a direction (<11-20> direction) perpendicular to the miscut direction (<10-10> direction) of the substrate 11 (see Figure 3A).

[0067] The growth rate of the underlayer 12 is preferably 0.5 μm / hr or more and less than 2 μm / hr. x Ga (1-x) When the growth rate of N is 0.5 μm / hr or more, the aforementioned wavy step-terrace structure is well formed, and better electrical properties can be obtained. Similarly, when the growth rate is less than 2 μm / hr, the aforementioned wavy step-terrace structure is well formed, and better electrical properties can be obtained. The growth rate of the underlayer 12 can be controlled by appropriately adjusting the temperature of the substrate 11, the degree of vacuum in the chamber, and the flow rate of the source gas. From the viewpoint of removing impurities, it may be preferable to anneal the substrate 11 in a hydrogen atmosphere at 1000° C. or higher, preferably 1200° C. or higher.

[0068] (1.4) Method for measuring physical properties of nitride semiconductor laminate The physical properties of the above-described nitride semiconductor stack 1 and the nitride semiconductor stacks 1A and 1B in the modified examples can be measured as follows.

[0069] (GaN layer coverage measurement) The coverage of the GaN layer 13 is measured using, for example, a scanning electron microscope (FE-SEM "SU9000" manufactured by Hitachi High-Technologies Corporation) and image processing software (image analysis software "A-Zo-kun" (registered trademark) manufactured by Asahi Kasei Engineering Co., Ltd.). More specifically, during SEM measurement, the exposed surface of the GaN layer 13 is measured at three arbitrary points within a measurement range of 50 μm × 50 μm. At this time, a backscattered electron image is obtained using a lower detector, resulting in an SEM image with clear contrast due to compositional differences.

[0070] The obtained SEM image is processed using image processing software. Areas with brightness 50% or more lower than the average brightness in the SEM image are defined as areas where the GaN layer 13 is not covering the substrate 11 directly below. The coverage rate is the proportion of the covered area, and the average value of any three points is defined as the coverage rate of the GaN layer 13.

[0071] The surface roughness is measured using an atomic force microscope (AFM) (Seiko Instruments Inc., "SPA400"). The same location as in the coverage measurement is measured using the AFM at three arbitrary points within a measurement range of 4 μm × 4 μm. The scan frequency is 0.2 Hz. The average value of the root mean square roughness at the three points obtained by the measurement is taken as the surface roughness of the GaN layer 13.

[0072] (Method for measuring GaN layer thickness and threading dislocations) The thickness of the GaN layer 13 can be measured by cutting out a predetermined cross section perpendicular to the substrate 11, observing this cross section with a transmission electron microscope (TEM), and using the length measurement function of the TEM. For the TEM measurement, for example, a transmission electron microscope "HD-2300" manufactured by Hitachi High-Technologies Corporation is used. As a measurement method, first, a cross section perpendicular to the major surface of the substrate 11 of the nitride semiconductor laminate is observed using a TEM. As an example, measurement on the a-plane (11-20) is preferred. Specifically, for example, within a TEM image showing a cross section perpendicular to the major surface of the substrate 11 of the nitride semiconductor laminate 1, an observation width of 2 μm or more is set in a direction parallel to the major surface of the substrate 11. Within this observation width, contrast is observed at the interface between two layers with different compositions, so the thickness up to this interface is observed in a continuous observation region 200 nm wide. The film thickness of each layer can be obtained by calculating the average thickness of each layer included in this 200-nm-wide observation region from five locations arbitrarily selected from the above-mentioned observation width of 2 μm or more.

[0073] Similarly, for threading dislocations, the number of threading dislocations per volume is calculated from the number of threading dislocations present in a cross section perpendicular to the main surface of the substrate 11, the field area, and the thickness of the sample. The number of threading dislocations is calculated from five samples, and the average value of these is taken as the number of threading dislocations.

[0074] (Measurement of strain, misfit dislocations, and stacking faults in nitride semiconductor layers) Misfit dislocations formed near the interface can be measured by cutting out a predetermined cross section parallel to the substrate 11 and observing it with a transmission electron microscope (TEM). As an example, a primary sample including an observation area of ​​20 μm square or more, including the GaN layer 13, is prepared from the substrate 11 by a focused ion beam method. Next, a secondary sample is prepared by thinning the primary sample to a thickness of 0.5 μm by polishing or the focused ion beam method. The secondary sample is <0001> Planar TEM images are obtained using a zone-axis incident electron beam. During this process, cross-sectional TEM images can be simultaneously obtained using the primary sample or a sample obtained using a similar method to the primary sample. Misfit dislocations were observed at a magnification of 10k to 20k with an applied voltage of 200kV. <0001> The counting is performed using a planar TEM image with the zone-axis incidence. The direction of the obtained dislocation lines is not perfectly parallel to the <10-10> direction throughout the entire field of view, and the number of lines may increase or decrease as they intersect with other dislocation lines. Therefore, the number of dislocation lines is counted by imagining a sampling line parallel to the <10-10> direction and determining the number of intersections between the sampling line and the dislocation line as the statistical average value over multiple sampling lines. The sampling lines are spaced at intervals of 1 μm or less, and counting is performed 20 times or more within a 20 μm field of view.

[0075] (Method for measuring Al composition and relaxation rate in AlxGa(1-x)N layers) The relaxation rate can be measured, for example, by reciprocal space mapping (RSM) using X-ray diffraction (XRD). For XRD measurements, a PANalytical "X'pert3 MRD" is used. In this case, the tube is set to 45 kV / 40 mA, a collimated radiation source using a double-crystal Ge (220) is used, the incident Soller slit is set to 0.04°, and the detector slit is set to 1 / 16 mm, and the axis is aligned with the (20-24) plane peak of the substrate 11. Then, a 2θ / ω scan is performed, and the ω is changed in 0.05° increments within a range of ±1.5°. From these measurements, the spatial coordinates Qx and Qy are calculated, and the relaxation rate and Al composition for the substrate 11 are calculated.

[0076] (1.5) Effects of this embodiment The nitride semiconductor stack and the method for manufacturing the nitride semiconductor stack according to this embodiment have the following advantages. (1) The method for manufacturing a nitride semiconductor laminate according to this embodiment uses metal organic chemical vapor deposition (MOCVD) to supply silicon gas as a raw material gas while Al x Ga (1-x) The method includes the steps of: forming an underlayer made of N (0.5≦x≦1); and forming a GaN layer on the underlayer at a growth rate of 0.5 μm / hr to 2.0 μm / hr using metal organic chemical vapor deposition in an environment where the temperature is 600°C to 900°C and the pressure is 20 mbar to 200 mbar, while supplying trimethylgallium gas as a source gas. This prevents two-dimensional hole gas (2DHG) from accumulating in the energy depression of the valence band and reduces misfit dislocations present at the interface between the underlayer and the GaN layer, resulting in a nitride semiconductor stack with excellent electrical properties.

[0077] (2) In the method for manufacturing a nitride semiconductor stack according to this embodiment, the underlayer is preferably formed in an environment at a temperature of 600° C. to 1000° C. and a pressure of 50 mbar to 500 mbar. This allows the formation of a step-terrace structure on the surface of the nitride semiconductor laminate, in which steps ST, which are stepped portions, and flat terraces TE are repeated in the miscut direction of the substrate, and the terrace ends ETE, which are the ends of the terraces TE, have a wave shape that has amplitude in the miscut direction of the nitride semiconductor substrate and extends in a direction perpendicular to the miscut direction of the nitride semiconductor substrate, thereby allowing the production of a nitride semiconductor laminate with better electrical properties.

[0078] (3) In the method for manufacturing a nitride semiconductor laminate according to this embodiment, it is preferable to use an aluminum nitride single crystal substrate as the nitride semiconductor substrate. This reduces the difference in lattice constant between the nitride semiconductor substrate and the nitride semiconductor layer formed on the nitride semiconductor substrate, and by growing the nitride semiconductor layer in a lattice-matched system, threading dislocations can be reduced, thereby improving the quality of the nitride semiconductor laminate.

[0079] (4) In the method for manufacturing a nitride semiconductor laminate according to this embodiment, it is preferable to use a nitride semiconductor substrate having a miscut angle of 0.1 degrees or more and 0.4 degrees or less. As a result, by providing the underlayer, it becomes possible to form each layer of the lattice-matched semiconductor laminate on the upper layer of the substrate even when using a substrate 11 with a large miscut angle of 0.1 degrees or more, and the electrical characteristics of the device formed using the nitride semiconductor laminate are improved.

[0080] (5) In the method for manufacturing a nitride semiconductor laminate according to this embodiment, it is preferable to use a nitride semiconductor substrate whose miscut direction is the <10-10> direction. This results in a step-terrace structure on the surface of the top layer of the nitride semiconductor laminate, where steps, which are level differences in the <10-10> direction, and flat terraces are repeated, improving the mobility and carrier concentration, and as a result, the electrical characteristics.

[0081] (6) The nitride semiconductor laminate according to this embodiment includes a nitride semiconductor substrate containing Al, and a nitride semiconductor layer having 1×10 Si and disposed on the nitride semiconductor substrate. 19 cm -3 More than 1×10 20 cm -3 Preferably, the Si content is 3×10 19 cm -3 6×10 or more 19 cm -3 Al including x Ga (1-x) The semiconductor device includes an underlayer made of N (0.5≦x≦1) and a GaN layer disposed on the underlayer. This prevents two-dimensional hole gas (2DHG) from accumulating in the energy depression of the valence band and reduces misfit dislocations present at the interface between the underlayer and the GaN layer, resulting in a nitride semiconductor stack with excellent electrical properties.

[0082] (7) In the nitride semiconductor stack according to this embodiment, the thickness of the underlayer is preferably 50 nm or more and 200 nm or less. This enhances the effect of depositing a nitride semiconductor layer having a lattice constant that is approximately identical to that of the substrate, thereby improving electrical characteristics.

[0083] (8) In the nitride semiconductor stack according to this embodiment, it is preferable that a diffusion layer containing Al and Ga is not formed at the interface between the underlayer and the GaN layer, where the diffusion layer is formed by Al of the underlayer diffusing into the GaN layer and Ga of the GaN layer diffusing into the underlayer. As a result, even when the miscut angle of the substrate is large, at 0.1 degrees or more, the layers of the semiconductor laminate formed on the substrate are less likely to relax, and new threading dislocations are less likely to be introduced into the nitride semiconductor laminate, resulting in a nitride semiconductor laminate with better electrical properties.

[0084] (9) In the nitride semiconductor stack according to this embodiment, the nitride semiconductor substrate is preferably an aluminum nitride single crystal substrate. This reduces the difference in lattice constant between the nitride semiconductor substrate and the nitride semiconductor layer formed on the nitride semiconductor substrate, and by growing the nitride semiconductor layer in a lattice-matched system, threading dislocations can be reduced, thereby improving the quality of the nitride semiconductor laminate.

[0085] (10) In the nitride semiconductor stack according to this embodiment, the miscut angle of the nitride semiconductor substrate is preferably 0.1 degrees or more and 0.4 degrees or less. As a result, by providing the underlayer, it becomes possible to form each layer of the lattice-matched semiconductor laminate on the upper layer of the substrate even when using a substrate 11 with a large miscut angle of 0.1 degrees or more, and the electrical characteristics of the device formed using the nitride semiconductor laminate are improved.

[0086] (11) In the nitride semiconductor laminate according to this embodiment, the miscut direction of the nitride semiconductor substrate is preferably the <10-10> direction. This allows a step-terrace structure, in which steps, which are level portions in the <10-10> direction, and flat terraces are repeated, to be exposed on the surface of the uppermost layer of the nitride semiconductor laminate.

[0087] (12) In the nitride semiconductor stack according to this embodiment, it is preferable that the surface of the layer furthest from the nitride semiconductor substrate opposite to the nitride semiconductor substrate has a step-terrace structure in which steps, which are level portions, and flat terraces are repeated in the miscut direction of the nitride semiconductor substrate, and the terrace edges, which are the ends of the terraces, have a wave shape that has an amplitude in the miscut direction of the nitride semiconductor substrate and extends in a direction perpendicular to the miscut direction of the nitride semiconductor substrate.

[0088] (13) In the nitride semiconductor stack according to this embodiment, the underlayer and the GaN layer formed on the nitride semiconductor substrate preferably have a pseudomorphic lattice match with the nitride semiconductor substrate. This further reduces the lattice mismatch between the nitride semiconductor substrate and each of the upper layers, further improving the electrical characteristics of the nitride semiconductor laminate.

[0089] (14) The nitride semiconductor laminate according to this embodiment is provided between the underlayer and the GaN layer, and z1 Ga (1-z1) It is preferable that the first low Al layer is formed of N (0≦z1<0.5), and the thickness of the first low Al layer is 0.5 nm or less. This increases the concentration of two-dimensional hole gas (2DHG), which is a two-dimensional carrier gas generated between the underlayer and the GaN layer, thereby improving the electrical characteristics.

[0090] (15) The nitride semiconductor laminate according to this embodiment is disposed on a GaN layer, and y Ga (1-y) It is preferable to have an electron barrier layer formed of N (0.7≦y≦1). This allows a two-dimensional electron gas (2DEG) to be formed at the interface between the GaN layer and the electron barrier layer, improving the electrical characteristics of the nitride semiconductor laminate.

[0091] (16) The nitride semiconductor laminate according to this embodiment is provided between the GaN layer and the electron barrier layer, and z2 Ga (1-z2) It is preferable that the second low Al layer is formed of N (0≦z2<0.7), and the thickness of the second low Al layer is 0.5 nm or less. This increases the concentration of two-dimensional electron gas (2DEG), which is a two-dimensional carrier gas generated between the GaN layer and the electron barrier layer, and further improves the electrical characteristics of the nitride semiconductor laminate.

[0092] (17) In the nitride semiconductor stack according to this embodiment, the interface between the GaN layer and the second low Al layer preferably has misfit dislocations in the same direction as the miscut direction of the nitride semiconductor substrate. This allows the strain at the interface between the underlayer and the GaN layer to be released without generating threading dislocations extending perpendicular to the substrate, resulting in improved quality of the two-dimensional hole gas (2DHG).

[0093] 2. Specific Examples of Embodiments A high electron mobility transistor (HEMT, hereinafter referred to as HEMT), which is a power device using a nitride semiconductor stack according to a first embodiment of the present disclosure, will be described with reference to Fig. 13. Fig. 13 is a cross-sectional view showing an example of the configuration of a HEMT 100. As shown in FIG. 13, the HEMT 100 includes a substrate 11, an underlayer 12, a GaN layer 13, and an electron barrier layer 14, and a gate electrode 101, a source electrode 102, and a drain electrode 103 are provided on the electron barrier layer 14. The substrate 11, the base layer 12, and the GaN layer 13 of the HEMT 100 are the same as the layers constituting the nitride semiconductor stack 1 described in the first embodiment, and the electron barrier layer 14 is the same as the electron barrier layer 14 constituting the nitride semiconductor stack 1A described in the first modification of the first embodiment, so detailed description thereof will be omitted.

[0094] The thicknesses of the underlayer 12, the GaN layer 13 and the electron barrier layer 14 of the HEMT 100 are, for example, 900 nm, 15 nm and 7.5 nm, respectively. A sheet-like two-dimensional electron gas (2DEG) layer with a high electron concentration is formed at the interface between the GaN layer 13 and the electron barrier layer 14. This two-dimensional electron gas (2DEG) layer has high saturated electron mobility, allowing the HEMT 100 to achieve high-frequency characteristics. The HEMT 100 is also a power device that combines low on-resistance due to high electron mobility with high breakdown voltage characteristics due to a wide band gap. In the HEMT 100, the two-dimensional electron gas (2DEG) layer serves as the channel of the HEMT 100. [Example]

[0095] Example 1 The nitride semiconductor stack of the present disclosure will be described below with reference to examples and comparative examples, but the nitride semiconductor stack of the present disclosure is not limited to these examples. The substrate used was a (0001) AlN single crystal substrate with a thickness of 550 μm, a miscut direction in the <10-10> direction, and a miscut angle of 0.2 degrees. Next, an AlN layer, a homoepitaxial layer similar to a conventional underlayer, was formed on the substrate. The AlN layer was formed to a thickness of 900 nm in an environment of 1200°C. At this time, the ratio of the supply rate of the Group III element source gas to the supply rate of the nitrogen source gas (V / III ratio) was set to 50. The growth rate of the AlN layer was 0.5 μm / hr. Trimethylaluminum (TMAl) was used as the Al source, and ammonia (NH3) was used as the N source.

[0096] On this AlN layer, Al with Al composition x=1 was grown to a thickness of 100 nm by metal organic chemical vapor deposition while supplying silicon gas as a source gas under an environment of 800°C and 200 mbar pressure. x Ga (1-x) The underlayer was formed by forming N (i.e., AlN). At this time, the silicon gas was supplied so that the Si content in the underlayer was 6×10 19 The V / III ratio was set to 3000, and the growth rate of the underlayer was set to 0.5 μm / hr.

[0097] Next, a 15-nm-thick GaN layer was grown on the underlayer. The GaN layer was grown at a temperature of 800°C and a pressure of 100 mbar using metalorganic vapor phase epitaxy (MOCVD) with a V / III ratio of 3650, using trimethylgallium gas as the source gas at a growth rate of 0.7 μm / hr.

[0098] <Example 2> The Si content in the underlayer is 1×10 19 A nitride semiconductor laminate of Example 2 was formed in the same manner as in Example 1, except that the supply amount of silicon gas as a raw material gas was adjusted so that

[0099] Example 3 The Si content in the underlayer is 3×10 19 A nitride semiconductor laminate of Example 3 was formed in the same manner as in Example 1, except that the supply amount of silicon gas as a raw material gas was adjusted so that

[0100] Example 4 The Si content in the underlayer is 1×10 20 The nitride semiconductor laminate of Example 4 was formed in the same manner as in Example 1, except that the supply amount of silicon gas as the raw material gas was adjusted so that

[0101] <Example 5> The underlayer was grown by supplying silicon gas as a source gas while growing Al with an Al composition of x=0.5. x Ga (1-x) N (i.e., Al 0.5 Ga 0.5 A nitride semiconductor laminate of Example 5 was formed in the same manner as in Example 1, except that it was formed using a nitride semiconductor layer (N).

[0102] Example 6 The underlayer was grown by supplying silicon gas as a source gas while growing Al with an Al composition of x=0.75. x Ga (1-x) N (i.e., Al 0.75 Ga 0.25 A nitride semiconductor laminate of Example 6 was formed in the same manner as in Example 1, except that it was formed using a nitride semiconductor layer (N).

[0103] Example 7 A nitride semiconductor laminate of Example 7 was formed in the same manner as in Example 1, except that the temperature for forming the GaN layer was set to 600°C.

[0104] Example 8 A nitride semiconductor laminate of Example 8 was formed in the same manner as in Example 1, except that the temperature for forming the GaN layer was 900°C.

[0105] Example 9 A nitride semiconductor laminate of Example 9 was formed in the same manner as in Example 1, except that the formation pressure of the GaN layer was set to 20 mbar.

[0106] Example 10 A nitride semiconductor laminate of Example 10 was formed in the same manner as in Example 1, except that the formation pressure of the GaN layer was set to 200 mbar.

[0107] Example 11 A nitride semiconductor laminate of Example 11 was formed in the same manner as in Example 1, except that the growth rate of the GaN layer was set to 0.5 μm / hr.

[0108] Example 12 A nitride semiconductor laminate of Example 12 was formed in the same manner as in Example 1, except that the growth rate of the GaN layer was set to 2.0 μm / hr.

[0109] Example 13 A nitride semiconductor laminate of Example 13 was formed in the same manner as in Example 1, except that the temperature when forming the underlayer was 550°C.

[0110] Example 14 A nitride semiconductor laminate of Example 14 was formed in the same manner as in Example 1, except that the temperature when forming the underlayer was 600°C.

[0111] Example 15 A nitride semiconductor laminate of Example 15 was formed in the same manner as in Example 1, except that the temperature when forming the underlayer was 1000°C.

[0112] Example 16 A nitride semiconductor laminate of Example 16 was formed in the same manner as in Example 1, except that the temperature during formation of the underlayer was set to 1100°C.

[0113] Example 17 A nitride semiconductor laminate of Example 17 was formed in the same manner as in Example 1, except that the pressure when forming the underlayer was 30 mbar.

[0114] Example 18 A nitride semiconductor laminate of Example 18 was formed in the same manner as in Example 1, except that the pressure when forming the underlayer was 50 mbar.

[0115] Example 19 A nitride semiconductor laminate of Example 19 was formed in the same manner as in Example 1, except that the pressure when forming the underlayer was 500 mbar.

[0116] Example 20 A nitride semiconductor laminate of Example 20 was formed in the same manner as in Example 1, except that the pressure when forming the underlayer was 550 mbar.

[0117] <Example 21> A nitride semiconductor laminate of Example 21 was formed in the same manner as in Example 1, except that the thickness of the underlayer was set to 30 μm.

[0118] <Example 22> A nitride semiconductor laminate of Example 22 was formed in the same manner as in Example 1, except that the thickness of the underlayer was set to 50 μm.

[0119] Example 23 A nitride semiconductor laminate of Example 23 was formed in the same manner as in Example 1, except that the thickness of the underlayer was set to 200 μm.

[0120] Example 24 A nitride semiconductor laminate of Example 24 was formed in the same manner as in Example 1, except that the thickness of the underlayer was set to 250 μm.

[0121] Example 25 A nitride semiconductor laminate of Example 25 was formed in the same manner as in Example 1, except that the miscut angle of the substrate was set to less than 0.1 degrees.

[0122] <Example 26> A nitride semiconductor laminate of Example 26 was formed in the same manner as in Example 1, except that the miscut angle of the substrate was set to 0.1 degrees.

[0123] Example 27 A nitride semiconductor laminate of Example 27 was formed in the same manner as in Example 1, except that the miscut angle of the substrate was set to 0.4 degrees.

[0124] Example 28 A nitride semiconductor laminate of Example 28 was formed in the same manner as in Example 1, except that the miscut angle of the substrate was set to 0.5 degrees.

[0125] <Comparative Example 1> The Si content in the underlayer is 5×10 18 A nitride semiconductor laminate of Comparative Example 1 was formed in the same manner as in Example 1, except that the supply amount of silicon gas as a raw material gas was adjusted so that

[0126] <Comparative Example 2> The Si content in the underlayer is 1.5×10 20 The nitride semiconductor laminate of Comparative Example 1 was formed in the same manner as in Example 2, except that the supply amount of silicon gas as the raw material gas was adjusted so that

[0127] <Comparative Example 3> A nitride semiconductor laminate of Comparative Example 3 was formed in the same manner as in Example 1, except that the underlayer was formed by sputtering.

[0128] <Comparative Example 4> Al that makes up the underlayer x Ga (1-x) The Al composition x of N is set to 0.4 (i.e., Al 0.4 Ga 0.6 A nitride semiconductor laminate of Comparative Example 4 was formed in the same manner as in Example 1, except that the nitride semiconductor laminate was formed using the same material as in Example 1.

[0129] <Comparative Example 5> A nitride semiconductor laminate of Comparative Example 5 was formed in the same manner as in Example 1, except that the temperature for forming the GaN layer was set to 1000°C.

[0130] <Comparative Example 6> A nitride semiconductor laminate of Comparative Example 6 was formed in the same manner as in Example 1, except that the formation pressure of the GaN layer was set to 250 mbar.

[0131] <Comparative Example 7> A nitride semiconductor laminate of Comparative Example 7 was formed in the same manner as in Example 1, except that the growth rate of the GaN layer was set to 0.4 μm / hr.

[0132] <Comparative Example 8> A nitride semiconductor laminate of Comparative Example 8 was formed in the same manner as in Example 1, except that the growth rate of the GaN layer was set to 2.1 μm / hr.

[0133] [evaluation] The carrier mobility, carrier concentration, and sheet resistance of the above-mentioned nitride semiconductor laminate were measured. For the measurements, electrodes were formed by laminating V, Al, Ni, and Au in this order at the four corners of the GaN layer, which was the outermost layer of a sample that had been cut into 10 mm sections, using electron beam (EB) deposition, and the sample was then heat-treated at 850°C. These samples were measured by the Van der Pauw method using a Hall measurement device manufactured by Toyo Corporation, with a magnetic field of 0.5 gauss applied. The evaluation results are shown in Tables 1 and 2 below.

[0134] [Table 1]

[0135] [Table 2]

[0136] As shown in Tables 1 and 2, Al was grown using metal organic chemical vapor deposition while supplying silicon gas as a source gas. x Ga (1-x) By forming an N (0.5≦x≦1) layer, Si is 19 cm -3 More than 1×10 20 cm -3 The nitride semiconductor stacks of the examples each had an underlayer containing the following, and a GaN layer formed on the underlayer by metal organic chemical vapor deposition at a growth rate of 0.5 μm or more / hr to 2.0 μm or less / hr while supplying trimethylgallium gas as a source gas in an environment of a temperature of 600°C to 900°C and a pressure of 20 mbar to 200 mbar using metal organic chemical vapor deposition. Compared with the nitride semiconductor stacks of the comparative examples formed by methods other than these methods, the nitride semiconductor stacks of the examples each had improved carrier mobility and carrier concentration and reduced sheet resistance, resulting in improved electrical properties.

[0137] Furthermore, in Examples 1 and 25-28, in which the underlayer and GaN layer were formed under the above conditions, the evaluation results were better than those of the comparative examples in which the underlayer and GaN layer were not formed under the specified conditions, regardless of the substrate miscut angle, and the electrical properties were improved. In particular, as can be seen from Examples 1, 26, and 27, the electrical properties were particularly improved when the substrate miscut angle was 0.1 or more and 0.4 or less.

[0138] Also, Si is 1×10 19 cm -3 In each of the examples having an underlayer containing Si in an amount exceeding the above range, the carrier concentration was significantly improved and the sheet resistance was significantly reduced compared to Comparative Example 1 having an underlayer containing Si in an amount outside the above range. 20 cm -3 In each example having an underlayer containing the following, the carrier concentration was improved, the sheet resistance was reduced, and the carrier mobility was significantly improved compared to Comparative Example 2 having an underlayer containing Si in an amount outside the above-mentioned range. Furthermore, Si is 3 × 10 19 cm -3 6×10 or more 19 cm -3 Examples 1 and 3, which have underlayers containing the following, have further improved carrier mobility and carrier concentration and further reduced sheet resistance compared to Examples 2 and 4, which contain Si outside this range.

[0139] Although the embodiments of the present disclosure have been described above, the above embodiments are merely examples of devices and methods for embodying the technical ideas of the present disclosure, and the technical ideas of the present disclosure do not specify the materials, shapes, structures, arrangements, etc. of the components. The technical ideas of the present disclosure can be modified in various ways within the technical scope defined by the claims. [Explanation of symbols]

[0140] 1, 1A, 1B Nitride semiconductor laminate 11 Nitride semiconductor substrate (substrate) 12 Base layer 13 GaN layer 14 Electron barrier layer 15 AlN layer 16,17 Low Al layer 101 gate electrode 102 Source electrode 103 Drain electrode

Claims

1. On a nitride semiconductor substrate containing Al, Al is grown by metal organic chemical vapor deposition while supplying silicon gas as a source gas. ｘ Ga （１－ｘ） forming an underlayer made of N (0.5≦x≦1); forming a GaN layer on the underlayer at a growth rate of 0.5 μm / hr to 2.0 μm / hr using metal organic chemical vapor deposition (MOCVD) in an environment of a temperature of 600° C. to 900° C. and a pressure of 20 mbar to 200 mbar while supplying trimethylgallium gas as a source gas; A method for manufacturing a nitride semiconductor stack comprising:

2. The underlayer is formed in an environment where the temperature is 600° C. or higher and 1000° C. or lower and the pressure is 50 mbar or higher and 500 mbar or lower. The method for producing the nitride semiconductor laminate according to claim 1 .

3. An aluminum nitride single crystal substrate is used as the nitride semiconductor substrate. The method for producing the nitride semiconductor laminate according to claim 1 or 2.

4. The nitride semiconductor substrate has a miscut angle of 0.1 degrees or more and 0.4 degrees or less. The method for producing the nitride semiconductor laminate according to claim 1 or 2.

5. The nitride semiconductor substrate has a miscut direction in the <10-10> direction. The method for producing the nitride semiconductor laminate according to claim 1 or 2.

6. a nitride semiconductor substrate containing Al; Si is placed on the nitride semiconductor substrate, １９ cm －３ 1x10 or more ２０ cm －３ Al including the following ｘ Ga （１－ｘ） an underlayer formed of N (0.5≦x≦1); a GaN layer disposed on the underlayer; Equipped with Nitride semiconductor stack.

7. The underlayer is made of 3×10 １９ cm －３ 6 x 10 or more １９ cm －３ The above Al including: ｘ Ga （１－ｘ） N (0.5≦x≦1) The nitride semiconductor stack according to claim 6 .

8. The thickness of the underlayer is 50 nm or more and 200 nm or less. The nitride semiconductor stack according to claim 6 or 7.

9. At the interface between the underlayer and the GaN layer, a diffusion layer containing Al and Ga formed by diffusing Al from the underlayer into the GaN layer and Ga from the GaN layer into the underlayer is not formed. The nitride semiconductor stack according to claim 6 or 7.

10. The nitride semiconductor substrate is an aluminum nitride single crystal substrate. The nitride semiconductor stack according to claim 6 or 7.

11. The miscut angle of the nitride semiconductor substrate is 0.1 degrees or more and 0.4 degrees or less. The nitride semiconductor stack according to claim 6 or 7.

12. The miscut direction of the nitride semiconductor substrate is the <10-10> direction. The nitride semiconductor stack according to claim 6 or 7.

13. The surface of the layer farthest from the nitride semiconductor substrate opposite to the nitride semiconductor substrate has a step-terrace structure in which steps, which are stepped portions, and flat terraces are repeated in the miscut direction of the nitride semiconductor substrate, and the terrace edges, which are the ends of the terraces, have a wave shape that has amplitude in the miscut direction of the nitride semiconductor substrate and extends in a direction perpendicular to the miscut direction of the nitride semiconductor substrate. The nitride semiconductor stack according to claim 6 or 7.

14. The underlayer and the GaN layer formed on the nitride semiconductor substrate are pseudomorphic to the nitride semiconductor substrate. The nitride semiconductor stack according to claim 6 or 7.

15. an Al layer provided between the underlayer and the GaN layer; ｚ１ Ga （１－ｚ１） a first low Al layer formed of N (0≦z1<x), The thickness of the first low Al layer is 0.5 nm or less. The nitride semiconductor stack according to claim 6 or 7.

16. an Al layer disposed on the GaN layer; ｙ Ga （１－ｙ） An electron barrier layer formed of N (0.7≦y≦1) The nitride semiconductor stack according to claim 12.

17. an Al layer provided between the electron barrier layer and the GaN layer; ｚ２ Ga （１－ｚ２） a second low Al layer formed of N (0≦z2<y), The second low Al layer has a thickness of 0.5 nm or less. The nitride semiconductor stack according to claim 16.

18. At the interface between the GaN layer and the underlayer, there are no misfit dislocations in the same direction as the miscut direction of the nitride semiconductor substrate. The nitride semiconductor stack according to claim 17.

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