Semiconductor apparatus and photoelectric conversion system

Abstract

To suppress diffusion of a metal element into a first semiconductor layer while improving protection performance for a semiconductor apparatus, thereby reducing deteriorate characteristics of the semiconductor apparatus.SOLUTION: A semiconductor apparatus includes a first substrate that includes a first wiring structure and a first semiconductor layer, and a second substrate that includes a second wiring structure and a second semiconductor layer. A first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are bonded to electrically connect the first semiconductor layer and the second semiconductor layer. In a plan view seen from a side of the first semiconductor layer, the second semiconductor layer is larger than the first semiconductor layer. The second wiring structure includes a guard structure that has a third metal pattern disposed at a same height as the second metal pattern. In the plan view, a contact portion between the third metal pattern and a diffusion preventing film in contact with the third metal pattern is disposed at a position outside the first semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a photoelectric conversion system. [Background technology]

[0002] In recent years, semiconductor devices have become known in which semiconductor layers of different sizes, each having a semiconductor element formed thereon, are stacked together. Patent Document 1 proposes a chip-on-wafer (CoW) technology in which a chip including a semiconductor layer and a wiring structure is bonded to a wafer including the semiconductor layer and the wiring structure using Cu-Cu bonding of metal patterns included in each wiring structure. In the Cu-Cu bonding, a metal pattern included in the wiring layer of the chip is directly bonded to a metal pattern included in the wiring layer of the wafer. Patent Document 1 also discloses forming a guard structure in a region of the wiring structure included in the wafer that is positioned outside the chip in a plan view to protect it from the effects of dicing in a subsequent process.

[0003] The technology disclosed in Patent Document 1 is said to enhance the protection performance of semiconductor devices by forming the guard structure on the same layer as the metal pattern included in the wafer, that is, up to the surface where the wafer and chip are bonded. Also, by forming the guard structure outside the chip in a plan view, it is possible to expand the area used as a circuit included in the wafer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-89275 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology disclosed in Patent Document 1, if the guard structure is formed outside the chip in a planar view and is formed up to the same layer as the metal pattern, the metal elements of the metal pattern may diffuse into the semiconductor layer included in the chip, possibly degrading the characteristics of the semiconductor layer included in the chip.

[0006] The semiconductor device of the present invention aims to suppress the diffusion of metal elements while improving the protection performance for the semiconductor device. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention comprises a first substrate including a first wiring structure and a first semiconductor layer, and a second substrate including a second wiring structure and a second semiconductor layer, wherein a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, and in a planar view viewed from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, and the second wiring structure includes a guard structure having a third metal pattern arranged at the same height as the second metal pattern, and in the planar view, a contact portion between the third metal pattern and a diffusion prevention film contacting the third metal pattern is located outside the first semiconductor layer.

[0008] In addition, a semiconductor device according to another embodiment has a first substrate including a first wiring structure and a first semiconductor layer, and a second substrate including a second wiring structure and a second semiconductor layer, wherein a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, and in a plan view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, and the second wiring structure includes a guard structure having a third metal pattern arranged at the same height as the second metal pattern, and in the plan view, a contact portion between the third metal pattern and a film in contact with the third metal pattern is located outside the first semiconductor layer, and the film is made of SiN, SiOC, SiON, or SiCN. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device that can suppress the diffusion of metal elements into the semiconductor layer included in the chip while improving the protection performance for the semiconductor device. [Brief explanation of the drawings]

[0010] [Figure 1] 1A and 1B are a schematic plan view and a schematic cross-sectional view of a semiconductor device according to a first embodiment; [Figure 2] 1 is a schematic cross-sectional view of a bonding portion of a semiconductor device according to a first embodiment; [Figure 3] 1 is a schematic cross-sectional view of a bonding portion of a semiconductor device according to a first embodiment; [Figure 4] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 5] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 8] 1A and 1B are a schematic plan view and a schematic cross-sectional view of a semiconductor device according to a second embodiment; [Figure 9] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 10] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 12] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 13] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a diagram showing the configuration of a photoelectric conversion system according to a third embodiment. [Figure 15] 10A and 10B are diagrams showing the configuration and operation of a moving body according to a fourth embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings. Note that the following embodiments do not limit the invention according to the claims. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0012] In the following embodiments, a photoelectric conversion device will be mainly described as an example of a semiconductor device. However, in each embodiment, the semiconductor device can be used for a light emitting device or the like in addition to a photoelectric conversion device. Furthermore, in the following, an imaging device will be described as an example of a photoelectric conversion device, but the photoelectric conversion device is not limited to this. For example, the semiconductor device can also be applied to photoelectric conversion devices such as a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)) and a photometric device (a device for measuring the amount of incident light).

[0013] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0014] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals.

[0015] In the following, a wafer refers to a substrate on which multiple semiconductor elements are formed by a semiconductor process before dicing, and a chip refers to an individual semiconductor element after dicing the wafer. For example, multiple imaging elements and multiple circuit units may be formed on the wafer.

[0016] (First embodiment) A semiconductor device 100 (photoelectric conversion device) according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS.

[0017] The schematic configuration of the semiconductor device 100 will be described with reference to FIG. 1. FIG. 1(a) is a schematic plan view of the semiconductor device 100, and FIG. 1(b) is a schematic cross-sectional view of plane AB of FIG. 1(a). In this specification, a plane refers to a plane viewed from the semiconductor layer 201 side (first semiconductor layer side) in a stacked structure of a semiconductor layer 201 (first semiconductor layer) and a semiconductor layer 301 (second semiconductor layer), which will be described later. A cross section refers to a plane viewed from a direction perpendicular to the stacking direction of the semiconductor layer 201 and the semiconductor layer 301, that is, a plane passing through the semiconductor layer 201 and the semiconductor layer 301. A planar view refers to a view taken from the above-mentioned plane, and a cross-sectional view refers to a view taken from a cross section passing through the semiconductor layer 201 and the semiconductor layer 301. For example, a planar view refers to a view taken from a direction perpendicular to a plane on which a plurality of pixels are arranged in a two-dimensional array.

[0018] As shown in FIG. 1, the semiconductor device 100 includes a substrate 200 (first substrate) having a semiconductor layer 201 and an interconnect structure 260 (first interconnect structure), and a substrate 300 (second substrate) having a semiconductor layer 301 and an interconnect structure 360 ​​(second interconnect structure). The interconnect structure 260 includes multiple interconnect layers 203 and interconnect interlayer films 202 disposed between the interconnect layers. Each interconnect layer has multiple metal patterns, and the interconnect interlayer films 202 are also disposed between the metal patterns. In addition, the metal pattern of one interconnect layer may be electrically connected to the metal pattern of an adjacent interconnect layer via a via plug. Similarly, the interconnect structure 360 ​​includes multiple interconnect layers 303 and interconnect interlayer films 302 disposed between the interconnect layers. Each interconnect layer has multiple metal patterns, and the interconnect interlayer films 302 are also disposed between the metal patterns.

[0019] The semiconductor layer 201 includes a first semiconductor element, and the semiconductor layer 301 includes a second semiconductor element. In the following, an example will be described in which the substrate 200 constitutes an imaging element and the substrate 300 constitutes a circuit section. In the following example, in the substrate 200, the semiconductor layer 201 includes a photodiode, which is a photoelectric conversion element, as the first semiconductor element. In addition, in the substrate 300, the semiconductor layer includes a signal processing circuit, which processes a signal from the photoelectric conversion element, as the second semiconductor element. Note that the first semiconductor element does not have to be a photoelectric conversion element, and may be an element such as a transistor, or a light-emitting element. When the first semiconductor element is a light-emitting element, the second semiconductor element may be, for example, a circuit that controls the light emission of the light-emitting element.

[0020] The semiconductor layer 201 has a plurality of pixels arranged therein, each pixel including a photoelectric conversion element, a transfer transistor, an amplification transistor, and a reset transistor. A configuration including at least one photoelectric conversion element is referred to as a pixel. In the following, a case where one pixel includes a photoelectric conversion element, a transfer transistor, an amplification transistor, and a reset transistor is described. The source of the transfer transistor is connected to the photoelectric conversion element, and the drain of the transfer transistor is connected to the gate electrode of the amplification transistor. The node that is the same as the gate electrode of the amplification transistor is referred to as a floating diffusion (FD). The reset transistor is connected to the FD, and sets the potential of the FD to an arbitrary potential (for example, a reset potential). Here, the amplification transistor is part of a source follower circuit, and outputs a signal corresponding to the potential of the FD to a signal line.

[0021] The arrangement of the amplifying transistor and the reset transistor is not limited to this. For example, the amplifying transistor and the reset transistor may be arranged in the semiconductor layer 301. This allows the area of ​​the photoelectric conversion element to be increased compared to when all components of the pixel are arranged in the semiconductor layer 201, thereby improving sensitivity. Furthermore, even if the area of ​​the photoelectric conversion element is not increased, it is possible to provide a large number of photoelectric conversion elements, thereby enabling a large number of pixels.

[0022] The semiconductor layer 301 is provided with peripheral circuits including a readout circuit and a control circuit. The peripheral circuits include a vertical scanning circuit, which is a control circuit for supplying control signals to the gate electrodes of the pixel transistors. The peripheral circuits also include a readout circuit that holds signals output from the pixels and performs signal processing such as amplification, addition, and AD conversion. The peripheral circuits also include a horizontal scanning circuit, which is a control circuit that controls the timing of sequentially outputting signals from the readout circuit.

[0023] The first semiconductor element may be an avalanche photodiode, in which case the semiconductor layer 201 does not need to include a transistor.

[0024] The semiconductor device 100 is constructed by bonding a substrate 200 and a substrate 300 together. The wiring layer located on the surface of the substrate 200 of the wiring structure 260 facing the second substrate has a metal pattern 204 (first metal pattern). Furthermore, the wiring layer located on the surface of the substrate 300 of the wiring structure 360 ​​facing the substrate 200 has a metal pattern 304 (second metal pattern). The substrates 200 and 300 are electrically connected by bonding the metal patterns included in each substrate. For example, the metal pattern 204 and the metal pattern 304 can each be made of a material mainly composed of Cu, and electrically connected by Cu-Cu bonding.

[0025] The substrate 300 has a guard structure 305 on the outer side of the substrate 200 in plan view. The guard structure 305 is provided to prevent the second semiconductor element of the substrate 300 from being affected by dicing when the semiconductor device 100 is diced into individual pieces. The guard structure 305 is connected to the semiconductor layer 301, and it is desirable that a metal layer is formed continuously up to the surface of the substrate 300 (the surface that will be bonded to the substrate 200). For example, as shown in FIG. 1(b), it is desirable that the guard structure 305 is formed by arranging a plurality of contact plugs, metal patterns, and via plugs to continuously connect the metal from the surface of the semiconductor layer 301 to the upper surface of the substrate 300. This makes it possible to reduce the effects of dicing.

[0026] The guard structure 305 has a metal pattern (third metal pattern) 317 that forms part of the bonding surface of the substrate 300. The metal pattern 317 is disposed at the same height as the metal pattern 304. The metal pattern 317 is located outside the semiconductor layer 201 in a planar view. By forming at least a part of the guard structure 305 outside the substrate 200 in a planar view, it is possible to expand the area of ​​the substrate 300 that can be effectively used. In a planar view, the contact portion between the metal pattern 317 and the diffusion prevention film 401 that contacts the metal pattern 317 is located outside the semiconductor layer 201. In other words, in a planar view, the contact portion is located outside the edge (end portion) of the semiconductor layer 201.

[0027] The metal pattern 317 is electrically connected to the semiconductor layer 301. For example, a fixed potential can be supplied to the metal pattern 317. This can prevent problems that may occur when the metal pattern 317 becomes floating.

[0028] The guard structure 305 may be, for example, ring-shaped in plan view. If metal elements contained in the metal pattern 317 of the guard structure 305 diffuse into the semiconductor layer 201, this may cause deterioration in the characteristics of the substrate 200. In other words, this may result in a decrease in the protective performance of the semiconductor device. Therefore, in this embodiment, a diffusion prevention film 401 (film) is provided in contact with the metal pattern 317 of the guard structure 305 to prevent the diffusion of metal elements. The diffusion prevention film 401 is preferably disposed so as to cover the top of the guard structure 305 in cross-sectional view. For example, as shown in FIG. 1( a), it may be disposed in a ring-shaped manner in plan view. Furthermore, a guard structure may also be disposed in the wiring structure 260 of the substrate 200.

[0029] The guard structure 305 does not have to be made entirely of metal, but may be made of an insulating material different from the wiring interlayer film 302, instead of a metal via plug, between metal patterns, as long as it is resistant to the effects of dicing.

[0030] 1(c), the substrate 200 may also have a guard structure 205. The guard structure 205 is provided to protect the first semiconductor elements of the substrate 200 from being affected by dicing when the substrate 200 is diced into individual pieces. The guard structure 205 is connected to the semiconductor layer 201, and it is desirable that a metal layer is formed continuously up to the surface of the substrate 200, and the guard structure 205 may further be connected to the metal pattern 304.

[0031] As shown in Fig. 1(a), a plurality of pads 600 are arranged inside the guard structure 305. The pads 600 have the function of outputting signals (image signals) based on charges generated in the photoelectric conversion elements to the substrates 200 and 300, and the function of inputting voltages for driving peripheral circuits supplied from the outside. Fig. 1(a) shows an example in which the pads are arranged on the substrate 300, but the pads 600 may also be arranged on the substrate 200.

[0032] On the surface of the substrate 200 of the semiconductor device 100 opposite to the circuit board that will become the substrate 300, optical structures such as a color filter 403 and a microlens 404 may be arranged.

[0033] As described above, the semiconductor device according to this embodiment is a back-illuminated stacked sensor using Chip On Wafer (CoW) technology.

[0034] 2(a), 2(b), 3(a), and 3(b) are examples showing enlarged views of metal patterns 204, 304, and 317 on the bonding surfaces of substrates 200 and 300. Any of these examples may be used in this embodiment.

[0035] As shown in FIGS. 2 and 3, the metal patterns 204, 304, and 317 may each include a conductor 204a, 304a, or 317a and a conductive film 204b, 304b, or 317b made of a material different from the conductor. The conductors 204a, 304a, and 317a may be made of different materials, but preferably the same material. The conductive films 204b, 304b, and 317b function as a film that prevents the diffusion of metal elements from the conductor. The conductive films 204b, 304b, and 317b may be made of different materials, but preferably the same material. The side surfaces of the conductor and the surface opposite to the surface that contacts another conductor are preferably covered with a conductive film. This ensures that the conductor remains covered with the conductive film even after bonding, thereby suppressing the generation of dark current and leakage current. For example, Cu can be used as the conductor.

[0036] In the following description, the conductors 204a, 304a, and 317a are made of the same material, and the conductive films 204b, 304b, and 317b are made of the same material. In the following description, a single damascene structure interconnect is formed by a single damascene method, in which a groove that becomes the interconnect is formed in an interconnect interlayer film and then filled with a conductive film or a conductor such as copper that functions as a barrier metal, and has the interconnect embedded in the interconnect interlayer film. A dual damascene structure interconnect is formed so that the interconnect and via are integrated, and has the interconnect and via embedded in the interconnect interlayer film. It is formed by a dual damascene method, in which a groove that becomes the interconnect and via is formed in an interconnect interlayer film and then filled with a conductive film or a conductor such as copper that functions as a barrier metal, and has the interconnect embedded in the interconnect interlayer film.

[0037] In FIG. 2(a), the conductor 204a of the metal pattern 204 and the conductor 304a of the metal pattern 304 are in contact with each other. A conductive film 204b is arranged in contact with the conductor 204a so as to cover the conductor 204a except for the contact surface with the conductor 304a. The conductive film 204b is arranged in contact with the metal pattern 206 of the adjacent wiring layer. The metal pattern 206 has a conductor 206a and a conductive film 206b. The conductor 206a is mainly composed of, for example, Cu, and the conductive film 206b is mainly composed of, for example, a material that prevents the diffusion of Cu. The conductive film 206b may also be arranged on the side opposite the metal pattern 204. The conductive film 204b penetrates a portion of the conductive film 206b and is in contact with the conductor 206a.

[0038] The conductor 317a of the metal pattern 317 is in contact with the diffusion prevention film 401. This makes it possible to prevent the conductor 317a from diffusing.

[0039] As shown in FIG. 2(b), the metal patterns 204 and 304 may be misaligned at the bonding surface. In this case, the conductor 203a comes into contact with both the conductor 304a and the conductive film 304b. Furthermore, if the metal patterns 204 and 304 are misaligned at the time of bonding, the metal elements of the conductors of each metal pattern may diffuse into the inter-wiring layer film. Therefore, to prevent the diffusion of metal between the metal patterns 204 and 304, diffusion barrier films 410a (second diffusion barrier film, second film) and 410b are provided. As described below, the diffusion barrier films 410a and 410b are provided before bonding the substrates 200 and 300, and can prevent the diffusion of metal elements of the metal patterns 204 and 304. On the other hand, since the chip-shaped substrate 200 is bonded to the wafer-shaped substrate 300, it is difficult to leave only the diffusion barrier film on the metal pattern 317. Therefore, the diffusion barrier film 410a and the diffusion barrier film 401 may be disposed in different processes.

[0040] The diffusion prevention film 410a and the diffusion prevention film 401 may be made of different materials or may be made of the same material. For example, the diffusion prevention film 410a may be made of silicon nitride or the like. As shown in Figures 2(a) and 2(b), the diffusion prevention film 401 is preferably thicker than the diffusion prevention film 410a. However, the diffusion prevention film 401 and the diffusion prevention film 410a may have the same thickness.

[0041] The thickness of the diffusion prevention film 401 is preferably, for example, in the range of 10 nm to 300 nm, and more preferably in the range of 20 nm to 150 nm. The thickness of the diffusion prevention film 401 is preferably, for example, in the range of 1 / 2 to 1 / 5 times the thickness of the metal pattern 317. In FIG. 3(a), the shapes of the metal patterns 204, 304, and 317 are different from those in FIG. 2(b). The metal pattern 206 may be composed of a conductor and a conductive film.

[0042] 3(b), the diffusion prevention films 410a and 410b may be disposed at positions away from the bonding surface, which still prevents diffusion of metal elements from the metal patterns 204 and 304 into the adjacent wiring layers.

[0043] Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 4 to 7. Figures 4 to 7 are cross-sectional views showing the steps in the method for manufacturing a semiconductor device according to this embodiment.

[0044] 4, substrate 200 including a chip-shaped imaging element is bonded to wafer-state substrate 300 including multiple circuit sections. Metal patterns 304 and 204, for example, mainly made of Cu, are arranged on substrate 300 and substrate 200, and can be bonded by Cu-Cu metal bonding and covalent bonding between wiring interlayer film 202 and wiring interlayer film 302. At this time, diffusion barrier films containing, for example, silicon nitride (SiN) can be formed on parts of wiring interlayer film 202 and wiring interlayer film 302 to suppress diffusion of metal elements included in metal pattern 304 of the wiring layer and metal pattern 204 of the wiring layer. At this time, guard structure 305 is in a state where the wiring layer on which metal pattern 304 is arranged is exposed.

[0045] 5, for example, a silicon nitride film is deposited, and then a diffusion barrier film 401 is formed using photolithography and etching techniques. Examples of materials for the diffusion barrier film 401 include silicon nitride, silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), and carbon-containing silicon nitride (SiCN). When forming the diffusion barrier film 401, a film similar to the diffusion barrier film may remain on the side surface of the substrate 200. In this case, it is possible to improve the moisture resistance of the substrate 200. Furthermore, by removing the diffusion barrier film 401 from the surface of the semiconductor device 100 that will be diced, problems such as film peeling during dicing can be avoided.

[0046] 6, for example, silicon oxide is deposited and planarized to form an insulating film 402, and the semiconductor layer 201 is further thinned to a suitable thickness. The step of thinning the semiconductor layer 201 can be performed by, for example, CMP, and may include a step of controlling the film thickness using a difference in etching rate with respect to a chemical solution due to a difference in the concentration of impurities contained in the semiconductor layer 201.

[0047] Subsequently, as shown in FIG. 7, optical structures such as color filters 403 and microlenses 404 are formed on the semiconductor layer 201, and the resulting semiconductor device is separated into individual pieces by dicing, thereby obtaining the semiconductor device shown in FIG.

[0048] According to the semiconductor device of this embodiment, the metal pattern of guard structure 305 is covered with diffusion prevention film 401, which prevents defects in semiconductor layer 201 caused by diffusion of metal elements in the metal pattern. Furthermore, according to the manufacturing method of the semiconductor device of this embodiment, guard structure 305 can prevent defects in substrate 300 caused by dicing, and the formation of diffusion prevention film 401 after dicing makes it possible to prevent defects such as peeling of diffusion prevention film 401.

[0049] (Second embodiment) A semiconductor device and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS.

[0050] The schematic configuration of the semiconductor device according to this embodiment will be described with reference to Fig. 8. Fig. 8(a) is a schematic plan view of the semiconductor device according to this embodiment, and Fig. 8(b) is a schematic cross-sectional view of the AB plane of Fig. 8(a).

[0051] The second embodiment differs from the first embodiment in that a circuit portion, which is a chip-state substrate 300 (first substrate), is bonded to a wafer-state substrate 200 (second substrate). Also, the substrate 300 has a memory circuit 300a and a logic circuit 300b, which are separate chips bonded to a single imaging element included in the substrate 200. Other than these points and points described below, the configuration is substantially the same as the first embodiment, and therefore, description may be omitted.

[0052] In this embodiment, the semiconductor layer 201 of the substrate 200 is larger than the semiconductor layer 301 of the substrate 300 in plan view.

[0053] The substrate 200 includes a guard structure 205. The guard structure 205 is similar to the guard structure 305 described in the first embodiment, and includes a metal pattern on the bonding surface with the substrate 300. The metal pattern of the guard structure 205 is covered with a diffusion prevention film 401. This prevents metal elements of the metal pattern of the guard structure 205 from diffusing into the semiconductor layer 301. Furthermore, at least a portion of the guard structure 205 is formed outside the memory circuit 300a and the logic circuit 300b in a plan view.

[0054] 8(c), the substrate 300 may include a guard structure 305. The guard structure 305 is similar to the guard structure 205 described in the first embodiment, and the guard structure 305 may be connected to the metal pattern 204.

[0055] A support substrate 500 is disposed on the side of the substrate 300 opposite to the substrate 200. Furthermore, similar to the first embodiment, optical structures such as a color filter 403 and a microlens 404 are disposed on the surface of the substrate 200 opposite to the substrate 300.

[0056] The diffusion prevention film 401 is disposed not only on the guard structure 205 but also on the side surfaces of the substrate 300 and the surface opposite to the bonding surface. As shown in Fig. 8(b), it is preferable that the diffusion prevention film 401 continuously covers the surfaces other than the bonding surface with the substrate 200. In Fig. 8(b), the diffusion prevention film 401 covers the side surfaces of the memory circuit 300a and the logic circuit 300b and the surface opposite to the bonding surface with the substrate 200.

[0057] Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 9 to 13. Figures 9 to 13 are cross-sectional views showing the steps in the method for manufacturing a semiconductor device according to this embodiment. In FIG. 9, a substrate 300 including a chip-shaped memory circuit 300a and a logic circuit 300b is bonded to a wafer-like substrate 200 having a plurality of imaging elements arranged thereon. In this embodiment, two circuit chips are bonded to one imaging element, but the number of bonded circuit chips may be one or more. As in the first embodiment, the memory circuit 300a and the logic circuit 300b are bonded by Cu-Cu metal bonding and covalent bonding between the wiring interlayer film 202 and the wiring interlayer film 302. After bonding the chips, a process of thinning the semiconductor layer 301 may be performed. At least a portion of the guard structure 205 is formed outside the memory circuit 300a and the logic circuit 300b in a plan view.

[0058] Next, as shown in FIG. 10, silicon nitride (SiN) is deposited as a diffusion prevention film 401. As in the first embodiment, materials such as silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), and carbon-containing silicon nitride (SiCN) can be used for the diffusion prevention film 401 in addition to silicon nitride. Among these, it is preferable to use silicon nitride or silicon oxynitride from the viewpoint of improving moisture resistance. In this embodiment, by leaving the diffusion prevention film 401 on the side and top surfaces of the memory circuit 300a and the logic circuit 300b, it is possible to improve the moisture resistance of the memory circuit 300a and the logic circuit 300b.

[0059] As in the first embodiment, a step of removing a portion of the silicon nitride that will become the diffusion prevention film 401 may be performed. When performing the removal step, for example, by removing the diffusion prevention film 401 from the dicing surface, problems such as film peeling during dicing can be avoided.

[0060] Next, for example, silicon oxide is deposited and planarized as shown in Fig. 11. After planarization, a bonding layer made of, for example, silicon nitride or silicon oxynitride may be formed on the upper surface.

[0061] 12, bonding is performed to a support substrate 500 via a bonding surface 501. A bonding layer made of silicon nitride or silicon oxynitride is formed on the support substrate 500. Then, the bonding layers made of silicon nitride or silicon oxynitride are bonded to each other at the bonding surface 501.

[0062] Next, as shown in FIG. 13, a step of thinning the semiconductor layer 201 is carried out, and optical structures such as a color filter 403 and a microlens 404 are formed.

[0063] (Third embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Fig. 14. Fig. 14 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0064] The semiconductor device (imaging device) described in the first and second embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Also included in the photoelectric conversion system is a camera module equipped with an optical system such as a lens and an imaging device. Fig. 14 illustrates a block diagram of a digital still camera as an example of such systems.

[0065] 14 includes an imaging device 1004, which is an example of a semiconductor device, and a lens 1002 that forms an optical image of a subject on the imaging device 1004. The imaging device 1004 further includes an aperture 1003 that adjusts the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the imaging device 1004. The imaging device 1004 is a semiconductor device (imaging device) according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0066] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as necessary to output image data. The signal processing unit 1007 may be formed on the same semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004. Alternatively, the imaging device 1004 and the signal processing unit 1007 may be formed on the same semiconductor substrate.

[0067] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0068] The photoelectric conversion system further includes an overall control and calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0069] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0070] As described above, according to this embodiment, it is possible to realize a photoelectric conversion system to which the semiconductor device (imaging device) according to any one of the above embodiments is applied.

[0071] (Fourth embodiment) The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 15. Fig. 14 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0072] FIG. 15(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 1300 includes an imaging device 1310. The imaging device 1310 is the semiconductor device (imaging device) described in any of the above embodiments. The photoelectric conversion system 1300 includes an image processing unit 1312 that performs image processing on multiple pieces of image data acquired by the imaging device 1310. The photoelectric conversion system 1300 also includes a parallax acquisition unit 1314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 1300. The photoelectric conversion system 1300 also includes a distance acquisition unit 1316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 1314 and the distance acquisition unit 1316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 1318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0073] The photoelectric conversion system 1300 is connected to a vehicle information acquisition device 1320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 1300 is also connected to a control ECU 1330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 1318. The photoelectric conversion system 1300 is also connected to an alarm device 1340 that issues an alarm to the driver based on the determination result of the collision determination unit 1318. For example, if the determination result of the collision determination unit 1318 indicates a high collision possibility, the control ECU 1330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0074] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 1300. Fig. 15(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 1350). A vehicle information acquisition device 1320 sends instructions to the photoelectric conversion system 1300 or the imaging device 1310. This configuration can further improve the accuracy of distance measurement.

[0075] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the subject vehicle, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generator that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generator can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, a propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0076] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0077] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present invention.

[0078] Furthermore, the photoelectric conversion systems shown in the third and fourth embodiments are examples of photoelectric conversion systems to which the semiconductor device can be applied, and photoelectric conversion systems to which the semiconductor device of the present invention can be applied are not limited to the configurations shown in Figures 14 and 15.

[0079] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0080] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), then even if the statement that "A is not B" (A≠B) is omitted, this specification is deemed to disclose or suggest that "A is not B." This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0081] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0082] The present invention also includes the following configurations.

[0083] (Configuration 1) a first substrate including a first wiring structure and a first semiconductor layer, and a second substrate including a second wiring structure and a second semiconductor layer, wherein a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, and in a planar view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, and the second wiring structure includes a guard structure having a third metal pattern arranged at the same height as the second metal pattern, and in the planar view, a contact portion between the third metal pattern and a diffusion prevention film contacting the third metal pattern is located outside the first semiconductor layer.

[0084] (Configuration 2) 2. The semiconductor device according to configuration 1, wherein the diffusion barrier film is made of SiN, SiOC, SiON, or SiCN.

[0085] (Configuration 3) 3. The semiconductor device according to claim 1, wherein the diffusion prevention film is disposed continuously up to the side surface of the first semiconductor layer.

[0086] (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein the diffusion prevention film is disposed continuously up to the side of the first semiconductor layer opposite to the side of the second semiconductor layer.

[0087] (Configuration 5) The semiconductor device according to configuration 4, wherein at least one of the first metal pattern and the second metal pattern is in contact with a second diffusion barrier film, and the thickness of the diffusion barrier film is greater than the thickness of the second diffusion barrier film.

[0088] (Configuration 6) a first substrate including a first wiring structure and a first semiconductor layer, and a second substrate including a second wiring structure and a second semiconductor layer, wherein a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, the second semiconductor layer is larger than the first semiconductor layer in a plan view seen from the first semiconductor layer side, the second wiring structure includes a guard structure having a third metal pattern arranged at the same height as the second metal pattern, a contact portion between the third metal pattern and a film in contact with the third metal pattern is located outside the first semiconductor layer in the plan view, and the film is made of SiN, SiOC, SiON, or SiCN.

[0089] (Configuration 7) 7. The semiconductor device according to claim 6, wherein the film is disposed continuously up to the side surface of the first semiconductor layer.

[0090] (Configuration 8) 8. The semiconductor device according to structure 6 or 7, wherein the film is disposed continuously up to the side of the first semiconductor layer opposite to the side of the second semiconductor layer.

[0091] (Configuration 9) At least one of the first metal pattern and the second metal pattern is in contact with a second film, 9. The semiconductor device according to any one of configurations 6 to 8, wherein the thickness of the film is greater than the thickness of the second film.

[0092] (Configuration 10) 10. The semiconductor device according to any one of configurations 1 to 9, wherein the third metal pattern is made of a material containing Cu as a main component.

[0093] (Configuration 11) 11. The semiconductor device according to any one of configurations 1 to 10, wherein the third metal pattern is electrically connected to the second semiconductor layer.

[0094] (Configuration 12) 12. The semiconductor device according to any one of structures 1 to 11, wherein the third metal pattern is connected to a contact plug connected to the second semiconductor layer through at least one of a metal pattern and a via plug in a cross section passing through the first semiconductor layer and the second semiconductor layer.

[0095] (Configuration 13) The semiconductor device described in structure 12, characterized in that, in the cross section, the third metal pattern is connected to the second semiconductor layer continuously through the contact plug, the metal pattern, and the via plug.

[0096] (Configuration 14) 14. The semiconductor device according to any one of structures 1 to 13, wherein the first semiconductor layer includes a photoelectric conversion element.

[0097] (Configuration 15) 14. The semiconductor device according to any one of structures 1 to 13, wherein the second semiconductor layer includes a photoelectric conversion element.

[0098] (Configuration 16) 16. The semiconductor device according to any one of configurations 1 to 15, wherein the contact portion is located outside an edge of the first semiconductor layer in the plan view.

[0099] (Configuration 17) 17. A photoelectric conversion system comprising: the semiconductor device according to any one of configurations 1 to 16; and a signal processing unit that generates an image using a signal output by the semiconductor device.

[0100] (Configuration 18) A moving object comprising the semiconductor device according to any one of claims 1 to 16, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the semiconductor device. [Explanation of symbols]

[0101] 100 Semiconductor device 200 boards 201 Semiconductor layer 202 Interlayer film 203 Wiring layer 204 Metal Pattern 205 Guard Structure 300 boards 301 Semiconductor layer 302 Interlayer film 303 Wiring layer 304 Metal Pattern 305 Guard Structure 401 Diffusion prevention film

Claims

1. a first substrate including a first wiring structure and a first semiconductor layer; a second substrate including a second wiring structure and a second semiconductor layer; a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined together, and the first semiconductor layer and the second semiconductor layer are electrically connected to each other; In a plan view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, the second wiring structure includes a guard structure having a third metal pattern disposed at the same height as the second metal pattern; In the plan view, a contact portion between the third metal pattern and a diffusion prevention film that contacts the third metal pattern is located outside the first semiconductor layer.

2. 2. The semiconductor device according to claim 1, wherein the third metal pattern is made of a material containing Cu as a main component.

3. 3. The semiconductor device according to claim 2, wherein the diffusion barrier film is made of SiN, SiOC, SiON, or SiCN.

4. 4. The semiconductor device according to claim 3, wherein the diffusion prevention film is disposed continuously up to a side surface of the first semiconductor layer.

5. 2. The semiconductor device according to claim 1, wherein the third metal pattern is electrically connected to the second semiconductor layer.

6. 2. The semiconductor device according to claim 1, wherein the third metal pattern is connected to a contact plug connected to the second semiconductor layer through at least one of a metal pattern and a via plug in a cross section passing through the first semiconductor layer and the second semiconductor layer.

7. 7. The semiconductor device according to claim 6, wherein the third metal pattern is connected to the second semiconductor layer through the contact plug, the metal pattern, and the via plug in the cross section.

8. The semiconductor device according to claim 1 , wherein the first semiconductor layer includes a photoelectric conversion element.

9. The semiconductor device according to claim 1 , wherein the second semiconductor layer includes a photoelectric conversion element.

10. 6. The semiconductor device according to claim 5, wherein the diffusion prevention film is disposed continuously up to the side of the first semiconductor layer opposite to the side of the second semiconductor layer.

11. At least one of the first metal pattern and the second metal pattern is in contact with a second diffusion barrier film, 2. The semiconductor device according to claim 1, wherein the thickness of the diffusion barrier film is greater than the thickness of the second diffusion barrier film.

12. The semiconductor device according to claim 1 , wherein the contact portion is located outside an edge of the first semiconductor layer in the plan view.

13. a first substrate including a first wiring structure and a first semiconductor layer; a second substrate including a second wiring structure and a second semiconductor layer; a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined together, and the first semiconductor layer and the second semiconductor layer are electrically connected to each other; In a plan view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, the second wiring structure includes a guard structure having a third metal pattern disposed at the same height as the second metal pattern; a contact portion between the third metal pattern and a film in contact with the third metal pattern is located outside the first semiconductor layer in the plan view; The semiconductor device is characterized in that the film is made of SiN, SiOC, SiON, or SiCN.

14. 14. The semiconductor device according to claim 13, wherein the third metal pattern is made of a material containing Cu as a main component.

15. The semiconductor device according to claim 13 , wherein the film is disposed continuously up to a side surface of the first semiconductor layer.

16. 14. The semiconductor device according to claim 13, wherein the third metal pattern is electrically connected to the second semiconductor layer.

17. 14. The semiconductor device according to claim 13, wherein the third metal pattern is connected to a contact plug connected to the second semiconductor layer through at least one of a metal pattern and a via plug in a cross section passing through the first semiconductor layer and the second semiconductor layer.

18. 18. The semiconductor device according to claim 17, wherein the third metal pattern is connected to the second semiconductor layer through the contact plug, the metal pattern, and the via plug in the cross section.

19. The semiconductor device according to claim 13 , wherein the first semiconductor layer includes a photoelectric conversion element.

20. The semiconductor device according to claim 13 , wherein the second semiconductor layer includes a photoelectric conversion element.

21. 16. The semiconductor device according to claim 15, wherein the film is disposed continuously up to the side of the first semiconductor layer opposite to the side of the second semiconductor layer.

22. At least one of the first metal pattern and the second metal pattern is in contact with a second film, 14. The semiconductor device according to claim 13, wherein the thickness of the film is greater than the thickness of the second film.

23. The semiconductor device according to claim 13 , wherein the contact portion is located outside an edge of the first semiconductor layer in the plan view.

24. A semiconductor device according to any one of claims 1 to 23; a signal processing unit that generates an image using a signal output from the semiconductor device.

25. A moving object comprising the semiconductor device according to any one of claims 1 to 23, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the semiconductor device.

Images