Hermetic layer above die and mold material within package

Abstract

To provide systems, apparatuses and processes for applying a hermetic layer within a semiconductor package to prevent or mitigate migration of moisture across a layer of material.SOLUTION: In a package 200, a protective layer 220, which may be a hermetic layer, a nitride layer, or a dielectric layer, is disposed on an encapsulant 216 and / or on a die 208. The hermetic layer is disposed within the package on top of one or more dies surrounded by the encapsulant. The hermetic layer or a bonding layer 218 on top of the hermetic layer can be used to facilitate bonding to a silicon wafer after removal of a glass layer 222.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] [Background technology] The continuous reduction in size of electronic devices such as smartphones and ultrabooks is a driving force behind the development of high quality, reduced size system-in-package components. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 shows a cross-sectional side view of a conventional package having a bonding layer on top of multiple dies surrounded by a filler material to which silicon wafers are fused.

[0003] [Figure 2A] 2A-2B show various diagrams and images illustrating a hermetic layer on multiple dies surrounded by a filler material, along with a bonding layer on the hermetic layer fused to a silicon wafer, according to various embodiments. [Figure 2B] 2A-2B show various diagrams and images illustrating a hermetic layer on multiple dies surrounded by a filler material, along with a bonding layer on the hermetic layer fused to a silicon wafer, according to various embodiments.

[0004] [Figure 3A] 3A-3B show perspective views of a silicon wafer being fused to another wafer containing multiple packages, and a top-down view of a cross section of the wafers after fusion bonding, according to various embodiments. [Figure 3B] 3A-3B show perspective views of a silicon wafer being fused to another wafer containing multiple packages, and a top-down view of a cross section of the wafers after fusion bonding, according to various embodiments.

[0005] [Figure 4] FIG. 4 illustrates a package according to various embodiments having a hermetic layer over multiple dies surrounded by a filler material, with the hermetic layer fused to the silicon wafer.

[0006] [Figure 5] FIG. 5 is a cross-sectional top-down view of a package having a layout of multiple dies separated by filler material and having an airtight layer over the dies within the filler material, according to various embodiments.

[0007] [Figure 6A] 6A-6G illustrate cross-sectional side views of various stages in a manufacturing process for creating a package according to various embodiments, including an airtight layer over multiple dies surrounded by a filler material, with a bonding layer on the airtight layer. [Figure 6B] 6A-6G illustrate cross-sectional side views of various stages in a manufacturing process for creating a package according to various embodiments, including an airtight layer over multiple dies surrounded by a filler material, with a bonding layer on the airtight layer. [Figure 6C] 6A-6G illustrate cross-sectional side views of various stages in a manufacturing process for creating a package according to various embodiments, including an airtight layer over multiple dies surrounded by a filler material, with a bonding layer on the airtight layer. [Figure 6D] 6A-6G illustrate cross-sectional side views of various stages in a manufacturing process for creating a package according to various embodiments, including an airtight layer over multiple dies surrounded by a filler material, with a bonding layer on the airtight layer. [Figure 6E] 6A-6G illustrate cross-sectional side views of various stages in a manufacturing process for creating a package according to various embodiments, including an airtight layer over multiple dies surrounded by a filler material, with a bonding layer on the airtight layer. [Figure 6F] 6A-6G illustrate cross-sectional side views of various stages in a manufacturing process for creating a package according to various embodiments, including an airtight layer over multiple dies surrounded by a filler material, with a bonding layer on the airtight layer. [Figure 6G]6A-6G illustrate cross-sectional side views of various stages in a manufacturing process for creating a package according to various embodiments, including an airtight layer over multiple dies surrounded by a filler material, with a bonding layer on the airtight layer.

[0008] [Figure 7A] 7A-7B illustrate cross-sectional side views of various stages in a manufacturing process for creating a package including a hermetic layer over multiple dies surrounded by a filler material, with a portion of a silicon wafer fusion-bonded to the hermetic layer, according to various embodiments. [Figure 7B] 7A-7B illustrate cross-sectional side views of various stages in a manufacturing process for creating a package including a hermetic layer over multiple dies surrounded by a filler material, with a portion of a silicon wafer fusion-bonded to the hermetic layer, according to various embodiments.

[0009] [Figure 8] FIG. 8 illustrates an example process for manufacturing a package that includes a hermetic layer over multiple dies surrounded by a filler material and a bonding layer over the hermetic layer, according to various embodiments.

[0010] [Figure 9] FIG. 9 is a diagram illustrating a schematic diagram of a computing device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiments of the present disclosure may generally relate to systems, devices, techniques, and / or processes directed to applying a layer of material within a semiconductor package, where the layer of material may have hermetic properties, for example, to prevent or mitigate moisture migration or movement across the layer of material. In embodiments, the layer of material may include nitrogen and may include a nitride, such as SiNx or silicon nitride (Si3N4). In embodiments, the layer of material may be a dielectric layer. In embodiments, the layer of material may be referred to as a protective layer or a hermetic layer.

[0012] In embodiments, the protective layer may be disposed above another layer within the package that includes one or more dies at least partially or partially surrounded by a filler material. In embodiments, this filler material may be referred to as a chip gap filler, mold, or molding compound. In embodiments, the filler material may include an epoxy used to bond filler particles, including, but not limited to, silicon dioxide (SiO2). In embodiments, the protective layer may contact a portion of the one or more dies and a portion of the filler material. In this manner, moisture that may be absorbed into the filler material during or after package assembly can be prevented from crossing the protective layer.

[0013] In embodiments, the nitride composition in the protective layer may allow the protective layer to conform to any uneven surfaces of the package layers, including the die and fill material, during application. In this manner, the conformal application may serve to prevent voids from forming between the protective layer and the fill material, thereby reducing the number of delaminations and / or failure points in the package.

[0014] In embodiments, the surface of the protective layer opposite the package layer containing the one or more dies and filler material may be substantially flat or may be polished to a flat surface, which may result in other materials being fused to the surface of the protective layer. In embodiments, the silicon wafer may be fused to the protective layer.

[0015] In other embodiments, a bonding layer, which may contain oxygen, may be placed on the surface of the protective layer, and another material, such as a silicon wafer or glass layer, may be fused to the bonding layer. In embodiments, this fusion may include a dielectric-to-dielectric bonding technique. In other embodiments, other bonding or direct bonding techniques may be used.

[0016] In embodiments, in addition to providing a hermetic seal to prevent or reduce moisture penetration into the protective layer, a protective layer including nitride may provide better adhesion with the fill material and one or more dies, as well as with a bonding layer including oxide that may be on the protective layer. Additionally, a protective layer including nitride may be more conformal to imperfections on the surface of the fill material or one or more dies.

[0017] In embodiments, a layer of the protective layer including nitride may be applied using a low-temperature deposition technique. In embodiments, this technique may include low-temperature physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin-coating. A bondable dielectric may then be applied to the protective layer in preparation for fusion bonding. In embodiments, this bondable dielectric may be applied as a layer using a different technique and under more flexible conditions, such as higher temperatures. In embodiments, the bondable dielectric may be applied using PVD, CVD, or plasma enhanced chemical vapor deposition (PECVD) techniques.

[0018] In embodiments, the protective layer may be a dielectric, and may also function as a stop layer for planarization of a bonding dielectric layer deposited on top of it, for example, using chemical mechanical polishing (CMP) or etching techniques.

[0019] In embodiments, the nitride-containing protective layer nominally provides a hermetic seal, but also promotes adhesion to the high-quality deposition of the bonding dielectric layer, thus enabling better fusing while reducing the risk of delamination of the bonding dielectric to the die backside. Additionally, the protective layer may also mitigate die cracking due to different properties of exposed materials, such as the material of one or more of the die and the fill material.

[0020] Furthermore, in embodiments, the nitride-containing protective layer allows for the flexibility of using several different processing techniques to deposit the bond dielectric layer with different, more severe processing conditions. This opens up the possibility of using a higher quality bond dielectric for the fusion process that is deposited under optimized conditions. In embodiments, the higher quality bond dielectric can include SiOx, SiCN, SiON, and / or SiNx.

[0021] Furthermore, in embodiments, in stacked die architectures having exposed silicon surfaces of one or more dies and a fill material surrounding the dies, there is often dishing on the die backside after the mold grinding process during manufacturing. The irregularities in this dishing on the die backside can result in uneven topography of the bonding dielectric when deposited directly on the die backside. Consequently, this can result in gaps and voids present after the structural silicon wafer fusion step. In embodiments, the protective layer may partially act as a fill layer, filling these dished areas using a conformal deposition technique. As a result, there may be a flatter final bonding surface for the bonding layer to adhere to, resulting in fewer or no voids in the package after fusion.

[0022] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, where like numerals indicate like parts throughout, and in which are shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0023] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0024] The descriptions may use perspectives such as top / bottom, in / out, above or above / below or over / under, etc. Such descriptions are used for ease of discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0025] The description may use the terms "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, terms such as "comprising," "including," and "having," when used with respect to embodiments of the present disclosure, are synonymous.

[0026] The term "coupled with," along with its derivatives, may be used herein. "Coupled" may have one or more of the following meanings: "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "coupled" may mean that two or more elements are in indirect contact with each other.

[0027] Various operations may be described sequentially as multiple discrete operations in a manner that is most helpful in understanding the claimed subject matter, however, the order of description should not be construed to imply that these operations are necessarily order dependent.

[0028] As used herein, the term "module" may refer to, be part of, or include an ASIC, electronic circuitry, processors (shared, dedicated, or group) and / or memory (shared, dedicated, or group) executing one or more software or firmware programs, combinatorial logic circuitry, and / or other suitable components that provide the described functionality.

[0029] Various drawings herein may show one or more layers of one or more package assemblies. The layers shown herein are shown as examples of the relative positions of layers of different package assemblies. The layers are depicted for illustrative purposes and are not drawn to scale. Therefore, relative sizes of layers should not be inferred from the drawings, and sizes, thicknesses, or dimensions may be assumed for some embodiments only when specifically shown or discussed.

[0030] Various embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) storing instructions that, when executed, result in the actions of any of the above-described embodiments. Additionally, some embodiments may include devices or systems having any suitable means for performing the various operations of the above-described embodiments.

[0031] 1 shows a cross-sectional side view of a legacy package having a bonding layer on top of multiple dies surrounded by a filler material to which silicon wafers are fused. The legacy package 100 includes a base die 102, which in some implementations may be a substrate. In some implementations, the base die 102 may have one or more conductive vias 104 extending through the base die 102 and electrically coupling with conductive bumps 106 on the surface of the base die 102.

[0032] In implementations, the redistribution layer 110 may be on the base die 102 and may include bumps 112 electrically coupled to one or more dies 108. In implementations, the bumps 112 may be electrically coupled to conductive vias 104 of the base die 102. In implementations, an underfill material 114 may be underneath one or more dies 108. In implementations, a filler material 116, which may be a mold compound including epoxy and filler particles, may be disposed between one or more dies 108 and on the underfill material 114.

[0033] In an implementation, a bonding layer 118, sometimes referred to as a bondable dielectric layer, may be disposed over one or more dies 108 and over filler material 116. After bonding layer 118 is disposed, layer 122 may be fused to bonding layer 118. In an implementation, layer 122 may be a silicon layer, a glass layer, another package component, a silicon layer, an interposer, or a structural element to support processing of multiple conventional packages 100 on a wafer. In an implementation, a backside metal layer 124 may be formed on a surface of layer 122.

[0034] In embodiments, bonding layer 118 may include oxygen, and may include an oxide such as silicon oxide. In these conventional implementations, a lack of adhesion promotion within bonding layer 118 may tend to cause delamination at the top of bonding layer 118, which may be a dielectric, and one or more dies 108, especially when bonding layer 118 has a greater thickness.

[0035] Additionally, processing techniques such as planarization steps after the fill material 116 is applied can result in a dishing pattern 116a on the surface of the fill material 116. As shown in diagram 100A, using an oxide-rich bonding layer 118 has a tendency to dish the fill material 116 during processing. As a result, this can result in voids 117 within the fill material 116. These voids 117 may be referred to as gaps. The voids 117 may form due to the non-conformal nature of the oxide-based bonding layer 118 when applied to the fill material 116. The voids 117 may exist after layer 122 is fused to the bonding layer 118. Also, in conventional implementations, water or water vapor (not shown) that may be present within the fill material 116 may migrate into the voids 117, causing them to expand or form additional voids (not shown).

[0036] As a result, delamination between the filler material 116 and the bonding layer 118, as well as between one or more dies 108 and the bonding layer 118, may begin to occur. Additionally, the bonding layer 118 above one or more dies 108 may experience an increased lack of adhesion-promoting effect due to differences in coefficient of thermal expansion (CTE), especially as the thickness of the bonding layer 118 increases. This lack of adhesion-promoting effect may also promote delamination between one or more dies 108 and the bonding layer 118.

[0037] Also, because certain dielectric deposition techniques involving lower temperatures may be required to be used for oxide-based materials in the bonding layer 118, the risk of delamination and void 117 formation may increase due to stress, CTE differences, and defects on the bonding interface, which may be due to material differences between the silicon in one or more dies 108 and the fill material 116.

[0038] In particular, filler material 116 may absorb moisture, and thermal cycling during operation of conventional package 100 may cause voids 117 to grow due to moisture expansion. Over time, layer 122 may begin to delaminate. While bond layer 118, which may contain an oxide, and layer 122, which may contain an oxide, may provide a solid fusion bonding, bond layer 118 may not be effective as a moisture barrier.

[0039] In 3D heterogeneous packaging, especially for large form factor products, layer 122 can take the form of structural silicon, which may be in the form of a wafer. The structural silicon can provide mechanical advantages for package support once the package components are thinned and can facilitate co-planarity between various heterogeneous components within the package. In addition to co-planarity, the structural silicon can also provide good thermal advantages in terms of heat dissipation to an attached heat spreader as an added benefit of co-planarity.

[0040] The use of structural silicon fused to the package may be applicable to several different architectures. For example, in architectures with an exposed chip gap filler, such as an epoxy mold, and silicon on the backside of the die 108, selecting an optimal bonding layer 118, which may be referred to as a dielectric deposition layer, for fusion bonding to the structural silicon layer becomes very important. There may be a limited number of dielectric bonding films / layers that have a good combination of material properties, such as good thermal conductivity, and process conditions, such as deposition temperature. Furthermore, deposition of the bonding layer 118 may cause delamination of the bonding layer 118 due to film stress and differences in the coefficient of thermal expansion (CTE) of the bonding layer 118, the silicon from one or more dies 108, and the fill material 116.

[0041] 2A-2B show various diagrams and images illustrating a hermetic layer over multiple dies surrounded by a filler material, along with a bonding layer on the hermetic layer fused to a silicon wafer, according to various embodiments. Figure 2A shows a cross-sectional side view of a package 200 that may be similar to package 100 of Figure 1. Package 200 includes a base die 202, which may be a substrate in an embodiment, with one or more conductive vias 204, which may be referred to as through-silicon vias (TSVs), extending through the base die 202 and electrically coupling to conductive bumps 206 on the surface of the base die 202.

[0042] In embodiments, a redistribution layer (RDL) 210 may be on the base die 202 and may include bumps 212 that electrically couple, also referred to as conductively coupling, with one or more dies 208. In embodiments, the bumps 212 may include copper pillars or solder. In embodiments, one or more dies 208 may be adjacent to one another. In embodiments, the bumps 212 may be electrically coupled to conductive vias 204 of the base die 202. In embodiments, the dies 208 may be directly or hybrid bonded to the RDL 210 and may be electrically coupled to the RDL 210 without the use of bumps 212.

[0043] In an embodiment, underfill material 214 may be disposed under one or more dies 208. Base die 202, conductive vias 204, conductive bumps 206, die 208, RDL 210, bumps 212, and underfill material 214 may be similar to base die 102, conductive vias 104, conductive bumps 106, die 108, redistribution layer 110, bumps 112, and underfill material 114 of FIG. 1. In an embodiment, underfill material 214 may fill under die 208 and between bumps 212 on RDL 210.

[0044] In embodiments, fill material 216, which may be referred to as a molding material and may be similar to fill material 116 of FIG. 1 , may be disposed around die 208. In embodiments, protective layer 220, which may be referred to as a nitride layer, hermetic layer, dielectric layer, or layer, may be disposed on fill material 116 and / or on die 208. In embodiments, protective layer 220 may include a nitride or nitride material. In some embodiments, layer 220 includes silicon nitride, such that layer 220 primarily includes silicon and nitrogen. When a structure, such as layer 220, is described herein as comprising approximately one or more elements, this means that the atomic composition of that structure, in terms of either atomic percentage or atomic weight, primarily includes the disclosed elements, although other elements may be present in lower percentages or by weight. In embodiments, bonding layer 218, which may be similar to bonding layer 118 of FIG. 1 , may be disposed on protective layer 220. In some embodiments, layer 118 primarily includes silicon and oxygen. In embodiments, layer 222, which may be similar to layer 122 of FIG. 1, may be fused onto bonding layer 218. In embodiments, backside metal layer 224, which may be similar to backside metal layer 124 of FIG. 1, may be formed on layer 222. In embodiments, layer 222 may be a silicon wafer, which may be used as a structural support. In some embodiments, layer 222 contains primarily silicon and less than 5% nitrogen and / or oxygen. In other words, in terms of elemental composition, the majority of the atoms in layer 222 are silicon, and less than 5% of the atoms in layer 222 are either nitrogen or oxygen, or a combination of nitrogen and oxygen atoms.

[0045] In embodiments, the nitride material in protective layer 220 may provide a hermetic barrier and may also increase the conformal properties and adhesion of protective layer 220 when applied to fill material 216 and one or more dies 208, as compared to bond layer 218. In embodiments, protective layer 220 may conform to a greater extent than bond layer 218 to uneven surfaces in fill material 216, such as dishing pattern 216a, which may be similar to dishing pattern 116a in FIG. 1. Additionally, protective layer 220 may act as a better moisture barrier between fill material 216 and layer 222, as compared to simply bond layer 218.

[0046] Furthermore, by using a nitride-based protective layer 220, the planarity of the top of the protective layer 220 may be increased due to its conformal properties, thus resulting in better adhesion with the bonding layer 218. Also, in embodiments, the composition and deposition technique of the bonding layer 218 may be tailored to achieve better fusion while minimizing cracking or delamination of the die structures below the protective layer 220, such as the one or more dies 208 and the fill material 216.

[0047] As a result, using a protective layer 220 containing a nitride material or nitrogen can enhance the overall integrity of the package 200 and reduce the risk of delamination of layers within the package. In embodiments in which the layer 220 includes silicon nitride, the layer 220 can include primarily silicon and nitrogen. These characteristics can be a result of the nitride, e.g., silicon nitride, in the protective layer 220. This contrasts with the lack of nitride in the bonding layer 218, which can contain oxygen in the form of an oxide. The presence of oxygen / oxide in the bonding layer 218, in addition to any hydrogen that may be present in the bonding layer 218, allows water and / or water vapor to penetrate into the bonding layer 218. As a result, in the absence of the protective layer 220, thermal cycling activities in which water cycles between a water vapor and a liquid state would tend to cause delamination of the bonding layer 218.

[0048] In embodiments, an initial protective layer 220, which may also be referred to as an adhesion-promoting dielectric, may be deposited at a temperature lower than the epoxy fill material deposition temperature, followed by the deposition of the tie layer 218. In embodiments, the protective layer 220 may be a thin layer, for example, less than 1.0 μm. In embodiments, both layers may be deposited using processes such as spin coating, PVD, CVD, or ALD. CSAM images (below) demonstrate good adhesion to the structural Si wafer of this process architecture. In embodiments, the protective layer 220 may contain some oxygen and / or some hydrogen. In embodiments, the amount of oxygen and / or hydrogen in the protective layer 220 may be 3% or less. In embodiments, the amount of oxygen and / or hydrogen comprises up to 3% of the protective layer 220 by cross-sectional area.

[0049] In embodiments, layer 222 may be a glass layer. In these embodiments, the glass layer may be substantially all glass. The glass layer may be a solid mass comprising glass material having an amorphous crystalline structure, and the solid glass core may also include various structures, such as vias, cavities, channels, or other features, filled with one or more other materials (e.g., metals, metal alloys, dielectric materials, etc.). Thus, glass layer 222 may be distinguished from, for example, the "prepreg" or "RF4" core of a printed circuit board (PCB) substrate, which typically comprises glass fibers embedded in a resinous organic material such as epoxy.

[0050] The glass layer may have any suitable dimensions. In certain embodiments, the glass layer may have a thickness of about 50 μm or greater. For example, the thickness of the glass layer may be about 50 μm to about 1.4 mm. However, smaller or larger thicknesses may also be used. The glass layer may have edge dimensions (e.g., length, width, etc.) of about 10 mm or greater. For example, the edge dimensions may be about 10 mm to about 250 mm. However, larger or smaller edge dimensions may also be used. More generally, the area dimensions (from a top plan view) of the glass layer may be about 10 mm x 10 mm to about 250 mm x 250 mm. In one embodiment, the glass layer 222 may have a first side, the first side being perpendicular or orthogonal to the second side. In other embodiments, the glass layer 222 may comprise a rectangular prismatic volume with sections (e.g., vias) removed and filled with another material (e.g., metal, etc.).

[0051] The glass layer may include a single monolithic layer of glass. In other embodiments, the glass layer may include two or more separate glass layers stacked together. The individual glass layers may be provided in direct contact with each other, or the individual glass layers may be mechanically bonded to each other, such as by an adhesive. The individual glass layers of the glass layers may each have a thickness of less than about 50 μm. For example, the individual glass layers of the glass layers may have a thickness of about 25 μm to about 50 μm. However, the individual glass layers may have a greater or lesser thickness in some embodiments.

[0052] The glass layer can be any suitable glass formulation having the necessary mechanical robustness and compatibility with semiconductor packaging manufacturing and assembly processes. For example, the glass layer can include aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, fused silica, etc. In some embodiments, the glass layer can include one or more additives, such as, but not limited to, Al2O3, BO3, MgO, CaO, SrO, BaO, SnO2, Na2O, KO, SrO, PO3, ZrO2, Li2O, Ti, and Zn. More generally, the glass layer can include silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In one embodiment, the glass layer can include at least 23 percent (by weight) silicon and at least 26 percent (by weight) oxygen. In some embodiments, the glass layer may further include at least 5 percent (by weight) aluminum.

[0053] FIG. 2B shows a cross-sectional side view of a scanning electron microscope (SEM) image of a package that may be similar to package 200 of FIG. 2A. The illustrated filler material 216 includes silicon dioxide particles 217a surrounded by epoxy material 217b. Overlying the filler material 216 is a protective layer 220. In embodiments, the protective layer 220 may include a nitride, such as silicon nitride (Si3N4). As shown, the top of the filler material 216 is highly irregular, e.g., non-planar, but the protective layer 220, due to its nitride content, may be highly conformal to the top of the filler material 216, resulting in no or minimal void formation.

[0054] Bond layer 218 can be conformal to the top of protective layer 220. Note that in conventional implementations, a bond layer without a nitride component is unlikely to provide a good hermetic bond layer.

[0055] After placement of bonding layer 218, a structural silicon wafer 223, which may be similar to layer 222 in Figure 2A, may be fused to the top of bonding layer 218. In embodiments, bonding layer 218, which may be referred to as a bonding dielectric, comprises an oxide, and structural silicon wafer 223 may also comprise an oxide. During a fusion process, which may also be referred to as direct bonding, structural silicon wafer 223 and bonding layer 218 are fused to one another.

[0056] 3A-3B are perspective views of a silicon wafer being fused to another wafer containing multiple packages, according to various embodiments, and a top-down cross section of the wafers after fusion bonding.

[0057] FIG. 3A shows a wafer 322, which may be similar to layer 222 of FIG. 2A or structural silicon wafer 223 of FIG. 2B. Wafer 322 may be a circular wafer having a diameter of 800 mm. In other embodiments, wafer 322 may be other shapes or have other dimensions. In embodiments, multiple packages 300, each of which may be similar to package 200 of FIG. 2A, may be on the surface of wafer 323 or otherwise integrated with wafer 323 to form layer 340. In embodiments, multiple packages 300 may include one or more components found in package 200 of FIG. 2A.

[0058] In embodiments, a protective layer (not shown, but which may be similar to protective layer 220 in FIGS. 2A-2B) may be disposed on layer 340, and a bonding layer (not shown, but which may be similar to bonding layer 218 in FIGS. 2A-2B) may be disposed on the protective layer. Wafer 322 may then be fused to the protective layer (not shown) on layer 340.

[0059] FIG. 3B shows a CSAM image illustrating the successful fusion of this process architecture to a structural Si wafer. As shown, wafer 322 is fused onto layer 340. Area 331 indicates a void area that appears under the edge of wafer 322, and area 332 indicates another void area under wafer 322. As shown, the void area shown in FIG. 3B is minimized by using a protective layer, such as protective layer 220 of FIG. 2A, which is highly conformal to the layer of fill material 216 of FIGS. 2A-2B and also highly adhesive to bonding layer 218 of FIGS. 2A-2B.

[0060] 4 illustrates a package having a hermetic layer over multiple dies surrounded by a filler material, the hermetic layer fusion bonded to a silicon wafer, according to various embodiments. Package 400, which may be similar to package 200 of FIG. 2A, includes layer 422, which may be over one or more top dies 408 and may be above layer 222, one or more top dies 208, and filler material 416, which may be similar to layer 222, one or more top dies 208, and filler material 216 of FIG. 2A.

[0061] In embodiments, a protective layer 420, which may be similar to protective layer 220 of Figure 2A, may be disposed over one or more top dies 408 and filler material 416. In embodiments, the thickness of protective layer 420 may be greater than the thickness of protective layer 220 of Figure 2A. In embodiments, layer 422 may be directly on protective layer 420 and may be fused directly to protective layer 420.

[0062] In embodiments, protective layer 420 may include a nitride, and layer 422 may be a silicon layer or a structural silicon layer in embodiments. In embodiments, layer 422 may include an oxide, such as silicon dioxide, and may not include a nitride. In addition to providing a layer for fusion bonding, protective layer 420 may be conformally applied on top of one or more top dies 408 and fill material 416, similar to protective layer 220 in FIG. 2A. Furthermore, protective layer 420 may act as a hermetic layer to prevent or reduce moisture migration between layer 422 and one or more top dies 408 and fill material 416.

[0063] 5 illustrates a top cross-sectional view of a package having a layout of multiple dies separated by filler material and having an airtight layer over the dies within the filler material, according to various embodiments. Diagram 500, which may be similar to a portion of package 300 in FIG. 3A, shows layer 540, which may be similar to a portion of layer 340 in FIG. 3A, including one or more dies 508 surrounded by filler material 516. In an embodiment, one or more dies 508 and filler material 516 may be similar to one or more dies 208 and filler material 216 in FIG. 2A.

[0064] In an embodiment, the dimensions and spacing of one or more dies 508 may be varied. As a result, the height of the fill material 516 may vary between the dies 508. In particular, the fill material 516 between the dies 508 may include different dishing patterns, such as dishing pattern 216a in FIG. 2A. In an embodiment, a protective layer 520, which may be similar to protective layer 220 in FIG. 2A and may include nitride, may be conformally applied over the fill material 516 and one or more dies 508.

[0065] After application of protective layer 520, protective layer 520 may be planarized, after which a layer (not shown, but which may be similar to layer 422 in FIG. 4) or a silicon wafer (not shown, but which may be similar to silicon wafer 322 in FIG. 3A) may be fused onto protective layer 520. In other embodiments, a bonding layer (not shown, but which may be similar to bonding layer 218 in FIG. 2A) may be placed onto protective layer 520 prior to fusion.

[0066] 6A-6G illustrate cross-sectional side views of various stages in a manufacturing process for producing a package including a hermetic layer over multiple dies surrounded by a filler material and having a bonding layer over the hermetic layer, according to various embodiments. Figure 6A illustrates a cross-sectional side view of a stage in the manufacturing process in which a base die 601, which may be similar to base die 202 of Figure 2A, may be provided. Base die 601 may include multiple conductive vias 604, which may be similar to conductive vias 204 of Figure 2A.

[0067] One or more dies 608 may be on the base die 601 and may be electrically coupled to one or more conductive vias 604 using bumps 612, which may be similar to bumps 212 of Figure 2A. In an embodiment, an RDL 610, which may be similar to RDL 210 of Figure 2A, may be between the one or more dies 608 and the base die 601. In other embodiments, the base die 601 may be a substrate.

[0068] 6B shows a cross-sectional side view of a stage in the manufacturing process where a filler material 616, which may be similar to filler material 216 of FIG. 2A, is disposed around one or more dies 608. In an embodiment, filler material 216 may include silicon-containing particles that may be bonded together by epoxy.

[0069] 6C shows a cross-sectional side view of a stage in the manufacturing process where a protective layer 620, which may be similar to protective layer 220 of FIG. 2A, may be disposed over fill material 616 and one or more dies 608. In an embodiment, fill material 616 and / or one or more dies 608 may undergo a planarization process. For example, a CMP process may be used before applying protective layer 620.

[0070] In embodiments, protective layer 620 may be deposited or applied using a PVD, CVD, ALD, or spin-coat process. In embodiments, protective layer 620 may be deposited at lower temperatures, for example, between 150°C and 400°C. In embodiments, the thickness of protective layer 620 may range from 100 nm to 1 μm. In embodiments, protective layer 620 may form a hermetic seal to prevent or reduce the transmission of water or water vapor through protective layer 620. In embodiments, this hermetic seal may be facilitated by using nitride for protective layer 620.

[0071] 6D shows a cross-sectional side view of a stage in a manufacturing process where a bonding layer 618, which may be similar to bonding layer 218 of FIG. 2A, may be disposed on protective layer 620. In embodiments, bonding layer 618 may be referred to as a bonding dielectric and may include a nitride, such as silicon nitride, or an oxide, such as silicon oxide. In embodiments, bonding layer 618 may be deposited using CVD, PVD, or ALD techniques. In embodiments, the top surface of bonding layer 618 may be planarized to meet a specific thickness or to meet a specific roughness in preparation for fusion bonding, as described below.

[0072] 6E shows a cross-sectional side view of a stage in the manufacturing process where layer 622, which may be similar to layer 222 of FIG. 2A, may be fused with bonding layer 618. In embodiments, layer 622 may be a dielectric material or may be a wafer that may include silicon. In embodiments, layer 622 may be a structural silicon wafer. In embodiments, layer 622 may act as a permanent carrier.

[0073] 6F shows a cross-sectional side view of a stage in the manufacturing process in which base die 601 of FIG. 6A is thinned to create base die 602. In an embodiment, the thinning may be achieved using a grinding process and may be referred to as through-silicon-via (TSV) exposure. In an embodiment, one or more of conductive vias 604 may be exposed at the bottom of base die 602. In an embodiment, after thinning, bumps 606, which may be similar to bumps 206 of FIG. 2A, may be applied to physically and / or electrically couple to base die 602. In an embodiment, package 600 of FIG. 6F may be similar to one of packages 300 of FIG. 3A.

[0074] 6G shows a cross-sectional side view of a stage in the manufacturing process where a ring frame 650 may be attached to the top of layer 622. As shown, there may be multiple packages 600 hybrid-bonded to layer 622, as shown with respect to FIG. 6F. In an embodiment, ring frame 650 may be used to support singulation of packages 600. In an embodiment, ring frame 650 may be referred to as a dicing tape.

[0075] 7A-7B illustrate cross-sectional side views of various stages in a manufacturing process for producing a package including a hermetic layer over multiple dies surrounded by a filler material to which a portion of a silicon wafer is fusion-bonded, according to various embodiments. Figure 7A illustrates a cross-sectional side view of a stage in the manufacturing process that may be similar to Figure 6C, in which a protective layer 720, which may be similar to protective layer 620 of Figure 6C or protective layer 220 of Figure 2A, may be disposed over filler material 716 surrounding one or more dies 708, which may be similar to filler material 216 and one or more dies 208 of Figure 2A.

[0076] In embodiments, protective layer 720 may be applied using a PVD, CVD, ALD, or spin-coat process. In embodiments, protective layer 720 may be used as a fusing layer, such that protective layer 720 may be thicker than protective layer 620 of FIG. 6C. In embodiments, protective layer 720 may include a nitride, such as silicon nitride.

[0077] 7B shows a cross-sectional side view of a stage of the manufacturing process in which layer 722 is fused to protective layer 720. In embodiments, layer 722 may be a layer of dielectric, may be a silicon layer, or may be a portion of a silicon wafer that is fused to protective layer 720. In embodiments, layer 722 may be a silicon structure wafer. Manufacturing stages subsequent to the stage shown in FIG. 7B may be performed similarly to those shown with respect to FIGS. 6E-6G.

[0078] 8 illustrates an example process for manufacturing a package including a hermetic layer over multiple dies surrounded by a filler material and including a bonding layer over the hermetic layer, according to various embodiments. In embodiments, process 800 may be performed using tools, techniques, devices, systems, or processes described herein, particularly those described with respect to FIGS. 1-7B.

[0079] At block 802, the process may include providing a substrate. In embodiments, the substrate may be similar to base die 202 of Figure 2A or base die 602 of Figure 6F. In other embodiments, the substrate may be similar to some other structure that may be part of a semiconductor package.

[0080] The process may further include providing one or more dies on the substrate at block 804. In an embodiment, the one or more dies may be similar to one or more dies 208 of Figure 2A, one or more dies 408 of Figure 4, one or more dies 508 of Figure 5, one or more dies 608 of Figures 6A-6G, or one or more dies 708 of Figures 7A-7B.

[0081] The process may further include disposing a molding material around at least a portion of the one or more dies at block 806. In embodiments, the molding material may be similar to filler material 216 of Figures 2A-2B, filler material 416 of Figure 4, filler material 516 of Figure 5, filler material 616 of Figures 6A-6G, or filler material 716 of Figures 7A-7B.

[0082] The process may further include disposing a layer containing primarily silicon and nitrogen over the mold material and the one or more dies at block 808. In embodiments, the layer may be similar to protective layer 220 of Figures 2A-2B, layer 420 of Figure 4, layer 520 of Figure 5, layer 620 of Figures 6C-6G, or layer 720 of Figures 7A-7B.

[0083] 9 is a schematic diagram of a computer system 900 according to an embodiment of the present invention. The illustrated computer system 900 (also referred to as electronic system 900) can embody a hermetic layer over a filler material and die according to any of the disclosed embodiments and their equivalents described in this disclosure. The computer system 900 can be a mobile device such as a netbook computer. The computer system 900 can be a mobile device such as a wireless smartphone. The computer system 900 can be a desktop computer. The computer system 900 can be a handheld reader. The computer system 900 can be a server system. The computer system 900 can be a supercomputer or high-performance computing system.

[0084] In one embodiment, electronic system 900 is a computer system that includes a system bus 920 that electrically couples the various components of electronic system 900. System bus 920 may be a single bus or any combination of buses, according to various embodiments. Electronic system 900 includes a voltage source 930 that provides power to integrated circuit 910. In some embodiments, voltage source 930 provides current to integrated circuit 910 via system bus 920.

[0085] The integrated circuit 910 is electrically coupled to the system bus 920 and includes any circuit or combination of circuits according to one embodiment. In one embodiment, the integrated circuit 910 includes a processor 912, which can be of any type. As used herein, the processor 912 can refer to any type of circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In one embodiment, the processor 912 includes or is coupled to a hermetic layer above the die and fill material as disclosed herein. In one embodiment, an SRAM embodiment is found within the memory cache of the processor. Other types of circuits that may be included in the integrated circuit 910 are custom circuits or application-specific integrated circuits (ASICs), such as communications circuitry 914 for use in wireless devices such as cell phones, smartphones, pagers, portable computers, two-way radios, and similar electronic systems, or communications circuitry for a server. In one embodiment, the integrated circuit 910 includes on-die memory 916, such as static random access memory (SRAM). In one embodiment, the integrated circuit 910 includes embedded on-die memory 916, such as embedded dynamic random access memory (eDRAM).

[0086] In one embodiment, integrated circuit 910 is complemented with a subsequent integrated circuit 911. A useful embodiment includes dual processors 913, dual communication circuits 915, and dual on-die memory 917, such as SRAM. In one embodiment, dual integrated circuit 910 includes embedded on-die memory 917, such as eDRAM.

[0087] In one embodiment, electronic system 900 also includes external memory 940, which may include one or more memory elements suitable for a particular application, such as main memory 942 in the form of RAM, one or more hard drives 944, and / or one or more drives for handling removable media 946, such as diskettes, compact discs (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. External memory 940, according to one embodiment, may be embedded memory 948, such as the first die in a die stack.

[0088] In one embodiment, electronic system 900 also includes a display device 950, an audio output 960. In one embodiment, electronic system 900 includes an input device such as a controller 970, which may be a keyboard, a mouse, a trackball, a game controller, a microphone, a voice recognition device, or any other input device for inputting information into electronic system 900. In one embodiment, input device 970 is a camera. In one embodiment, input device 970 is a digital sound recorder. In one embodiment, input device 970 is both a camera and a digital sound recorder.

[0089] As shown herein, the integrated circuit 910 can be implemented in several different embodiments, including a package substrate having a hermetic layer over the die and filler material according to any of several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of manufacturing an integrated circuit, and one or more methods of manufacturing an electronic assembly including a package substrate having a hermetic layer over the die and filler material according to any of several disclosed embodiments as described herein in various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be modified to suit specific I / O coupling requirements, including array contact counts and array contact configurations, for a microelectronic die embedded in a processor mounting substrate according to any of several disclosed package substrates having a hermetic layer over the die and filler material embodiments and their equivalents. A base substrate may be included, as represented by the dashed line in FIG. 9 . Passive devices may also be included, as also shown in FIG. 9 .

[0090] While specific embodiments have been shown and described herein for purposes of illustration, a wide variety of alternative and / or equivalent embodiments or implementations calculated to achieve the same purpose may be substituted for the shown and described embodiments without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments described herein. Accordingly, it is manifestly intended that the embodiments described herein be limited only by the scope of the claims.

[0091] Where the present disclosure recites "a" or "a first" element or its equivalent, such disclosure includes one or more such elements, and does not require or exclude two or more such elements. Furthermore, identified element order indicators (e.g., first, second, or third) are used to distinguish elements and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular location or order of such elements unless otherwise expressly stated.

[0092] Various embodiments may include any suitable combination of the above embodiments, including alternative (or) embodiments of the embodiments described in conjunction (and) above (e.g., "and" can be "and / or"). Further, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) storing instructions that, when executed, cause the actions of any of the above-described embodiments. Further, some embodiments may include devices or systems having any suitable means for performing the various operations of the above-described embodiments.

[0093] The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. While specific embodiments have been described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of the embodiments.

[0094] These modifications can be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0095] Example

[0096] The following paragraphs describe examples of various embodiments.

[0097] Example 1 is an apparatus, A substrate; one or more dies on a surface of the substrate; a nitrogen-containing layer on a surface of the one or more dies.

[0098] Example 2 includes the device of Example 1, further comprising: a filler material at least partially surrounding the one or more dies; The nitrogen-containing layer overlies the fill material.

[0099] Example 3 includes the device of example 2, At least a portion of the filler material immediately adjacent the nitrogen-containing layer is not in the plane of the surface of the one or more dies.

[0100] Example 4 includes the device of example 2 or 3, The filler material includes a selected one or more of epoxy, silicone, or oxygen.

[0101] Example 5 includes the device of example 2, 3, or 4; The composition of the nitrogen-containing layer contains up to 3% oxygen in a cross-sectional area.

[0102] Example 6 includes the device of example 2, 3, 4, or 5; the nitrogen-containing layer is a first layer; A second layer is further provided on the first layer.

[0103] Example 7 includes the device of example 6, the second layer contains one or more selected from oxygen and nitrogen; The first layer is an airtight layer.

[0104] Example 8 includes the device of example 2, 3, 4, 5, 6, or 7; The nitrogen-containing layer further contains a nitride.

[0105] Example 9 includes the device of example 2, 3, 4, 5, 6, 7, or 8; The nitrogen-containing layer has a thickness in the range of 100 nm to 1 μm.

[0106] Example 10 includes the device of example 2, 3, 4, 5, 6, 7, 8, or 9; The nitrogen-containing layer is deposited using one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating.

[0107] Example 11 includes the device of example 2, 3, 4, 5, 6, 7, 8, 9, or 10; The substrate includes a base die.

[0108] Example 12 is a system comprising: substrate and; one or more dies on a surface of the substrate, the one or more dies being electrically and physically coupled to the substrate; a filler material at least partially surrounding the one or more dies; a first layer containing nitride over the one or more dies and the filler material, the first layer being a hermetic layer; a second layer over the first layer;

[0109] Example 13 includes the system of example 12, The first layer is directly adhered to the second layer.

[0110] Example 14 includes the system of example 12 or 13, further comprising: a third layer between the first layer and the second layer; The second layer contains oxygen.

[0111] Example 15 includes the system of example 14, The third layer is directly adhered to the second layer.

[0112] Example 16 includes the system of examples 12, 13, 14, or 15. the substrate includes a die; The second layer includes a selected one of an interposer, a silicon wafer, or glass.

[0113] Example 17 includes the system of examples 12, 13, 14, 15, or 16; The composition of the first layer containing nitrogen contains up to 3% oxygen in a cross-sectional area.

[0114] Example 18 is a method comprising: providing a substrate; providing one or more dies on the substrate; disposing a filler material around at least a portion of the one or more dies; and disposing a nitride-containing layer over the one filler material and the one or more dies.

[0115] Example 19 includes the method of example 18, the layer comprising nitride is a first layer; The method further comprises: The method further includes the step of placing a second layer on the first layer, the first layer being an airtight layer.

[0116] Example 20 includes the method of example 19, The method further includes a step of directly bonding a third layer onto the second layer, the second layer including oxygen, and the third layer including a selected one of an interposer, a silicon wafer, or glass.

[0117] Example 21 is an apparatus comprising: a first die having through silicon vias (TSVs); a second die over the first die, the second die conductively coupled to the TSVs; a third die above the first die and adjacent to the second die, the third die conductively coupled to the TSVs; a molding material above the first die and between the second die and the third die; a first layer over the first die, the second die, and the molding material, the first layer containing primarily silicon and nitrogen; a second layer over the first layer, the second layer containing primarily silicon and oxygen; a third layer on the second layer, the third layer containing primarily silicon and less than 5% nitrogen and / or oxygen;

[0118] Example 22 includes the apparatus of example 21; At least a portion of the top of the molding material immediately adjacent the first layer is not in the plane of the top surface of the second die or is not in the plane of the top surface of the third die.

[0119] Example 23 includes the device of example 22; The at least a portion of the molding material immediately adjacent to the first layer is below the plane of the top surface of the second die or below the plane of the top surface of the third die.

[0120] Example 24 includes the device of example 22 or 23; The molding material includes a selected one or more of epoxy, silicon, or oxygen.

[0121] Example 25 includes the device of example 21, 22, 23, or 24; A first percentage of nitrogen in a first cross-sectional area of ​​the first layer exceeds a second percentage of nitrogen in a second cross-sectional area of ​​the second layer.

[0122] Example 26 includes the device of example 21, 22, 23, 24, or 25; The first layer is an airtight layer.

[0123] Example 27 includes the device of example 21, 22, 23, 24, 25, or 26; The first layer contains a glass material having an amorphous crystalline structure.

[0124] Example 28 includes the device of example 21, 22, 23, 24, 25, 26, or 27; The first layer further contains a nitride.

[0125] Example 29 includes the device of example 21, 22, 23, 24, 25, 26, 27, or 28; The first layer has a thickness in the range of 100 nm to 1 μm.

[0126] Example 30 includes the device of example 21, 22, 23, 24, 25, 26, 27, 28, or 29; The first layer is deposited using a selected one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular layer deposition (ALD), or spin coating.

[0127] Example 31 includes the device of example 21, 22, 23, 24, 25, 26, 27, 28, 29, or 30; The second die or the third die is directly attached to the first die.

[0128] Example 32 is a system comprising: substrate and; one or more dies on a surface of the substrate, the one or more dies being electrically and physically coupled to the substrate; a molding material over the substrate at least partially surrounding the one or more dies; a first layer containing nitride over the one or more dies and the mold material, the first layer being a hermetic layer; a second layer over the first layer, the second layer containing primarily silicon and oxygen.

[0129] Example 33 includes the system of example 32, The first layer is directly adhered to the second layer.

[0130] Example 34 includes the system of example 32 or 33. The method further comprises a third layer over the second layer, the third layer containing less than 5% nitrogen and / or oxygen.

[0131] Example 35 includes the system of example 34, The third layer is directly adhered to the second layer.

[0132] Example 36 includes the system of example 34 or 35, the substrate includes a die; The third layer includes a selected one of an interposer, a silicon wafer, or glass.

[0133] Example 37 includes the system of example 32, 33, 34, 35, or 36. At least a portion of the top of the molding material is below the plane of the top of one of the one or more dies.

[0134] Example 38 is a method comprising: providing a substrate; providing one or more dies on the substrate; disposing a molding material around at least a portion of the one or more dies; disposing a layer containing primarily silicon and nitrogen over the molding material and the one or more dies.

[0135] Example 39 includes the method of Example 38; the layer is a first layer, The method further comprises: The method includes disposing a second layer over the first layer, the second layer containing primarily silicon and oxygen.

[0136] Example 40 includes the method of example 39, The method includes disposing a third layer over the second layer, the third layer containing primarily silicon and less than 5% nitrogen and / or oxygen.

Claims

1. a first die having a through silicon via (TSV); a second die above the first die, the second die conductively coupled to the TSV; a third die above the first die and adjacent to the second die, the third die conductively coupled to the TSV; a molding material above the first die and between the second die and the third die; a first layer over the first die, the second die, and the molding material, the first layer containing primarily silicon and nitrogen; a second layer over the first layer, the second layer containing primarily silicon and oxygen; a third layer on the second layer, the third layer containing predominantly silicon and less than 5% nitrogen and / or oxygen; Device.

2. at least a portion of the top of the molding material immediately adjacent to the first layer is not in the plane of the top surface of the second die or is not in the plane of the top surface of the third die; 10. The apparatus of claim 1.

3. the at least a portion of the molding material immediately adjacent to the first layer is below the plane of the top surface of the second die or below the plane of the top surface of the third die; 3. The apparatus of claim 2.

4. the molding material includes one or more selected from epoxy, silicon, and oxygen; 4. The device according to claim 2 or 3.

5. a first percentage of nitrogen in a first cross-sectional area of ​​the first layer exceeds a second percentage of nitrogen in a second cross-sectional area of ​​the second layer; 4. The device according to claim 2 or 3.

6. The first layer is an airtight layer.

4. The device according to claim 2 or 3.

7. the first layer contains a glass material having an amorphous crystalline structure; 7. The apparatus of claim 6.

8. the first layer further comprises a nitride; 4. The device according to claim 2 or 3.

9. the first layer has a thickness in the range of 100 nm to 1 μm; 4. The device according to claim 2 or 3.

10. the first layer is deposited using selected one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating; 4. The device according to claim 2 or 3.

11. the second die or the third die is directly attached to the first die; 4. The device according to claim 2 or 3.

12. a substrate; one or more dies on a surface of the substrate, the one or more dies being electrically and physically coupled to the substrate; a molding material over the substrate at least partially surrounding the one or more dies; a first layer containing nitride over the one or more dies and the mold material, the first layer being a hermetic layer; a second layer over the first layer, the second layer containing primarily silicon and oxygen; system.

13. the first layer is directly adhered to the second layer; The system of claim 12.

14. further comprising a third layer on the second layer, the third layer containing less than 5% nitrogen and / or oxygen; 14. A system according to claim 12 or 13.

15. the third layer is directly adhered to the second layer; 15. The system of claim 14.

16. the substrate includes a die; the third layer comprises a selected one of an interposer, a silicon wafer, or glass; 15. The system of claim 14.

17. at least a portion of the top of the molding material is below a plane of the top of one of the one or more dies; 14. A system according to claim 12 or 13.

18. providing a substrate; providing one or more dies on the substrate; disposing a molding material around at least a portion of the one or more dies; and disposing a layer containing primarily silicon and nitrogen over the molding material and the one or more dies. method.

19. the layer is a first layer, The method further comprises: disposing a second layer over the first layer; the second layer contains primarily silicon and oxygen, 20. The method of claim 18.

20. and disposing a third layer on the second layer, the third layer containing primarily silicon and less than 5% nitrogen and / or oxygen.

20. The method of claim 19.

Images