Functional safety protection method for computing circuit and functional safety computing circuit

Abstract

To provide a functional safety protection method for a computing circuit and a functional safety computing circuit.SOLUTION: This computing circuit includes a computing array with a plurality of computing units. This method includes: generating test data; invoking the computing units to respectively perform computations based on the test data, to obtain first computation results respectively corresponding to the computing units; determining a matching degree between the first computation results respectively corresponding to the computing units; and determining a functional safety detection result of the computing array based on the matching degree. According to this disclosure, functional safety abnormalities that occur in the computing circuit can be detected, thereby facilitating protection for the computing circuit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to chip technology, and in particular to a functional safety protection method for a computing circuit and a functionally safe computing circuit. [Background technology]

[0002] Currently, the applications of chips are very wide. Chips can be equipped with computing circuits. During chip operation, functional abnormalities may occur in the computing circuits. In order to ensure the reliability of the computing circuits and ultimately the chip, it is necessary to perform functional safety (FUSA) detection for functional abnormalities occurring in the computing circuits. Summary of the Invention [Problem to be solved by the invention]

[0003] To solve the above technical problems, the present disclosure provides a functional safety protection method for a computing circuit and a functionally safe computing circuit. [Means for solving the problem]

[0004] According to one aspect of the embodiment of the present disclosure, a method for protecting functional safety of a computing circuit including a computing array having a plurality of computing units includes: generating test data; calling each of the computing units to perform a calculation based on the test data, and obtaining a first calculation result corresponding to each of the computing units; determining a matching degree between the first calculation results respectively corresponding to each of the calculation units; and determining a functional safety detection result of the computing array based on the matching degree.

[0005] A functionally safe computing circuit according to another aspect of the embodiment of the present disclosure includes: a test data generation module for generating test data; a computation array having a plurality of computation units, each of which performs a computation based on the test data to obtain a first computation result corresponding to each of the computation units; and a functional safety protection module for determining a matching degree between the first calculation results corresponding to each of the calculation units, and determining a functional safety detection result of the calculation array based on the matching degree.

[0006] According to yet another aspect of the present disclosure, a computing system includes: the functionally safe computing circuit comprising a multiplexing device; and a determination module for determining a current state of a computational array included in the computation circuit and causing a multiplexer included in the computation circuit to be in a mode that is compatible with the current state of the computational array.

[0007] A computer-readable storage medium according to yet another aspect of the present disclosure stores a computer program for executing the functional safety protection method for a computing circuit.

[0008] According to yet another aspect of the present disclosure, there is provided an electronic device including a processor and a memory for storing instructions executable by the processor, The processor reads and executes the executable instructions from the memory to implement the functional safety protection method for the computing circuit.

[0009] A computer program product according to yet another aspect of an embodiment of the present disclosure performs the method for functional security protection of the computing circuit when executable instructions in the computer program product are executed by a processor. [Effects of the Invention]

[0010] According to the above-described embodiments of the present disclosure, the functional safety protection method for a computational circuit, the functionally safe computational circuit, the computational system, the storage medium, the electronic device, and the computer program product can call each computational unit in a computational array to perform a calculation based on test data, thereby obtaining a first computation result corresponding to each computational unit. Because each computational unit performs calculations using the same test data, the first computation results corresponding to each computational unit should theoretically match. Based on the degree of match between the first computation results corresponding to each computational unit, it can be verified whether the first computation results corresponding to each computational unit actually match. Based on whether the theoretical situation matches the actual situation, it can be determined whether a functional safety anomaly has occurred in the computational array, thereby obtaining a corresponding functional safety detection result. For example, if the theoretical situation does not match the actual situation, it can be determined that a functional safety anomaly has occurred in the computational array. Therefore, the embodiments of the present disclosure can detect functional safety anomalies that occur in a computational circuit, which is advantageous for protecting the computational circuit. [Brief explanation of the drawings]

[0011] [Figure 1-1] 1 is a structural schematic diagram of a functionally safe computing circuit according to some example embodiments of the present disclosure. [Figure 1-2] FIG. 1 is a structural schematic diagram of a computational array according to some example embodiments of the present disclosure. [Figure 2] 1 is a schematic flowchart of a method for functional security protection of a computing circuit according to some example embodiments of the present disclosure. [Figure 3] 1 is a schematic flowchart of a method for obtaining a first calculation result in some exemplary embodiments of the present disclosure. [Figure 4] 1 is a schematic flowchart of a mode setting method for a multiplexing device in some exemplary embodiments of the present disclosure. [Figure 5] 10 is a schematic flowchart of a method for obtaining and outputting a second calculation result in some exemplary embodiments of the present disclosure. [Figure 6] 10 is a schematic flowchart of a mode setting method for a multiplexing device according to some other exemplary embodiments of the present disclosure. [Figure 7] 1 is a schematic flowchart of a method for converting data layout formats in some exemplary embodiments of the present disclosure. [Figure 8] 10 is a schematic flowchart of a method for converting a data layout format in some other exemplary embodiments of the present disclosure. [Figure 9] 1 is a structural schematic diagram of a functionally safe computing circuit according to some other exemplary embodiments of the present disclosure. [Figure 10] FIG. 1 is a structural schematic diagram of a functional safety protection module according to some exemplary embodiments of the present disclosure. [Figure 11] 1 is a structural schematic diagram of an electronic device according to some example embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] In order to explain the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the drawings. The described embodiments are not all of the embodiments of the present disclosure, but are merely a part of the embodiments of the present disclosure, and the present disclosure is not limited to the exemplary embodiments.

[0013] The relative arrangement of parts and steps, formulas, and numerical values ​​described in these examples do not limit the scope of the present disclosure unless specifically stated otherwise.

[0014] [Application Summary] The chip may include a computation circuit, for example, a computation circuit capable of implementing a convolution operation or a computation circuit capable of implementing a pooling operation.

[0015] During chip operation, functional anomalies may occur in the computing circuit due to factors such as the process and the environment. For example, the presence of electromagnetic interference in the environment may cause functional anomalies in the computing circuit. If functional anomalies occurring in the computing circuit cannot be detected in a timely manner, it will have a negative impact on the reliability of the computing circuit and ultimately the chip. Therefore, some countermeasures must be used to perform functional safety detection of functional anomalies occurring in the computing circuit.

[0016] [Example System] In an embodiment of the present disclosure, as shown in FIG. 1-1 , a computing circuit may include a test data generation module 10, a computing array 20, and a functional safety protection module 30. The test data generation module 10 may generate test data. As shown in FIG. 1-2 , the computing array 20 may include multiple computing units 201. Each computing unit 201 in the computing array 20 may perform calculations based on test data to obtain corresponding first calculation results. The functional safety protection module 30 may determine functional safety detection results for the computing array 20 based on the first calculation results corresponding to each computing unit 201. In this way, the cooperation of the test data generation module 10, the computing array 20, and the functional safety protection module 30 can detect functional safety anomalies occurring in the computing circuit, which is advantageous for realizing functional safety protection for the computing circuit.

[0017] Optionally, the computation circuit may further include a data acquisition module and a multiplexer. The multiplexer may connect the test data generation module 10 and the computation array 20 so that, in one operation mode of the multiplexer, test data generated by the test data generation module 10 can be sent to the computation array 20. The multiplexer may connect the data acquisition module and the computation array 20 so that, in another operation mode of the multiplexer, true data to be computed acquired by the data acquisition module can be sent to the computation array 20.

[0018] [Exemplary Method] An embodiment of the present disclosure provides a method for functional security protection of a computing circuit.

[0019] Optionally, the type of operation that the computation circuitry is intended to implement may be referred to as a target operation, including, but not limited to, a convolution operation, a pooling operation, a tensor operation, and the like.

[0020] Optionally, the computational circuit may include a computational array for executing the target operation. The computational array may be an essential component of the computational circuit, and detection of a functional safety anomaly occurring in the computational circuit may be understood as detection of a functional safety anomaly occurring in the computational array.

[0021] Optionally, the computation array may include multiple computation units. For example, the computation circuit may include N rows and M columns of computation units. The values ​​of N and M may be the same or different. Each computation unit in the computation array can perform a target operation.

[0022] As shown in FIG. 2 , the functional security protection method for a computing circuit may include steps 210 , 220 , 230 , and 240 .

[0023] In step 210, test data is generated.

[0024] For example, when the target operation is a convolution operation, the test data may include tensor data and weight data. The tensor data may be image data or feature maps. The weight data may be convolution kernels. For example, when the target operation is a max pooling operation or an average pooling operation, the test data may include tensor data and a pooling window size.

[0025] In step 220, each calculation unit is called to perform calculation based on the test data, and a first calculation result corresponding to each calculation unit is obtained.

[0026] For example, when the test data includes tensor data and weight data, for any calculation unit, the calculation unit can be called to perform a convolution operation on the tensor data in the test data using the weight data in the test data, thereby obtaining a corresponding convolution calculation result, which can be used as the first calculation result corresponding to the calculation unit.

[0027] Similarly, when the test data includes tensor data and a pooling window size, for any computing unit, a corresponding pooling calculation result can be obtained by a pooling operation, and this pooling calculation result can be used as the first calculation result corresponding to this computing unit.

[0028] In step 230, the matching degree between the first calculation results respectively corresponding to each calculation unit is determined.

[0029] Alternatively, if two first calculation results are the same, it can be determined that the matching degree between the two first calculation results is 1. If two first calculation results are different, it can be determined that the matching degree between the two first calculation results is 0.

[0030] In step 240, the functional safety detection result of the computing array is determined based on the matching degree.

[0031] Optionally, by performing step 230, a matching degree between any two first calculation results can be determined. Based on the determined matching degrees, a functional safety detection result of the computational array can be determined. For example, if at least one of the matching degrees is 0, a functional safety detection result indicating that a functional abnormality has occurred in the computational array can be obtained. Also, for example, if all of the matching degrees are 1, a functional safety detection result indicating that no functional abnormality has occurred in the computational array can be obtained.

[0032] Optionally, when a functional abnormality occurs in the computing array, functional safety warning information can be reported to a central processing unit (CPU). If the chip including the computing circuit is an autonomous driving chip, the autonomous driving chip operates in an autonomous driving mode of the vehicle, and after receiving the functional safety warning information, the central processing unit can control the vehicle to exit the autonomous driving mode.

[0033] In an embodiment of the present disclosure, each computing unit in a computing array can be called to perform a calculation based on test data, thereby obtaining a first computation result corresponding to each computing unit. Because each computing unit performs calculations using the same test data, the first computation results corresponding to each computing unit should theoretically match. Based on the degree of matching between the first computation results corresponding to each computing unit, it can be verified whether the first computation results corresponding to each computing unit actually match. Based on whether the theoretical situation matches the actual situation, it can be determined whether a functional safety anomaly has occurred in the computing array, thereby obtaining a corresponding functional safety detection result. For example, if the theoretical situation does not match the actual situation, it can be determined that a functional safety anomaly has occurred in the computing array. Therefore, the embodiment of the present disclosure can detect functional safety anomalies occurring in a computing circuit, which is advantageous for protecting the computing circuit.

[0034] In some alternative examples, as shown in FIG. 3, the method according to the embodiment of the present disclosure may further include step 310.

[0035] In step 310, the current state of the computational array is determined.

[0036] Optionally, in embodiments of the present disclosure, a determination module can be provided, which can determine the current state of the computational array. For example, a compiler for assigning computational tasks to computational circuits can run on the determination module. If the compiler assigns a computational task to a computational circuit, it can determine that the current state of the computational array is in an active state, i.e., the computational array has a real computational task that currently needs to be executed. If the compiler does not assign a computational task to a computational circuit, it can determine that the current state of the computational array is in an idle state, i.e., the computational array does not have a real computational task that currently needs to be executed, and the computational array is in a normal computation intermission.

[0037] Step 220 may include step 2201 .

[0038] In step 2201, in response to the current state of the computation array being an idle state, each computation unit is called to perform a computation based on test data, and a first computation result corresponding to each computation unit is obtained.

[0039] In some optional embodiments of the present disclosure, as shown in Figure 4, the method according to the embodiment of the present disclosure may further include step 410. Optionally, step 410 is performed after step 310.

[0040] In step 410, in response to the current state of the computational array being an idle state, a multiplexer included in the computational circuitry is placed in a first mode.

[0041] In the first mode, the multiplexing device conducts between the test data generation module for generating test data in the computation circuit and the computation array, such that the data generation module transmits test data to the computation array, and each computation unit performs a calculation based on the test data.

[0042] Optionally, the computation circuit may include a multiplexing device. The multiplexing device may also be referred to as a MUX. The multiplexing device may be configured to include a plurality of modes. The plurality of modes may include a first mode. In the first mode, the multiplexing device may connect the test data generation module and the computational array. In modes other than the first mode among the plurality of modes, the multiplexing device may disconnect the test data generation module from the computational array.

[0043] Optionally, when the current state of the computing array is an idle state, the multiplexing device can be set to a first mode, in which the multiplexing device connects the test data generation module and the computing array, and the test data generated by the test data generation module can be sent to the computing array by the multiplexing device, so that each computing unit in the computing array can obtain test data for calculation, and the functional safety protection module can determine whether a functional safety abnormality has occurred in the computing circuit based on the test data.

[0044] 4, when the current state of the computing array is idle, the mode of the multiplexer can be controlled to connect the test data generation module and the computing array, so that the test data generated by the test data generation module is provided to the computing array. In this way, during the pause period of normal calculation of the computing array, it can be determined whether a functional abnormality has occurred in the computing circuit through testing, which is advantageous in preventing the testing process from affecting the normal operation of the computing circuit.

[0045] In some embodiments, the multiplexing device is not installed, and the test data generated by the test data generation module can be sent directly to the computational array; and when the current state of the computational array is idle, the compiler can provide a trigger signal to the computational array to trigger each computation unit in the computational array to perform calculations based on the test data.

[0046] In the embodiment shown in FIG. 3, the normal calculation pause period of the calculation array can be used to perform functional safety detection on the calculation circuit, which is advantageous in ensuring the normal operation of the calculation circuit.

[0047] In some alternative examples, as shown in FIG. 5, the method according to the embodiment of the present disclosure may further include step 510, step 520, step 530, step 540, and step 550.

[0048] In step 510, the current state of the computational array is determined.

[0049] For a specific embodiment of step 510, please refer to the description of the specific embodiment of step 310 above, and redundant description will be omitted here.

[0050] In step 520, in response to the current state of the computation array being in an operational state, true computation-waiting data is obtained.

[0051] Alternatively, if the current state of the computation array is in an operational state, the true computation-ready data can be obtained, for example, the computation-ready data can be obtained from a true data source.

[0052] Alternatively, the true data source may be set within a chip including the computing circuit. For example, the chip including the computing circuit may include a double data rate synchronous dynamic random access memory (DDR SDRAM), which may also be abbreviated as DDR, and the DDR may be used as the true data source. For example, the chip including the computing circuit may include a cache memory, which may be used as the true data source. The true data source may be located outside the chip including the computing circuit, and the present disclosure is not limited thereto.

[0053] Alternatively, for the configuration of the data to be calculated, the description of the configuration of the test data above may be referred to, and a duplicate description will be omitted here.

[0054] In step 530, a plurality of sub-computation tasks are determined based on the data to be computed.

[0055] Optionally, N*M sub-computation tasks can be determined based on the data to be calculated. For example, the data to be calculated can include tensor data and weight data. If the tensor data is image data, the image data can be divided into N*M sub-image data, and the N*M sub-image data can correspond to the N*M sub-computation tasks. There is a one-to-one correspondence between the N*M sub-image data and the N*M sub-computation tasks.

[0056] In step 540, different computation units are invoked to perform different sub-computation tasks to obtain second computation results corresponding to the data to be computed.

[0057] Optionally, the N*M sub-computation tasks determined in step 530 can be assigned to the N*M computation units in a one-to-one correspondence, and the N*M computation units can be called to respectively execute the corresponding sub-computation tasks and obtain corresponding computation results, thereby obtaining the computation results respectively corresponding to the N*M computation units. The computation results respectively corresponding to the N*M computation units can be combined to obtain a second computation result corresponding to the data to be computed.

[0058] In one example, the data to be calculated may include tensor data and weight data. When the tensor data is image data and the values ​​of N and M are both 4, the image data may be evenly divided into 16 sub-image data, each of which may correspond to 16 sub-calculation tasks. A first of the 16 calculation units may use the weight data in the data to be calculated to perform a convolution operation on the sub-image data corresponding to the first sub-calculation task. A second of the 16 calculation units may use the weight data in the data to be calculated to perform a convolution operation on the sub-image data corresponding to the second sub-calculation task. A sixteenth of the 16 calculation units may use the weight data in the data to be calculated to perform a convolution operation on the sub-image data corresponding to the sixteenth sub-calculation task. In this manner, calculation results corresponding to the 16 calculation units may be obtained, and a second calculation result may be obtained by combining these calculation results. The second calculation result may be a feature map.

[0059] In step 550, the second calculation result is output to the designated module.

[0060] Optionally, the designation module can be a memory, and the designation module can store the second calculation result. In one example, the designation module and the above-mentioned true data source can be the same memory.

[0061] Optionally, the chip including the calculation circuit may include several subsequent modules. The subsequent modules may receive the second calculation result from the designated module and perform further calculations on the second calculation result. For example, the subsequent modules may perform calculations on the second calculation result based on a pooling operation or a rectified linear unit (ReLU) operation.

[0062] In the embodiment of the present disclosure, when the computing array is in an operational state, a computing task corresponding to data to be computed can be divided into multiple sub-computation tasks, and different sub-computation tasks can be executed by different computing units, so that different computing units can execute target operations in parallel, which is advantageous for improving the execution efficiency of the computing task corresponding to data to be computed.

[0063] 6, the method according to the embodiment of the present disclosure may further include step 610. Optionally, step 610 may be performed after step 510.

[0064] In step 610, in response to the current state of the computational array being an operational state, a multiplexer included in the computational circuitry is placed in a second mode.

[0065] In a second mode, the multiplexing device can conduct the data acquisition module in the computation circuit for acquiring data to be computed and the computation array, such that the data acquisition module transmits data to be computed to the computation array, and different computation units perform different sub-computation tasks.

[0066] As described above, the computation circuit may include a multiplexing device, and the multiplexing device may be configured to operate in a plurality of modes. In addition to the first mode, the plurality of modes may further include a second mode. In the second mode, the multiplexing device may connect the data acquisition module to the computation array. In the second mode, the multiplexing device may also disconnect the test data generation module from the computation array.

[0067] In the embodiment of the present disclosure, when the current state of the computing array is in the operating state, the mode of the multiplexer can be controlled to connect the data acquisition module and the computing array, so that the data to be calculated acquired by the data acquisition module is provided to the computing array, and each computing unit in the computing array can execute a corresponding sub-computing task, and based on this, the computing task corresponding to the data to be calculated can be normally executed. That is, the computing circuit in the embodiment of the present disclosure can not only meet the normal computing requirements, but also meet the test requirements (detection of functional safety anomalies through testing).

[0068] In some alternative examples, step 230 includes: determining a set of calculation results based on the first calculation results respectively corresponding to each calculation unit; determining, based on the set of calculation results, a first sequence including at least two first calculation results arranged in order, and a second sequence including at least two other first calculation results arranged in order; determining a degree of matching between first calculation results at the same rank in the first sequence and the second sequence.

[0069] Alternatively, a set of first calculation results corresponding to each calculation unit may be used as the set of calculation results. Then, the set of calculation results may be divided into two parts, each of which may include at least two first calculation results. A first sequence may be formed by sequentially arranging the at least two first calculation results in one of the parts. A second sequence may be formed by sequentially arranging the at least two first calculation results in the other part. The number of first calculation results in the first sequence and the second sequence may be the same or different.

[0070] In an embodiment of the present disclosure, a first calculation result ranked first in a first sequence can be compared to a first calculation result ranked first in a second sequence to determine whether they are the same, thereby obtaining a corresponding matching degree. Similarly, a first calculation result ranked second in a first sequence can be compared to a first calculation result ranked second in a second sequence to determine whether they are the same, thereby obtaining a corresponding matching degree. Similarly, a first calculation result ranked third in a first sequence can be compared to a first calculation result ranked third in a second sequence to determine whether they are the same, thereby obtaining a corresponding matching degree. The same applies below, and redundant explanations will be omitted here. If at least one of the determined matching degrees is 0, a functional safety detection result indicating that a functional safety anomaly has occurred in the computational array can be obtained. If all of the determined matching degrees are 1, a functional safety detection result indicating that no functional safety anomaly has occurred in the computational array can be obtained.

[0071] In one example, the first sequence and the second sequence each include 20 first calculation results, and the 20 first calculation results in the first sequence and the 20 first calculation results in the second sequence can form 20 result pairs. For example, the first result pair can include the first calculation result ranked first in the first sequence and the first calculation result ranked first in the second sequence, and the second result pair can include the first calculation result ranked second in the first sequence and the first calculation result ranked second in the second sequence, and so on, with no further explanation. Here, the two first calculation results in the first result pair can be compared to obtain corresponding matching degrees, and the two first calculation results in the second result pair can be compared to obtain corresponding matching degrees, with no further explanation. In this way, 20 matching degrees can be obtained. If at least one of these 20 matching degrees is 0, a functional safety detection result can be obtained to indicate that a functional abnormality has occurred in the computational array. If all of these 20 matching degrees are 1, a functional safety detection result can be obtained to indicate that no functional abnormality has occurred in the computational array.

[0072] In the embodiments of the present disclosure, a first sequence and a second sequence are obtained based on the first calculation results corresponding to each calculation unit, and the first calculation results at the same rank in the first sequence and the second sequence are compared to determine the corresponding matching degree. This eliminates the need to compare two first calculation results corresponding to each calculation unit, which is advantageous for reducing the amount of calculation required for the functional safety anomaly detection process and is also advantageous for saving resources and power consumption.

[0073] In some selectable examples, the number of test data is plural, each test data includes tensor data and weight data, and any two test data satisfy at least one of the following conditions: The tensor data included in one test data set is different from the tensor data included in the other test data set. The weight data included in one test data set is different from the weight data included in the other test data set.

[0074] Alternatively, the number of test data may be 2, 3, 5, 10, 15, 20, etc., and is not exemplified here.

[0075] In one example, after determining that the current state of the computation array is idle, test data 1 is generated at time t1, and the test data 1 is sent to the computation array. The computation array invokes N*M computation units to perform calculations based on the test data 1, and a first group of matching degrees is obtained based on the generated test data. Furthermore, test data 2 different from test data 1 is generated at time t2 (time t2 is later than time t1), and the test data 2 is sent to the computation array. The computation array invokes N*M computation units to perform calculations based on the test data 2, and a second group of matching degrees is obtained based on the generated test data. Similarly, test data 3 different from test data 1 and test data 2 is generated at time t3 (time t3 is later than time t2), and the test data 3 is sent to the computation array. The computation array invokes N*M computation units to perform calculations based on the test data 3, and a third group of matching degrees is obtained based on the generated test data. If at least one of the matching degrees of the first group, the second group, and the third group is 0, a functional safety detection result can be obtained to indicate that a functional safety abnormality has occurred in the computational array. If all of the matching degrees of the first group, the second group, and the third group are 1, a functional safety detection result can be obtained to indicate that a functional safety abnormality has not occurred in the computational array.

[0076] In the embodiments of the present disclosure, there are differences between any two test data, and by using these test data to perform tests, the calculation logic can be flipped as much as possible, which allows for more comprehensive testing of the calculation array and is advantageous for ensuring the accuracy and reliability of the final functional safety detection results.

[0077] In some alternative examples, before step 530 of the present disclosure, the method according to the embodiment of the present disclosure may further include step 710, step 720, and step 730, as shown in FIG.

[0078] In step 710, a first data layout format for the data to be calculated is determined.

[0079] Step 720 determines a second data layout format supported by the computational array.

[0080] In step 730, the to-be-computed data is converted from a first data layout format to a second data layout format.

[0081] Alternatively, the first data layout format of the data to be computed may be a format in which tensor data in the data to be computed is laid out in a true data source. The second data layout format supported by the computation array may be a data layout format specified for tensor data input to the computation array. The data layout format may also be referred to as a Layout. The data layout format may be expressed by the size of the tensor data in each dimension. For example, a data layout format may be 4h4w16c, which indicates that the height dimension size of the tensor data is 4, the width dimension size is 4, and the channel dimension size is 16. Another example data layout format may be 2h16w8c, which indicates that the height dimension size of the tensor data is 2, the width dimension size is 16, and the channel dimension size is 8.

[0082] In an embodiment of the present disclosure, after determining a first data layout format of data to be computed and a second data layout format supported by the first data layout format, it can be determined whether the first data layout format and the second data layout format are the same. If the first data layout format and the second data layout format are the same, data layout format conversion is not required. If the first data layout format and the second data layout format are different, data migration can be used to convert the data to be computed from the first data layout format to the second data layout format. For example, tensor data in the data to be computed can be converted from the first data layout format to the second data layout format. Here, data migration can be understood as data reordering. Therefore, the tensor data in the data to be computed acquired by the computation array is represented in the second data layout format, which is consistent with the data layout format supported by the computation array, and is advantageous for ensuring accurate processing of the data to be computed by the computation array.

[0083] In some alternative examples, before step 550 of the present disclosure, the method according to the embodiment of the present disclosure may further include step 840, step 850, and step 860, as shown in FIG.

[0084] In step 840, a third data layout format of the second calculation result is determined.

[0085] In step 850, a fourth data layout format supported by a preset consumer of the second calculation result is determined.

[0086] In step 860, the second calculation result is converted from the third data layout format to a fourth data layout format.

[0087] Optionally, the third data layout format of the second calculation result can be the data layout format of the second calculation result in a data array. The preset consumer of the second calculation result can be the above-mentioned subsequent module. The fourth data layout format supported by the preset consumer of the second calculation result can be the data layout format specified for the input of the preset consumer of the second calculation result.

[0088] In an embodiment of the present disclosure, after determining the third data layout format of the second calculation result and the fourth data layout format supported by the preset user of the second calculation result, it can be determined whether the third data layout format and the fourth data layout format are the same. If the third data layout format and the fourth data layout format are the same, data layout format conversion is not required. If the third data layout format and the fourth data layout format are different, data migration can be performed to convert the second calculation result from the third data layout format to the fourth data layout format. Therefore, the second calculation result subsequently output to the designated module is expressed in the fourth data layout format, which is consistent with the data layout format supported by the preset user of the second calculation result, and is advantageous to ensuring accurate processing of the second calculation result by the preset user of the second calculation result.

[0089] As described above, according to the embodiments of the present disclosure, it is possible to detect functional safety anomalies occurring in a computing circuit by utilizing a period during which normal calculations in the computing circuit are paused, with a relatively simple circuit configuration and at a relatively low cost, which is advantageous for implementing real-time protection for the computing circuit.

[0090] [Example Computational Circuit] The embodiments of the present disclosure provide a functionally safe computing circuit, which can be an important component of a chip. Hereinafter, the functionally safe computing circuit can be abbreviated as a computing circuit.

[0091] As shown in FIGS. 1 and 9, the computational circuit may include a test data generation module 10, a computational array 20, and a functional safety protection module 30.

[0092] The test data generation module 10 generates test data.

[0093] The computational array 20 includes a plurality of computational units 201, each of which performs a computation based on test data to obtain a first computation result corresponding to the computational unit 201.

[0094] The functional safety protection module 30 determines the matching degree between the first calculation results respectively corresponding to each computing unit 201, and determines the functional safety detection result of the computing array 20 based on the matching degree.

[0095] Optionally, the computational array 20 can execute a target operation, and the computational array 20 is an essential component of the computational circuit, and detection of functional safety anomalies occurring in the computational circuit can be understood as detection of functional safety anomalies occurring in the computational array 20. The test data generation module 10 and the functional safety protection module 30 are modules introduced to support functional safety detection of functional anomalies occurring in the computational circuit.

[0096] Optionally, the configuration of the test data can refer to the above description, and the duplicated description will be omitted here.

[0097] In the embodiment of the present disclosure, the test data generation module 10 and the computational array 20 can be electrically connected. The test data generation module 10 can transmit test data to the computational array 20 through the electrical connection between the test data generation module 10 and the computational array 20. Each computation unit 201 in the computational array 20 can perform calculations based on the test data, thereby obtaining a first calculation result corresponding to each computation unit 201.

[0098] Furthermore, the functional safety protection module 30 and the computing array 20 can be electrically connected. The computing array 20 can transmit the first calculation results corresponding to each computing unit 201 to the functional safety protection module 30 through the electrical connection between the functional safety protection module 30 and the computing array 20. For example, the computing array 20 can divide the first calculation results corresponding to each computing unit 201 into several groups and transmit them to the functional safety protection module 30. The functional safety protection module 30 can determine the matching degree between the first calculation results corresponding to each computing unit 201. For example, if two first calculation results are the same, it can determine that the matching degree between the two first calculation results is 1. For example, if two first calculation results are different, it can determine that the matching degree between the two first calculation results is 0.

[0099] The functional safety protection module 30 can determine the degree of matching between any two first calculation results. The functional safety protection module 30 can determine a functional safety detection result for the computational array 20 based on the determined degrees of matching. For example, if at least one of the degrees of matching is 0, a functional safety detection result indicating that a functional abnormality has occurred in the computational array 20 can be obtained. Alternatively, for example, if all of the degrees of matching are 1, a functional safety detection result indicating that no functional abnormality has occurred in the computational array 20 can be obtained.

[0100] Optionally, when a functional abnormality occurs in the computational array 20, the functional safety protection module 30 can report functional safety warning information to the central processing unit.

[0101] In an embodiment of the present disclosure, each computing unit 201 in the computing array 20 can perform a calculation based on the test data generated by the test data generation module 10 to obtain a first calculation result corresponding to each computing unit 201. Because each computing unit 201 performs calculations using the same test data, the first calculation results corresponding to each computing unit 201 should theoretically match. The functional safety protection module 30 can verify whether the first calculation results corresponding to each computing unit 201 actually match based on the degree of match between the first calculation results corresponding to each computing unit 201. Based on whether the theoretical situation matches the actual situation, it can be determined whether a functional safety anomaly has occurred in the computing array 20, and a corresponding functional safety detection result can be obtained. For example, if the theoretical situation does not match the actual situation, it can be determined that a functional safety anomaly has occurred in the computing array 20. Therefore, according to the embodiment of the present disclosure, the test data generation module 10, the computational array 20, and the functional safety protection module 30 cooperate to realize detection of functional abnormalities occurring in a computational circuit with a relatively simple circuit configuration and at a relatively low cost, which is advantageous for realizing functional safety protection for a computational circuit.

[0102] In some alternative examples, the computation circuitry may further comprise a multiplexer 40, as shown in FIG.

[0103] In response to the current state of the computational array 20 being an idle state, the multiplexer 40 enters a first mode, in which the multiplexer 40 conducts between the test data generation module 10 and the computational array 20.

[0104] The computational array 20 further receives test data from the test data generation module 10, and each computation unit 201 in the computational array 20 performs a respective computation based on the test data.

[0105] Optionally, the multiplexing device 40 can be configured to include multiple modes. The multiple modes can include a first mode. In the first mode, the multiplexing device 40 can connect the test data generation module 10 and the computational array 20. In modes other than the first mode among the multiple modes, the multiplexing device 40 can disconnect the test data generation module 10 from the computational array 20.

[0106] Optionally, the current state of the computational array 20 can be determined by the determination module described above.

[0107] Optionally, the determination module can be electrically connected to the multiplexing device 40. When the current state of the computational array 20 is an idle state, the determination module can send a control signal to the multiplexing device 40 through the electrical connection between the determination module and the multiplexing device 40 to cause the multiplexing device 40 to enter a first mode. In the first mode, the multiplexing device 40 connects the test data generation module 10 and the computational array 20, and the test data generated by the test data generation module 10 can be sent to the computational array 20 by the multiplexing device 40, so that each computation unit 201 in the computational array 20 can obtain test data for calculation. Then, the functional safety protection module 30 can determine whether a functional safety abnormality has occurred in the computational circuit.

[0108] In the embodiment of the present disclosure, when the current state of the computational array 20 is idle, the mode of the multiplexer 40 can be controlled to connect the test data generation module 10 and the computational array 20, so that the test data generated by the test data generation module 10 is provided to the computational array 20. In this way, during the pause period of the normal computation of the computational array 20, it can be determined whether a functional abnormality has occurred in the computational circuit through testing, which is advantageous in avoiding the test process from affecting the normal operation process of the computational circuit.

[0109] In some alternative examples, the computation circuitry may further comprise a data acquisition module 50 and a data output module 55, as shown in FIG.

[0110] The data acquisition module 50 acquires true data waiting to be calculated in response to the current state of the computational array 20 being in an operating state.

[0111] The computation array 20 determines multiple sub-computation tasks based on the data to be computed, and calls different computation units 201 to execute the different sub-computation tasks to obtain second computation results corresponding to the data to be computed.

[0112] The data output module 55 outputs the second calculation result to the designation module 60 .

[0113] Optionally, data acquisition module 50 and data output module 55 may be modules for supporting the normal operation of computational array 20 .

[0114] As described above, the determination module can determine the current state of the computational array 20. If the current state of the computational array 20 is in an operational state, the data acquisition module 50 can acquire the true data to be calculated. For example, the data acquisition module 50 can acquire the data to be calculated from the true data source.

[0115] The types of true data sources and the configuration of data to be calculated can be found in the above explanations, and a duplicate explanation will be omitted here.

[0116] In the embodiment of the present disclosure, the data acquisition module 50 and the computational array 20 can be electrically connected. Through the electrical connection between the data acquisition module 50 and the computational array 20, the data acquisition module 50 can send data to be calculated to the computational array 20. The computational array 20 can determine N*M sub-computation tasks based on the data to be calculated. The computational array 20 can assign the N*M sub-computation tasks to the N*M computation units 201 in a one-to-one correspondence, and call the N*M computation units 201 to respectively execute the corresponding sub-computation tasks and obtain corresponding computation results, thereby obtaining computation results respectively corresponding to the N*M computation units 201, and combining the computation results respectively corresponding to the N*M computation units 201 to obtain a second computation result corresponding to the data to be calculated.

[0117] In addition, the data output module 55 can be electrically connected to the computational array 20. The electrical connection between the data output module 55 and the computational array 20 allows the computational array 20 to transmit the second computation result to the data output module 55.

[0118] Optionally, the data output module 55 can be electrically connected to the designation module 60 via the system bus 70. The data output module 55 can transmit the second calculation result to the designation module 60 via the system bus 70. The designation module 60 can be used as a memory, and the designation module 60 can store the second calculation result. In one example, the designation module 60 and the above-mentioned true data source can be the same memory, and therefore the data acquisition module 50 can acquire the data to be calculated from the designation module 60 via the system bus 70.

[0119] In the embodiment of the present disclosure, when the computational array 20 is in an operating state, a computation task corresponding to data to be computed can be divided into multiple sub-computation tasks, and different sub-computation tasks can be executed by different computation units 201. In this way, different computation units 201 can execute target operations in parallel, which is advantageous for improving the execution efficiency of the computation task corresponding to data to be computed.

[0120] In some alternative examples, the computation circuitry may further comprise a multiplexer 40, as shown in FIG.

[0121] In response to the current state of computational array 20 being an operational state, multiplexer 40 enters a second mode, in which multiplexer 40 communicates between data acquisition module 50 and computational array 20.

[0122] The computational array 20 acquires data to be computed from the data acquisition module 50, and each computational unit 201 in the computational array 20 performs a different sub-computation task.

[0123] As described above, the multiplexing device 40 can be set to a plurality of modes. In addition to the first mode, the plurality of modes can further include a second mode. In the second mode, the multiplexing device 40 can establish electrical communication between the data acquisition module 50 and the computational array 20. In the second mode, the multiplexing device 40 can also disconnect the test data generation module 10 from the computational array 20.

[0124] 9 , the multiplexing device 40 may have a first input P1, a second input P2, and an output P3. The first input P1 may be electrically connected to the test data generation module 10. The second input P2 may be electrically connected to the data acquisition module 50. The output P3 may be electrically connected to the computational array 20. When the current state of the computational array 20 is an idle state, the determination module may send a control signal to the multiplexing device 40 so that the multiplexing device 40 is in a first mode, with the first input P1 and the output P3 conducting. When the current state of the computational array 20 is an operating state, the determination module may send a control signal to the multiplexing device 40 so that the multiplexing device 40 is in a second mode, with the second input P2 and the output P3 conducting.

[0125] In the embodiment of the present disclosure, when the current state of the computational array 20 is in the working state, the mode of the multiplexer 40 can be controlled to connect the data acquisition module 50 and the computational array 20, so that the data to be calculated acquired by the data acquisition module 50 is provided to the computational array 20, and thus each computation unit 201 in the computational array 20 can respectively execute the corresponding sub-computation task, and based on this, can normally execute the computation task corresponding to the data to be calculated. That is, the computation circuit in the embodiment of the present disclosure can not only meet the normal computation requirements, but also meet the test requirements.

[0126] In some alternative examples, as shown in FIG. 10, the functional safety protection module 30 may include a determination unit 301 and a comparison unit 303.

[0127] The determination unit 301 determines a set of calculation results based on the first calculation results respectively corresponding to each calculation unit 201, and determines, based on the set of calculation results, a first sequence including at least two first calculation results arranged in order, and a second sequence including at least two other first calculation results arranged in order.

[0128] The comparison unit 303 determines the matching degree between the first calculation results at the same rank in the first sequence and the second sequence.

[0129] Optionally, the determination unit 301 may determine a set of first calculation results corresponding to each calculation unit 201 as a set of calculation results. Then, the determination unit 301 divides the set of calculation results into two parts, each of which includes at least two first calculation results. A first sequence can be formed by sequentially arranging the at least two first calculation results in one of the parts. A second sequence can be formed by sequentially arranging the at least two first calculation results in the other part. The number of first calculation results in the first sequence and the second sequence may be the same or different.

[0130] In an embodiment of the present disclosure, the comparison unit 303 and the determination unit 301 can be electrically connected. The determination unit 301 can transmit the first sequence and the second sequence to the comparison unit 303 through the electrical connection between the comparison unit 303 and the determination unit 301. The comparison unit 303 can compare the first calculation result ranked first in the first sequence with the first calculation result ranked first in the second sequence to determine whether they are the same, thereby obtaining a corresponding matching degree. The comparison unit 303 can also compare the first calculation result ranked second in the first sequence with the first calculation result ranked second in the second sequence to determine whether they are the same, thereby obtaining a corresponding matching degree. The comparison unit 303 can also compare the first calculation result ranked third in the first sequence with the first calculation result ranked third in the second sequence to determine whether they are the same, thereby obtaining a corresponding matching degree. The same applies below, and redundant explanations will be omitted here. If at least one of the matching degrees determined by the comparison unit 303 is 0, the functional safety protection module 30 can obtain a functional safety detection result indicating that a functional safety abnormality has occurred in the computational array. If all of the matching degrees determined by the comparison unit 303 are 1, the functional safety protection module 30 can obtain a functional safety detection result indicating that no functional safety abnormality has occurred in the computational array.

[0131] In one example, the first sequence and the second sequence each include 20 first calculation results, and the 20 first calculation results in the first sequence and the 20 first calculation results in the second sequence may constitute 20 result pairs. The comparison unit 303 may include 20 comparators, where a first comparator performs a comparison operation on two first calculation results in the first result pair to obtain a signal representing the comparison result, a second comparator performs a comparison operation on two first calculation results in the second result pair to obtain a signal representing the comparison result, and so on, and redundant description will be omitted here. In this way, the 20 comparators can obtain 20 signals representing the comparison results. If all of these 20 signals are high-level signals, each matching degree determined by the comparison unit 303 is 1. If at least one of these 20 signals is low-level signals, each matching degree determined by the comparison unit 303 is 0.

[0132] In the embodiment of the present disclosure, the determination unit 301 can obtain a first sequence and a second sequence based on the first calculation result corresponding to each calculation unit 201, and the comparison unit 303 can compare the first calculation results at the same rank in the first sequence and the second sequence to determine the corresponding matching degree, which does not need to compare the first calculation results corresponding to each calculation unit 201 two by two, which is advantageous to reducing the amount of calculation required for the functional safety anomaly detection process and further advantageous to saving resources and power consumption.

[0133] In some selectable examples, the number of test data is plural, and each test data may include tensor data and weight data, and any two test data satisfy at least one of the following conditions: The tensor data included in one test data set is different from the tensor data included in the other test data set. The weight data included in one test data set is different from the weight data included in the other test data set.

[0134] In the embodiments of the present disclosure, there are differences between any two test data, and by using these test data to perform tests, the calculation logic can be flipped as much as possible, which can test the calculation array 20 more comprehensively and is advantageous for ensuring the accuracy and reliability of the final functional safety detection results.

[0135] An embodiment of the present disclosure further provides a computing system. As shown in FIG. 9, the computing system includes: the functionally safe computing circuit as described above, comprising a multiplexing device 40; and a determination module for determining the current state of a computational array included in the computation circuit and causing a multiplexer included in the computation circuit to be in a mode consistent with the current state of the computational array.

[0136] Optionally, if the current state of the computational array is an idle state, the determination module can place the multiplexing device 40 in a first mode, and if the current state of the computational array is an operating state, the determination module can place the multiplexing device 40 in a second mode.

[0137] In the embodiment of the present disclosure, the computing circuit can perform normal calculations, and during the pause period of the normal calculation, a test can be performed to determine whether a functional safety abnormality occurs in the computing circuit, so that the computing circuit can not only meet the normal calculation requirements but also meet the test requirements.

[0138] [Example Electronic Devices] FIG. 11 shows a block diagram of an electronic device 1100 according to an embodiment of the present disclosure, where the electronic device 1100 includes one or more processors 1110 and a memory 1120 .

[0139] The processor 1110 may be a central processing unit (CPU) or other form of processing unit having data processing and / or instruction execution capabilities, and may control other components within the electronic device 1100 to perform desired functions.

[0140] The memory 1120 may include one or more computer program products, which may include various forms of computer-readable storage media, such as, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. The computer-readable storage media may store one or more computer program instructions, and the processor 1110 may execute the one or more program instructions to implement the methods of each embodiment of the present disclosure described above and / or other desired functions.

[0141] In one example, the electronic device 1100 may further include input devices 1130 and output devices 1140 connected to each other via a bus system and / or other type of connection mechanism (not shown).

[0142] The input device 1130 may include a keyboard, a mouse, or the like.

[0143] The output device 1140 can output various information to the outside, and can include, for example, a display, a speaker, a printer, a communication network, and a remote output device connected thereto.

[0144] 11 shows only some of the components related to the present disclosure in the electronic device 1100, and omits components such as buses, input / output interfaces, etc. In addition, the electronic device 1100 may further include any appropriate components depending on specific application requirements.

[0145] Exemplary Computer Program Products and Computer-Readable Storage Media In addition to the above-described methods and apparatus, embodiments of the present disclosure may provide a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to the embodiments described in the "Exemplary Methods" section above.

[0146] The computer program product may have program code for carrying out operations of embodiments of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and traditional procedural programming languages ​​such as "C" or similar programming languages. The program code may execute entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on the remote computing device or a server.

[0147] Additionally, embodiments of the present disclosure may further provide a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to the embodiments described in the "Exemplary Method" section above.

[0148] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0149] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the benefits, advantages, effects, etc. mentioned in the present disclosure are merely illustrative and not limiting, and these benefits, advantages, effects, etc. are not necessarily possessed by each embodiment of the present disclosure. Furthermore, the specific details of the above disclosure are merely illustrative and easy-to-understand functions and are not limiting, and the above details do not necessarily limit the present disclosure to those realized by the above specific details.

[0150] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A method for protecting functional safety of a computing circuit, comprising: the computation circuit comprises a computation array having a plurality of computation units; The method for protecting functional safety of the computing circuit includes: generating test data; calling each of the computing units to perform a calculation based on the test data, and obtaining a first calculation result corresponding to each of the computing units; determining a matching degree between the first calculation results respectively corresponding to each of the calculation units; determining a functional safety detection result of the computing array based on the matching degree.

2. The method for functional security of the computing circuit further includes determining a current state of the computing array; The step of calling each of the calculation units to perform calculations based on the test data and obtaining first calculation results respectively corresponding to each of the calculation units includes:

2. The method for protecting functional safety of a computing circuit according to claim 1, further comprising: in response to a current state of the computing array being an idle state, calling each of the computing units to perform a calculation based on the test data, and obtaining a first calculation result corresponding to each of the computing units.

3. The method for protecting functional security of the computing circuit further includes placing a multiplexer included in the computing circuit in a first mode in response to the current state of the computing array being an idle state; 3. The method for protecting functional safety of a computing circuit according to claim 2, wherein in the first mode, the multiplexing device conducts between the test data generation module in the computing circuit and the computing array such that a data generation module for generating the test data transmits the test data to the computing array, and each of the computing units performs a calculation based on the test data.

4. The method for protecting functional safety of the computing circuit includes: determining a current state of the computational array; acquiring true data to be calculated in response to the current state of the computational array being in an operational state; determining a plurality of sub-computation tasks based on the to-be-computed data; calling a different one of the computing units to execute a different one of the sub-computation tasks to obtain a second computation result corresponding to the data to be computed; 2. The method for protecting functional safety of a computing circuit according to claim 1, further comprising the step of: outputting the second calculation result to a designated module.

5. The method for protecting functional security of the computing circuit further includes placing a multiplexer included in the computing circuit in a second mode in response to the current state of the computing array being an operating state; 5. The method for protecting functional safety of a computing circuit according to claim 4, wherein in the second mode, the multiplexing device conducts the data acquisition module in the computing circuit and the computing array, such that a data acquisition module for acquiring the data to be computed transmits the data to be computed to the computing array, and different computing units execute different sub-computation tasks.

6. determining a matching degree between the first calculation results corresponding to each of the calculation units, determining a set of calculation results based on the first calculation results respectively corresponding to each of the calculation units; determining, based on the set of calculation results, a first sequence including at least two of the first calculation results arranged in order, and a second sequence including at least two other of the first calculation results arranged in order; determining the degree of matching between the first calculation results that are in the same order in the first sequence and the second sequence.

7. the number of test data is plural, and each test data includes tensor data and weight data; Any two of the test data are 6. The method for protecting functional safety of a computing circuit according to claim 1, wherein at least one of two conditions is satisfied: a condition that the tensor data included in one of the test data is different from the tensor data included in the other of the test data; and a condition that the weight data included in one of the test data is different from the weight data included in the other of the test data.

8. a test data generation module for generating test data; a computation array having a plurality of computation units, each of which performs a computation based on the test data to obtain a first computation result corresponding to each of the computation units; a functional safety protection module for determining a matching degree between the first calculation results corresponding to each of the calculation units, and determining a functional safety detection result of the calculation array based on the matching degree.

9. The functionally safe computing circuit comprises: a multiplexing device that, in response to the current state of the computational array being an idle state, places the computational array in a first mode and conducts the test data generation module and the computational array in the first mode; 9. The functionally safe computing circuit of claim 8, further comprising: a computational array that is also used to obtain the test data from the test data generation module, wherein each of the computational units in the computational array performs a respective calculation based on the test data.

10. The functionally safe computing circuit comprises: a data acquisition module that acquires true data to be calculated in response to the current state of the computational array being in an operating state; The computation array is also used to determine a plurality of sub-computation tasks based on the data to be computed, and to call different computation units to execute different sub-computation tasks, thereby obtaining a second computation result corresponding to the data to be computed; The functionally safe computing circuit according to claim 8 , further comprising: a data output module for outputting the second computation result to a designated module.

11. a multiplexing device that, in response to the current state of the computational array being in an operational state, places the computational array in a second mode and communicates the data acquisition module and the computational array in the second mode; 11. The functionally safe computing circuit of claim 10, further comprising: the computing array also used to acquire the computation-ready data from the data acquisition module, wherein each computing unit in the computing array performs a different sub-computation task.

12. The functional safety protection module includes: a determination unit for determining a set of calculation results based on the first calculation results respectively corresponding to each of the calculation units, and determining, based on the set of calculation results, a first sequence including at least two of the first calculation results arranged in order, and a second sequence including at least two other of the first calculation results arranged in order; 12. The functionally safe computing circuit according to claim 8, further comprising a comparison unit for determining a degree of matching between the first computation results at the same rank in the first sequence and the second sequence.

13. A functionally safe computing circuit according to any one of claims 9 to 11; a determination module that determines a current state of a computational array included in the computation circuit and causes a multiplexer included in the computation circuit to be in a mode that is consistent with the current state of the computational array.

14. A computer-readable storage medium, comprising: A computer-readable storage medium storing a computer program for executing the method for protecting the functional safety of a computing circuit according to any one of claims 1 to 5.

15. 1. An electronic device comprising: a processor; and a memory for storing instructions executable by the processor, An electronic device that implements the method for protecting functional safety of a computing circuit according to any one of claims 1 to 5 by the processor reading and executing the executable instructions from the memory.

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