Manufacturing method of SOI wafer for high frequency

Abstract

To provide a manufacturing method capable of improving harmonic characteristics of a silicon substrate having a general resistivity in the same level as a high-resistivity substrate.SOLUTION: A manufacturing method of SOI wafer for high frequency includes steps of: forming a high resistivity epilayer having different thicknesses on another substrate, measuring harmonic characteristics, and determining a thickness of the epilayer based on a measurement result; preparing a first substrate having a resistivity of 1 Ω*cm or more to be a base wafer; forming the epilayer with the determined thickness on a surface of the first substrate; forming a Trap-rich layer (a polysilicon layer) on the surface of the first substrate; forming a first thermal oxide film on the surface of the first substrate; preparing a second substrate that becomes a bond wafer; forming a second heat oxidation film onto the surface; adhering the base wafer with the bond wafer via the first and second heat oxidation films that become a BOX layer; and reducing a film thickness of the second substrate to make a SOI layer with the predetermined thickness.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a high frequency SOI wafer. [Background technology]

[0002] Silicon wafers produced by the Czochralski (CZ) method are primarily used as semiconductor substrates (hereinafter simply referred to as "substrates") for manufacturing semiconductor integrated circuits (hereinafter simply referred to as "integrated circuits"). In particular, there is a strong demand for high performance and miniaturization of integrated circuits in communication devices.

[0003] Integrated circuits in communications equipment combine active elements such as transistors and passive elements such as inductors. The signal levels handled by these elements range from large signals to very weak signals. Therefore, it is necessary to minimize interference between signals from different integrated circuits on the semiconductor substrate. Furthermore, for both active and passive elements, it is desirable to have extremely low harmonic distortion levels, as failure to minimize resistance loss and stray capacitance will increase current consumption and shorten the operating time of communications equipment.

[0004] Here, the indicator of harmonic distortion may be referred to as harmonic distortion characteristics, second harmonic characteristics, harmonic characteristics, or simply harmonic distortion, but in the following it will mainly be referred to as harmonic characteristics.

[0005] These high-frequency integrated circuits often use silicon wafers. The silicon wafers used must have high resistivity to reduce resistance loss. It is known that the higher the resistivity, the better the insulating properties, resulting in improved harmonic characteristics.

[0006] To further improve the characteristics, wafers using a Trap-rich layer are widely used. Specifically, a polysilicon layer (polycrystalline silicon layer) is often used as the Trap-rich layer (see Patent Document 1).

[0007] On the other hand, it is known that manufacturing silicon wafers with high resistivity is technically more difficult than manufacturing silicon wafers with a typical resistivity of around 10 Ω·cm. The reason for this is that contamination by dopant elements in each process must be controlled to an extremely low concentration.

[0008] The concentration is 1×10 for a p-type material with a resistivity of 10 Ω cm. 15 cm 3 On the other hand, when the resistivity is 10000 Ω cm, which is where the harmonic characteristics improve significantly, the 12 cm 3 This is a concentration three orders of magnitude lower than when the resistivity is 10 Ω·cm. Therefore, even if the dopant contamination concentration does not affect the resistivity when the resistivity is 10 Ω·cm, it may cause fluctuations in the resistivity when the resistivity is 10,000 Ω·cm.

[0009] Contamination by dopant elements can occur not only during the single crystal pulling process, but also during ingot processing, wafer cleaning, and polishing, so countermeasures must be taken at every step. This makes it extremely difficult and costly to manufacture high-resistivity silicon wafers.

[0010] As a countermeasure, Patent Document 2 describes a silicon wafer for high-frequency devices in which the minimum resistivity of the silicon substrate is 500 Ω·cm, an epitaxial layer of 100 to 5000 Ω·cm is formed on the silicon substrate, and then a polysilicon layer that becomes a Trap-rich layer is formed.

[0011] The harmonic characteristics of this wafer are improved by forming an epitaxial layer, but the resistivity of the silicon substrate is specified to be at least 500 Ω·cm, and harmonic characteristics do not improve if the resistivity is lower than that. Furthermore, the thickness of the epitaxial layer is specified to be 0.2 to 20 μm, but there is no mention of how the film thickness is determined.

[0012] Furthermore, Patent Document 3 discloses an SOI substrate having a low-resistivity silicon substrate, a high-resistivity epitaxial layer, a polysilicon layer, an insulating film, and a silicon single crystal layer, but does not mention harmonic characteristics. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Special Publication No. 2015-503853 [Patent Document 2] Special Publication No. 2019-536260 [Patent Document 3] Japanese Patent Application Publication No. 6-163678 Summary of the Invention [Problem to be solved by the invention]

[0014] As described above, further improvements in harmonic characteristics are desired for high-frequency integrated circuits used in communication devices and the like, due to demands for miniaturization and reduced power consumption. However, if high-resistivity silicon wafers are used for this purpose, measures to prevent contamination by dopant elements are required in all processes, which makes manufacturing difficult and increases costs.

[0015] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a method for manufacturing a high frequency SOI wafer that can improve the harmonic characteristics to the same level as a high resistivity silicon single crystal substrate, even when a silicon single crystal substrate having a normal resistivity, rather than a high resistivity, is used. [Means for solving the problem]

[0016] In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a high frequency SOI wafer having a structure in which a silicon single crystal substrate, a high resistivity epitaxial layer, a Trap-rich layer, a BOX layer, and an SOI layer are laminated in this order, the method comprising the steps of: previously depositing high resistivity epitaxial layers of different thicknesses on the surface of another silicon single crystal substrate, measuring harmonic characteristics, and determining the thickness of the high resistivity epitaxial layer based on the measurement results; preparing a first silicon single crystal substrate having a resistivity of 1 Ω cm or more to serve as a base wafer; depositing a high resistivity epitaxial layer on the surface of the first silicon single crystal substrate to the thickness determined in the step of determining the thickness of the high resistivity epitaxial layer; a base wafer manufacturing process including a step of forming a polysilicon layer as a Trap-rich layer on the surface of a high-yield epitaxial layer and a step of forming a first thermal oxide film on the surface of the polysilicon layer; a bond wafer manufacturing process including a step of preparing a second silicon single crystal substrate to be a bond wafer and a step of forming a second thermal oxide film on the surface of the second silicon single crystal substrate; a step of bonding the base wafer and the bond wafer together via the first thermal oxide film and the second thermal oxide film to be a BOX layer; and a step of thinning the second silicon single crystal substrate to an SOI layer of a predetermined thickness.

[0017] With this manufacturing method, by depositing a high-resistivity epitaxial layer of an appropriate thickness based on pre-measured harmonic characteristics on the surface of a first silicon single crystal substrate (which is not a high-resistivity substrate but has a typical resistivity of 1 Ω·cm or more), it is possible to reliably increase the resistivity up to the depth region where harmonic signals propagate, improving the harmonic characteristics to a level equivalent to that of a high-resistivity silicon single crystal substrate. In addition, by depositing a polysilicon layer as a Trap-rich layer, the harmonic characteristics can be further improved.

[0018] Furthermore, the step of determining the thickness of the high resistivity epitaxial layer preferably involves depositing high resistivity epitaxial layers of different thicknesses on the surface of another silicon single crystal substrate having the same resistivity as the first silicon single crystal substrate that will serve as the base wafer, measuring the harmonic characteristics of the high resistivity epitaxial layers of different thicknesses at the same desired frequency, and focusing on changes in the harmonic characteristics with increasing thickness, to determine the thickness of the high resistivity epitaxial layer to be equal to or greater than the thickness at which the harmonic characteristics no longer change.

[0019] By forming a high-resistivity epitaxial layer of the thickness determined in this way on the surface of a first single-crystal silicon substrate with a resistivity of 1 Ω·cm or more, the high-resistivity epitaxial layer covers the depth region through which harmonic signals propagate, preventing the harmonic signals from reaching the first single-crystal silicon substrate, thereby ensuring improved harmonic characteristics.

[0020] Furthermore, it is preferable that the resistivity of the first silicon single crystal substrate that serves as the base wafer is set to 10 Ω·cm or more and less than 30,000 Ω·cm.

[0021] If the resistivity is within this range, a silicon single crystal substrate with a general resistivity can be used, and the harmonic characteristics can be reliably improved.

[0022] In addition, in the step of forming the high resistivity epitaxial layer, it is preferable to use a silane-based source gas that does not contain a dopant gas for adjusting resistivity, and only hydrogen gas as a carrier gas.

[0023] By using only these gases, it is possible to form a high-resistivity epitaxial layer with an appropriate resistivity. Furthermore, since the gas does not contain a dopant gas for adjusting resistivity, it is possible to prevent fluctuations in resistivity due to contamination by dopant elements for adjusting resistivity.

[0024] Furthermore, it is preferable that the resistivity of the high resistivity epitaxial layer is 6000 Ω·cm or more.

[0025] Such a resistivity can satisfy the resistivity required for use in high frequency devices. [Effects of the Invention]

[0026] With the method for manufacturing high-frequency SOI wafers of the present invention, by depositing a high-resistivity epitaxial layer of an appropriate thickness based on pre-measured harmonic characteristics on the surface of a first silicon single crystal substrate with a non-high resistivity, general resistivity of 1 Ω cm or more, it is possible to reliably increase the resistivity up to the depth region through which harmonic signals propagate, improving the harmonic characteristics to a level equivalent to that of a high-resistivity silicon single crystal substrate. In addition, by depositing a polysilicon layer as a Trap-rich layer, the harmonic characteristics can be further improved.

[0027] Furthermore, it is now possible to use general-purpose substrates with low resistivity, which have traditionally been considered unsuitable for high-frequency devices, thereby reducing the cost and making SOI wafers more versatile.

[0028] Furthermore, when high-resistivity silicon wafers are used as in the past, measures to prevent contamination by dopant elements are required in all processes, but this is no longer necessary, manufacturing is easy, and reductions in manufacturing costs are expected. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 2 is a flow diagram for determining the thickness of a high resistivity epitaxial layer in one embodiment of the present invention. [Figure 2] FIG. 1 is a schematic diagram showing an example of a method for measuring harmonic characteristics. [Figure 3] 1 is a graph showing the relationship between the thickness of a high resistivity epitaxial layer and harmonic characteristics. [Figure 4] FIG. 1 is a flow chart showing an example of a method for manufacturing a high frequency SOI wafer. DETAILED DESCRIPTION OF THE INVENTION

[0030] The present invention will be described in detail below, but the present invention is not limited thereto.

[0031] As described above, in high-frequency integrated circuits used in communication devices and the like, further improvements in harmonic characteristics (reduction of harmonic distortion) have been required due to demands for miniaturization and reduced power consumption.

[0032] The inventors have conducted extensive research into this issue. In one experiment, epitaxial layers with high resistivity (10,000 Ω·cm) and thicknesses ranging from 2 μm to 20 μm were formed on silicon single crystal substrates with a typical resistivity of 10 Ω·cm. A 400 nm oxide film was then formed on each wafer. Co-planar waveguide (CPW) electrodes with a line length of 2,200 μm were then formed on these wafers, and the harmonic characteristics (second-harmonic characteristics) were measured at a frequency of 1 GHz. The results showed that second-harmonic distortion decreased as the epitaxial layer thickness increased when the epitaxial layer thickness was 5 μm or less, but remained unchanged when the epitaxial layer thickness was greater than 5 μm.

[0033] The inventors suspected that this was due to the skin effect. It is generally known that the higher the frequency of a high-frequency signal, the shallower the propagation region becomes due to the skin effect. In the above experiment, the use of an epitaxial wafer with a high resistivity in the surface region allowed the high-frequency signal to propagate only in the surface region with high resistivity by taking advantage of the skin effect, and prevented the signal from propagating to the silicon single crystal substrate with low resistivity, which is believed to be why harmonic distortion was reduced.

[0034] In addition, in experiments with different frequencies, epitaxial layers with a high resistivity of 10,000 Ω·cm and thicknesses ranging from 1 μm to 15 μm were formed on silicon single crystal substrates with a typical resistivity of 10 Ω·cm. A 400 nm oxide film was then formed, and CPW electrodes with a line length of 2,200 μm were formed on these wafers, and the second-harmonic characteristics were measured at a frequency of 0.5 GHz. The results showed that second-harmonic distortion decreased as the epitaxial layer thickness increased when the epitaxial layer was 7 μm or less, but remained unchanged when the epitaxial layer was thicker than 7 μm.

[0035] In addition, in another experiment at a different frequency, epitaxial layers with a high resistivity of 10,000 Ω·cm and thicknesses ranging from 0.1 μm to 5 μm were formed on silicon single crystal substrates with a typical resistivity of 10 Ω·cm. A 400 nm oxide film was then formed, and CPW electrodes with a line length of 2,200 μm were formed on these wafers, and the second-harmonic characteristics were measured at a frequency of 10 GHz. The results showed that second-harmonic distortion decreased as the epitaxial layer thickness increased when the epitaxial layer thickness was 1 μm or less, but remained unchanged when the epitaxial layer thickness was greater than 1 μm.

[0036] Based on the above findings, the inventors discovered that even with silicon wafers that have a typical resistivity of about 10 Ω cm and are inexpensive to manufacture, which inherently have large harmonic distortion and are therefore unsuitable for high-frequency devices, it is possible to reduce harmonic distortion to the same level as when a high-resistivity silicon single crystal substrate is used, by forming a high-resistivity epitaxial layer of a predetermined thickness on the silicon wafer, thereby completing the present invention.

[0037] That is, the present invention is a method for manufacturing a high frequency SOI wafer having a structure in which a silicon single crystal substrate, a high resistivity epitaxial layer, a Trap-rich layer, a BOX layer, and an SOI layer are laminated in this order, the method comprising the steps of: previously depositing high resistivity epitaxial layers of different thicknesses on the surface of another silicon single crystal substrate, measuring the harmonic characteristics, and determining the thickness of the high resistivity epitaxial layer based on the measurement results; preparing a first silicon single crystal substrate having a resistivity of 1 Ω cm or more to serve as a base wafer; depositing a high resistivity epitaxial layer on the surface of the first silicon single crystal substrate to the thickness determined in the step of determining the thickness of the high resistivity epitaxial layer; a base wafer manufacturing process including a step of forming a polysilicon layer as a Trap-rich layer on a surface of a taxial layer and a step of forming a first thermal oxide film on the surface of the polysilicon layer; a bond wafer manufacturing process including a step of preparing a second silicon single crystal substrate to be a bond wafer and a step of forming a second thermal oxide film on the surface of the second silicon single crystal substrate; a step of bonding the base wafer and the bond wafer together via the first thermal oxide film and the second thermal oxide film to be a BOX layer; and a step of thinning the second silicon single crystal substrate to an SOI layer of a predetermined thickness.

[0038] The following description will be made with reference to the drawings.

[0039] [Step of determining the thickness of the high resistivity epitaxial layer] FIG. 1 shows a flow diagram for determining the thickness of a high resistivity epitaxial layer in one embodiment of the present invention.

[0040] First, prepare another silicon single crystal substrate with the same resistivity as the first silicon single crystal substrate that will become the base wafer in the subsequent steps. There are no particular restrictions on the resistivity as long as it is 1 Ω·cm or higher, but it is preferable to prepare a p-type silicon single crystal substrate with a common resistivity, for example, 10 Ω·cm or higher (Figure 1a).

[0041] Epitaxial layers of varying thicknesses are then deposited on the surface of the substrate (Figure 1b). The resistivity of the epitaxial layer in this case should be the resistivity required for use in high-frequency devices. While not particularly limited, it is preferable to use a silane-based source gas (monosilane, dichlorosilane, trichlorosilane, etc.) that does not contain a dopant gas for resistivity adjustment, and hydrogen gas alone as the carrier gas (hereafter referred to as "non-doped"). While not particularly limited, the resistivity of the non-doped epitaxial layer is preferably 6000 Ω·cm or higher. The resistivity of the non-doped epitaxial layer is more preferably in the range of 6000 to 30,000 Ω·cm.

[0042] Then, epitaxial layers of different thicknesses are formed, and then an oxide film having a thickness of, but not limited to, 400 nm is formed on the wafers (FIG. 1c).

[0043] Thereafter, although not limited to this, a CPW electrode with a line length of 2200 μm is formed (FIG. 1d), and the second harmonic characteristics are measured as harmonic characteristics at the same desired frequency (FIG. 1e).

[0044] Figure 2 shows an example of a method for measuring harmonic characteristics, showing the state of a CPW electrode. The frequency of the input high-frequency signal in this case is the frequency used in the high-frequency device. A signal line 12 is placed between two ground lines 11, with a line length of 2200 μm, and measurement probes 13 and 14 are connected to both sides for measurement. For example, with measurement probe 13 as the input side and measurement probe 14 as the output side, various propagation characteristics, including harmonic characteristics, can be measured by applying an input at the desired frequency from measurement probe 13 and detecting the output from measurement probe 14.

[0045] From the results obtained in the above experiments, focusing on the change in harmonic characteristics with increasing epitaxial layer thickness, in the thin epitaxial layer region, harmonic distortion is reduced as the epitaxial layer thickness increases, but once the epitaxial layer thickness exceeds a certain thickness, there is no change. From these results, by determining the thickness of the high resistivity epitaxial layer to be equal to or greater than the thickness at which the harmonic characteristics no longer change, it is possible to form a high resistivity epitaxial layer with little harmonic distortion.

[0046] Figure 3 shows the relationship between the thickness of the high-resistivity epitaxial layer (EP thickness) and harmonic characteristics (2HD). The circles in the figure represent the results of determining harmonic characteristics by varying the thickness under the conditions of a substrate resistivity of 10 Ω·cm, an epitaxial layer resistivity of 10,000 Ω·cm, and a high-frequency signal frequency of 1 GHz. The dashed line in the figure also represents the harmonic characteristics of a conventional high-resistivity substrate with a substrate resistivity of 10,000 Ω·cm. These results demonstrate that in this embodiment, if the epitaxial layer thickness is 5 μm or more, second-harmonic distortion can be reduced and harmonic characteristics equivalent to those of conventional high-resistivity substrates can be obtained.

[0047] [Manufacturing method for high frequency SOI wafers] Next, a method for manufacturing a high frequency SOI wafer will be described.

[0048] FIG. 4 is a flow chart showing an example of a method for manufacturing a high frequency SOI wafer.

[0049] [Base wafer manufacturing process] First, a first silicon single crystal substrate 21 is prepared, which is a p-type silicon single crystal substrate having a resistivity of, for example, 10 Ω cm or more, although the resistivity is not particularly limited as long as it is 1 Ω cm or more (FIG. 4a).

[0050] The resistivity of the first silicon single crystal substrate 21 is not particularly limited, but is preferably 10 Ω·cm or more and less than 30,000 Ω·cm. However, it goes without saying that the first silicon single crystal substrate may have a higher resistivity.

[0051] However, it is necessary to prepare a silicon single crystal substrate having the same resistivity as that used in the above-mentioned [Step of determining the thickness of the high resistivity epitaxial layer].

[0052] Thereafter, a high resistivity epitaxial layer 22 having the thickness determined in the above-mentioned [Step of determining the thickness of the high resistivity epitaxial layer] is formed on the surface of the first silicon single crystal substrate 21 (FIG. 4b).

[0053] In this case, the resistivity of the high resistivity epitaxial layer 22 is set to a high resistivity. By setting the resistivity to a high value in this manner, even if the resistivity of the first silicon single crystal substrate 21 is a general resistivity, it is possible to obtain harmonic characteristics equivalent to those obtained when a high-resistivity silicon single crystal substrate is used, thereby expanding the range of resistivities that can be used for the first silicon single crystal substrate 21. The resistivity of the high resistivity epitaxial layer 22 is not particularly limited, but specifically, it is preferably set to 6000 Ω·cm or more without doping.

[0054] Next, a polysilicon layer 23 is formed as a Trap-rich layer on the surface of the high resistivity epitaxial layer 22 (FIG. 4c). The thickness of the polysilicon layer 23 is not particularly limited.

[0055] Thereafter, a first thermal oxide film 24 is formed on the surface of the polysilicon layer 23 (FIG. 4d). In this step, the heat treatment temperature is not particularly limited as long as the first thermal oxide film 24 can be formed on the surface of the polysilicon layer 23. At this time, although not particularly limited, it is preferable that the thickness of the first thermal oxide film 24 is 400 nm or more.

[0056] The first silicon single crystal substrate 21 thus produced becomes the base wafer when bonding is performed.

[0057] [Bond wafer manufacturing process] Furthermore, a second silicon single crystal substrate 25 is prepared separately from the first silicon single crystal substrate 21 (FIG. 4e). The second silicon single crystal substrate 25 may be a p-type silicon single crystal substrate having a resistivity of, for example, about 10 Ω cm, but is not limited to this.

[0058] Next, a second thermal oxide film 26 is formed on the surface of the second silicon single crystal substrate 25 (FIG. 4f). This second thermal oxide film 26 can be formed using a known technique such as a CVD method. In this way, the second thermal oxide film 26 can be formed on the entire surface of the second silicon single crystal substrate 25 by thermal oxidation. This second silicon single crystal substrate 25 serves as a bond wafer when bonding.

[0059] The order of steps a, b, c, and d in Figure 4 and steps e and f in Figure 4 does not matter. Either can be done first, or they can be done in parallel.

[0060] Furthermore, although the first silicon single crystal substrate and the second silicon single crystal substrate are of p-type conductivity, they may be of n-type conductivity depending on the application.

[0061] [Laminating process] As described above, a first silicon single crystal substrate 21 is prepared as a base wafer, on which a high-resistivity epitaxial layer 22 and a polysilicon layer 23 are formed, followed by the formation of a first thermal oxide film 24. Then, the first thermal oxide film 24 on the polysilicon layer 23 of the first silicon single crystal substrate 21 is bonded to a second thermal oxide film 26 of a second silicon single crystal substrate 25 serving as a bond wafer. The bonded first thermal oxide film 24 and second thermal oxide film 26 form a so-called BOX layer 27. In this manner, an SOI wafer can be manufactured (FIG. 4g).

[0062] [Thinning process] After bonding, the second silicon single crystal substrate 25 can be thinned to form an SOI layer of a desired thickness (FIG. 4h). This thinning can be achieved by a known method of polishing the single crystal substrate on the bond wafer side or by an ion implantation delamination method.

[0063] In this way, a high frequency SOI wafer can be manufactured. The high frequency SOI wafer of this embodiment has a structure in which a high resistivity epitaxial layer, a polysilicon layer (Trap-rich layer), a thermal oxide film layer (BOX layer), and a silicon single crystal layer (SOI layer) are stacked in this order on a base wafer of a silicon single crystal substrate.

[0064] [Measurement of harmonic characteristics] This paper explains the measurement of harmonic characteristics of silicon wafers and SOI wafers.

[0065] Although there is no particular limitation on the method for measuring the harmonic characteristics of the high frequency SOI wafer of this embodiment, the following method is convenient.

[0066] The method for measuring the second harmonic characteristic, which is a typical harmonic characteristic, is to first remove the top silicon single crystal layer from the SOI wafer, then form a metal coplanar waveguide (CPW) on the thermal oxide layer, and ground probes to both ends of this metal electrode. Then, as explained above with reference to Figure 2, a high-frequency signal is input from either side, and the second harmonic characteristic output from the other side can be measured. The input at this time is not particularly limited, but can be, for example, a frequency of 1 GHz and an input power of 15 dBm. [Example]

[0067] EXAMPLES The present invention will be described in detail below with reference to examples and comparative examples, but the present invention is not limited thereto.

[0068] [Example 1] First, the thickness of the high-resistivity epitaxial layer was determined using the flow shown in Figure 1. A high-resistivity epitaxial layer with a resistivity of 10,000 Ω·cm was deposited on a 300 mm diameter p-type silicon single crystal substrate with a substrate resistivity of 10 Ω·cm. After that, a 400 nm thick thermal oxide film was formed on these substrates, and a CPW with a line length of 2,200 μm was then formed. As a harmonic characteristic, the second-order harmonic characteristics were measured at a frequency of 1 GHz.

[0069] As a result, it was found that the second harmonic characteristics decreased as the epitaxial layer thickness increased up to 5 μm, and remained almost unchanged at thicknesses greater than that. From these results, it was found that at a frequency of 1 GHz, an epitaxial layer thickness of 5 μm can reduce harmonic distortion.

[0070] Next, an SOI wafer was fabricated using the process shown in Figure 4.

[0071] A non-doped epitaxial layer with a resistivity of 10,000 Ω·cm and a thickness of 5 μm was formed on a first p-type silicon single crystal substrate with a diameter of 300 mm and a resistivity of 10 Ω·cm. Then, a polysilicon layer with a thickness of 2 μm was formed to become the Trap-rich layer. This was then heat-treated in an oxidizing atmosphere at 1,050°C to form a thermal oxide film with a thickness of 400 nm on the polysilicon layer.

[0072] In addition, a second p-type silicon single crystal substrate having a diameter of 300 mm was separately heat-treated in an oxidizing atmosphere at 1050° C. to form a thermal oxide film having a thickness of 100 nm.

[0073] Next, the thermal oxide film on the epitaxial layer of the first silicon single crystal substrate was bonded to the thermal oxide film of the second silicon single crystal substrate, and the silicon single crystal layer on the surface of the bonded wafers was then thinned by polishing to produce an SOI wafer with a single crystal silicon film (SOI layer) thickness of 1 μm.

[0074] [Example 2] A Trap-rich SOI wafer was produced under the same conditions as in Example 1, except that a first silicon single crystal substrate with a high resistivity of 10,000 Ω·cm was used.

[0075] Then, the second harmonic characteristics of the Trap-rich SOI wafer produced in Example 1 and the Trap-rich SOI wafer produced in Example 2 were measured.

[0076] Specifically, the SOI layer of each SOI wafer was polished away to expose the oxide layer, and then an electrode with a line length of 2200 μm was formed on the oxide layer, and the second-harmonic characteristics were measured at a frequency of 1 GHz and an input power of 15 dBm.

[0077] As a result, it was confirmed that the harmonic distortion was approximately -90dBm for both, with no difference.

[0078] As described above, according to Examples 1 and 2, it was found that the harmonic characteristics can be improved even with a general first silicon single crystal substrate having a resistivity of 10 Ω cm, without using a first silicon single crystal substrate having a high resistivity such as 10,000 Ω cm as in the past.

[0079] [Comparative Example 1, Examples 3, 4, and 5] The thickness of the high-resistivity epitaxial layer was determined using the flow shown in Figure 1. Epitaxial layers with a resistivity of 10,000 Ω·cm and thicknesses ranging from 2 μm to 20 μm were formed on p-type silicon single crystal substrates (Example 3) with a diameter of 300 mm and a substrate resistivity of 10 Ω·cm. A 400 nm-thick oxide film was then formed on these substrates, after which a CPW with a line length of 2,200 μm was formed. Second-order harmonic characteristics were measured at a frequency of 1 GHz to determine the harmonic characteristics.

[0080] Furthermore, evaluation was also carried out in the same manner when the substrate resistivity was 0.1 Ω·cm (Comparative Example 1), 1 Ω·cm (Example 4), and 100 Ω·cm (Example 5).

[0081] As a result, it was found that when the substrate resistivity was 1, 10, or 100 Ω·cm, the second harmonic characteristics became smaller as the epitaxial layer thickness increased up to 5 μm, and remained almost unchanged at thicknesses greater than that. From these results, it was found that at a frequency of 1 GHz, harmonic distortion could be reduced by setting the epitaxial layer thickness to 5 μm or more.

[0082] On the other hand, when the substrate resistivity is 0.1 Ω·cm, it was found that the second harmonic characteristics do not decrease even when the epitaxial layer thickness increases.

[0083] Considering the reason for this, when the substrate resistivity is 0.1 Ω cm, the dopant concentration is approximately 10 17 atoms / cm 3 It is thought that the resistivity was so high that boron diffused into the epitaxial layer during the process of forming the thermal oxide film, lowering the resistivity, and as a result, the second harmonic characteristics did not improve.

[0084] [Comparative Example 2, Examples 6, 7, and 8] The thickness of the high-resistivity epitaxial layer was determined using the flow shown in Figure 1. Epitaxial layers with a resistivity of 10,000 Ω·cm and thicknesses ranging from 0.1 μm to 20 μm were deposited on p-type silicon single crystal substrates (Example 6) with a diameter of 300 mm and a substrate resistivity of 10 Ω·cm. A 400 nm-thick oxide film was then formed on these substrates, after which a CPW with a line length of 2,200 μm was formed. Second-order harmonic characteristics were measured at a frequency of 10 GHz to determine the harmonic characteristics.

[0085] The same evaluation was also carried out when the substrate resistivity was 0.1 Ω·cm (Comparative Example 2), 1 Ω·cm (Example 7), and 100 Ω·cm (Example 8).

[0086] As a result, it was found that when the substrate resistivity was 1, 10, or 100 Ω·cm, the second harmonic characteristics became smaller as the epitaxial layer thickness increased up to 1 μm, and remained almost unchanged at thicknesses greater than that. From these results, it was found that at a frequency of 10 GHz, harmonic distortion could be reduced by setting the epitaxial layer thickness to 1 μm or more.

[0087] On the other hand, when the substrate resistivity is 0.1 Ω·cm, it was found that the second harmonic characteristics do not decrease even when the epitaxial layer thickness increases.

[0088] Considering the reason for this, when the substrate resistivity is 0.1 Ω·cm, as in Comparative Example 1, the dopant concentration is about 10 17 atoms / cm 3 It is thought that the resistivity was so high that boron diffused into the epitaxial layer during the process of forming the thermal oxide film, lowering the resistivity, and as a result, the second harmonic characteristics did not improve.

[0089] As described above, the harmonic characteristics were not improved when the substrate resistivity was 0.1 Ω cm as in Comparative Examples 1 and 2, but were improved when the substrate resistivity was 1 to 10,000 Ω cm as in Examples 1 to 8. Therefore, according to this example, it was shown that a general-purpose substrate with low resistivity can be used without being limited to a conventional high-resistivity silicon single crystal substrate, thereby enabling cost reduction and versatility of SOI wafers.

[0090] The present invention includes the following aspects. [1]: 1. A method for manufacturing a high frequency SOI wafer having a structure in which a silicon single crystal substrate, a high resistivity epitaxial layer, a Trap-rich layer, a BOX layer, and an SOI layer are stacked in this order, comprising: a step of previously depositing high resistivity epitaxial layers of different thicknesses on the surface of another silicon single crystal substrate, measuring the harmonic characteristics, and determining the thickness of the high resistivity epitaxial layer based on the measurement results; a base wafer manufacturing process including the steps of: preparing a first silicon single crystal substrate having a resistivity of 1 Ω cm or more to serve as a base wafer; depositing a high resistivity epitaxial layer on a surface of the first silicon single crystal substrate to a thickness determined in the step of determining the thickness of the high resistivity epitaxial layer; depositing a polysilicon layer as a Trap-rich layer on the surface of the high resistivity epitaxial layer; and forming a first thermal oxide film on the surface of the polysilicon layer; A bond wafer manufacturing process including the steps of: preparing a second silicon single crystal substrate to be a bond wafer; and forming a second thermal oxide film on a surface of the second silicon single crystal substrate; bonding the base wafer and the bond wafer together via the first thermal oxide film and the second thermal oxide film, which will become a BOX layer; thinning the second silicon single crystal substrate to an SOI layer of a predetermined thickness; 2. A method for manufacturing a high frequency SOI wafer, comprising: [2]: The step of determining the thickness of the high resistivity epitaxial layer comprises: forming a high resistivity epitaxial layer having a different thickness on the surface of another silicon single crystal substrate having the same resistivity as the first silicon single crystal substrate to be the base wafer; measuring the harmonic characteristics of the high resistivity epitaxial layers having different thicknesses at the same desired frequency; The method for manufacturing a high frequency SOI wafer according to the above [1], characterized in that the thickness of the high resistivity epitaxial layer is determined to be equal to or greater than the thickness at which the harmonic characteristics do not change, by focusing on the change in harmonic characteristics with increasing thickness. [3]: The method for producing a high frequency SOI wafer according to [1] or [2] above, wherein the resistivity of the first silicon single crystal substrate serving as the base wafer is set to 10 Ω·cm or more and less than 30,000 Ω·cm. [4]: The method for manufacturing a high frequency SOI wafer according to any one of [1] to [3] above, wherein in the step of forming the high resistivity epitaxial layer, a silane-based source gas containing no dopant gas for adjusting resistivity and only hydrogen gas as a carrier gas are used. [5]: The method for producing a high frequency SOI wafer according to any one of [1] to [4] above, wherein the resistivity of the high resistivity epitaxial layer is set to 6000 Ω·cm or more.

[0091] The present invention is not limited to the above-described embodiments. The above-described embodiments are merely examples, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and that provides similar effects is included within the technical scope of the present invention. [Explanation of symbols]

[0092] 11...ground line, 12...signal line, 13, 14...measurement probe, 21...first silicon single crystal substrate, 22...high resistivity epitaxial layer, 23...polysilicon layer (trap-rich layer), 24...first thermal oxide film, 25...second silicon single crystal substrate, 26...second thermal oxide film, 27...BOX layer.

Claims

1. A method for manufacturing a high frequency SOI wafer having a structure in which a silicon single crystal substrate, a high resistivity epitaxial layer, a trap-rich layer, a BOX layer, and an SOI layer are stacked in this order, comprising: a step of previously depositing high resistivity epitaxial layers of different thicknesses on the surface of another silicon single crystal substrate, measuring the harmonic characteristics, and determining the thickness of the high resistivity epitaxial layer based on the measurement results; a base wafer manufacturing process including the steps of: preparing a first silicon single crystal substrate having a resistivity of 1 Ω cm or more to be a base wafer; depositing a high resistivity epitaxial layer on a surface of the first silicon single crystal substrate to a thickness determined in a step of determining a thickness of the high resistivity epitaxial layer; depositing a polysilicon layer as a trap-rich layer on the surface of the high resistivity epitaxial layer; and forming a first thermal oxide film on the surface of the polysilicon layer; A bond wafer manufacturing process including the steps of: preparing a second silicon single crystal substrate to be a bond wafer; and forming a second thermal oxide film on a surface of the second silicon single crystal substrate; bonding the base wafer and the bond wafer together via the first thermal oxide film and the second thermal oxide film, which will become a BOX layer; thinning the second silicon single crystal substrate to an SOI layer of a predetermined thickness; A method for manufacturing a high frequency SOI wafer, comprising:

2. The step of determining the thickness of the high resistivity epitaxial layer comprises: forming a high resistivity epitaxial layer having a different thickness on the surface of another silicon single crystal substrate having the same resistivity as the first silicon single crystal substrate that will be the base wafer; measuring the harmonic characteristics of the high resistivity epitaxial layers having different thicknesses at the same desired frequency; 2. The method for manufacturing a high frequency SOI wafer according to claim 1, wherein the thickness of the high resistivity epitaxial layer is determined to be equal to or greater than the thickness at which the harmonic characteristics do not change, by focusing on changes in harmonic characteristics with increasing thickness.

3. 3. The method for producing a high frequency SOI wafer according to claim 1, wherein the resistivity of the first silicon single crystal substrate serving as the base wafer is set to 10 Ω·cm or more and less than 30,000 Ω·cm.

4. 3. The method for manufacturing a high frequency SOI wafer according to claim 1, wherein in the step of forming the high resistivity epitaxial layer, a silane-based source gas containing no dopant gas for adjusting resistivity and only hydrogen gas as a carrier gas are used.

5. 3. The method for producing a high frequency SOI wafer according to claim 1, wherein the resistivity of the high resistivity epitaxial layer is set to 6000 Ω·cm or more.

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