Semiconductor device

Abstract

To provide a semiconductor device capable of improving durability.SOLUTION: A semiconductor device according to an embodiment includes a first electrode, first to third semiconductor regions, a conductor, and a second electrode. The conductor includes first and second gate electrode parts, a first wiring part, and first and second connection parts. The first gate electrode part is located on the first part. The second semiconductor region is located between the first gate electrode part and the second gate electrode part. The first wiring part is located on the second part. The first gate electrode part, the second gate electrode part, and the first wiring part extend in a third direction. The first connection part is connected between a first end part of the first gate electrode part in the third direction and an end part of the first wiring part in the third direction. The second connection part is connected between the second end part of the second gate electrode part in the third direction and the end part of the first wiring part. Each of the first connection part and the second connection part has an inclined surface inclined with respect to the second direction and the third direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, etc. It is desirable for semiconductor devices to have high withstand voltages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-94676 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of improving the withstand voltage. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductor, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes a first portion and a second portion located around the first portion along a plane perpendicular to a first direction extending from the first electrode toward the first semiconductor region. The second semiconductor region is provided on the first portion. The third semiconductor region is provided on the second semiconductor region. The conductor is provided on the first semiconductor region via an insulating layer. The conductor includes a first gate electrode portion, a second gate electrode portion, a first wiring portion, a first connection portion, and a second connection portion. The first gate electrode portion is located on the first portion. The first gate electrode portion faces the second semiconductor region in a second direction perpendicular to the first direction. The first gate electrode portion extends in a third direction perpendicular to the first and second directions. The second semiconductor region is located between the first gate electrode portion and the second gate electrode portion. The second gate electrode portion extends in the third direction. The first wiring portion is located on the second portion and extends in the third direction. The first connection portion is connected between a first end of the first gate electrode portion in the third direction and an end of the first wiring portion in the third direction. The second connection portion is connected between a second end of the second gate electrode portion in the third direction and the end of the first wiring portion. The position of the first wiring portion in the second direction is between the position of the first gate electrode portion in the second direction and the position of the second gate electrode portion in the second direction. The first connection portion and the second connection portion have inclined surfaces inclined with respect to the second direction and the third direction. The second electrode is provided on the second semiconductor region and the third semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged plan view of a portion II of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV of FIG. [Figure 6] FIG. 6 is an enlarged plan view of a part of FIG. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a plan view showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 9] 9(a) and 9(b) are cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment. [Figure 10] 10(a) and 10(b) are cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a plan view showing a part of a semiconductor device according to a reference example. [Figure 12] 12(a) and 12(b) are plan views showing the manufacturing process of the semiconductor device according to the reference example and the embodiment, respectively. [Figure 13] FIG. 13 is a plan view showing a part of a semiconductor device according to a modification of the embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already described are designated by the same reference numerals, and detailed description will be omitted as appropriate. In the following description and drawings, n+ , n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] Fig. 1 is a plan view showing a semiconductor device according to an embodiment. Fig. 2 is an enlarged plan view of a portion II of Fig. 1. Fig. 3 is a cross-sectional view taken along III-III in Fig. 2. Fig. 4 is a cross-sectional view taken along IV-IV in Fig. 2. Fig. 5 is a cross-sectional view taken along VV in Fig. 2. The semiconductor device 100 according to the embodiment is a MOSFET. As shown in FIGS. - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + source region 3 (third semiconductor region), p + Semiconductor area 4, n + The semiconductor device includes a drain region 5, a conductor 10, an insulating layer 20, an insulating layer 25, a drain electrode 31 (first electrode), a source electrode 32 (second electrode), a gate pad 33, and a wiring layer 33a. In Fig. 2, the insulating layer 20, the insulating layer 25, and the source electrode 32 are omitted, and the wiring layer 33a is represented by a dashed line.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the Y direction (second direction) and the X direction (third direction). -The direction toward the n-type drift region 1 is called "up" and the opposite direction is called "down." These directions are - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0010] 1, a source electrode 32 and a gate pad 33 are provided on the upper surface of the semiconductor device 100. The source electrode 32 and the gate pad 33 are spaced apart from each other and electrically isolated from each other.

[0011] 2, a conductor 10 is provided below the source electrode 32 and the gate pad 33. The conductor 10 is electrically isolated from the source electrode 32. The conductor 10 is electrically connected to the gate pad 33 via a wiring layer 33a provided on the outer periphery of the semiconductor device 100.

[0012] As shown in FIGS. 3 and 4, a drain electrode 31 is provided on the bottom surface of the semiconductor device 100. + The drain region 5 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31. - The drift region 1 is n + The n-type drain region 5 is provided on the n-type drain region 5. - The drift region 1 is n + The n-type drain region 5 is electrically connected to the drain electrode 31. - The n-type impurity concentration in the n-type drift region 1 is + The n-type impurity concentration in the n-type drain region 5 is lower than that in the n-type drain region 5 .

[0013] n - As shown in FIGS. 1 and 3 to 5, the drift region 1 includes a first portion 1a and a second portion 1b. The second portion 1b is located around the first portion 1a in the XY plane. The first portion 1a is located in the cell region. The cell region is a region through which current mainly flows when the semiconductor device 100 is in operation. The second portion 1b is located in the termination region. The termination region is a region where a depletion layer spreads toward the periphery of the semiconductor device 100 when the semiconductor device 100 is at its breakdown voltage.

[0014] As shown in FIG. 3, the p-type base region 2 is provided on the first portion 1a. + Shape source region 3 and p + The p-type semiconductor region 4 is provided on the p-type base region 2. + The p-type impurity concentration in the p-type semiconductor region 4 is higher than the p-type impurity concentration in the p-type base region 2.

[0015] The conductor 10 is n - The conductor 10 is provided on the drift region 1 via an insulating layer 20. As shown in FIG.

[0016] 3, a plurality of gate electrode portions 11 are provided on the first portion 1a. Each gate electrode portion 11 extends in the X direction. In the Y direction, the gate electrode portion 11 faces the p-type base region 2 with the insulating layer 20 interposed therebetween. In the Y direction, the p-type base regions 2 and the gate electrode portions 11 are arranged alternately.

[0017] As shown in Fig. 4, a plurality of wiring portions 12 are provided on the second portion 1b. Each wiring portion 12 extends in the X direction. In the Y direction, n - Parts of the drift region 1 and a plurality of wiring portions 12 are arranged alternately.

[0018] 2, the connection portion 13 is connected between the gate electrode portion 11 and the wiring portion 12, and electrically connects one end in the X direction of the gate electrode portion 11 to one end in the X direction of the wiring portion 12. The connection portion 13 has a surface inclined with respect to the X direction and the Y direction.

[0019] The other ends of the wiring portions 12 in the X direction are connected to each other in the Y direction and are also connected to the wiring layer 33a.

[0020] The position of one wiring portion 12 in the Y direction is between the position of one gate electrode portion 11 in the Y direction and the position of the adjacent gate electrode portion 11 in the Y direction. When viewed from the X direction, the multiple gate electrode portions 11 and the multiple wiring portions 12 are arranged alternately in the Y direction.

[0021] As shown in FIG. 3, the p-type base region 2, n + Shape source region 3, and p + A source electrode 32 is provided on the p-type semiconductor region 4. The source electrode 32 is connected to the p-type base region 2, the n-type + Shape source region 3, and p + The conductor 10 is electrically connected to the semiconductor region 4. The insulating layer 25 is provided between the conductor 10 and the source electrode 32. The conductor 10 and the source electrode 32 are electrically separated by the insulating layer 25.

[0022] FIG. 6 is an enlarged plan view of a part of FIG. 6, as a specific example of the conductor 10, the multiple gate electrode portions 11 include a first gate electrode portion 11a and a second gate electrode portion 11b. The multiple wiring portions 12 include a first wiring portion 12a. The first gate electrode portion 11a and the second gate electrode portion 11b are adjacent to each other in the Y direction. A position P2a in the Y direction of the first wiring portion 12a is between a position P1a in the Y direction of the first gate electrode portion 11a and a position P1b in the Y direction of the second gate electrode portion 11b.

[0023] The first gate electrode portion 11a includes a first end E1a in the X direction. The second gate electrode portion 11b includes a second end E1b in the X direction. The first wiring portion 12a includes an end E2a in the X direction. The multiple connection portions 13 include a first connection portion 13a and a second connection portion 13b. The first connection portion 13a is connected between the first end E1a of the first gate electrode portion 11a and the end E2a of the first wiring portion 12a. The second connection portion 13b is connected between the second end E1b of the second gate electrode portion 11b and the end E2a of the first wiring portion 12a.

[0024] The first gate electrode portion 11a has a side surface S1a parallel to the X direction. The second gate electrode portion 11b has a side surface S1b parallel to the X direction. The first connection portion 13a has a first inclined surface S2a inclined with respect to the X direction and the Y direction. The second connection portion 13b has a second inclined surface S2b inclined with respect to the X direction and the Y direction. The first inclined surface S2a is continuous with the side surface S1a. The second inclined surface S2b is continuous with the first inclined surface S2a. The side surface S1b is continuous with the second inclined surface S2b.

[0025] An intermediate portion 14 is present between the gate electrode portion 11 and the connection portion 13, and between the wiring portion 12 and the connection portion 13. For example, as shown in FIG. 5 , the lower end of the intermediate portion 14 is located lower than the lower end of the wiring portion 12. The position in the Z direction of the lower end of the gate electrode portion 11 and the position in the Z direction of the lower end of the connection portion 13 are substantially the same as the position in the Z direction of the lower end of the wiring portion 12. Therefore, the lower end of the intermediate portion 14 is located lower than the lower end of the gate electrode portion 11 and the lower end of the connection portion 13.

[0026] 6, the plurality of gate electrode portions 11 may further include a third gate electrode portion 11c. The plurality of wiring portions 12 may further include a second wiring portion 12b. The plurality of connecting portions 13 may further include a third connecting portion 13c and a fourth connecting portion 13d. The second gate electrode portion 11b and the third gate electrode portion 11c are adjacent to each other in the Y direction. A position P2b in the Y direction of the second wiring portion 12b is between a position P1b in the Y direction of the second gate electrode portion 11b and a position P1c in the Y direction of the third gate electrode portion 11c.

[0027] The third gate electrode portion 11c includes a third end E1c in the X direction. The second wiring portion 12b includes an end E2b in the X direction. The third connection portion 13c is connected between the second end E1b of the second gate electrode portion 11b and the end E2b of the second wiring portion 12b. The fourth connection portion 13d is connected between the third end E1c of the third gate electrode portion 11c and the end E2b of the second wiring portion 12b. The third connection portion 13c and the fourth connection portion 13d have inclined surfaces that are inclined with respect to the X direction and the Y direction.

[0028] As shown in FIGS. 2 and 6, at the height (position in the Z direction) where the p-type base region 2 is provided, - The p-type drift region 1 and the p-type base region 2 are separated by a connection portion 13 and an intermediate portion 14. By dividing the range in which the p-type base region 2 is provided by the conductor 10, variations in the range of the p-type base region 2 can be suppressed compared to when the p-type base region 2 is not divided. Variations in the breakdown voltage of the semiconductor device 100 due to variations in the range of the p-type base region 2 can be suppressed.

[0029] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 31 relative to the source electrode 32, a voltage equal to or greater than the threshold is applied to the conductor 10. This forms a channel (inversion layer) in the p-type base region 2 facing the gate electrode portion 11. Electrons pass through the channel and are transferred from the source electrode 32 to the n-type - The current flows to the p-type drift region 1, turning on the semiconductor device 100. When the voltage applied to the conductor 10 then falls below the threshold, the channel in the p-type base region 2 disappears, turning the semiconductor device 100 off.

[0030] An example of the material for each component is explained below. - p-type drift region 1, p-type base region 2, n + Shape source region 3, p + shaped semiconductor region 4, and n + The drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The conductor 10 and the wiring layer 33a include a conductive material such as polysilicon. The conductor 10 may be doped with an impurity. The insulating layer 20 and the insulating layer 25 include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 31, the source electrode 32, and the gate pad 33 include a metal such as titanium, gold, or aluminum.

[0031] 7, 9(a), 9(b), 10(a), and 10(b) are cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment, and FIG. 8 is a plan view showing the manufacturing process of the semiconductor device according to the embodiment. First, n - Shape drift region 1 and n + A semiconductor substrate Sub including a shaped drain region 5 is prepared. By reactive ion etching (RIE), an n-type semiconductor substrate is formed as shown in FIG. - An opening 40 is formed in the upper surface of the drift region 1 .

[0032] As shown in FIG. 8 , the opening 40 includes a plurality of first trenches 41, a plurality of second trenches 42, a plurality of third trenches 43, and an intermediate portion 44. The first trench 41 is located on the first portion 1a. The second trench 42 is located on the second portion 1b. The third trench 43 is located between the end of the first trench 41 in the Y direction and the end of the second trench 42 in the Y direction. The side surfaces of the third trench 43 are inclined with respect to the X direction and the Y direction. The intermediate portion 44 is located between the first trench 41 and the third trench 43, or between the second trench 42 and the third trench 43.

[0033] By thermal oxidation, n - An insulating layer 20 is formed along the upper surface of the drift region 1 and the inner surface of the opening 40. A conductive layer that fills the opening 40 is formed on the insulating layer 20. The upper surface of the conductive layer is recessed by wet etching or chemical dry etching (CDE), thereby forming a conductor 10 inside the opening 40, as shown in FIG.

[0034] The conductor 10 formed inside the first trench 41 corresponds to the gate electrode portion 11. The conductor 10 formed inside the second trench 42 corresponds to the wiring portion 12. The conductor 10 formed inside the third trench 43 corresponds to the connection portion 13. The conductor 10 formed inside the intermediate portion 44 corresponds to the intermediate portion 14.

[0035] P-type impurities and n-type impurities are ion-implanted sequentially into the regions between the first trenches 41 to form the p-type base region 2 and the n-type + A source region 3 is formed. An insulating layer 25 is formed on the conductor 10. As shown in FIG. 9(b), a part of the insulating layer 20 and a part of the insulating layer 25 are removed to form an opening 50.

[0036] Through the opening 50, p-type impurities are introduced into the n + Ion implantation is performed in the region between the source regions 3, + As shown in FIG. 10(a), a source electrode 32 is formed by sputtering to fill the opening 50. + The n-type drain region 5 is then grown to a predetermined thickness. + The bottom surface of the shaped drain region 5 is ground. As shown in FIG. 10(b), + A drain electrode 31 is formed by sputtering on the lower surface of the drain region 5. In this way, the semiconductor device 100 according to the embodiment is manufactured.

[0037] FIG. 11 is a plan view showing a part of a semiconductor device according to a reference example. In the semiconductor device 100r shown in FIG. 11, the conductor 10r includes a gate electrode portion 11, a wiring portion 12, and a connection portion 13r. The connection portion 13r is connected between the gate electrode portion 11 and the wiring portion 12. The orientation of the connection portion 13r differs from the orientation of the connection portion 13 in the semiconductor device 100 according to the embodiment. The side surface of the connection portion 13r is perpendicular to the X direction and parallel to the Y direction. The conductor 10r also includes an intermediate portion 14r. The intermediate portion 14r is located between the gate electrode portion 11 and the connection portion 13r or between the wiring portion 12 and the connection portion 13r.

[0038] The advantages of the embodiment will be described. In the manufacture of the semiconductor device 100, when the conductor 10 is formed, an opening 40 is formed as shown in FIGS. 7 and 8. Dry etching is used to form the opening 40 in the semiconductor layer. In dry etching, plasma of a gas that is reactive with the semiconductor material is used. The semiconductor material reacts with radicals from the gas, removing the semiconductor material and forming the opening 40. At this time, radicals can more easily penetrate into the interior of the opening in a wider portion of the opening 40 than in a narrower portion of the opening 40, and etching progresses more easily.

[0039] 12(a) and 12(b) are plan views showing the manufacturing process of the semiconductor device according to the reference example and the embodiment, respectively. 12(a), an opening 40r for forming a conductor 10r is formed. The opening 40r includes a first trench 41, a second trench 42, a third trench 43r, and an intermediate portion 44r.

[0040] The third trench 43r is located between the Y-direction end of the first trench 41 and the Y-direction end of the second trench 42. The side surfaces of the third trench 43r are perpendicular to the X-direction and parallel to the Y-direction. The intermediate portion 44r is located between the first trench 41 and the third trench 43r, or between the second trench 42 and the third trench 43r. A conductive layer containing polysilicon is buried in the opening 40r to form the conductor 10r. At this time, a portion of the conductor 10r is located inside the intermediate portion 44r. This portion of the conductor 10r corresponds to the intermediate portion 14r.

[0041] As shown in FIG. 11 , the width of the intermediate portion 14r is wider than the widths of the gate electrode portion 11, the wiring portion 12, and the connection portion 13r. Therefore, as shown in FIG. 12 , the width of the intermediate portion 44r where the intermediate portion 14r is formed is also wider than the widths of the gate electrode portion 11, the wiring portion 12, and the connection portion 13r. Therefore, etching progresses more easily in the intermediate portion 44r than in the first trench 41, the second trench 42, and the third trench 43r. The lower end of the intermediate portion 44r is formed deeper than the lower ends of the first trench 41, the second trench 42, and the third trench 43r. As a result, in the conductor 10r formed inside the opening 40r, the lower end of the intermediate portion 14r is located lower than the lower ends of other portions, such as the gate electrode portion 11, the wiring portion 12, and the connection portion 13r. That is, the lower end of the intermediate portion 14r protrudes downward relative to the lower ends of the other portions.

[0042] The further the lower end of the intermediate portion 14r protrudes downward, the more likely an electric field concentration occurs near the lower end of the intermediate portion 14r. That is, the electric field strength near the lower end of the intermediate portion 14r is greater than the electric field strength near the lower ends of other portions. This may cause dielectric breakdown of the insulating layer 20 near the lower end of the intermediate portion 14r, resulting in destruction of the semiconductor device 100r.

[0043] In the semiconductor device 100, the connection portion 13 has an inclined surface inclined with respect to the X direction and the Y direction. In this case, when the conductor 10 is formed, the side surface of the third trench 43 also inclines with respect to the X direction and the Y direction, as shown in FIG. 12(b).

[0044] In the example shown in FIG. 12(a), the first trench 41 or the second trench 42 intersects with the third trench 43r in a direction perpendicular to the third trench 43r. In the example shown in FIG. 12(b), the first trench 41 or the second trench 42 intersects with the third trench 43 in a direction not perpendicular to the third trench 43. When the structure shown in FIG. 12(b) is used, the area of ​​the intermediate portion 44 located therebetween is smaller than the area of ​​the intermediate portion 44r shown in FIG. 12(a). Therefore, in manufacturing the semiconductor device 100, although etching progresses more easily in the intermediate portion 44 than in the first trench 41, the second trench 42, and the third trench 43, the amount of etching in the intermediate portion 44 can be suppressed more than the amount of etching in the intermediate portion 44r. In the conductor 10, the amount of protrusion of the lower end of the intermediate portion 14 relative to other portions can be suppressed, thereby suppressing electric field concentration near the lower end of the intermediate portion 14. The electric field strength in the vicinity of the lower end of the intermediate portion 14 can be reduced, and the occurrence of breakdown of the semiconductor device 100 can be suppressed.

[0045] 6, the first inclined surface S2a of the first connecting portion 13a is not parallel to the second inclined surface S2b of the second connecting portion 13b. Preferably, the angle between the first inclined surface S2a and the second inclined surface S2b is greater than 90 degrees and less than 150 degrees. If the angle is within this range, the area of ​​the intermediate portion 14 in the XY plane can be effectively reduced. In other words, the electric field strength near the lower end of the intermediate portion 14 can be effectively reduced.

[0046] 5, the insulating layer 20 may include a first insulating region 21 and a second insulating region 22. The first insulating region 21 is located between the end E2a of the first wiring portion 12a and the second portion 1b. The second insulating region 22 is located between the other end E2b of the first wiring portion 12a in the Y direction and the second portion 1b. The thickness of the second insulating region 22 is greater than the thickness of the first insulating region 21.

[0047] The portion of the conductor 10 that is more peripheral than the wiring portion 12 is pulled up higher than the semiconductor region and connected to the wiring layer 33a. In the portion that is pulled up, a corner C is generated, as shown in FIG. 5 . The corner C is more susceptible to electric field concentration than other portions. By making the second insulating region 22 thicker than the first insulating region 21, the electric field concentration near the corner C can be suppressed, and the occurrence of breakdown of the semiconductor device 100 can be further suppressed.

[0048] As shown in FIG. 6, the p-type base region 2 has a first surface S3a and a second surface S3b. The first surface S3a faces the first gate electrode portion 11a in the Y direction. The second surface S3b faces the second gate electrode portion 11b in the Y direction. The plane orientation of the first surface S3a and the plane orientation of the second surface S3b are preferably {100} planes or {110} planes. This is because, when the semiconductor device 100 is in an on-state, the mobility of electrons in the channel can be increased, and the on-resistance of the semiconductor device 100 can be reduced. In this case, the plane orientation of the first inclined surface S2a and the plane orientation of the second inclined surface S2b are inclined with respect to the {100} plane or {110} plane.

[0049] (Variation) Fig. 13 is a plan view showing a part of a semiconductor device according to a modified example of the embodiment. Fig. 14 is a cross-sectional view taken along line XIV-XIV of Fig. 13. Note that insulating layer 20, insulating layer 25, and source electrode 32 are omitted from Fig. 13. In a semiconductor device 110 according to the modification, as shown in Fig. 13, a contact plug 33b is provided on the wiring portion 12. As shown in Fig. 14, the wiring portion 12 is electrically connected to a wiring layer 33a via the contact plug 33b. An insulating layer 25 is provided between the wiring portion 12 and the wiring layer 33a.

[0050] In the semiconductor device 100, as shown in FIG. 2, the ends of the wiring portions 12 in the X direction are connected to each other. This is because the wiring layer 33a and the conductor 10 are formed together. On the other hand, in the semiconductor device 110, as shown in FIG. 13, the ends E3 of the wiring portions 12 in the X direction are separated from each other in the Y direction. This structure can prevent the width of the openings at the ends from increasing when forming openings for the wiring portions 12. This can prevent localized etching when forming the openings. As a result, as shown in FIG. 14, the protrusion amount of the lower end of the end E3 can be reduced. This can reduce the electric field strength near the lower end of the end E3, thereby preventing damage to the semiconductor device 110.

[0051] Furthermore, according to the semiconductor device 110, the electric field strength in the vicinity of the lower end of the end portion E3 can be reduced, so that the relatively thick second insulating region 22 as shown in FIG. 5 is not necessary.

[0052] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first portion and a second portion located around the first portion along a plane perpendicular to a first direction from the first electrode toward the first semiconductor region; a second semiconductor region of a second conductivity type provided on the first portion; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a conductor provided on the first semiconductor region via an insulating layer, a first gate electrode portion located on the first portion, facing the second semiconductor region in a second direction perpendicular to the first direction, and extending in a third direction perpendicular to the first direction and the second direction; a second gate electrode portion extending in the third direction, the second semiconductor region being located between the first gate electrode portion and the second gate electrode portion; a first wiring portion located on the second portion and extending in the third direction; a first connection portion connected between a first end portion of the first gate electrode portion in the third direction and an end portion of the first wiring portion in the third direction; a second connection portion connected between a second end portion of the second gate electrode portion in the third direction and the end portion of the first wiring portion; the conductor including: a first wiring portion having a position in the second direction between a position of the first gate electrode portion in the second direction and a position of the second gate electrode portion in the second direction; and the first connection portion and the second connection portion having inclined surfaces inclined with respect to the second direction and the third direction; a second electrode provided on the second semiconductor region and the third semiconductor region; A semiconductor device comprising: (Feature 2) the conductor includes an intermediate portion located between the first connection portion, the second connection portion, and the end portion of the first wiring portion, 2. The semiconductor device according to claim 1, wherein a lower end of the intermediate portion is located lower than a lower end of the first wiring portion. (Feature 3) the first connection portion has a first inclined surface inclined with respect to the second direction and the third direction, the second connection portion has a second inclined surface that is inclined with respect to the second direction and the third direction and is connected to the first inclined surface, 3. The semiconductor device according to feature 1 or 2, wherein an angle between the first inclined surface and the second inclined surface is greater than 90 degrees and less than 150 degrees. (Feature 4) The insulating layer is a first insulating region located between the end of the first wiring portion and the second portion; a second insulating region located between the other end of the first wiring portion in the third direction and the second portion; Including, 4. The semiconductor device according to any one of Features 1 to 3, wherein the second insulating region has a thickness greater than a thickness of the first insulating region. (Feature 5) A semiconductor device described in any one of features 1 to 4, wherein the length of the first wiring portion in the second direction is longer than the length of the first gate electrode portion in the second direction and longer than the length of the second gate electrode portion in the second direction. (Feature 6) the second semiconductor region has a first surface facing the first gate electrode portion in the second direction, the plane orientation of the first plane is a {100} plane or a {110} plane, 6. The semiconductor device according to any one of Features 1 to 5, wherein the plane orientation of the inclined plane is inclined with respect to the {100} plane and the {110} plane. (Feature 7) The conductor is a third gate electrode portion extending in the third direction, with another second semiconductor region located between the second gate electrode portion and the third gate electrode portion; a second wiring portion located above the second portion; a third connection portion located between the second end portion and an end portion of the second wiring portion in the third direction; a fourth connection portion located between a third end portion of the third gate electrode portion in the third direction and the end portion of the second wiring portion; further comprising a position of the second wiring portion in the second direction is between a position of the second gate electrode portion in the second direction and a position of the third gate electrode portion in the second direction, 7. The semiconductor device according to any one of features 1 to 6, wherein the third connecting portion and the fourth connecting portion have inclined surfaces inclined with respect to the second direction and the third direction. (Feature 8) a plurality of gate electrode portions including the first gate electrode portion and the second gate electrode portion are arranged in the second direction on the first portion; 8. The semiconductor device according to any one of features 1 to 7, wherein a plurality of wiring portions including the first wiring portion are arranged in the second direction on the second portion. (Feature 9) 9. The semiconductor device according to feature 8, wherein, when viewed from the third direction, the gate electrode portions and the wiring portions are arranged alternately in the second direction.

[0053] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0054] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0055] 1:n - p-type drift region, 1a: first portion, 1b: second portion, 2: p-type base region, 3: n + 4: p-type source region; 5: n-type semiconductor region +drain region, 10, 10r: conductor, 11: gate electrode portion, 11a: first gate electrode portion, 11b: second gate electrode portion, 11c: third gate electrode portion, 12: wiring portion, 12a: first wiring portion, 12b: second wiring portion, 13, 13r: connection portion, 13a: first connection portion, 13b: second connection portion, 13c: third connection portion, 13d: fourth connection portion, 14, 14r: intermediate portion, 20: insulating layer, 21: first insulating region, 22: second insulating region, 25: insulating layer, 31: drain electrode, 32: source electrode, 33: gate pad, 33a: wiring layer, 33b: contact plug, 40, 40r: opening, 41: first trench, 42: second trench, 43: third trench, 43r: third trench, 44,44r: intermediate part, 50: opening, 100,100r,110: semiconductor device, C: corner, E1a: first end, E1b: second end, E1c: third end, E2a,E2b: end, P1a~P1c,P2a,P2b: position, S1a, S1b: Side surface, S2a: First inclined surface, S2b: Second inclined surface, S3a: First surface, S3b: Second surface, Sub: Semiconductor substrate

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first portion and a second portion located around the first portion along a plane perpendicular to a first direction from the first electrode toward the first semiconductor region; a second semiconductor region of a second conductivity type provided on the first portion; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a conductor provided on the first semiconductor region via an insulating layer, a first gate electrode portion located on the first portion, facing the second semiconductor region in a second direction perpendicular to the first direction, and extending in a third direction perpendicular to the first direction and the second direction; a second gate electrode portion extending in the third direction, the second semiconductor region being located between the first gate electrode portion and the second gate electrode portion; a first wiring portion located on the second portion and extending in the third direction; a first connection portion connected between a first end portion of the first gate electrode portion in the third direction and an end portion of the first wiring portion in the third direction; a second connection portion connected between a second end portion of the second gate electrode portion in the third direction and the end portion of the first wiring portion; the conductor including: a first wiring portion having a position in the second direction between a position of the first gate electrode portion in the second direction and a position of the second gate electrode portion in the second direction; and the first connection portion and the second connection portion having inclined surfaces inclined with respect to the second direction and the third direction; a second electrode provided on the second semiconductor region and the third semiconductor region; A semiconductor device comprising:

2. the conductor includes an intermediate portion located between the first connection portion, the second connection portion, and the end portion of the first wiring portion, The semiconductor device according to claim 1 , wherein a lower end of said intermediate portion is located lower than a lower end of said first wiring portion.

3. the first connection portion has a first inclined surface inclined with respect to the second direction and the third direction, the second connection portion has a second inclined surface that is inclined with respect to the second direction and the third direction and is connected to the first inclined surface, 2. The semiconductor device according to claim 1, wherein an angle between said first inclined surface and said second inclined surface is greater than 90 degrees and less than 150 degrees.

4. The insulating layer is a first insulating region located between the end of the first wiring portion and the second portion; a second insulating region located between the other end of the first wiring portion in the third direction and the second portion; Including, The semiconductor device according to claim 1 , wherein the thickness of said second insulating region is greater than the thickness of said first insulating region.

5. 2. The semiconductor device according to claim 1, wherein the length of the first wiring portion in the second direction is longer than the length of the first gate electrode portion in the second direction and longer than the length of the second gate electrode portion in the second direction.

6. the second semiconductor region has a first surface facing the first gate electrode portion in the second direction; the plane orientation of the first plane is a {100} plane or a {110} plane, 2. The semiconductor device according to claim 1, wherein the inclined plane has a plane orientation inclined with respect to a {100} plane and a {110} plane.

7. The conductor is a third gate electrode portion extending in the third direction, with another second semiconductor region located between the second gate electrode portion and the third gate electrode portion; a second wiring portion located above the second portion; a third connection portion located between the second end portion and an end portion of the second wiring portion in the third direction; a fourth connection portion located between a third end portion of the third gate electrode portion in the third direction and the end portion of the second wiring portion; further comprising a position of the second wiring portion in the second direction is between a position of the second gate electrode portion in the second direction and a position of the third gate electrode portion in the second direction; The semiconductor device according to claim 1 , wherein the third connecting portion and the fourth connecting portion have inclined surfaces inclined with respect to the second direction and the third direction.

8. a plurality of gate electrode portions including the first gate electrode portion and the second gate electrode portion are arranged in the second direction on the first portion; 8. The semiconductor device according to claim 1, wherein a plurality of wiring portions including said first wiring portion are arranged in said second direction on said second portion.

9. 9. The semiconductor device according to claim 8, wherein when viewed from the third direction, the plurality of gate electrode portions and the plurality of wiring portions are arranged alternately in the second direction.

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