Semiconductor device

Abstract

To provide a semiconductor device that can be miniaturized or highly integrated.SOLUTION: A cell 600 included in a memory device includes a transistor 300A, a transistor 200A, and a capacitance 100A, and one memory cell 600A is formed. The transistor 300A includes a semiconductor layer 301 and an oxide 230 of the transistor 200A. The transistor 300A includes a conductor 316A functioning as a gate, and a conductor 316A is electrically connected to one of a source and a drain of the transistor 200A. One or a plurality of steps of conductors 208A are provided over the conductor 316A and electrically connected to the conductor 316A. A top surface of a conductor 208A is connected to a bottom surface of the one of a source and a drain of the transistor 200A, and thus, the conductor 316A is electrically connected to the one of the source and the drain of the transistor 200A.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a memory device, a processor, and a semiconductor device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device, a processor, and a semiconductor device. The present invention relates to semiconductor wafers, modules, and electronic devices.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, semiconductor circuits, and The electronic equipment may include semiconductor devices. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, especially in the areas of LSI, CPU, GPU, and other processors. The processor is separated from the semiconductor wafer. A semiconductor integrated circuit (at least a transistor and a memory) is included, and electrodes serving as connection terminals are It is a collection of formed semiconductor elements.

[0005] LSI, processors such as CPU and GPU, and semiconductor circuits (IC chips) such as memory A chip is mounted on a circuit board, such as a printed wiring board, and is used in a variety of devices, including computers. It is used as one of the components in electronic devices.

[0006] In addition, a transistor is constructed using a semiconductor thin film formed on a substrate having an insulating surface. The transistor is used in integrated circuits (ICs) and image display devices (simply called displays). It is widely used in electronic devices such as transistors. Silicon-based semiconductor materials are widely known as usable semiconductor thin films, but other materials and Oxide semiconductors have been attracting attention as a solution.

[0007] Furthermore, a transistor including an oxide semiconductor has a very low leakage current in a non-conducting state. For example, the leakage current of a transistor using an oxide semiconductor is known to be small. By utilizing the low charge retention characteristics, a memory that can retain charge for a long time has been disclosed (Patent (See Reference 1.) On the other hand, in recent years, with the increase in the amount of data handled, there has been a demand for larger storage capacities. In addition, there is a demand for semiconductor devices with a large memory capacity per unit area. Placement is required.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, transistors and other components have been integrated at high density. There is also a growing demand for improved productivity of semiconductor devices, including integrated circuits. In addition, the semiconductor device described above is expected to be used for artificial intelligence (AI). It is applicable to AI systems and is therefore preferred. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-256813 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. One embodiment of the present invention is to provide a semiconductor device with a reduced memory cell size. An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. One object of one embodiment of the present invention is to provide a semiconductor device having favorable frequency characteristics. One object of one embodiment of the present invention is to provide a semiconductor device with high reliability. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity. One of the challenges is to:

[0011] One embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. One object of one embodiment of the present invention is to provide a semiconductor device with a high data writing speed. One object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. One object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device. This is one of the challenges.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a capacitor, and a first conductor. the first transistor has a first gate electrode, a second gate electrode, and a third gate electrode; The first transistor has a first gate, a second source, and a second drain. a third gate on the gate, a first low resistance region, and a second low resistance region; and an oxide sandwiched between the second gate and the third gate, and the capacitor is a second electrode on the first electrode, an insulator sandwiched between the first electrode and the second electrode, The first low resistance region overlaps with the first gate, and the first conductor is electrically connected to the first gate. The first conductor is connected to the bottom surface of the first low resistance region, and the capacitance is The first electrode is electrically connected to the first low resistance region, and the second conductor is connected to the drain. The third conductor is electrically connected to the second conductor, and the third conductor overlaps the second conductor. and a semiconductor device connected to the side of the second low resistance region.

[0014] One aspect of the present invention is a semiconductor device comprising a first transistor and a second transistor on the first transistor. a third transistor, a fourth transistor on the third transistor, and a first capacitor a quantity, a second capacitance, a first conductor, a second conductor, a third conductor, and a fourth conductor; and the first transistor has a first gate, a first source, and a first drain. the second transistor has a second gate and a third gate on the second gate; , a first low resistance region, and a second low resistance region, and a second gate and a third gate a third transistor having a fourth gate and an oxide sandwiched between the second source and the fourth gate; the fourth transistor has a fifth gate and a second drain; a sixth gate on the gate, a second low resistance region, and a third low resistance region; and an oxide sandwiched between the gate and the sixth gate, and the first capacitor has a first electrode and a second electrode on the first electrode, the first electrode, and a first insulator sandwiched between the second electrode; The second capacitor has a third electrode and a fourth electrode on the third electrode, and a third electrode and a fourth electrode on the third electrode. a second insulator sandwiched between the electrodes, and the first low resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate, and the first conductor is connected to the first low resistance region. The first capacitor is connected to the bottom surface of the first low resistance region, and the first electrode is connected to the first low resistance region. the third low-resistivity region overlaps with the fourth gate, and the fourth conductive layer , electrically connected to the fourth gate, and the fourth conductor connected to a bottom surface of the third low resistance region; The second capacitor overlaps with the third low resistance region, and the third electrode is electrically connected to the third low resistance region. the second conductor is electrically connected to the first drain and the second drain; The third conductor overlaps the second conductor, and the third conductor overlaps the second conductor, the second low resistance region. The semiconductor device is connected to the side of the semiconductor region.

[0015] In the above, the first drain and the second drain are provided in the fourth low resistance region. It is preferable that

[0016] In the above, the second gate and the first transistor are connected in the channel length direction of the first transistor. The distance between the second gate and the third gate is preferably equal to or less than half the width of the first gate.

[0017] In the above, in the channel length direction of the first transistor, a second gate and a second The distance between the first gate and the second conductor is preferably equal to or less than half the width of the first gate.

[0018] In the above, the semiconductor device further includes a first insulator and a second insulator, the insulator covers the first transistor, the second insulator contacts a side surface of the second gate, The second insulator preferably has a different composition than the first insulator.

[0019] In the above, the semiconductor device further includes a third insulator and a fourth insulator, the insulator covers the second transistor, the fourth insulator contacts a side surface of the third gate, The fourth insulator preferably has a different composition from the third insulator. [Effects of the Invention]

[0020] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having a reduced memory cell size can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having favorable frequency characteristics can be provided. According to the present invention, a semiconductor device with good reliability can be provided. According to this aspect, a semiconductor device with high productivity can be provided.

[0021] Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with a high data writing speed can be provided. It is possible to provide a semiconductor device with high flexibility. A semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided. .

[0022] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0023] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 7] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 10] FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a block diagram showing an example of the configuration of an AI system according to one embodiment of the present invention. [Figure 14] FIG. 1 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention. [Figure 15] 1 is a schematic perspective view showing an example of the configuration of an IC incorporating an AI system according to one embodiment of the present invention. [Figure 16] 1A and 1B illustrate configuration examples of an electronic device and a system according to one embodiment of the present invention. [Figure 17] 1A and 1B are diagrams illustrating exemplary configurations of a parallel computer, a computer, and a PC card according to an embodiment of the present invention. [Figure 18] FIG. 1 illustrates an example of the configuration of a system according to one embodiment of the present invention. [Figure 19] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be practiced in various different ways without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0025] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in the drawings as a schematic illustration, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this may not be reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals between different drawings. In addition, when referring to similar functions, In such cases, the hatch pattern may be the same and no particular reference numeral may be assigned.

[0026] In addition, the invention can be easily understood, especially in top views (also called "plan views") and perspective views. In order to simplify the description, some components may be omitted. The information may be omitted.

[0027] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" The term "the" or "third" can be used interchangeably in the description. The ordinal numbers listed may not match the ordinal numbers used to identify an aspect of the present invention. There may be cases where this is the case.

[0028] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in describing the same with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those described above, and can be rephrased appropriately depending on the situation.

[0029] For example, in this specification, it is explicitly stated that X and Y are connected. In this case, X and Y are directly connected, and X and Y are electrically connected. The case where X and Y are functionally connected is disclosed in the present specification. Therefore, it is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text may not be included in the drawings or text. It shall be.

[0030] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, layer, etc.).

[0031] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements that function as When a diode, display element, light-emitting element, load, etc. is not connected between X and Y, and elements (e.g., switches, transistors, capacitors) that allow electrical connection between X and Y. without using any capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. In this case, X and Y are connected.

[0032] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state) and allows current to flow. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, X This includes the case where Y is directly connected to Y.

[0033] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (synthesis circuit, memory circuit, control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If a signal is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. This includes the case where Y is electrically connected.

[0034] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain drain region, or drain electrode) and source (source terminal, source region, or source electrode) A region where a channel is formed is provided between the electrodes. It is possible to pass a current between the source and the drain. The region where a channel is formed refers to a region where a current mainly flows.

[0035] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0036] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode (the part of the semiconductor through which current flows) is The source (source region or source This refers to the distance between the source electrode and the drain (drain region or drain electrode). In a single transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. In this specification, the channel length is defined as any one of the values ​​in the region where the channel is formed, It can be the maximum, minimum, or average value.

[0037] The channel width is, for example, the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the electrode (the area where current flows) is called the channel. The length of the part where the source and drain face each other in the region where the source and drain are connected. In this transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. In this specification, the channel width is any one value, the maximum value, in the region where the channel is formed. The maximum, minimum, or average value.

[0038] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter also referred to as the "effective channel width") of the transistor in a top view is The channel width indicated by the For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width becomes The effect of this may become larger than the channel width of the In a transistor in which the gate electrode covers the side surface of the semiconductor, In this case, the ratio of the channel formation region may be larger than the apparent channel width. , the effective channel width becomes larger.

[0039] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, the effective Channel width is difficult to measure accurately.

[0040] Therefore, in this specification, the apparent channel width is referred to as the "enclosed channel width (SCW:S In addition, in this specification, In this document, when simply referring to channel width, it refers to the enclosed channel width or apparent channel width. In this specification, when simply referred to as a channel width, It may refer to the effective channel width. Note that the channel length, channel width, and effective channel The channel width, apparent channel width, and enclosed channel width can be determined by analyzing cross-sectional TEM images. The value can be determined by, for example,

[0041] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. The DOS (Density of States) of the semiconductor increases and the crystallinity decreases. When the semiconductor is an oxide semiconductor, the semiconductor properties may be The impurities to be changed include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 14 elements. These include elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as: Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of semiconductors, water may also function as an impurity. In some cases, oxygen vacancies may be formed due to the inclusion of impurities. In this case, impurities that change the properties of semiconductors include, for example, oxygen and Group 1 elements excluding hydrogen. , Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0042] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. For example, the oxygen content is preferably 55 atomic % or more and 65 atomic % or less. , nitrogen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen The concentration range of 0.1 atomic % to 10 atomic % is also referred to as nitride oxide. The silicon film has a composition in which the nitrogen content is higher than the oxygen content. Preferably, nitrogen is 55 atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, Silicon concentration is 25 atomic % or more and 35 atomic % or less, and hydrogen concentration is 0.1 atomic % or more and 10 atomic % or less It refers to what is included in the range.

[0043] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0044] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be replaced with "semiconductor film" or "semiconductor layer." can.

[0045] Furthermore, unless otherwise specified, the transistors described in this specification and the like are field-effect transistors. In addition, unless otherwise specified, the transistors shown in this specification and the like are n Therefore, the threshold voltage (also called "Vth") is Unless otherwise specified, it shall be greater than 0V.

[0046] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes cases where the angle is between -5 degrees and 5 degrees. "Almost parallel" means that the two lines are arranged at an angle of between -30 degrees and 30 degrees. "Perpendicular" means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it includes the case where the angle is between 85 degrees and 95 degrees. " refers to a state in which two straight lines are arranged at an angle of between 60 degrees and 120 degrees.

[0047] In this specification, the term "barrier film" refers to a film that prevents impurities such as hydrogen and oxygen from permeating. If the barrier film has conductivity, it is called a conductive barrier film. It is sometimes called.

[0048] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the semiconductor layer of a transistor, Such metal oxides are sometimes called oxide semiconductors. When referring to a transistor, it refers to a transistor having an oxide or oxide semiconductor. This can be rephrased as ta.

[0049] In this specification, normally off means that no potential is applied to the gate, or The current per 1 μm of channel width that flows through a transistor when a ground potential is applied to the gate is 1×10 at room temperature -20 A or less, 1 x 10 at 85°C -18 A or below, or 1 x 10 at 125°C -16 This means that it is A or below.

[0050] (Embodiment 1) An example of a semiconductor device that functions as a memory device according to one embodiment of the present invention will be described below. 1 to 3 will be used to explain this.

[0051] FIG. 1A is a top view of a cell 600 that constitutes a memory device. 1(B) is a cross-sectional view of the cell 600. Here, FIG. 1(B) is a cross-sectional view of the cell 600 taken along a line A1-A2 in FIG. 1(A). 1 is a cross-sectional view of the area indicated by the dashed line, showing the transistor 200 (transistor 200A and transistor 2 is also a cross-sectional view of the transistor 200B in the channel length direction. 1(A) is a diagram showing an equivalent circuit of the filter 600. In the top view of FIG. 1(A), In the figure, some elements are omitted.

[0052] The cell 600 constituting the memory device includes a transistor 300A, a transistor 300B, a transistor 300C, a transistor 300D, a transistor 300E, a transistor 300F, a transistor 300G, a transistor 300H ... Transistor 200A on transistor 300A, transistor 300B on transistor 300B 200B, capacitance 100A, capacitance 100B. 200A and a capacitance of 100A constitute one memory cell 600A, and transistor 300 B, a transistor 200B, and a capacitor 100B constitute one memory cell 600B. That is, the cell 600 has two memory cells. The details will be described later.

[0053] The transistor 300A and the transistor 300B have a common semiconductor layer 301. , transistor 200A, and transistor 200B have a common oxide 230 .

[0054] The transistor 300A has a conductor 316A that functions as a gate. is electrically connected to one of the source and drain of the transistor 200A. The transistor 300B has a conductor 316B that functions as a gate. The source and drain of the transistor 200B are electrically connected to each other.

[0055] On the conductor 316A, one or more stages of the conductor 208A are provided, and the conductor 31 The top surface of the conductor 208A is electrically connected to the source and The conductor 316A is connected to one bottom surface of the drain of the transistor 200A. One of the source and drain is electrically connected. A stage or stages of conductor 208B are provided and electrically connect with conductor 316B. The top surface of the conductive body 208B is in contact with the bottom surface of one of the source and drain of the transistor 200B. By connecting the conductor 316B to one of the source and drain of the transistor 200B, are electrically connected.

[0056] The source of the transistor 300A and the source of the transistor 300B are respectively It is electrically connected to the wiring SL1 and the wiring SL2.

[0057] The drain of transistor 300A is shared with the drain of transistor 300B. The other of the source and drain of the transistor 200A is connected to the source of the transistor 200B. The transistor 300A and the transistor 300B share the same source and drain. The drain of transistor 200B is connected to the source and drain of transistor 200A and transistor 200B. The other of the drains is electrically connected to the wiring BL via a conductor. In this embodiment, the drains of the transistors 300A and 300B are connected to The conductor 209 is electrically connected to the upper surface of the conductor 209. The electrically connecting conductor 240 is provided in an opening provided through the oxide 230. 230. However, the present invention does not include this. The upper surface of the conductor 209 and the bottom surface of the oxide 230 are connected, and the conductor 240 is connected to the oxide It may be electrically connected to the top surface of 230.

[0058] One of the source and drain of the transistor 200A is electrically connected to the capacitor 100A. In addition, one of the source and drain of the transistor 200B is connected to a capacitor 100B. There are no particular restrictions on the shape of the capacitance 100A and capacitance 100B. One of the source and drain of the transistor 200A and the transistor 200B is connected to The capacitors 100A and 100B are first electrodes, and a dielectric layer is disposed above the first electrodes. A so-called flat-plate capacitor may be provided in which a second electrode is provided via an insulator that functions as a conductor. Alternatively, an opening may be made in the insulator covering the transistor 200A and the transistor 200B. a first electrode is provided on the bottom and side of the opening, and a dielectric is provided inside the first electrode; A functional insulator is provided, and a second electrode is provided inside the insulator, which is a so-called cylindrical capacitor 1. 00A and capacitance 100B may be provided.

[0059] Transistor 200A includes a first conductor 260A that serves as a gate, and a second conductor 260B that serves as a gate. The transistor 200B has a conductor 205A that functions as a gate. Conductor 260B acts as a gate, and conductor 205 acts as a second gate. At least the side and top surfaces of the conductor 260A and the conductor 260B have An insulator 275 is provided to act as an etching stopper. This acts as an etching stopper when forming an opening for providing the insulating body 240. The edge 275 is an insulator (side) that protects the sides of the conductor 260A and the conductor 260B. and a protective wall (sometimes called a wall) for protecting the upper surfaces of the conductor 260A and the conductor 260B. The insulator 275 may be made of a material different from the insulator in which the opening is formed. or a different composition, which acts as an etching stopper when the opening is formed. By providing an etching stopper, the mask used to form the opening can be aligned. Even if misalignment occurs and the opening overlaps with the conductor 260A or conductor 260B, The conductors 260A and 260B are covered with an etching stopper. These are not exposed inside the opening. This can prevent short circuits caused by contact of the conductor 260B.

[0060] In addition, at least the side and top surfaces of the conductor 205A and the conductor 205B are provided with edges. An insulator 207 is provided to function as a conductor stopper. It functions as an etching stopper when forming an opening for providing the insulating layer 09. 207 is an insulator (side wall) that protects the sides of the conductor 205A and the conductor 205B. and an insulating layer that protects the top surfaces of the conductors 205A and 205B. Alternatively, the insulator 207 may be made of a conductor 205A and a conductive material. Insulators protecting the sides and bottom of conductor 205B, conductor 205A, and conductor 205 The insulator 207 may be made of an insulator that protects the upper surface of B. The insulator 207 has an opening formed therein. The opening is made of a material or composition different from that of the insulator, and is etched away when the opening is formed. It functions as a stopper. By providing an etching stopper, it is possible to form an opening. The mask is misaligned, and the opening overlaps the conductor 205A or the conductor 205B. Even if the conductor 205A and the conductor 205B are covered with the etching stopper, Therefore, the conductor 209 and the conductor This can prevent short circuits caused by contact between the conductive body 205A and the conductive body 205B.

[0061] Next, the cell size of the memory cell 600A will be described. The cell size of the memory cell 600B will be described below, but the same applies to the cell size of the memory cell 600B. In this embodiment, the minimum feature size (F) of the memory cell 600A is The width of the conductor 316A in the channel length direction is 300A. The width or diameter of the conductor 240, the conductor 208, and the wiring SL1 is represented by F. The distance (space) between the conductor 316A and the wiring SL1 is also determined in consideration of alignment accuracy. On the other hand, since the conductor 205A is provided with an etching stopper, The space between the conductor 205A and the conductor 208, and the space between the conductor 205A and the conductor 209 The thickness does not necessarily have to be F, and can be smaller than F. Specifically, the thickness of the conductor 205A and The space between the conductor 208 and the space between the conductors 205A and 209 are F 1 / 2, preferably less than F / 2, thereby reducing the cell size of the memory cell 600A. In addition, since the wiring BL is shared with the adjacent memory cells, Within the cell, the width of the conductor 209 and the conductor 240 is F / 2, preferably less than F / 2. In addition, since the wiring SL is shared with the adjacent memory cells, In this embodiment, the width of the wiring SL is F / 2, preferably less than F / 2. In the memory cell 600A shown in FIG. 1, the width of the transistor 300A in the channel length direction is 5F. This becomes:

[0062] As shown in FIG. 1A, the channel width of the transistor 300A and the The channel width of the transistor 200A is F, and the channel width of the transistor 300A adjacent to the transistor 200A in the channel width direction is The distance between adjacent transistors 200A in the channel width direction is F. The width of the cell 600A in the channel width direction of the transistor 300A is 2F. That is, the cell size of the memory cell 600A is 5F × 2F = 10F 2 Note that The cell size of the rechargeable battery 600B can be designed in the same way, and the value is 10F 2 In this embodiment, the minimum processing dimension is the width of the conductor 316. The invention is not limited to this. The width of the conductor 205A, the width of the conductor 260A, the width of the conductor 209, Alternatively, the width of the conductor 240 may be set as the minimum processing dimension.

[0063] FIG. 2 is a circuit diagram showing a cell 600 according to this embodiment. The cell 600 is a memory cell 6 The cell 600 has a memory cell 600A and a memory cell 600B. The wiring WL (WL1, WL2), wiring BL, wiring CNODE (CNODE1, CN The memory cell 600A has a transistor (S1) and a wiring SL (SL1, SL2). The memory cell 600B has a capacitor 300A, a transistor 200A, and a capacitor 100A. The memory cell has a transistor 300B, a transistor 200B, and a capacitor 100B. The memory cell 600A and the memory cell 600B share the wiring BL. , transistor 300A, and transistor 300B are p-channel transistors. However, the present invention is not limited to this. 300B may be an n-channel transistor.

[0064] The gate of transistor 300A is connected to one of the source and drain of transistor 200A. The gate of the transistor 300B is electrically connected to one of the electrodes of the capacitor 100A. The gate is connected to one of the source and drain of the transistor 200B and the electrode of the capacitor 100B. and electrically connect it to one of the terminals.

[0065] The source of the transistor 300A is electrically connected to the wiring SL1. The source of the transistor 300B is electrically connected to the wiring SL2. , the drain of transistor 300B, the source and drain of transistor 200A, and The other of the source and drain of the transistor 200B is electrically connected to the wiring BL. Connect.

[0066] The gate of the transistor 200A is electrically connected to the wiring WL1. The gate of the transistor 200B is electrically connected to the wiring WL2. The transistors 200A and 200B each have a back gate BG. The gate of the transistor 200B is referred to as the first gate or the top gate. In addition, the back gate B of the transistor 200A and the transistor 200B The back gate BG may be referred to as a second gate. A potential may be applied to control the threshold voltage of the transistor 200B and the transistor 200C. In the latter case, for each transistor, the same potential may be applied to the first gate of the transistor. It is preferable that the first gate and the second gate are electrically connected.

[0067] The other electrode of the capacitance 100A is electrically connected to CNODE1, and the other electrode of the capacitance 100B is The other is electrically connected to CNODE2.

[0068] The memory device shown in FIGS. 1 and 2 is configured so that the potential of the gate of the transistor 300 can be maintained. This property makes it possible to write, store, and read information, as shown below. be.

[0069] The writing and retention of information will be explained. First, the potential of the wiring WL1 is set to 0V by the transistor. This sets the potential at which transistor 200A is in a conducting state, thereby making transistor 200A in a conducting state. As a result, the potential of the wiring BL is applied to the gate of the transistor 300A and the electrode of the capacitor 100A. That is, the voltage of the transistor 300A is supplied to a node SN electrically connected to one of the A predetermined charge is applied to the gate (write). Here, two different potential levels are applied. The charge that gives the low level charge and the high level charge are given. After that, the potential of the wiring WL1 is set to a value that the transistor 200A is in a non-conducting state. By setting the potential at node SN to The charge is retained (retention).

[0070] When the off-state current of the transistor 200 is small, the charge of the node SN is maintained for a long period of time. It will be held.

[0071] Next, reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring SL1, In this state, when an appropriate potential (read potential) is applied to the wiring CNODE1, the wiring BL The potential depends on the amount of charge held in SN. If a high level charge is applied to the gate of transistor 300A, The apparent threshold voltage V th_H applies a low level voltage to the gate of transistor 300A. The apparent threshold voltage V under load th_L This is because it will be higher. The apparent threshold voltage is the wiring required to turn on the transistor 300A. Therefore, the potential of the wiring CNODE1 is V th_ H and V th_L By setting the potential V0 between For example, in a write operation, if a high level charge is applied to the node SN, When the potential of the wiring CNODE1 is V0( <V th_H ), then transistor 300 On the other hand, if a low-level charge is applied to node SN, The potential of the wiring CNODE1 is V0 (> V th_L ), transistor 300A is not Therefore, by determining the potential of the wiring BL, the node SN is held The information stored in the memory can be read.

[0072] When memory cells are arranged in an array, the information of a desired memory cell is read out. For example, if the memory cell array is a NOR type, the information By making the transistor 300 of the memory cell from which information is not to be read non-conductive, the desired memory cell In this case, the charge applied to node SN is The potential at which the transistor 300 is in a non-conductive state regardless of the th_H Higher A potential may be applied to the wiring CNODE connected to the memory cell from which information is not read. For example, if the memory cell array is a NAND type, the memory By turning on the transistor 300 of the cell, only the information of the desired memory cell can be read. In this case, the charge applied to the node SN is not related to the transistor 300. is in a conducting state, that is, V th_L Lower potential does not read information It is sufficient to provide it to the wiring CNODE connected to the memory cell.

[0073] FIG. 3 shows a more specific structure of the cell 600. In the cell 600, the memory The cell 600A and the memory cell 600B are arranged on the left and right sides of the conductor 209 and the conductor 240. The memory cells 600A and 600B have a symmetrical structure. Therefore, the symbols and descriptions of each component are the same. This applies not only to memory cell 600A but also to memory cell 600B.

[0074] The transistor 300 (transistor 300A, transistor 300B) is a semiconductor layer 3 301, an insulator 315 on the semiconductor layer 301, and a conductor 316 on the insulator 315. Note that a part of a semiconductor substrate may be used as the semiconductor layer 301, or a semiconductor layer provided on an insulator may be used as the semiconductor layer 301. The semiconductor layer 301 may be formed by the conductor 316. The insulator 315 functions as the gate of the transistor 300. The source of transistor 300A is electrically connected to SL1, and the transistor The source of transistor 300B is electrically connected to SL2. The insulator 216 is not limited to a single layer, but may have a laminated structure of two or more layers. The insulator 216 may include a transistor 200 (transistor 200A, transistor A conductor 205 is embedded in the gate electrode 200 to function as a second gate of the gate electrode 200B. The side and bottom surfaces of the conductor 205 are provided with an insulator 207a. An insulator 207b is provided on the top surface of the conductor 205, and the conductor 205 is provided on the top surface of the insulator 207a. The periphery is covered with the insulator 207a and the insulator 207b. 07b is made of a different material or composition from the insulator 216 and is heated by the insulator 216. It functions as an etching stopper during etching.

[0075] An insulator 224 is provided on the insulator 216, the insulator 207a, and the insulator 207b. The insulator 224 functions as a second gate insulator. The insulator 224 is limited to a single layer. For example, a silicon oxynitride film and a silicon oxide film may be used. Alternatively, the silicon nitride film may have a three-layer structure including a laminate of silicon nitride and silicon oxynitride.

[0076] The conductor 208 is embedded in the insulator 224 and the insulator 216. , electrically connected to the conductor 316. Also, the insulator 224, the insulator 216, and the insulator The conductor 209 is embedded in the conductive layer 315. The conductor 209 is shared by the transistor 300A and the transistor 300B. The drain of the transistor 300A is electrically connected to the drain of the transistor 300B. In forming the conductor 208 and the conductor 209, the insulator 224 and the insulator 21 6, and when forming an opening in the insulator 315, alignment is performed on a mask for forming the opening. Even if misalignment occurs and the opening overlaps the conductor 205, the conductor 205 remains in the etching state. Since these are covered by the conductor, they are not exposed inside the opening. 208 or conductor 209 and conductor 205, which may cause a short circuit. .

[0077] An oxide 230 is provided on the insulator 224, the conductor 208, and the conductor 209. Conductor 208 and conductor 209 connect to the bottom of oxide 230, and conductor 316 Electrically connected to one of the source and drain of the transistor 200 via a conductor 208 In addition, the drain of the transistor 300A and the drain of the transistor 300B is electrically connected to the other of the source and drain of the transistor 200 via a conductor 209. Connect to.

[0078] Conductors 242 (conductors 242a, 242b, and 242c) are deposited on the oxide 230. 42c) is provided. The conductor 242a is connected to the source electrode of the transistor 200A, and Conductor 242c serves as one of the drain electrodes of transistor 200B. The conductor 242b serves as one of the input and drain electrodes of the transistor 200A. the other of the source electrode and drain electrode of transistor 200B, and the source electrode of transistor 200C. , and serves as the other of the drain electrodes.

[0079] In addition, the conductors 242a, 242b, and 242c are in contact with the oxide 230. As a result, a region 243 (region 243a, region 243b) that functions as a low resistance region is formed in the oxide 230. The conductive material 242 may have a shape similar to that of the conductive material 242. During or after the formation, the conductor 242 extracts oxygen contained in the oxide 230, and the oxide To form oxygen vacancies in the substance 230 and to remove hydrogen, water, halogens, and metal elements from the oxide. In this case, the region 243a is , which serves as one of the source and drain regions of transistor 200A, and region 2 43c serves as one of the source and drain regions of transistor 200B. The region 243b is the other of the source and drain regions of the transistor 200A. and serves as the other of the source and drain regions of transistor 200B. In addition, the conductor 208 and the conductor 209 are formed on the oxide 230. The low-resistance region is electrically connected to the insulating film.

[0080] On the oxide 230, between the conductor 242a and the conductor 242b and between the conductor 242 Between b and the conductor 242c, a conductor 260 is provided via an insulator 250. 250 serves as the first gate insulator of transistor 200, and conductor 260 serves as the first gate insulator of transistor 200. It functions as the first gate electrode of the transistor 200 .

[0081] In FIG. 3, the insulator 250 is designed to cover not only the bottom surface of the conductor 260 but also the side surface. The insulator 250 is made of at least the oxide 230 and On the other hand, the conductor 260 may be provided between the conductor 242 and the short If there is a risk of overheating, an insulator 250 is also provided between the conductor 242 and the conductor 260. In addition, a parasitic capacitance occurs between the conductor 242 and the conductor 260, If the operating frequency of the transistor 200 is adversely affected, the making the insulator 250 thicker than the insulator 250 between the oxide 230 and the conductor 260; or It is preferable to use a material with a large dielectric constant. The insulator 250 between the conductive material 260 and the insulating material 250 may have a laminated structure.

[0082] An insulator 273 is provided on the side wall of the conductor 260 via an insulator 250. An insulator 270 is provided on the conductive body 260 and the insulator 250. The insulator 273 is The insulator 273 and the insulator 270 are sometimes called sidewalls. The insulating material 280 covering the sinter 200 is made of a different material or composition from the insulating material 280. It acts as an etching stopper when processing 0.

[0083] The conductor 110 is provided so as to be embedded in the insulator 280. The conductor 110 is a capacitor. It functions as one of the electrodes of 100 (capacity 100A, capacity 100B). The conductor 110, which functions as one of the poles, is electrically connected to the conductor 242a, and the capacitance 100 The conductor 110, which functions as one of the electrodes of B, is electrically connected to the conductor 242b. In forming the conductor 110, when forming an opening in the insulator 280, Even if the mask is misaligned and the opening overlaps the conductor 260, the conductor 260 is covered by the etching stopper, so they are exposed inside the opening. Therefore, it is possible to prevent a short circuit caused by contact between the conductor 110 and the conductor 260. do.

[0084] The insulator 130 is provided to cover the insulator 280 and the conductor 110. 130 is provided along the inside of the conductor 110 and functions as a dielectric of the capacitor 100 .

[0085] The conductor 120 is provided on the insulator 130. The conductor 120 is provided on the inside of the insulator 130. The insulator 130 is provided along the conductor 1 and functions as the other electrode of the capacitor 100. 10 and a conductor 120 to form a capacitor 100.

[0086] An insulator 150 is provided to cover the capacitor 100. The conductor 240 is provided so as to be embedded in the edge 280. 40 is provided to penetrate the conductor 242 and the oxide 230, and and the side surface of the region 243b of the oxide 230. This is not limited to this.

[0087] The conductor 240 is only required to be electrically connected to at least the conductor 209, and the conductor 242b , and may be electrically connected to the conductor 209 via the region 243b. The body 240 is provided so as to penetrate the conductor 242b and is connected to the upper surface of the region 243b. Good too.

[0088] When the transistor 200 is viewed from the channel width direction, the conductor 240 242b and / or oxide 230, and the conductor 209 In this case, a wire may be inserted through the conductor 242 and / or the oxide 230. There is no need to form such an opening.

[0089] In forming the conductor 240, the insulators 150, 130, and 28 When forming an opening at 0, misalignment occurs in the mask used to form the opening, causing the opening and Even if the conductor 260 overlaps, the conductor 260 is covered by the etching stopper. Therefore, they are not exposed inside the opening. This prevents short circuits caused by contact with 0.

[0090] Wiring BL is provided on the insulator 150 and the conductor 240, and electrically connects the conductor 240 to the wiring BL. The wiring BL is connected to the transistor via the conductor 240 and the conductor 209. 300 and the other of the source and drain of transistor 200. Connect.

[0091] The memory cells 600A and 600B of the cell 600 shown in FIG. , and the conductor 260 are covered with the etching stopper. Distance (space) between 205 and conductor 208, space between conductor 205 and conductor 209 , the space between the conductor 260 and the conductor 110, and the space between the conductor 260 and the conductor 240 For example, the distance can be set to F / 2, preferably F This allows the memory cell 600A and the memory cell 60 The width of the channel length direction of 0B can be designed to be 5F and the width of the channel width direction to be 2F. Size is 10F 2 In this embodiment, a memory cell having a minimum The width of the conductor 316 is used as the work dimension, but the present invention is not limited to this. The width of the conductor 260, the width of the conductor 209, or the width of the conductor 240 is set as the minimum processing dimension. Good too.

[0092] <Example of Cell 600 configuration> Next, a specific example of the configuration of the cell 600 will be described with reference to FIGS.

[0093] 4 to 9, the transistor 200a, the transistor 200b, the transistor 3 1. The transistor 300a, the transistor 300b, the capacitor 100a, and the capacitor 100b are respectively 3, the transistor 200A, the transistor 200B, and the transistor 300A. , transistor 300B, capacitor 100A, and capacitor 100B. 9, the components corresponding to those shown in FIGS. 1 to 3 are denoted by the same reference numerals. This may occur.

[0094] As described above, the transistors 200A and 200B and the transistor 30 0A and transistor 300B, and capacitors 100A and 100B are connected to conductor 2 The transistor 200b has a symmetrical configuration with respect to the conductor 240 and the conductor 240. Considering the description of the transistor 200a, the transistor 300b is The description of capacity 100b can be taken into consideration. The configurations of the transistor 200b, the transistor 300b, and the capacitor 100b will be described below. is omitted.

[0095] First, referring to FIG. 4, the transistor 200a (transistor 200b) corresponding to the upper configuration of the cell 600 is The configurations of the transistor 200b and the capacitor 100a (capacitor 100b) will be described. 1 is a cross-sectional view of a transistor 200a and a transistor 200b in the channel length direction. .

[0096] [Transistor 200a] As shown in FIG. 4, the transistor 200a is disposed on a substrate (not shown). An insulator 214, an insulator 216 disposed on the insulator 214, and a wiring board including the insulator 214 and the insulator 216. The conductor 205 is disposed so as to be embedded in the insulator 216, and the insulator 216 and the conductor 20 5, an insulator 220 disposed on the insulator 220, and an insulator 222 disposed on the insulator 220. An insulator 224 is disposed on the edge 222, and an insulator 222 is disposed on the insulator 224. 6, an oxide 230a disposed on the insulator 226, and a an oxide 230b, a conductor 242 disposed on the oxide 230b, an insulator 226, The oxide 230a, the oxide 230b, and the insulator 244 covering the conductor 242, and the insulator 244 44 and having an opening, and an insulator 280 disposed on the insulator 244 within the opening. The insulator 273, the top surface of the oxide 230b, the side surface of the conductor 242, and the insulator 2 The oxide 230c is provided in contact with the side of the insulating body 273 and one side of the insulating body 273. and an insulator 250 provided inside the oxide 230c. an insulator 272, a conductor 260a provided inside the insulator 272, and a conductor 260a and one side surface of the insulator 273. , the top surface of oxide 230c, the top surface of insulator 250, the top surface of insulator 272, and conductor 26 an insulator 270 provided in contact with the upper surface of the conductor 260a and the upper surface of the conductor 260b; Furthermore, an insulator 207a is disposed in contact with the bottom and side surfaces of the conductor 205, An insulator 207 b is disposed in contact with the upper surface of the insulator 205 .

[0097] In the transistor 200a, a region where a channel is formed (hereinafter, referred to as a channel forming region) ) and in the vicinity thereof, oxide 230a, oxide 230b, and Although a configuration in which three layers of oxide 230c are stacked is shown, the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or a laminated structure of four or more layers. In addition, in the transistor 200a, the conductor 260 (the conductor 260a and Although the conductive layer 260a and the conductive layer 260b are shown as a two-layer structure, the present invention is not limited to this. For example, the conductor 260 may have a single layer structure or a laminated structure of three or more layers.

[0098] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and The conductor 242b functions as a source electrode and a drain electrode, respectively. As shown, the conductor 260 is inserted through the opening in the insulator 280 and the conductors 242a and 242b. The insulating material 273 and the insulating material 250 are formed so as to be embedded in the sandwiched region. Here, the arrangement of the conductor 260, the conductor 242a, and the conductor 242b is such that the insulating The opening of the transistor 200a is selected in a self-aligned manner with respect to the opening of the transistor 280. This allows the gate electrode to be positioned between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 260 can be formed without providing a margin for alignment. This allows the area occupied by the transistor 200a to be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0099] Furthermore, a conductor 260 is formed in a self-aligned manner in the region between the conductors 242a and 242b. Therefore, the conductor 260 has an overlapping area with the conductor 242a or the conductor 242b. This prevents the formation of a gap between the conductor 260 and the conductors 242a and 242b. Therefore, the parasitic capacitance of the transistor 200a can be reduced. This improves the scanning speed and provides high frequency characteristics.

[0100] In addition, the insulators 270 and 273 function as etching stoppers. The side and top surfaces of the conductor 260 are covered with the insulators 270 and 273. Therefore, even if misalignment occurs when forming the opening in which the conductor 240 is to be embedded, Therefore, the conductor 240 and the conductor 260 can be prevented from being exposed to the opening. In this way, it is possible to prevent a short circuit caused by contact between the conductor 240 and the conductor 260. Since there is no need to provide a margin for aligning the conductor 260, the conductor 240 and the conductor 26 It can be placed with a small distance of 0.

[0101] The insulator 207 (insulator 207a and insulator 207b) serves as an etching stopper. The side and top surfaces of the conductor 205 are covered with an insulator 207. Therefore, even if misalignment occurs when forming an opening in which the conductor 209 is to be embedded, Therefore, the conductor 205 can be prevented from being exposed to the opening. Therefore, it is possible to prevent a short circuit caused by contact between the conductor 209 and the conductor 205. Since there is no need to provide a margin for aligning the conductor 205, the conductor 209 and the conductor 2 In this way, the occupied surface of the cell 600 can be reduced. This allows for a reduction in area, thereby enabling miniaturization and high integration of semiconductor devices.

[0102] The transistor 200a also includes an oxide 230 (oxide 230 a, oxide 230b, and oxide 230c) are metal oxides that function as oxide semiconductors. It is preferable to use a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0103] The transistor 200a having an oxide semiconductor in a channel formation region is in a non-conducting state. Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Semiconductors can be deposited using methods such as sputtering, making it possible to form highly integrated semiconductor devices. This can be used for the transistor 200a.

[0104] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. As the oxide 230, metal oxides such as In—Ga oxide, In Zn oxide may also be used.

[0105] Here, the oxide 230 becomes oxidized when impurities such as hydrogen, nitrogen, or metal elements are present. The carrier density may increase, resulting in a lower resistance. If the resistance decreases, the carrier density increases, which may result in a lower resistance.

[0106] The conductive layer 230 is provided on the oxide 230 and functions as a source electrode and a drain electrode. The conductor 242 (the conductor 242a and the conductor 242b) absorbs oxygen from the oxide 230. or when the oxide 230 contains impurities such as hydrogen, nitrogen, or metal elements. When the oxide 230 has a function of supplying the oxide, a low resistance region may be partially formed in the oxide 230. be.

[0107] As shown in FIG. 4, a conductor 242 is provided on the oxide 230 so as to be in contact with the oxide 230. 30, a region 243 (region 2 Region 243 is formed on the lower surface of oxide 230a. It is preferable that one of the regions 243a and 243b is formed up to the source. The region 243a functions as a drain region, and the other functions as a drain region. The region between the gate electrodes 3b functions as a channel forming region. The region 243b, which functions as the other of the source and drain regions of the transistor 200a, is It is shared with Transitor 200b.

[0108] Region 243 has a low oxygen concentration or contains impurities such as hydrogen, nitrogen, and metal elements. This increases the carrier concentration and reduces the resistance of the region 243. Compared to the channel formation region, this region has a high carrier density and low resistance. The formation region has a higher oxygen concentration or a lower impurity concentration than the region 243. This is a high resistance region with low silicon dioxide density.

[0109] When the region 243, which is a low resistance region, contains a metal element, the region 243 is an oxide 23 In addition to 0, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum Lithium, tungsten, hafnium, vanadium, niobium, manganese, magnesium, Zirconium, beryllium, indium, ruthenium, iridium, strontium, la It contains one or more metal elements selected from metal elements such as tungsten is preferred.

[0110] In addition, it may be difficult to clearly detect the boundaries of each region in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are It is not limited to gradual changes in each area, but also to continuous changes within each area (also known as gradation). In other words, the closer to the channel forming region, the more metal elements, etc. It is sufficient that the concentrations of impurity elements such as hydrogen and nitrogen are reduced.

[0111] To selectively reduce the resistance of the oxide 230, for example, aluminum is used as the conductor 242. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten Iron, hafnium, vanadium, niobium, manganese, magnesium, zirconium, Conductive materials such as sulphur, indium, ruthenium, iridium, strontium, and lanthanum It is preferable to use a material containing at least one of a metal element and an impurity that enhances the resistance. Alternatively, oxygen vacancies are formed in the oxide 230 during the formation of the conductive film that will become the conductor 242. Materials and film formation methods into which impurities such as elements or elements captured by oxygen vacancies are implanted For example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, etc. may be used as the element. Yellow, chlorine, and rare gases. Representative examples of rare gases include helium, neon, Examples include argon, krypton, and xenon.

[0112] Here, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region where the In addition, oxygen vacancies may be present in the region where a channel is formed in the oxide semiconductor. Therefore, the transistor tends to have normally-on characteristics. It is preferable that oxygen deficiency in the region is reduced as much as possible.

[0113] To prevent the transistor from becoming normally on, the oxide 230 and the adjacent insulator (e.g. For example, the insulator 250 may contain more oxygen than the stoichiometric composition (also known as excess oxygen). The oxygen contained in the insulator 250 diffuses into the oxide 230. , the oxygen vacancies in the oxide 230 can be reduced, and the transistor can be prevented from becoming normally on. can.

[0114] That is, oxygen contained in the insulator 250 diffuses into the channel forming region of the oxide 230. This reduces oxygen vacancies in the channel formation region of the oxide 230.

[0115] In addition, the oxide 230 and the insulator 250 have oxygen, which is more effective than the transistor 200a. In order to suppress outward diffusion, the insulators 222, 226, 244, and 2 It is preferable to provide an insulator 73, an insulator 272, an insulator 270, etc. Therefore, it is preferable to use a material that is difficult for oxygen to permeate. For example, aluminum and Oxides containing one of fluorine and silicon nitride can be used. These insulating films are made of materials that are difficult for impurities such as hydrogen, water, nitrogen, and metal elements to penetrate. By using such a material, it is possible to easily see the transistor 200a from the outside. This can prevent impurities from entering the resistor 200a.

[0116] In addition, oxide semiconductors can be deposited by sputtering or other methods, making them suitable for highly integrated semiconductors. It can be used in transistors that constitute semiconductor devices. Transistors using semiconductors have extremely low leakage current (off-state current) when they are off. Because of its small size, a semiconductor device with low power consumption can be provided.

[0117] As described above, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, the fluctuation of electrical characteristics is suppressed, and the electrical characteristics are stable, and reliability is improved. Therefore, it is possible to provide a semiconductor device having such a structure.

[0118] The following describes in detail the structure of a semiconductor device including a transistor 200a according to one embodiment of the present invention. This section explains the composition of the system.

[0119] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Preferably, the conductor 205 is embedded in the insulator 216 .

[0120] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also serve as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. By changing the voltage independently of the voltage applied to the transistor 200a, the Vth In particular, by applying a negative potential to the conductor 205, By increasing the Vth of the resistor 200a above 0V, it is possible to reduce the off-current. Therefore, applying a negative potential to the conductor 205 increases the current density of the conductor 205 compared to when no negative potential is applied. The drain current can be reduced when the potential applied to 60 is 0V.

[0121] The conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably formed larger than the channel forming region in the oxide 230. In particular, the conductor 205 is formed on the sides of the oxide 230a and the oxide 230b in the channel width direction. It is preferable that the oxide 230 extends beyond the surface. On the outer side of the side surface in the channel width direction, the conductor 205 and the conductor 260 are insulated from each other. Preferably, they overlap via their bodies.

[0122] With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, The electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected, and the oxide 2 The channel forming region formed in 30 can be covered.

[0123] That is, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductor 205, which functions as an electrode, electrically connects the channel forming region. In this specification, the first gate electrode and the second gate electrode The structure of a transistor in which the channel formation region is electrically surrounded by an electric field is called surro This is called an unded channel (S-channel) structure.

[0124] Although the transistor 200a has a single-layer structure of the conductor 205, The present invention is not limited to this. For example, the conductor 205 may have a laminated structure of two or more layers. When the structure has a laminated structure, ordinal numbers are assigned in the order of formation, For example, the conductor 205 may have a first conductive layer inside the opening of the insulator 216. The first conductive body may be formed on the inner side, and the second conductive body may be formed further inside.

[0125] Here, the first conductor of the conductor 205 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom ... Suppresses the diffusion of impurities such as elementary molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms It is preferable to use a conductive material that has the function of preventing the impurities from penetrating. or a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the above-mentioned properties (which is difficult for oxygen to permeate). In the above, the function of suppressing the diffusion of impurities or oxygen is to suppress the diffusion of the impurities or oxygen. The function is to suppress the spread of any one or all of the above.

[0126] The first conductor of the conductor 205 has a function of suppressing the diffusion of oxygen, and thus the conductor 2 The second conductor 05 can be prevented from being oxidized and its conductivity can be prevented from decreasing. Examples of conductive materials that have the function of suppressing scattering include tantalum, tantalum nitride, and tantalum fluoride. It is preferable to use ruthenium oxide or ruthenium oxide. In this case, the conductive material may be a single layer or a multilayer.

[0127] The second conductor of the conductor 205 is mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material that serves as a component. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0128] The insulator 214 prevents impurities such as water or hydrogen from mixing with the transistor 200a from the substrate side. Therefore, it is preferable that the insulator 2 functions as a barrier insulating film that suppresses the penetration of oxygen. 14 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, and a nitrogen oxide molecule (NO, N O, NO2, etc.), and copper atoms. It is preferable to use an insulating material that is difficult to permeate. It has the function of suppressing the diffusion of at least one of the elementary molecules (the oxygen mentioned above is difficult to pass through) It is preferable to use an insulating material.

[0129] For example, aluminum oxide or silicon nitride may be used as the insulator 214. This is preferable. Impurities such as hydrogen and water are transported from the substrate side to the transistor rather than the insulator 214. It is possible to suppress the diffusion of the oxides to the insulator 200a side. This can prevent the oxygen from diffusing toward the substrate side of the insulator 214.

[0130] In addition, the insulators 216, 280, and 281, which function as interlayer films, are insulating films. It is preferable that the dielectric constant is lower than that of the insulating layer 214. By using a material with a low dielectric constant as the interlayer film, Therefore, the parasitic capacitance occurring between the wirings can be reduced.

[0131] For example, the insulators 216, 280, and 281 may be silicon oxide, oxide, or the like. Silicon nitride, silicon oxide nitride, aluminum oxide, hafnium oxide, tantalum oxide , zirconium oxide, lead zirconate titanate (PZT), strontium titanate (Sr Insulators such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST) are used in single or multilayer configurations. Alternatively, these insulators may contain, for example, aluminum oxide or bismuth oxide. , germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, oxide Yttrium or zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator. It may also be used as such.

[0132] The insulator 207 includes an insulator 207a and an insulator 207b. An insulator 207a is disposed in contact with the side and bottom surfaces of the conductor 205, and an insulator 207b is disposed in contact with the top surface of the conductor 205. The insulator 207b is disposed on the insulating layer 207. The insulator 207 functions as an etching stopper. Insulator 207 includes hafnium, aluminum, gallium, yttrium, and zirconium. Sm, tungsten, titanium, tantalum, nickel, germanium, or magnesium A metal oxide containing one or more metals selected from the group consisting of fluorine, fluorine, arsenic ... Alternatively, silicon nitrides such as silicon nitride and silicon oxynitride can be used. .

[0133] In particular, it is an insulator containing oxides of either or both of aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use hafnium aluminate. Therefore, the heat resistance of the hafnium oxide film is higher than that of the hafnium oxide film. This is preferable because it is less likely to crystallize.

[0134] The insulators 207a and 207b are formed by the ALD method, which has good coating properties. It is preferable that

[0135] The insulators 220, 222, 224, 226, and 250 are It functions as a gate insulator.

[0136] The insulator 226 includes an oxide 230c, an insulator 250, an insulator 272, a conductor 260, etc. When forming an opening for forming the insulating material 244, the conductor 242a, and the conductive material When forming the body 242b, it functions as an etching stopper. In the case where the insulator 224 or the like functions as an etching stopper, the insulator 226 is not necessary. It is not necessarily necessary to set one up.

[0137] Here, when the insulator 226 is not provided and the oxide 230 and the insulator 224 are in contact with each other, the insulator 2 24, it is preferable to use an insulator that contains more oxygen than the oxygen that satisfies the stoichiometric composition. In other words, it is preferable that an excess oxygen region is formed in the insulator 224. By providing an insulator containing such excess oxygen in contact with the oxide 230, This can reduce oxygen vacancies and improve the reliability of the transistor 200a.

[0138] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 Above 1.0, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower, or The temperature is preferably in the range of 00°C or higher and 400°C or lower.

[0139] Also, if the insulator 224 has an excess oxygen region, the insulator 222 may be oxygen-rich (e.g., It has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the oxygen is permeable It is preferable that the temperature is high enough to prevent the temperature from passing through.

[0140] The insulators 222 and 226 have the function of suppressing the diffusion of oxygen and impurities. This is preferable because the oxygen contained in the oxide 230 does not diffuse to the insulator 220 side. In order to prevent the conductor 205 from reacting with the insulator 224 and the oxygen contained in the oxide 230, It is possible.

[0141] The insulators 222 and 226 may be made of, for example, aluminum oxide, hafnium oxide, or Tantalum, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3 (BST), It is preferable to use an insulator containing a k material in a single layer or a stacked layer. As integration increases, the gate insulator becomes thinner, causing problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, This makes it possible to reduce the gate potential during transistor operation while maintaining the film thickness.

[0142] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is less likely to permeate). a) Insulating materials containing oxides of one or both of aluminum and hafnium It is recommended to use an insulator containing oxides of either or both aluminum and hafnium. The oxides include aluminum oxide, hafnium oxide, aluminum and hafnium. It is preferable to use oxide (hafnium aluminate) or the like. When the insulators 222 and 226 are formed using the above-mentioned method, the insulators 222 and 226 are The release of oxygen from the oxide 230 and the transfer of water from the periphery of the transistor 200a to the oxide 230 It functions as a layer that suppresses the inclusion of impurities such as silicon.

[0143] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0144] Furthermore, it is preferable that the insulators 220 and 226 are thermally stable. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. Combining high-k material insulators with silicon oxide or silicon oxide-oxynitride As a result, it is possible to obtain the insulators 220 and 226 having a laminated structure that is thermally stable and has a high relative dielectric constant. can be done.

[0145] The insulators 220, 222, and 224 each have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, but may be made of different materials. It may have a laminated structure.

[0146] Insulator 214, insulator 216, insulator 220, insulator 222, insulator 224, and insulator The conductor 209 is disposed so as to be embedded in the opening formed in the body 226. As described above, the drain and the voltage of the transistor 300a and the transistor 300b are connected to each other. The upper surface of the conductor 209 is exposed from the insulator 226. , contacting one or both of the lower surface of the conductor 240 and the region 243b of the oxide 230.

[0147] The conductor 209 has a first conductor formed in contact with the inner wall of the opening, and a second conductor formed inside the first conductor. Preferably, two conductors are formed. The first conductor and the second conductor of the conductor 209 The conductive bodies are conductive bodies that can be used as the first conductive body and the second conductive body of the conductive body 205, respectively. By configuring the conductor 209 in this manner, the area below the insulator 214 can be reduced. The layer prevents impurities such as hydrogen and water from entering the oxide 230 through the conductor 209. It is possible.

[0148] Similarly to the conductor 209, the insulators 214, 216, 220, and 222 2, the insulator 224 and the conductor are embedded in the openings formed in the insulator 226. The conductor 208a is the gate of the transistor 300a, as described above. The upper surface of the conductor 208a is exposed from the insulator 226. The conductor 208a is in contact with the region 243a of the oxide 230. Do the same as in 209.

[0149] Here, the conductor 205 is covered with an insulator 207 that functions as an etching stopper. Therefore, the alignment of the conductor 205 with the conductor 209 and the conductor 205 with the conductor 208a is Therefore, it is not necessary to provide a margin for the distance between the conductor 205 and the conductor 209, and The distance between the conductor 205 and the conductor 208a can be reduced. This reduces the area occupied by the cell 600, and allows for miniaturization and high integration of the semiconductor device. Cut.

[0150] Similar to the conductor 208a, the conductor electrically connected to the gate of the transistor 300b An electrical current 208b may be provided.

[0151] In the transistor 200a, the conductor 209, the conductor 208a, and the conductor 208b In the above, a configuration in which a first conductor and a second conductor are stacked is shown, but in the present invention, The present invention is not limited to this. For example, the conductor 209, the conductor 208a, and the conductor 208b may be provided as a single layer or a laminated structure of three or more layers. When a layer structure is present, it may be distinguished by assigning an ordinal number in the order of formation.

[0152] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b. The oxide 230c is located on the surface of the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0153] The oxide 230 has a layered structure made of oxides with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the constituent elements are preferably The atomic ratio of element M in the oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. Oxide 230c is a metal oxide that can be used for oxide 230a or oxide 230b. Things can be used.

[0154] The energy of the conduction band minimum of the oxide 230a and the oxide 230c is It is preferable that the energy of the conduction band minimum of 0b is higher than that of the oxide. The electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b. It is preferable that

[0155] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, The energy level of the conduction band minimum changes gradually. The energy level of the conduction band minimum at the junction of the oxide 230c and the oxide 230b is It can also be said that the oxide layer is continuously changed or continuously bonded. At the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c In this case, the defect level density of the mixed layer formed in the step (b) is preferably reduced.

[0156] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c, By having a common element other than oxygen (as the main component), a mixed layer with low defect level density is formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a and oxide 230c, In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium nitride or the like may be used.

[0157] At this time, the main path of the carriers is the oxide 230b. By configuring 30c as described above, the interface between oxide 230a and oxide 230b and the oxide This can reduce the defect state density at the interface between the oxide 230b and the nitride 230c. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200a A high on-current can be obtained.

[0158] The oxide 230 also includes regions 243a and 243b that function as source and drain regions. and a region 243b, and a channel forming region sandwiched between the region 243a and the region 243b. By selecting the range of each area appropriately, it is possible to obtain the electrical characteristics that meet the requirements according to the circuit design. Therefore, a transistor having the desired characteristics can be easily provided.

[0159] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. For example, the metal oxide that will be the channel forming region has a band gap of 2 eV or more. It is preferable to use a material with a band gap of 2.5 eV or more. By using a thick metal oxide, the off-state current of a transistor can be reduced.

[0160] A transistor using an oxide semiconductor has extremely low leakage current in the off state. Therefore, a semiconductor device with low power consumption can be provided. Since the film can be formed using the above, it can be used for transistors that constitute highly integrated semiconductor devices. This can be done.

[0161] On the oxide 230b, a conductor 242 is formed, which functions as a source electrode and a drain electrode. (conductor 242a and conductor 242b) are provided. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tantalum Gusten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, Choose from beryllium, indium, ruthenium, iridium, strontium, and lanthanum. or an alloy containing the above-mentioned metal elements or a combination of the above-mentioned metal elements. For example, tantalum nitride, titanium nitride, tungsten nitride, etc. titanium and aluminum nitrides, tantalum and aluminum nitrides, and titanium oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing titanium. Nitrides containing tantalum and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel Oxides are conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen. Therefore, it is preferable.

[0162] By providing the conductor 242 so as to be in contact with the oxide 230, the oxygen concentration in the region 243 In addition, the metal contained in the conductor 242 and the oxide 23 may be mixed in the region 243. In such a case, a metal compound layer containing the component 0 may be formed. The carrier density increases, and the region 243 becomes a low resistance region.

[0163] Here, the region between the conductor 242a and the conductor 242b overlaps the opening of the insulator 280. As a result, the conductor 260 is formed between the conductor 242a and the conductor 242b. It can be arranged in a consistent manner.

[0164] In addition, a conductor serving as the other of the source electrode and the drain electrode of the transistor 200a 242b is shared with transistor 200b.

[0165] The insulator 244 is provided to cover the conductor 242 and prevents oxidation of the conductor 242. At this time, the insulator 244 covers the side surface of the oxide 230 and is in contact with the insulator 226. It may be provided.

[0166] The insulator 244 may be hafnium, aluminum, gallium, yttrium, or zirconium. Sm, tungsten, titanium, tantalum, nickel, germanium, or magnesium A metal oxide containing one or more metals selected from the group consisting of fluorine, fluorine, arsenic ...

[0167] In particular, it is an insulator containing oxides of either or both of aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use hafnium aluminate. Therefore, the heat resistance of the hafnium oxide film is higher than that of the hafnium oxide film. The insulator 244 is provided to suppress oxidation of the conductor 242. Therefore, the conductor 242 is made of an oxidation-resistant material or a material that does not lose conductivity even when it absorbs oxygen. If there is no significant decrease in the electrical conductivity, the insulator 244 is not necessarily provided. It may be designed appropriately depending on the transistor characteristics.

[0168] An insulator 273 is disposed on the insulator 244. The insulator 273 has a sidewall and The insulator 273 is made of hafnium, aluminum, gallium, yttrium, and yttrium. Thorium, zirconium, tungsten, titanium, tantalum, nickel, germanium, Alternatively, a metal oxide containing one or more selected from magnesium, etc. may be used. Alternatively, silicon nitride such as silicon nitride or silicon oxynitride may be used. It can be used.

[0169] In particular, it is an insulator containing oxides of either or both of aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use hafnium aluminate. Therefore, the heat resistance of the hafnium oxide film is higher than that of the hafnium oxide film. This is preferable because it is less likely to crystallize.

[0170] The oxide 230c is formed on the top surface of the oxide 230b, the side surface of the conductor 242, and the side surface of the insulator 244. , and is provided so as to contact the side surface of the insulator 273.

[0171] The insulator 250 functions as a gate insulator. It is preferable to place the insulator 250 in contact with the wall (top and side). It is preferable to form the insulating material from which the element is released. For example, In the DS analysis, the amount of oxygen released was 1.0 x 10 18 molecul es / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 That's all, Preferably 2.0 x 10 19 molecules / cm 3 or more, or 3.0 x 10 2 0molecules / cm 3 The oxide film is as described above. The surface temperature of the film is preferably in the range of 100°C or higher and 700°C or lower.

[0172] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0173] The insulator 250 is an insulator that releases oxygen when heated, and is placed on the top surface of the oxide 230c. By providing the oxide 230b in contact with the insulator 250, the oxide 230c passes through the oxide 230b. In addition, oxygen can be effectively supplied to the channel forming region of the insulator 224. In addition, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0174] In addition, in order to efficiently supply excess oxygen contained in the insulator 250 to the oxide 230, An insulator 272 may be provided between the edge 250 and the conductor 260. The insulator 272 is an insulating It is preferable to inhibit oxygen diffusion from the body 250. By providing the insulating material 250, the diffusion of excess oxygen from the insulating material 250 to the conductor 260 is suppressed. This makes it possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 230. This can suppress oxidation of the conductor 260 due to the heat.

[0175] In addition, the insulator 272 may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the insulator 272 It is preferable to use metal oxide, which is a high-k material with a high dielectric constant, for the gate. The insulator has a laminated structure of the insulator 250 and the insulator 272, which is stable against heat and Therefore, the physical thickness of the gate insulator can be reduced to It is possible to reduce the gate potential applied during transistor operation while maintaining the same. This makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0176] Specifically, the insulator 272 may be hafnium, aluminum, gallium, yttrium, or the like. aluminum, zirconium, tungsten, titanium, tantalum, nickel, germanium, or The present invention is directed to a method for manufacturing a metal oxide containing one or more metals selected from the group consisting of magnesium, tungsten, and the like. This can be done.

[0177] In particular, it is an insulator containing oxides of either or both of aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use hafnium aluminate. Therefore, the heat resistance of the hafnium oxide film is higher than that of the hafnium oxide film. The insulator 272 is preferably formed of a material that is hard to crystallize, since it is hard to crystallize. Therefore, the conductor 260 is made of an oxidation-resistant material or a material that can absorb oxygen without being conductive. If the electrical conductivity is not significantly reduced, the insulator 272 is not necessarily provided. The design can be appropriately adjusted depending on the transistor characteristics.

[0178] The conductor 260 that functions as the first gate electrode is shown as a two-layer structure in FIG. However, it may have a single layer structure or a laminated structure of three or more layers. In the case of a two-layer structure, the conductor 260a is hydrogen-conductive, similar to the first conductor of the conductor 205. Atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.) It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) can be suppressed. It is preferable to use a conductive material that has the function of

[0179] The conductor 260a has a function of suppressing the diffusion of oxygen, and thus the conductor 260a is contained in the insulator 250. The oxygen in the conductive material 260b can prevent oxidation of the conductive material 260b and decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and tantalum nitride. It is preferable to use talc, ruthenium, or ruthenium oxide.

[0180] The conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated structure. For example, a laminated structure of titanium, titanium nitride and the above conductive material may be used. .

[0181] Also, the conductor 260, the insulator 272, the insulator 250, and the On top of the oxide 230c, an insulator 270 is provided to function as an etching stopper. The insulator 270 is preferably hafnium, aluminum, gallium, yttrium, or the like. aluminum, zirconium, tungsten, titanium, tantalum, nickel, germanium, or The present invention is directed to a method for manufacturing a metal oxide containing one or more metals selected from the group consisting of magnesium, tungsten, and the like. Alternatively, silicon nitride such as silicon nitride or silicon oxynitride can be used. It is possible.

[0182] In particular, it is an insulator containing oxides of either or both of aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use hafnium aluminate. Therefore, the heat resistance of the hafnium oxide film is higher than that of the hafnium oxide film. This is preferable because it is less likely to crystallize.

[0183] The insulator 280 is provided on the conductor 242 via the insulator 244. Preferably, the insulator 280 has an excess oxygen region. For example, silicon oxide is used as the insulator 280. , silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide , carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, vacancy-containing silicon oxide It is preferable that the insulating layer contains silicon oxide or resin. In particular, silicon oxide and oxide Silicon nitride is preferred because it is thermally stable.

[0184] If the insulator 244 is not provided, the insulator 280 is formed of the oxide 230a and the oxide 2 At this time, the oxygen contained in the insulator 280 is converted into oxide 2 by heating. The water or hydrogen in the insulator 280 may be supplied to the channel forming region of the insulator 280. It is preferable that the concentration of impurities such as the above be reduced.

[0185] In addition, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 280. The insulator 281, like the insulator 224 and the insulator 280, is a material that prevents water or hydrogen from entering the film. It is preferable that the concentration of impurities such as the above be reduced.

[0186] [Capacity 100a] As shown in FIG. 4, the capacitor 100a is provided in a region overlapping with the transistor 200a. The volume 100a has a conductor 110, an insulator 130, and a conductor 120 on the insulator 130. Here, the conductor 110 and the conductor 120 are used for the conductor 205 or the conductor 260, etc. Any conductive material that can be used may be used.

[0187] The capacitor 100a is formed in the openings of the insulators 244, 280, and 281. A conductor 1 serving as a lower electrode is provided on the bottom and side surfaces of the opening. 10, a conductor 120 acting as the upper electrode, and an insulator 130 acting as the dielectric. Here, the conductor 110 of the capacitor 100a is located between the transistor 20. It is formed in contact with the conductor 242a of 0a.

[0188] In particular, by increasing the depth of the openings of the insulators 280 and 281, the projection surface The capacitance of the capacitor 100a can be increased without changing the product. It is preferable that a is cylindrical (the side area is larger than the bottom area).

[0189] By adopting the above configuration, the capacitance per unit area of ​​the capacitor 100a can be increased, and the semiconductor This allows for miniaturization or high integration of the device. The capacitance value of the capacitor 100a can be set appropriately by adjusting the film thickness of the insulator 281. Therefore, a semiconductor device with a high degree of freedom in design can be provided.

[0190] It is preferable to use an insulator with a large dielectric constant for the insulator 130. For example, aluminum Insulators containing oxides of one or both of tungsten and hafnium can be used. As an insulator containing oxides of one or both of aluminum and hafnium, aluminum oxide Hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminum It is preferable to use a nitrate or the like.

[0191] The insulator 130 may also have a laminated structure, for example, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, aluminum Select two or more layers from oxides containing hafnium (hafnium aluminate) For example, hafnium oxide, aluminum oxide, and the like may be deposited by the ALD method. It is preferable to form a laminated structure by depositing hafnium oxide and hafnium oxide in this order. The thickness of the aluminum oxide film is 0.5 nm or more and 5 nm or less. By using such a laminated structure, the capacitance value is large and the leakage current is small, and the capacitance is 100a. It is possible.

[0192] The conductor 110 or the conductor 120 may have a laminated structure. 110 or the conductor 120 may be titanium, titanium nitride, tantalum, or tantalum nitride. Conductive materials based on tungsten, copper, or aluminum The conductor 110 or the conductor 120 may have a laminated structure with a conductive material. It may have a structure of three or more layers, or may have a laminated structure of three or more layers.

[0193] Here, the conductor 260 is formed on the insulating layer 270, which functions as an etching stopper. 273, a margin for aligning the conductor 260 and the conductor 110 is provided. Therefore, the distance between the conductor 260 and the conductor 110 can be reduced. In this way, the area occupied by the cell 600 can be reduced, and the miniaturization and high performance of semiconductor devices can be achieved. Integration can be achieved.

[0194] In addition, when a space is formed inside the conductor 120 in the opening that forms the capacitor 100a, In this case, it is preferable to provide an insulator in the space. Any insulator that can be used may be used. It is preferable that the surface is approximately flush with the upper surface. However, this is not limited to this. For example, With an opening formed inside the insulating layer 150, the opening may be filled by forming a film of the insulating layer 150.

[0195] An insulator 150 is disposed on the capacitor 100a and the capacitor 100b. 0 may be an insulator that can be used for the insulator 281. A conductor 160 is disposed on top of the wiring BL. The conductor 160 functions as the wiring BL described above.

[0196] [Conductor 240 acting as a plug] The conductor 240 is connected to the wiring BL (conductor 160), the transistor 300a, and the transistor The insulator 150 functions as a plug connecting the drain of the insulator 300b to the insulator 150. 30, insulator 281, insulator 280, insulator 244, conductor 242b, oxide 230 region The conductor 240 is disposed so as to be embedded in the opening formed in the region 243b. The conductor 240 is connected to the top surface of the insulator 273, the other side surface of the insulator 273, and the conductor 20 The conductor 240 is in contact with the top surface of the conductor 242b and the side of the oxide 230b. The upper surface of the conductor 240 is in contact with the surface of the insulator 150 and the side surface of the oxide 230a. and contacts the conductor 160.

[0197] In addition, the insulator 150, the insulator 130, the insulator 281, the insulator 280, the insulator 244, the conductor The conductor 242b, the oxide 230a, and the oxide 230b are in contact with the inner wall of the opening. The first conductor 40 is formed on at least a part of the bottom of the opening. 9 is located, and the first conductor of the conductor 240 contacts the conductor 209. The second conductor of the conductor 240 is formed inside the first conductor of the conductor 240. The first and second conductors of 240 are respectively the first and second conductors of conductor 205. Any conductor that can be used for the first and second conductors may be used.

[0198] In this way, the first conductor of the conductor 240 has a property of suppressing the permeation of impurities such as water or hydrogen. It is preferable to use a conductive material that has a function of controlling the temperature. For example, tantalum, tantalum nitride, etc. It is preferable to use titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. In addition, the conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen is a single layer. Alternatively, the conductive material may be used as a first conductive material of the conductive material 240. Impurities such as hydrogen and water from the upper layer of the insulator 281 pass through the conductor 240 and are transferred to the oxide 2 30 can be prevented from being mixed in.

[0199] In this embodiment, the first conductor of the conductor 240 and the second conductor of the conductor 240 Although a body stacking configuration is shown, the present invention is not limited to this. The conductor 240 may be a single layer or a laminated structure of three or more layers. When a body has a layered structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them.

[0200] Here, the conductor 260 is formed on the insulating layer 270, which functions as an etching stopper. 273, a margin for aligning the conductor 260 and the conductor 240 is provided. Therefore, the distance between the conductor 260 and the conductor 240 can be reduced. In this way, the area occupied by the cell 600 can be reduced, and the miniaturization and high performance of semiconductor devices can be achieved. Integration can be achieved.

[0201] Depending on the size of the opening for embedding the conductor 240, the conductor 242b and the acid The compound 230 may be divided into a transistor 200a side and a transistor 200b side. Additionally, openings may form in the conductor 242b and the oxide 230.

[0202] In FIG. 4, an opening is formed in the conductor 242b and the oxide 230, and the conductor 240 and the oxide 230 are Although the electric conductor 209 is in direct contact with the electrode 201, the present invention is not limited to this. For example, As shown in FIG. 5(A), the lower surface of the conductor 240 is in contact with the conductor 242b, and the lower surface of the conductor 209 is in contact with the conductor 242b. The upper surface may be in contact with the region 243b of the oxide 230a. 10 is an enlarged view of the configuration shown in FIG. 10, in which the vicinity of the conductor 240 and the conductor 209 is modified. The conductor 240 and the conductor 209 are connected to the conductor 242b and the oxide 230b and the oxide 230. In this case, the resistance of the region 243b is sufficiently high. It is preferable that the size is small.

[0203] 5B shows the structure shown in FIG. 4, in which the conductor 240 and the conductor 209 are close to each other. As shown in Figure 5(B), the channel width direction is enlarged. In the width direction of the panel, the conductor 240 is connected to the top and side surfaces of the conductor 242b and the oxide 230. b, the side of oxide 230a, and the top surface of conductor 209. In this case, the channel width direction of the conductor 242b, the oxide 230b, and the oxide 230a The length of the conductor 240 and the conductor 209 in the channel width direction is smaller than the length of the conductor 240 and the conductor 209 in the channel width direction.

[0204] As shown above, both transistor 200a and transistor 200b are made of oxide 2 30, and one of the source and drain of the transistor 200a and the transistor Either the source or the drain of the transistor 200b is in contact with the conductor 240. This allows the transistor 200a and the transistor 200b to share a contact portion. This reduces the number of plugs and contact holes. By sharing the wiring electrically connected to one of the drains, the occupied area of ​​the memory cell array is reduced. can be further reduced.

[0205] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0206] The following materials are deposited by sputtering, chemical vapor deposition (CVD), Vapor Deposition (Vapor Deposition), Molecular Beam Epitaxy (MBE) Microbeam Epitaxy (Pulse Laser Deposition (PLD) d Laser Deposition) method or Atomic Layer Deposition (ALD) method This can be done using a method such as Layer Deposition.

[0207] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0208] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can suppress plasma damage to the processed object because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device These may become charged up by receiving electric charges from the plasma. The accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage does not occur. In addition, the thermal CVD method does not require the use of a metal oxide film, which increases the yield of semiconductor devices. Since no plasma damage occurs inside the film, a film with few defects can be obtained.

[0209] The ALD method is also a film formation method that can suppress plasma damage to the workpiece. Therefore, a film with few defects can be obtained. For this reason, films formed by ALD are more susceptible to impurities than those formed by other film formation methods. In some cases, the film contains more impurities such as carbon than the film formed by the method described above. The quantitative determination of This can be done using endoscopic imaging.

[0210] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0211] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transport or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0212] The constituent material may be processed using a lithography method. Dry etching or wet etching can be used. This method is suitable for microfabrication.

[0213] In the lithography method, first, the resist is exposed to light through a mask. The areas are removed or left behind using a developer to form a resist mask. By etching through a resist mask, conductors, semiconductors, insulators, etc. can be formed as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used, in which the substrate is exposed to light by filling the substrate with liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. In this case, the pattern is written directly on the resist, so the above-mentioned resist exposure mask is not required. The resist mask is used for dry etching such as ashing, and is also used for wet etching. Etching is performed, dry etching is performed followed by wet etching, or can be removed by wet etching followed by dry etching, etc. Cut.

[0214] In addition, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film that will be the hard mask material is formed on the constituent material. Then, a resist mask is formed on the hard mask, and the hard mask material is etched. A hard mask of the desired shape can be formed. The etching of the constituent material is performed in a resist pattern. This may be done after removing the resist mask, or may be done with the resist mask left in place. In the latter case, the resist mask may disappear during etching. After etching, the hard mask may be removed by etching. If there is no effect on the subsequent process or if it can be used in the subsequent process, it is not necessary to remove the hard mask. There's no need to.

[0215] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) A plasma etching device or the like can be used.

[0216] <<Substrate>> The substrate on which the transistor 200a and the transistor 200b are formed may be, for example, An insulating substrate, a semiconductor substrate, or a conductive substrate may be used. For example, glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized As for the semiconductor substrate, for example, silicon dioxide substrate, resin substrate, etc. Semiconductor substrates such as silicon, germanium, or silicon carbide, silicon germanium, Compound semiconductor substrates made of gallium arsenide, indium phosphide, zinc oxide, and gallium oxide Furthermore, the semiconductor substrate having an insulating region therein, for example, SOI (Silicon On Insulator) substrates are also available. Examples of substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. There are also substrates with conductive materials on insulating substrates, and substrates with metal oxides. or a substrate on which a semiconductor is provided, a substrate on which a conductor or an insulator is provided on a semiconductor substrate, There are also substrates in which semiconductors or insulators are provided on a conductive substrate. The elements provided on the substrate may include a capacitance element, a resistance element, and the like. These include transistors, switching elements, light-emitting elements, and memory elements.

[0217] A flexible substrate may be used as the substrate. As a method for providing the transistor, a transistor is formed on a non-flexible substrate, and then the transistor is peeled off. There is also a method of separating the substrate and transferring it to a flexible substrate. It is preferable to provide a release layer between the substrate and the transistor. The substrate may also have flexibility. The plate may have the property of returning to its original shape when the bending or stretching is stopped, or The substrate may have a property of not returning to its original shape. Preferably, 10 μm or more and 500 μm or less, and more preferably, 15 μm or more and 300 μm or less By thinning the substrate, the semiconductor device having the transistor can be manufactured lighter. Furthermore, by making the substrate thinner, it is possible to achieve stretchability even when glass or other materials are used. Some have the property of returning to their original shape when bending or pulling is stopped. Therefore, it is necessary to reduce the impact that is applied to the semiconductor device on the board when it is dropped. That is, a robust semiconductor device can be provided.

[0218] The flexible substrate may be made of, for example, a metal, an alloy, a resin, or glass, or any of these. These fibers can be used as the substrate. A flexible substrate with a lower linear expansion coefficient is more environmentally friendly. The substrate that is flexible is preferably a substrate having a linear expansion coefficient of 0.05 to 0.15. 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less As the resin, for example, polyester, polyolefin, polyamide ( Nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. Aramid has a low linear expansion coefficient and is therefore suitable for use as a flexible substrate.

[0219] <<Insulators>> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0220] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. Therefore, materials should be selected accordingly.

[0221] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides with aluminum, aluminum and hafnium, oxides with silicon and hafnium, oxides with silicon and hafnium, Examples include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0222] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, Silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, or resin be.

[0223] In particular, silicon oxide and silicon oxynitride are thermally stable. For example, by combining it with resin, it is possible to create a laminated structure that is thermally stable and has a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon), Polyimide, polycarbonate, acrylic, etc. For example, silicon oxide and silicon oxynitride can be combined with insulators with high dielectric constants. By doing so, it is possible to obtain a laminated structure that is thermally stable and has a high relative dielectric constant.

[0224] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the This can be done.

[0225] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium, or tantalum may be used in single or multilayer configurations. Specifically, it is an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. , aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide Sodium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Metal oxides such as tantalum, silicon nitride oxide, or silicon nitride can be used. Cut.

[0226] For example, the insulators 207, 270, and 273 may be made of hafnium, aluminum, or the like. Aluminum, Gallium, Yttrium, Zirconium, Tungsten, Titanium, Tantalum, Nickel Contains one or more elements selected from the group consisting of zinc, germanium, magnesium, etc. Metal oxides containing silicon can also be used. Nitrides thereof, that is, silicon nitride, silicon oxynitride, etc. can be used.

[0227] Insulators 270 and 273 are in contact with insulators 280 and 281. In order to function as an etching stopper when forming the insulating layer 280, the insulating layer Use a material with an etching rate different from that of the 281 process. Similarly, the insulator 207 preferably forms a contact with the insulator 216. In this case, since it functions as an etching stopper, it is possible to prevent etching in the processing of the insulator 216. It is preferable to use a material that has an etching rate different from the etching rate.

[0228] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Even if the hafnium oxide is used, it is possible to suppress the diffusion of hydrogen and nitrogen. Although the barrier properties are lower than those of aluminum oxide, the barrier properties can be improved by increasing the film thickness. Therefore, by adjusting the thickness of the hafnium oxide film, it is possible to The amount of addition can be adjusted appropriately.

[0229] For example, the insulator 250 that functions as the gate insulator is an insulator with excess oxygen regions. It is also preferable that the insulator 226 is not provided, and the insulating layer 226 functions as a part of the gate insulator. When the insulator 224 contacts the oxide 230, the insulator 224 becomes an insulating layer with an excess oxygen region. For example, silicon oxide or silicon oxynitride having excess oxygen regions. By making the silicon contact with the oxide 230, the oxygen vacancies in the oxide 230 are compensated. It is possible.

[0230] Also, for example, insulator 222, which functions as part of the gate insulator, and insulator 226 containing one or more oxides of aluminum, hafnium, and gallium Insulators including aluminum and / or hafnium may be used. Insulators containing oxides of aluminum oxide, hafnium oxide, aluminum and It is preferable to use an oxide containing hafnium (hafnium aluminate) or the like.

[0231] For example, the insulator 220 may be made of silicon oxide or silicon oxynitride, which is stable against heat. It is preferable to use a film that is stable against heat and has a high dielectric constant as the gate insulator. By using a laminated structure with a thin film, the equivalent oxide thickness of the gate insulator can be reduced while maintaining the physical film thickness. It is possible to reduce the EOT.

[0232] By using the above stacked structure, the on-current can be reduced without weakening the influence of the electric field from the gate electrode. In addition, the physical thickness of the gate insulator allows the gate electrode and By keeping the distance between the gate electrode and the region where the channel is formed, The leakage current between the two electrodes can be suppressed.

[0233] The insulators 150, 216, 280, and 281 have a low dielectric constant. It is preferable to have an insulator. For example, the insulator 150, the insulator 216, the insulator 280, The insulator 281 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride. silicon dioxide doped with fluorine, silicon dioxide doped with carbon, silicon dioxide doped with carbon and nitrogen It is preferred to have added silicon oxide, silicon oxide with voids, or resin. Alternatively, the insulators 150, 216, 280, and 281 may be made of an acid. silicon nitride, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added oxide silicon dioxide, silicon dioxide doped with carbon, silicon dioxide doped with carbon and nitrogen, or It is preferable that the silicon oxide layer has a laminated structure of silicon oxide having pores and a resin. Silicon and silicon oxynitride are thermally stable, so by combining them with resin, It is possible to obtain a laminated structure that is thermally stable and has a low relative dielectric constant. polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, Recarbonate or acrylic.

[0234] The insulators 130, 214, 244, and 272 may be hydrogen or the like. An insulator having a function of suppressing the permeation of impurities and oxygen may be used. , and the insulator 274 may be, for example, aluminum oxide, hafnium oxide, mafnium oxide, or the like. magnesium, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Metal oxides such as lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide Alternatively, silicon nitride or the like may be used.

[0235] <<Conductors>> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, Zirconium, Beryllium, Indium, Ruthenium, Iridium, Strontium Materials containing one or more metal elements selected from the group consisting of ammonium, lanthanum, etc. can be used. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, Conductors, silicides such as nickel silicide may also be used.

[0236] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0237] When an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminated structure in which a conductive material containing oxygen is used. It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0238] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Alternatively, a conductive material containing nitrogen, such as indium tin oxide or tungsten oxide, may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may also be used. By using such a material, the channel is formed. In some cases, hydrogen contained in the metal oxides surrounding the outer insulating layer can be captured. It may be possible to capture hydrogen that is mixed in from the surroundings.

[0239] Conductor 110, Conductor 120, Conductor 160, Conductor 260, Conductor 205, Conductor 2 42, the conductor 208a, the conductor 208b, the conductor 209 and the conductor 240 are Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, ungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, iridium, strontium, and lanthanum The metal elements mentioned above, or alloys containing the above metal elements, or combinations of the above metal elements It is preferable to use alloys of tantalum nitride, titanium nitride, tungsten nitride, etc. titanium and aluminum nitrides, tantalum and aluminum nitrides, oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and niobium It is preferable to use oxides containing nickel. Nitrides containing tantalum and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide Ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel The oxides contained are conductive materials that are resistant to oxidation, or materials that maintain conductivity even when they absorb oxygen. In addition, it is preferable to use polycrystalline silicon containing impurity elements such as phosphorus. Alternatively, a semiconductor having high electrical conductivity, such as nickel silicide, may be used. .

[0240] <<Metal oxides>> The oxide 230 is a metal oxide that functions as an oxide semiconductor (hereinafter referred to as an oxide semiconductor). It is preferable to use the oxide 230 according to the present invention. The metal oxide will now be described.

[0241] The metal oxide preferably contains at least indium or zinc. It is preferable that the alloy contains aluminum and zinc. , yttrium, or tin. Also, boron, titanium, Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium One selected from the group consisting of tungsten, hafnium, tantalum, magnesium, etc. Alternatively, multiple types may be included.

[0242] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M can be aluminum, gallium, yttrium, or is tin, etc. Other elements that can be used for element M include boron, titanium, iron, Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Hafnium, tantalum, tungsten, magnesium, etc. However, as the element M In some cases, a combination of the above elements may be used.

[0243] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0244] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0245] In this specification, CAAC (c-axis aligned crystal) l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. An example is shown below.

[0246] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconductor properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the semiconductor of a transistor. When used in a dielectric layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the functions of the two complementary to each other, the switching function (On / Off) is realized. CAC-OS or CAC-metal oxide is given the function of In CAC-OS or CAC-metal oxide, By separating the functions, the functionality of both can be maximized.

[0247] In addition, CAC-OS or CAC-metal oxide is a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive and insulating regions in the material are formed by nanoparticles. The conductive region and the insulating region may be separated by different materials. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0248] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0249] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0250] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0251] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor), and Examples include amorphous oxide semiconductors.

[0252] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0253] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is difficult to confirm the lattice distortion. This is because the CAAC-OS crystals are grown in the ab-plane direction. In the case of the SiO2, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0254] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0255] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS should be free from impurities and defects (oxygen vacancies (V O :oxygen v It can also be called a metal oxide with low acancy. Metal oxides with CAAC-OS have stable physical properties. The metal oxides used are heat resistant and highly reliable.

[0256] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0257] Indium gallium oxide, a type of metal oxide containing indium, gallium, and zinc, is used. The IGZO nanocrystals mentioned above are stable. In particular, IGZO tends to have difficulty growing crystals in the atmosphere. , small crystals (e.g., crystals of several mm or several cm) are more likely to be formed than large crystals (here, crystals of several mm or several cm). For example, the nanocrystals mentioned above may be structurally more stable.

[0258] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low density regions. The ke-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0259] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention may be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more of them.

[0260] [Transistors with metal oxides] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0261] Note that by using the above metal oxide for the channel formation region of a transistor, a high field efficiency can be achieved. It is possible to realize a transistor with high mobility. It can be realized.

[0262] It is also preferable to use a metal oxide with a low carrier density for the transistor. When the carrier density of the metal oxide film is reduced, the impurity concentration in the metal oxide film is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides , the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. stomach.

[0263] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low density of defect states. Therefore, the trap level density may also be low.

[0264] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. be.

[0265] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be kept low. In order to reduce the impurity concentration in the metal oxide, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0266] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0267] When metal oxides contain silicon or carbon, which are elements of Group 14, they become metal oxides. Defect levels are formed in the oxides. This leads to the formation of silicon and carbon concentrations in the metal oxides. The concentration of silicon and carbon near the interface with the metal oxide was measured by secondary ion mass spectrometry (SIM). S: Secondary Ion Mass Spectrometry) concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0268] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor that uses a metal oxide containing metals in the channel formation region is normally on. Therefore, the concentration of alkali metals or alkaline earth metals in metal oxides It is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm3 Below, I prefer Or 2 x 10 16 atoms / cm 3 Do the following:

[0269] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carriers As a result, the density increases and it becomes easier to make the metal oxide containing nitrogen into a channel type. The transistors used in the metal-doped region tend to be normally-on. In the oxide, it is preferable that the nitrogen content in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in metal oxides is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following .

[0270] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, resulting in the formation of chiral ions. Therefore, metal oxides containing hydrogen can generate electrons that are carriers. The transistor used tends to have normally-on characteristics.

[0271] In addition, hydrogen contained in metal oxides is generated at shallow defect levels (sDOS) in the metal oxides. Low level Density of States may be formed. The shallow defect level refers to the interface state located near the bottom of the conduction band. It is estimated that it exists near the boundary between the high density region and the low density region in the oxide. High density and low density regions in metal oxides are distinguished by the amount of hydrogen contained in the regions. That is, the high density region contains more hydrogen than the low density region. The area near the boundary between the high density and low density regions in the center is subject to microcracks due to the stress and strain between the two regions. Oxygen vacancies and indium dangling bonds occur near the cracks. When impurities such as hydrogen or water are localized here, shallow defect levels are formed. It is estimated that

[0272] Furthermore, the high density regions in the metal oxide may be more crystalline than the low density regions. Furthermore, the high density region in the metal oxide may have a higher film density than the low density region. Furthermore, when the metal oxide has a composition containing indium, gallium, and zinc, The high density region comprises indium, gallium, and zinc, and the low density region comprises indium. In other words, the low density region may have more gallium than the high density region. The proportion of um may be low.

[0273] The shallow defect level is presumed to be caused by oxygen vacancies. As the loss increases, the density of shallow defect states as well as the density of deep defect states (dDOS) increases. It is estimated that the veloci- cal density of states will also increase. This is because the deep defect level is also thought to be due to oxygen vacancies. This refers to a defect level located near the center of the band gap.

[0274] Therefore, by suppressing oxygen vacancies in metal oxides, shallow and deep defect levels can be reduced. It is possible to reduce the density of both shallow defect levels. It may be possible to control this to some extent by adjusting the temperature during metal oxide film formation. The temperature during the deposition of the metal oxide is set to 170°C or thereabouts, preferably 130°C or By setting the temperature at around that temperature, or more preferably at room temperature, the density of shallow defect levels can be reduced. do.

[0275] In addition, the shallow defect levels of metal oxides are important for the electrical conductivity of transistors that use metal oxides as semiconductor layers. The shallow defect levels affect the electrical characteristics of the transistor. -In the gate voltage (Id-Vg) characteristics, the drain current Id is The change is gradual, and the rise characteristics of the transistor from the OFF state to the ON state are The S value (also called Subthreshold Swing, SS) is one of the indicators of sound quality. ) deteriorates. This is thought to be due to electrons being trapped in shallow defect levels.

[0276] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5x1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, stable electrical properties can be imparted.

[0277] [Effect of vacuum baking] Here, we will explain the weak Zn-O bond contained in metal oxides and the structure of this bond. An example of a method for reducing oxygen atoms and zinc atoms will be described below.

[0278] Defects that lead to poor electrical characteristics in transistors using metal oxides For example, a metal oxide film containing oxygen vacancies is used. The threshold voltage of the transistor tends to fluctuate in the negative direction, and the transistor has normally-on characteristics. This is because donors are generated due to oxygen vacancies in the metal oxide, and This is because the rear concentration increases. This can cause various problems, such as malfunctions occurring more frequently and power consumption increasing when not in operation. A problem arises.

[0279] In addition, the thermal history (thermal barrier) in the process of forming the connection wiring for manufacturing the module This causes changes in the electrical characteristics of transistors, such as threshold voltage fluctuations and increased parasitic resistance. This leads to problems such as deterioration of electrical properties, and an increase in the variation in electrical properties due to the deterioration of electrical properties. These problems directly lead to a decrease in manufacturing yield, so it is important to consider countermeasures. It is possible to quickly evaluate the change in transistor characteristics (aging) that occurs during use. The electrical characteristics deteriorate even in stress tests that can be performed. The deterioration of the electrical characteristics occurs during the thermal history process. Metal oxidation occurs due to high temperature treatment or electrical stress applied during stress testing. It is presumed that this is due to a lack of oxygen in the material.

[0280] Metal oxides contain oxygen atoms that are weakly bonded to metal atoms and are prone to oxygen vacancies. In particular, when the metal oxide is an In-Ga-Zn oxide, zinc atoms and oxygen atoms are weakly bonded. Here, a weak Zn-O bond is formed. , high temperature treatment during thermal history, or electrical stress during stress testing. The bond between a zinc atom and an oxygen atom is strong enough to be broken by a force. When weak Zn-O bonds exist in metal oxides, they can be easily broken down by thermal history or current stress. The bond is broken and oxygen vacancies are formed. The stability of the transistors, such as resistance to shocks and stress tests, is reduced. do.

[0281] The bond between the oxygen atom that is bonded to the zinc atom and the zinc atom is a weak Zn- O bonds. Compared to gallium atoms, zinc atoms have weaker bonds with oxygen atoms. Therefore, oxygen atoms that are bonded to many zinc atoms are easily lost. The bond that forms between the electron and the oxygen atom is presumably weaker than the bond with other metals.

[0282] In addition, it is speculated that when impurities exist in metal oxides, weak Zn-O bonds are more likely to form. Impurities in metal oxides include, for example, water molecules and hydrogen. The presence of water molecules and hydrogen allows hydrogen atoms to bond with oxygen atoms that make up the metal oxide. (Also called OH bond.) The oxygen atoms that make up the metal oxide are In-Ga-Z n When the oxide is a single crystal, it is bonded to four metal atoms that make up the metal oxide. However, when an oxygen atom bonded to a hydrogen atom is bonded to two or three metal atoms, When the number of metal atoms bonded to an oxygen atom decreases, the oxygen atom is lost. In addition, when a zinc atom is bonded to an oxygen atom that forms an OH bond, The bond between the oxygen atom and the zinc atom is presumed to be weak.

[0283] Additionally, weak Zn-O bonds are formed in the strain that exists in the regions where multiple nanocrystals are connected. Nanocrystals are basically hexagonal, but in this distortion, pentagonal and heptagonal In this distortion, the bond distance between atoms is not uniform, resulting in weak Zn- It is presumed that an O bond is formed.

[0284] It is also speculated that weak Zn-O bonds are more likely to form when the crystallinity of the metal oxide is low. When the crystallinity of a metal oxide is high, the zinc atoms that make up the metal oxide are spaced apart by up to four oxygen atoms. However, when the crystallinity of the metal oxide decreases, the number of atoms bonded to the zinc atoms decreases. The number of oxygen atoms bonded to the zinc atom tends to decrease. The zinc atom is easily lost. That is, the bond formed between the zinc atom and the oxygen atom is The bonds are presumably weaker than those that occur in single crystals.

[0285] By reducing the oxygen and zinc atoms that make up the weak Zn-O bonds, This suppresses the formation of oxygen vacancies due to current stress and improves the stability of transistors. In addition, it is possible to reduce only the oxygen atoms that make up the weak Zn-O bond, and When the zinc atoms constituting the bond do not decrease, supplying oxygen atoms to the vicinity of the zinc atoms results in a weak Zn-O bonds can be reformed. Therefore, the zinc that forms the weak Zn-O bond It is preferable to reduce the amount of carbon atoms and oxygen atoms.

[0286] One way to reduce the oxygen and zinc atoms that make up the weak Zn-O bond is to After forming an oxide film, vacuum baking is performed. The vacuum atmosphere is evacuated using a turbo molecular pump or similar. The pressure in the processing chamber is maintained at 1×10 -2 Pa or less, preferably 1×10 - 3 The substrate temperature during the heat treatment is 300° C. or higher, preferably The temperature should be 400°C or higher.

[0287] By performing vacuum baking, oxygen atoms and zinc atoms that make up the weak Zn-O bond are reduced. In addition, the vacuum baking process heats the metal oxide, which reduces the amount of weak After reducing the oxygen and zinc atoms that make up the Zn-O bond, the elements that make up the metal oxide are The rearrangement of the atoms increases the number of oxygen atoms bonded to four metal atoms. By reducing the oxygen and zinc atoms that make up the weak Zn-O bond, The reformation of the bond can be inhibited.

[0288] Furthermore, if impurities exist in the metal oxide, vacuum baking can be performed to remove the metal oxide. The OH bond in the metal oxide can be reduced by releasing water molecules or hydrogen. The decrease in bonding increases the proportion of oxygen atoms bonded to four metal atoms. When a water molecule or hydrogen is released, the atoms that make up the metal oxide rearrange to form four There are more oxygen atoms bonded to the metal atoms, so the weak Zn-O bond is reformed. This can prevent the risk of infection from increasing.

[0289] As described above, by performing vacuum baking after forming the metal oxide film, the weak Zn-O bond can be broken down. Therefore, the oxygen atoms and zinc atoms that constitute the bond can be reduced by this process. This can improve the stability of the transistor. This increases the freedom of choice of materials and forming methods.

[0290] In the following, using Figs. 6 and 7, a different structure from that shown in the previous <Configuration Example of Cell 600> will be described. An example of a cell 600 according to an embodiment of the present invention will be described. 1 is a cross-sectional view of the transistor 200a and the transistor 200b in the channel length direction. 6 and 7, the components corresponding to those shown in FIG. 4 are denoted by the same reference numerals. In the following, unless otherwise specified, the configurations shown in FIGS. 6 and 7 are the same as those shown in FIG. The description of the configuration shown below can be taken into consideration.

[0291] <Modification 1 of Cell 600> In the configuration shown in FIG. 6, the shapes of the transistors 200a and 200b are the same as those in FIG. The transistor 200a shown in FIG. 6 has a different configuration from the transistor shown in FIG. The configuration different from that of the controller 200a will be described.

[0292] The transistor 200a shown in FIG. 6 includes an insulator 2 disposed on a substrate (not shown). 14, an insulator 216 disposed on the insulator 214, and a wiring board made of the insulator 214 and the insulator 21 6, and a conductor 205 disposed so as to be embedded in the insulator 216 and the conductor 205. An insulator 220 is disposed on the insulator 220, an insulator 222 is disposed on the insulator 220, and an insulator 22 2, an insulator 224 disposed on the insulating layer 224, and an oxide 230a disposed on the insulating layer 224; An oxide 230b is disposed on the oxide 230a, and an oxide 230b is disposed on the oxide 230b. an oxide 230c, an insulator 250 disposed on the oxide 230c, and a The insulator 272 is disposed on the conductor 260, and the conductor 26 0, an insulator 270 disposed on the insulator 270, and an insulator 271 disposed on the insulator 270. The insulator 273 is disposed adjacent to the side of the edge 250, the conductor 260, and the insulator 270. and a metal oxide layer 230, an insulator 273, and an insulator 271. Furthermore, the insulator 244 is in contact with the bottom surface and side surface of the conductor 205. An insulator 207a is disposed on the upper surface of the conductor 205, and an insulator 207b is disposed in contact with the upper surface of the conductor 205. An insulator 280 is provided on the edge 244, and an insulator 282 is provided on the insulator 280. An insulator 281 is provided on top of the insulator 282 .

[0293] The transistor 200a shown in FIG. 6 includes an oxide 230c, an insulator 250, an insulator 272, The conductor 260 and the insulator 270 are embedded in the openings provided in the insulator 280. The conductor 11 does not have the conductor 242a and the conductor 242b. 0 is in contact with the oxide 230b, has the insulator 271, has the insulator 226, 4 in that it does not include an insulator 282, and in that it includes an insulator 282. is different from.

[0294] When viewed from above perpendicularly to the substrate, the position of the side surface of the insulator 270 is It is preferable that the position of the insulator 250 is approximately the same as the position of the side of the oxide 230c. The body 271 is formed in contact with the upper surface of the insulator 270. The insulator 273 is formed between the insulator 271 and the The insulating material 270, the conductor 260, the insulating material 250, and the oxide 230c are provided in contact with the side surfaces of the insulating material 270, the conductor 260, the insulating material 250, and the oxide 230c. The insulator 271 may be made of an insulating material that can be used for the insulator 280. In addition, the insulating material that can be used for the insulator 270 may be used for the insulator 271. In this case, the insulator 270 may not be provided.

[0295] The insulator 273 is formed by depositing an insulating film and then anisotropically etching the insulating film. That is, insulator 271, insulator 270, conductor 260, insulator 272, insulator 250, and It is preferable to leave the portion in contact with the side surface of the oxide 230c.

[0296] By providing the insulator 271, the insulator 270, the conductor 260, the insulator 272, the insulator 2 50, and when processing the oxide 230c, the sides of these structures are approximately vertical, specifically, The angle between the side surface and the substrate surface is 75 degrees or more and 100 degrees or less, preferably 80 degrees or more and 95 degrees or less. By processing the side surface into such a shape, the anisotropic edge can be formed. The chipping allows the insulator 273 to be formed into the desired shape.

[0297] The oxide 230b of the transistor 200a shown in FIG. 6 also includes regions 243a and 243b. As shown in FIG. 6, the region 243 overlaps with the conductor 260 of the oxide 230. As in the transistor 200a shown in FIG. Region 243a can function as one of the source and drain regions, and the region of oxide 230 Region 243b can function as the other of the source and drain regions. The region between 3a and region 243b can function as a channel forming region.

[0298] To form region 243, for example, a region of oxide 230 that does not overlap with conductor 260 is A film containing a metal element may be provided in contact with the metal film. For example, an oxide film containing a metal element or a nitride film containing a metal element can be used. In this case, it is preferable that a compound layer is formed between the film containing the metal element and the oxide 230. For example, a heat treatment is performed in an atmosphere containing nitrogen to remove oxide from the film containing the metal element. The metal is diffused into the oxide 230. The compound layer is formed on the top and side surfaces of the oxide 230. The compound layer may be formed by mixing the component of the film containing the metal element and the oxide 230 For example, the compound layer may be a layer having a metal compound containing the component of the oxide 230. A layer may be formed in which the metal element and the added metal element are alloyed. If the film containing the element has insulating properties due to the above heat treatment or the like, it is used as the insulator 244. In addition, the film containing the metal element can be etched after the formation of the region 243. It may be removed by means of a method such as

[0299] The insulator 282 may be an insulator that can be used for the insulator 214, etc. As a result, the insulator 282 prevents impurities such as water or hydrogen from entering the transistor from the insulator 281 side. It can function as a barrier insulating film that prevents the metal from being mixed into the transistor 200a and the like. Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen.

[0300] <Modification 2 of Cell 600> The configuration shown in FIG. 7 differs from the configuration shown in FIG. 6 in the shapes of the capacitors 100a and 100b. The following describes the configuration of the capacitor 100a shown in FIG. 7 that differs from the capacitor 100a shown in FIG. 6. Reveal.

[0301] Capacitor 100a is formed by region 243a (oxide 230) which connects the source and drain of transistor 200a. the region 243a serving as one of the drains, the insulator 130 on the region 243a, and the insulator 130 The conductor 120 is connected to at least one of the insulating layers 130 via the insulating layer 130. It is preferable that the portion is arranged so as to overlap with the region 243a.

[0302] In the capacitor 100a, the region 243a functions as one of the electrodes, and the conductor 120 functions as the electrode The insulator 130 functions as the dielectric of the capacitor 100a. Here, the region 243a is connected to one of the source and drain of the transistor 200a and the capacitor. The electrode 100a functions as one of the electrodes.

[0303] The insulator 130 and the conductor 120 are provided to cover the side surface of the oxide 230. By adopting such a configuration, the capacitance of the oxide 230 is 100 a, which increases the capacitance per unit area of ​​the capacitance 100a It is possible.

[0304] Next, referring to FIG. 8, the transistor 300a (transistor 300b) corresponding to the lower configuration of the cell 600 will be described. The configuration of the transistor 300a and the transistor 300b will be described. 10 is a cross-sectional view of a transistor 300b in the channel length direction.

[0305] [Transistor 300a] As shown in FIG. 8, the transistor 300a is provided on a substrate 311 and includes a conductor 316. , an insulator 315, a semiconductor region 313 consisting of a portion of the substrate 311, and a source region or It has a low resistance region 314a that functions as a drain region, and a low resistance region 314b.

[0306] The transistor 300a has an insulating top surface and side surfaces in the channel width direction of the semiconductor region 313. The transistor 300a is covered with the conductor 316 through the body 315. By using the in-type transistor, the effective channel width is increased, and the transistor 300 The on-state characteristics of a can be improved. In addition, by increasing the contribution of the electric field of the gate electrode, This improves the off-state characteristics of the transistor 300a.

[0307] The transistor 300a may be either a p-channel or an n-channel type. In addition, a cell 600 having a transistor 300a and a transistor 300b is mounted on a substrate 3. When a plurality of cells 600 are provided in the cell 11, an insulator 321 is provided between each cell 600.

[0308] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region or the drain region In the low resistance region 314a and the low resistance region 314b, which are the drain region, silicon is It preferably contains a semiconductor such as a silicon-based semiconductor, and more preferably contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium It may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (Gallium Aluminum Arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, we can control the effective mass of silicon. Alternatively, GaAs and GaAlAs may be used to form a transistor. The 300a is a HEMT (High Electron Mobility Transistor) stor) can also be used.

[0309] The low resistance region 314a and the low resistance region 314b are formed by the semiconductor layer applied to the semiconductor region 313. In addition to the conductive material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron, are added. The transistor 300a and the transistor 3 00b share the low resistance region 314b.

[0310] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used. .

[0311] Since the work function is determined by the conductor material, the The Vth of the transistor can be adjusted. It is preferable to use a material such as tantalum. It is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor. In particular, tungsten is preferably used in terms of heat resistance.

[0312] The transistor 300a shown in FIG. 8 is an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the structure and driving method.

[0313] An insulator 320 and an insulator 322 are stacked in this order to cover the transistor 300a. It is being used.

[0314] The insulators 320 and 322 may be, for example, silicon oxide or silicon oxynitride. , silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, nitriding oxide Aluminum oxide, aluminum nitride, etc. may be used.

[0315] The insulator 322 is formed to cover a step formed by the transistor 300a and the like provided below. For example, the top surface of the insulator 322 may have a function as a planarizing film. In order to improve the flatness, the surface is planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like. It may also be used.

[0316] The insulator 320 and the insulator 322 are connected to the capacitor 100a and the capacitor 100b. or a conductor 20 electrically connected to the transistor 200a and the transistor 200b. 8 (conductor 208a, conductor 208b), and conductor 209, wiring SL (wiring SL1, The conductors 211 (conductors 211a, conductors 211b) electrically connected to the wiring SL2 are The conductors 208, 209, and 211 are plugs. The conductor that functions as a plug or wiring may have a plurality of structures. In this specification and the like, the same reference numerals may be used to denote the wiring and the wiring structure. The wire and the plug that electrically connects thereto may be an integral part. In some cases, the conductor functions as a plug, and in other cases, a part of the conductor functions as a plug.

[0317] Materials of each plug and wiring (conductor 208, conductor 209, conductor 211, etc.) Examples of the conductive material include metal materials, alloy materials, metal nitride materials, and metal oxide materials. The material can be used in a single layer or in a laminated form. Tungsten has both heat resistance and electrical conductivity. It is preferable to use a high melting point material such as molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to form it from a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0318] Conductor 208a is electrically connected to conductor 316, which serves as the gate of transistor 300a. and electrically connected to one of the source and drain of the transistor 200a. At this time, the conductor 208a is formed in the region 243 of the oxide 230 of the transistor 200a. It is preferable that the conductor 316 is connected to the bottom of the conductor 208a, the region 24a. It is electrically connected to one of the electrodes (conductor 110) of the capacitor 100a via 3a and the like.

[0319] The conductor 209 is electrically connected to the low resistance region 314b and is electrically connected to the conductor 240. The low resistance region 314b is connected to the wiring BL via the conductors 209, 240, etc. The conductor 160 functions as a

[0320] The conductor 211a is electrically connected to the low resistance region 314a and is electrically connected to the wiring SL1. In addition, the conductor 211a may function as the wiring SL1. Region 314a serves as the source region of transistor 300a, and low-resistivity region 314b serves as the It functions as the drain region of the transistor 300a. and transistor 300b share low resistance region 314b. is connected to the drain region of transistor 300a as well as the drain region of transistor 300b. It also functions as a territory.

[0321] Hereinafter, a different example of the transistor 300a according to one embodiment of the present invention will be described with reference to FIG. 9. FIG. 9 is a cross-sectional view of the transistor 300a in the channel length direction. Among the components shown in FIG. 9, those corresponding to those shown in FIG. 8 are given the same reference numerals, and the description thereof will be omitted. In the following, unless otherwise specified, the configuration shown in FIG. 9 is the same as that shown in FIG. The description of the configuration can be taken into consideration.

[0322] [Modification of Transistor 300a] The transistor 300a can be a planar transistor. The transistor 300a shown has a gate insulator 312 formed on a semiconductor region 313 having a flat surface. and a conductor 316 that functions as a gate electrode. The insulator 315 and the conductor 316 are provided with side walls and The transistor 300a is also provided with an insulator 317 that functions as a gate insulator. It is preferable that the insulating layer 320 is covered with an insulating material containing nitride. A body 322 is provided.

[0323] The transistor 300a shown in FIG. 9 is similar to the transistor 300a shown in FIG. A low-resistance region 314a is provided on the 311 and functions as a source region or a drain region. , and a low resistance region 314b. A plurality of cells 600 are provided on the substrate 311. In this case, an insulator 321 is provided between each cell 600 .

[0324] Also, the conductor 316 and the electrical wiring conductor 316 are embedded in the insulator 322 and the insulator 320. The conductive material 208 (conductive material 208a, conductive material 208b) and the low resistance region 314b are electrically connected to each other. A conductor 209 electrically connected to the low resistance region 314a and a conductor electrically connected to the low resistance region 314a 211 (conductor 211a, conductor 211b) is provided.

[0325] The configurations, structures, methods, etc. shown in this embodiment may be the same as those shown in other embodiments. , and other methods can be used in combination as appropriate.

[0326] (Embodiment 2) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. A transistor (hereinafter referred to as an OS transistor) and a capacitor element are applied. As an example of a memory device that is widely used, NOSRAM (registered trademark) will be explained. The mark stands for "Nonvolatile Oxide Semiconductor RAM " and refers to RAM with gain cell type (2T type, 3T type) memory cells. In the following, a memory device using OS transistors such as NOSRAM will be referred to as O It is sometimes called S memory.

[0327] NOSRAM is a memory device that uses OS transistors in memory cells (hereinafter referred to as The OS memory is composed of at least a capacitive element and a This is a memory that has an OS transistor that controls the charging and discharging of the element. Since it is a transistor with a small off-state current, the OS memory has excellent retention characteristics and is nonvolatile. It can function as a harpoon.

[0328] < <nosram1600>> An example of the configuration of NOSRAM is shown in Figure 10. NOSRAM 1600 shown in Figure 10 is a memory Cell array 1610, controller 1640, row driver 1650, column driver 1660 , and an output driver 1670. Note that the NOSRAM 1600 can store multiple data in one memory cell. It is a multi-level NOSRAM that stores value data.

[0329] The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, and a plurality of The word line RWL, the bit line BL, and the source line SL are The word line RWL is the read word line. One memory cell 1611 stores 3-bit (8-value) data.

[0330] The controller 1640 controls the entire NOSRAM 1600 and outputs the data WDA Writes data to [31:0] and reads data from RDA[31:0]. Controller 1 640 is an external command signal (for example, a chip enable signal, a write enable signal, etc.). 1650, column drivers 1660, and output drivers 1670 control signals are generated.

[0331] The row driver 1650 has the function of selecting a row to access. has a row decoder 1651 and a word line driver 1652.

[0332] The column driver 1660 drives the source lines SL and bit lines BL. 60 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.

[0333] The DAC1663 converts 3-bit digital data into an analog voltage. 3 converts the 32-bit data WDA[31:0] into an analog voltage every 3 bits. .

[0334] The write driver 1662 has a function of precharging the source line SL, A function for electrically floating a source line SL, a function for selecting a source line SL, and a function for selecting a source line SL. This function inputs the write voltage generated by the DAC1663 and precharges the bit line BL. and the function of electrically floating the bit line BL.

[0335] The output driver 1670 includes a selector 1671, an ADC (analog-to-digital conversion circuit), 1672 and an output buffer 1673. The selector 1671 selects the source line to be accessed. SL is selected, and the potential of the selected source line SL is sent to the ADC1672. 72 has the function of converting an analog voltage into 3-bit digital data. The potential is converted into 3-bit data by the ADC 1672 and output to the output buffer 1673 holds the data output from the ADC1672.

[0336] In this embodiment, the row driver 1650, the column driver 1660, and the output driver The configuration of the driver 1670 is not limited to the above. Depending on the configuration or driving method, these drivers and the wiring connected to the drivers may be The layout of the lines may be changed, and the layout of these drivers and the wiring connected to them may be changed. The functions of the source line SL may be changed or added. The portion may be provided on the bit line BL.

[0337] In the above, the amount of information stored in each memory cell 1611 is set to 3 bits. The configuration of the memory device shown in this embodiment is not limited to this. The amount of information to be transmitted may be 2 bits or less, or 4 bits or more. When the amount of information stored in memory cell 1611 is set to 1 bit, the DAC1663 and AD A configuration without C1672 is also possible.

[0338] <Memory cells 1611 to 1614> 11A is a circuit diagram showing a configuration example of the memory cell 1611. is a 2T type gain cell, and the memory cell 1611 has a word line WWL, a word line RWL, The memory cell 161 is electrically connected to the bit line BL, the source line SL, and the wiring BGL. 1 indicates the node SN, the OS transistor MO61, the transistor MP61, and the capacitance element C61 The OS transistor MO61 is a write transistor. 61 is a read transistor, which is made up of, for example, a p-channel Si transistor. The capacitor C61 is a storage capacitor for holding the potential of the node SN. This corresponds to the gate of transistor MP61 in this example.

[0339] The write transistor of memory cell 1611 is composed of OS transistor MO61. Therefore, the NOSRAM 1600 can retain data for a long time.

[0340] In the example of FIG. 11(A), the bit line is a common bit line for writing and reading. As shown in FIG. 11B, a bit line WBL functions as a write bit line, and a read bit line WBL functions as a read bit line. A bit line RBL may be provided to function as an output bit line.

[0341] 11(C) to 11(E) show other configuration examples of memory cells. 11(E) shows an example in which a write bit line WBL and a read bit line RBL are provided. However, as shown in FIG. 11(A), a bit line is provided that is shared between writing and reading. That's fine.

[0342] The memory cell 1612 shown in FIG. 11C is a modified example of the memory cell 1611. The output transistor has been changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor. stomach.

[0343] In the memory cell 1611 and the memory cell 1612, the OS transistor MO61 is a bottom It may be an OS transistor without a gate.

[0344] The memory cell 1613 shown in FIG. 11(D) is a 3T-type gain cell, and is connected to the word line WWL. , RWL, bit line WBL, bit line RBL, source line SL, wiring BGL, wiring PCL The memory cell 1613 is electrically connected to the node SN, the OS transistor MO6 2, transistor MP62, transistor MP63, and capacitance element C62. Transistor MO62 is a write transistor. Transistor MP62 is a read transistor. transistor MP61 is a select transistor.

[0345] The memory cell 1614 shown in FIG. 11(E) is a modified example of the memory cell 1613. The output transistor and the selection transistor are n-channel transistors (transistor M N62, transistor MN63). The transistor MN63 may be an OS transistor or a Si transistor. .

[0346] The OS transistors provided in the memory cells 1611 to 1614 are bottom The transistor may be a gateless transistor or a bottom gate transistor. .

[0347] In the above, memory cells 1611 and the like are connected in parallel, so-called NOR type memory cells. Although the storage device has been described above, the storage device shown in this embodiment is not limited to this. For example, the following memory cells 1615 are connected in series, so-called NAND The storage device may be of the same type.

[0348] 12 is a circuit diagram showing an example of the configuration of a NAND-type memory cell array 1610. The memory cell array 1610 shown in FIG. 1 includes source lines SL, bit lines RBL, bit lines WBL, It has word lines WWL, word lines RWL, wiring BGL, and memory cells 1615. The memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, The transistor MN64 is, for example, an n-channel Si transistor. The transistor MN64 is not limited to this, but may be a p-channel Si The transistor may be a silicon nitride semiconductor (SiN) transistor or an OS transistor.

[0349] In the following, the memory cell 1615a and the memory cell 1615b shown in FIG. 12 are taken as examples. Here, the connection to either memory cell 1615a or memory cell 1615b is The symbols of the wiring or circuit elements are indicated by adding the symbol a or b.

[0350] In the memory cell 1615a, the gate of the transistor MN64a and the gate of the OS transistor One of the source and drain of the capacitor MO63a and one of the electrodes of the capacitance element C63a are connected to a potential The bit line WBL and the source and The other of the drains is electrically connected to the word line WWLa. The gate of the transistor MO63a is electrically connected to the wiring BGLa. The bottom gate of the OS transistor MO63a is electrically connected to the The wire RWLa and the other electrode of the capacitance element C63a are electrically connected to each other.

[0351] The memory cell 1615b is symmetrical about the contact portion with the bit line WBL. Therefore, the memory cell 1615b can be provided symmetrically to the memory cell 1615a. The circuit elements are connected to the wiring in the same manner as the memory cell 1615a.

[0352] Furthermore, the source of the transistor MN64a of the memory cell 1615a is connected to the The drain of the transistor MN64b in the memory cell 1615b is electrically connected to the drain of the transistor MN64b in the memory cell 1615b. The drain of the transistor MN64a in the 615a is electrically connected to the bit line RBL. The source of the transistor MN64b in the memory cell 1615b is connected to a plurality of memory The resistor 1615 is electrically connected to the source line SL through a transistor MN64. In this way, in the NAND type memory cell array 1610, the bit line RBL and the source A plurality of transistors MN64 are connected in series between the lines SL.

[0353] In the memory device having the memory cell array 1610 shown in FIG. or word line RWL) (hereinafter referred to as a memory cell column). For example, a write operation is performed as follows: The OS transfer is applied to the word line WWL connected to the memory cell column to be written. Apply a voltage that turns on the register MO63, and the OS transistor of the memory cell row to be written This turns on the transistor MO63 of the specified memory cell column. The potential of the bit line WBL is applied to the gate of N64 and one of the electrodes of the capacitance element C63. A predetermined charge is applied to the gate of the OS transistor M When O63 is turned off, the gate can retain a certain amount of charge. In this way, data can be written to the memory cells 1615 in the specified memory cell column. can be done.

[0354] Also, for example, a read operation can be performed as follows. First, A word line RWL not connected to a memory cell column is connected to the gate of transistor MN64. A potential is applied so that the transistor MN64 is turned on regardless of the charge stored in the memory cell. The transistors MN64 in the memory cell columns other than the one to be read are turned on. The gate of the transistor MN64 is connected to the word line RWL connected to the memory cell column to be read. The charge stored in the transistor MN64 selects the on or off state. A constant potential is applied to the source line SL, and a constant potential is applied to the bit line RB. The read circuit connected to the source line SL and the bit line R is set to an operating state. The multiple transistors MN64 between the BLs are in the on state except for the memory cell column to be read. Therefore, the conductance between the source line SL and the bit line RBL is This is determined by the state (on or off) of transistor MN64 in the memory cell column. The charge on the gate of the transistor MN64 in the memory cell column to be read is Therefore, the conductance of the transistors is different, and the voltage of the bit line RBL is accordingly The potential of the bit line RBL is read by the read circuit. This allows information to be read from the memory cells 1615 in the specified memory cell column.

[0355] Data is written by charging and discharging the capacitor C61, capacitor C62, or capacitor C63. Therefore, in principle, NOSRAM1600 has no restrictions on the number of times it can be rewritten, and It is possible to write and read data with low energy consumption. Since it is possible to maintain the data, the frequency of refreshing can be reduced.

[0356] The semiconductor device shown in the above embodiment is a memory cell 1611, a memory cell 1612, and a memory When used in the cell 1613, the memory cell 1614, and the memory cell 1615, an OS transistor Transistors MO61, OS transistor MO62, and OS transistor MO63 200 is used, and capacitance 100 is used as capacitance element C61, capacitance element C62, and capacitance element C63. Transistor MP61, transistor MP62, transistor MP63, transistor transistor MN61, transistor MN62, transistor MN63, and transistor MN64. The transistor 300 can be used as a pair of a transistor and a capacitor. Since the area occupied by the hits in a top view can be reduced, the memory according to this embodiment Therefore, the unit of the memory device according to this embodiment can be The storage capacity per area can be increased.

[0357] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0358] (Embodiment 3) In this embodiment mode, a semiconductor device according to the above embodiment mode is applied to a semiconductor device A. I will explain the system.

[0359] FIG. 13 is a block diagram showing an example of the configuration of the AI ​​system 4041. 41 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.

[0360] The calculation unit 4010 includes an analog calculation circuit 4011, a DOSRAM 4012, and a NOSR. AM4013 and FPGA (Field Programmable Gate Array) 4014. As the NOSRAM4013, the NOSRAM1600 shown in the above embodiment is used. The FPGA4014 also has a configuration memory and In this article, we will refer to this type of FPGA as an "OS-FPG." It's called "A".

[0361] The control unit 4020 includes a CPU (Central Processing Unit) 40 21, GPU (Graphics Processing Unit) 4022, and P LL (Phase Locked Loop) 4023 and SRAM (Static R andom Access Memory) 4024 and PROM (Programma ble Read Only Memory) 4025 and memory controller 4026 , a power supply circuit 4027, and a PMU (Power Management Unit) 40 28 and has.

[0362] The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, and a video a codec 4033, a general-purpose input / output module 4034, and a communication module 4035; It has.

[0363] The calculation unit 4010 can perform learning or inference using a neural network. Cut.

[0364] The analog arithmetic circuit 4011 is an A / D (analog / digital) conversion circuit, a D / A (digital It has a digital / analog conversion circuit and a multiply-and-accumulate circuit.

[0365] The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog arithmetic circuit 4011 using a transistor has an analog memory and performs learning or This makes it possible to perform the multiply-and-accumulate operations required for inference with low power consumption.

[0366] The DOSRAM4012 is a DRAM formed using OS transistors. The SRAM4012 temporarily stores digital data sent from the CPU4021. The DOSRAM4012 is a memory that uses memory cells that include OS transistors and Si The memory cell and the readout circuit section are stacked. Since the DOSRAM4012 can be placed on different layers, the total circuit area can be reduced It can be made smaller.

[0367] Calculations using neural networks can involve more than 1,000 pieces of input data. When storing the above input data in SRAM, the SRAM has a limited circuit area and memory capacity. Since the size of the memory is small, the input data must be divided into smaller pieces and stored. 2 allows memory cells to be highly integrated even in a limited circuit area, and SRA The memory capacity is larger than that of the M. Therefore, the DOSRAM4012 can efficiently store the above input data. It can be stored efficiently.

[0368] NOSRAM4013 is a non-volatile memory that uses OS transistors. The M4013 is a memory card that can be used with flash memory and ReRAM (Resistive Random Access Memory). Access Memory), MRAM (Magnetoresistive Ran Compared to other non-volatile memories such as DDR Memory (DDR3), writing data is It consumes less power when writing data. The elements do not deteriorate when writing, and there is no limit to the number of times data can be written.

[0369] In addition to 1-bit binary data, the NOSRAM4013 can also handle multi-level data of 2 or more bits. NOSRAM4013 can store multi-value data. The memory cell area per bit can be reduced.

[0370] In addition, NOSRAM4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 uses the NOSRAM 4013 as an analog memory. The NOSRAM4013 can also be used as a memory. Therefore, D / A conversion circuits and A / D conversion circuits are not required. The RAM 4013 can reduce the area of ​​the peripheral circuits. Analog data refers to data with a resolution of 3 bits (8 values) or more. Multi-valued data may also be included in analog data.

[0371] The data and parameters used in the neural network calculations are stored in NOSRA. The above data and parameters can be stored in the M4013 via the CPU4021. The data may be stored in a memory provided outside the AI ​​system 4041, but may also be stored in a memory provided inside the AI ​​system 4041. The NOSRAM4013, which is equipped with the DDR3 RAM, stores the above data and parameters at higher speeds and with lower power consumption. The NOSRAM4013 also has a higher bit rate than the DOSRAM4012. Since the bit lines can be made longer, the storage capacity can be increased.

[0372] The FPGA 4014 is an FPGA that uses OS transistors. 1 uses FPGA4014 to implement the deep neural network described below in hardware. Neural Networks (DNN), Convolutional Neural Networks (CNN), Recurrent Neural Networks (RNN) Neural Networks (RNN), Autoencoders, Deep Boltzmann Machines (DBM), Deep It is possible to configure the connections of neural networks, such as layered belief networks (DBNs). By configuring the above neural network connections in hardware, it is possible to achieve higher performance. It can be executed quickly.

[0373] The FPGA 4014 is an FPGA that has OS transistors. The memory area can be made smaller than that of an FPGA that is configured with SRAM. Even if a context switching function is added, the area increase is small. Staging allows data and parameters to be transmitted at high speed.

[0374] The AI ​​system 4041 is composed of an analog arithmetic circuit 4011, a DOSRAM 4012, and an NOS The RAM4013 and FPGA4014 can be mounted on a single die (chip). Therefore, the AI ​​system 4041 is designed to be fast, low power consumption, and to use neural networks. In addition, the analog arithmetic circuit 4011 and the DOSRAM4 The 012, NOSRAM4013, and FPGA4014 are manufactured using the same manufacturing process. Therefore, the AI ​​system 4041 can be manufactured at low cost. .

[0375] The calculation unit 4010 includes a DOSRAM 4012, a NOSRAM 4013, and an FP It is not necessary to have all of GA4014. Depending on the problem that AI system 4041 wants to solve, DOSRAM4012, NOSRAM4013, and FPGA4014. A plurality of the above may be selected and provided.

[0376] AI System 4041 uses deep neural networks to solve various problems. (DNN), Convolutional Neural Network (CNN), Recurrent Neural Network RNN, autoencoder, deep Boltzmann machine (DBM), deep belief network The PROM4025 can implement techniques such as DBN. It is possible to store a program for executing at least one program. Some or all of the program may be stored in NOSRAM 4013.

[0377] Existing programs that exist as libraries are based on GPU processing. Therefore, it is preferable that the AI ​​system 4041 has a GPU 4022. The system 4041 performs the multiply-and-accumulate operation, which is the rate-limiting operation used in learning and inference. The multiplication and accumulation operations can be executed by the calculation unit 4010, and other multiplication and accumulation operations can be executed by the GPU 4022. This allows for faster learning and inference.

[0378] The power supply circuit 4027 not only generates a low power supply potential for the logic circuit but also The power supply circuit 4027 may also use an OS memory. 27 can reduce power consumption by storing the reference potential in the OS memory.

[0379] PMU4028 has the function of temporarily turning off the power supply to AI System 4041. do.

[0380] The CPU 4021 and the GPU 4022 preferably have OS memory as a register. The CPU 4021 and the GPU 4022 have OS memory, so the power supply is Even when the power is turned off, the data (logical values) can still be stored in the OS memory. As a result, the AI ​​system 4041 can save power.

[0381] The PLL 4023 has the function of generating a clock. It operates based on the clock generated by PLL4023. PLL4023 has OS memory. It is preferable that the PLL4023 has an OS memory, which allows the clock oscillation period to be adjusted. The analog potential to be controlled can be held.

[0382] The AI ​​system 4041 may store data in external memory such as DRAM. Therefore, the AI ​​System 4041 uses memory that acts as an interface with external DRAM. It is preferable that the memory controller 4026 is included. It is preferable to place it near the CPU 4021 or the GPU 4022. This allows for high-speed data exchange.

[0383] Some or all of the circuits shown in the control unit 4020 are formed on the same die as the operation unit 4010. By doing so, the AI ​​system 4041 can achieve high speed and low power consumption. Neural network calculations can be performed.

[0384] The data used for neural network calculations is stored in an external storage device (HDD). Hard Disk Drive, SSD (Solid State Drive), etc.) Therefore, the AI ​​system 4041 does not have an interface with an external storage device. It is preferable that the external memory control circuit 4031 functions as an interface.

[0385] Learning and inference using neural networks often involves audio and video, so The I system 4041 has an audio codec 4032 and a video codec 4033 . The audio codec 4032 encodes and decodes audio data. The video codec 4033 encodes and decodes the video data.

[0386] The AI ​​system 4041 performs learning or inference using data obtained from external sensors. Therefore, the AI ​​system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 is, for example, a USB (Universal Ser ial Bus) and I2C (Inter-Integrated Circuit), etc. Includes:

[0387] AI system 4041 uses data obtained via the internet to learn or Therefore, the AI ​​system 4041 can perform inference. It is preferred to have 5.

[0388] The analog arithmetic circuit 4011 uses a multi-value flash memory as an analog memory. However, flash memory has a limit to the number of times it can be rewritten. Flash memory is embedded (the arithmetic circuit and memory are formed on the same die). It is very difficult to

[0389] The analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limit to the number of times it can be rewritten, and there are also problems with memory accuracy. Furthermore, because it is a device with two terminals, the circuit design allows for separate writing and reading of data. It gets complicated.

[0390] Also, the analog arithmetic circuit 4011 may use the MRAM as an analog memory. However, the MRAM has a low resistance change rate and has problems in terms of memory accuracy.

[0391] In view of the above, the analog arithmetic circuit 4011 preferably uses the OS memory as an analog memory. This is preferable.

[0392] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments. This is possible.

[0393] (Embodiment 4) <Application Examples of AI System> In this embodiment, the application examples of the AI system shown in the above embodiment will be described with reference to FIG. 14. This will be described.

[0394] FIG. 14(A) shows an AI system 4041A in which the AI systems 4041 described in FIG. 13 are arranged in parallel and signals can be transmitted and received between the systems via bus lines. The AI system 4041A illustrated in FIG. 14(A) includes a plurality of AI systems 4041_1

[0395] to AI systems 4041_n (n is a natural number). The AI systems 4041_1 to AI systems 4041_n are connected to each other via a bus line 4098. The AI systems 4041_1 to

[0396] Also, FIG. 14(B) shows an AI system 4041B in which the AI systems 4041 described in FIG. 13 are arranged in parallel as in FIG. 14(A) and signals can be transmitted and received between the systems via a network. The AI system 4041B illustrated in FIG. 14(B) includes a plurality of AI systems 4041_1 This is the AI system 4041B.

[0397] The AI system 4041B illustrated in FIG. 14(B) includes a plurality of AI systems 4041_1 The AI ​​systems 4041_1 to 4041_n are 041_n are connected to each other via a network 4099.

[0398] The network 4099 includes the AI ​​systems 4041_1 to 4041_n. Each of them may be provided with a communication module, and configured to perform wireless or wired communication. The communication module can communicate via an antenna. For example, World Wi The Internet, intranets, and extranets that form the foundation of the World Wide Web (WWW) PAN (Personal Area Network), LAN (Local A rea Network), CAN (Campus Area Network), MA N (Metropolitan Area Network), WAN (Wide Ar Network), GAN (Global Area Network), etc. It is possible to connect each electronic device to a computer network and communicate with it. In this case, LTE (Long Term Evolution) is used as the communication protocol or technology. ), GSM (Global System for Mobile Comm) unication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Divisi on Multiple Access 2000), W-CDMA (registered trademark), etc. Communication standards, such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigB Specifications standardized by IEEE, such as ee (registered trademark), can be used.

[0399] By using the configurations shown in Fig. 14(A) and Fig. 14(B), the analysis obtained by an external sensor etc. Log signals can be processed by separate AI systems, e.g., biometrics, brain The information such as brain wave, pulse, blood pressure, and body temperature is transmitted through a brain wave sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor. The analog signals can be acquired by various sensors such as sensors, and processed by separate AI systems. By processing signals or learning in separate AI systems, a single AI can be realized. The amount of information processing per system can be reduced, so signals can be processed with less calculations. As a result, recognition accuracy can be improved. The information obtained from this AI system allows for instant and comprehensive understanding of complex changes in biological information. It is expected that you will be able to grasp it.

[0400] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0401] (Embodiment 5) In this embodiment, an example of an IC in which the AI ​​system shown in the above embodiment is incorporated will be described. vinegar.

[0402] The AI ​​system shown in the above embodiment is a digital processor such as a CPU, which is made up of Si transistors. logic circuits, analog arithmetic circuits using OS transistors, OS-FPGA and DOSR OS memory such as AM and NOSRAM can be integrated onto a single die.

[0403] Figure 15 shows an example of an IC incorporating an AI system. C7000 has leads 7001 and a circuit portion 7003. AI system IC 700 0 is mounted on, for example, a printed circuit board 7002. These are electrically connected to each other on the printed circuit board 7002, and electronic components are mounted. The circuit portion 7003 has the same structure as that shown in the above embodiment mode. The various circuits described above are provided on one die. As shown in the figure, it has a laminated structure, and is made up of a Si transistor layer 7031, a wiring layer 7032, an OS transistor layer 7033, and a The OS transistor layer 7033 is divided into a Si transistor layer 703 1, making it easy to miniaturize the AI ​​system IC7000. .

[0404] In Figure 15, the AI ​​system IC7000 is packaged in a QFP (Quad Flat Packaging) However, the form of the package is not limited to this.

[0405] Digital processing circuits such as CPUs and analog arithmetic circuits using OS transistors, FPGAs and OS memories such as DOSRAM and NOSRAM are all made of Si transistors. layer 7031, a wiring layer 7032, and an OS transistor layer 7033. In other words, the elements that make up the AI ​​system can be formed in the same manufacturing process. Therefore, the IC shown in this embodiment can be manufactured in a simple manner even if the number of constituent elements increases. There is no need to increase the number of servers, and the AI ​​system can be incorporated at low cost.

[0406] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0407] (Sixth embodiment) <Electronic equipment> A semiconductor device according to one embodiment of the present invention is a processor such as a CPU or a GPU, or 16 to 18 show examples of a CPU and a GP according to one embodiment of the present invention. Specific examples of electronic devices equipped with a processor such as U or a computer are given below.

[0408] <Electronic devices and systems> A processor such as a CPU or a GPU, or a computer according to one embodiment of the present invention can The present invention can be mounted on electronic devices, such as television sets, Desktop or notebook personal computers, computer monitors, etc. digital signage, pachinko machines, etc. In addition to electronic devices with relatively large screens such as large game consoles, digital cameras, Digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals Furthermore, an integrated circuit or a computer according to one embodiment of the present invention can be used in a variety of applications. By providing a computer in an electronic device, it is possible to equip the electronic device with artificial intelligence.

[0409] The electronic device according to one embodiment of the present invention may include an antenna. This allows the display of images, information, etc. on the display unit. In the case where the device has a secondary battery, the antenna may be used for contactless power transmission.

[0410] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, etc.). , distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared radiation) It may be possible.

[0411] The electronic device according to one embodiment of the present invention can have various functions. Still images, videos, text images, etc.) on the display, touch panel function, calendar It has the functions of displaying the date, time, etc., and running various software (programs). functions, wireless communication functions, and functions to read programs or data recorded on recording media. The electronic device may have the following functions: Fig. 16 shows an example of the electronic device.

[0412] [mobile phone]

[0413] FIG. 16(A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510. It is prepared for.

[0414] The information terminal 5500 uses artificial intelligence by applying a computer according to one embodiment of the present invention. It is possible to run applications that utilize artificial intelligence. For example, an application that recognizes a conversation and displays the conversation content on the display unit 5511 may be used. The display unit 5511 displays characters, figures, etc. that the user inputs to the touch panel. It recognizes the user's identity and displays the application on the display unit 5511, and performs biometric authentication such as fingerprint and voiceprint authentication. Examples of applications include:

[0415] [Information terminal] 16(B) shows a desktop information terminal 5300. The information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard. 5303 and has.

[0416] The desktop information terminal 5300 is an embodiment of the present invention, similar to the information terminal 5500 described above. By applying such computers, it is possible to execute applications that utilize artificial intelligence. Examples of applications that use artificial intelligence include design support software. These include software for writing correction, software for automatically generating menus, etc. By using the desktop information terminal 5300, new artificial intelligence can be developed. .

[0417] In the above description, a smartphone and a desktop information terminal are used as examples of electronic devices. As shown in Figures 16(A) and 16(B), the smartphone and desktop It can be applied to information terminals other than smartphones and desktops. Examples of information terminals other than information terminals include PDAs (Personal Digital Assistants). Assistant), notebook information terminals, and workstations.

[0418] [electric appliances] FIG. 16(C) shows an electric refrigerator-freezer 5800, which is an example of the electric appliance. The refrigerator 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. .

[0419] By applying a computer according to one embodiment of the present invention to the electric refrigerator-freezer 5800, It is possible to realize an intelligent electric refrigerator-freezer 5800. Using artificial intelligence Electric refrigerator-freezer 5800 is a refrigerator-freezer that can It has a function to automatically generate menus based on the expiration dates of ingredients, and stores them in an electric refrigerator / freezer (5800). It can have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0420] In this example, an electric refrigerator-freezer was described as an electrical appliance, but other electrical appliances may also be used. For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water boilers, induction cookers, Water server, heating and cooling appliances including air conditioner, washing machine, dryer, Examples include audiovisual equipment.

[0421] [Game consoles]

[0422] FIG. 16(D) shows a portable game machine 5200, which is an example of a game machine. The device includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0423] By applying a GPU or a computer according to one embodiment of the present invention to the portable game console 5200, This makes it possible to realize a portable game machine 5200 with low power consumption. This reduces heat generated by the circuit, preventing damage to the circuit itself, peripheral circuits, and And the impact on the module can be reduced.

[0424] Furthermore, the GPU or computer according to one embodiment of the present invention may be applied to the portable game machine 5200. This makes it possible to realize a portable game machine 5200 with artificial intelligence.

[0425] Originally, it was a representation of the game's progress, the behavior of the creatures that appear in the game, and the phenomena that occur in the game. Currently, the game is determined by the program that the game has, but the portable game console 5200 By applying artificial intelligence to the game, it becomes possible to express things that are not limited to game programs. For example, the content of the player's questions, the game progress, the time, and the characters that appear in the game. It becomes possible to express things such as a character's words and actions changing.

[0426] Also, when playing games that require multiple players on the handheld game console 5200, the AI Therefore, it is possible to create anthropomorphic game players, and opponents can be controlled by artificial intelligence. By having multiple game players, the game can be played by one person.

[0427] In FIG. 16(D), a portable game machine is illustrated as an example of a game machine. The game machine to which the GPU or computer of the present invention is applied is not limited to this. Examples of game machines that use the GPU or computer include home-use stationary game machines. arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), Examples include pitching machines for batting practice installed at sports facilities.

[0428] [Moving object] The GPU or computer of one embodiment of the present invention is used in a vehicle, which is a moving object, and a driver's seat of the vehicle. It can be applied to the surrounding area.

[0429] FIG. 16(E1) shows an automobile 5700 as an example of a moving object, and FIG. 16(E2) shows an automobile FIG. 16(E2) shows the area around the windshield in the interior of the vehicle. In addition to the display panel 5701, the display panel 5702, and the display panel 5703 attached to the board , showing a display panel 5704 mounted on a pillar.

[0430] The display panels 5701 to 5703 display a speedometer, a tachometer, a driving It can provide a variety of information, including distance, fuel level, gear status, air conditioning settings, and more. In addition, the display items and layout displayed on the display panel can be customized to suit the user's preferences. The display panel 5701 can be changed as needed, enhancing the design. The display panel 5703 can also be used as a lighting device.

[0431] The display panel 5704 displays images from an imaging device (not shown) provided in the automobile 5700. By projecting images, it is possible to compensate for the blind spots obstructed by the pillars. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, This can compensate for blind spots and increase safety. By doing so, the driver can check for safety more naturally and without any discomfort. 4 can also be used as a lighting device.

[0432] Since the GPU or computer according to one aspect of the present invention can be used as a component of artificial intelligence, For example, the computer can be used in an automated driving system for the automobile 5700. In addition, the computer can be used in systems that provide road guidance, risk prediction, etc. The display panels 5701 to 5704 display information such as road guidance and risk prediction. The configuration shown below may also be used.

[0433] In the above description, an automobile is used as an example of a moving body. For example, the moving object may be a train, a monorail, a ship, or an aircraft (helicopter). , unmanned aerial vehicles (drones), airplanes, rockets, etc., and these movements Applying a computer according to one aspect of the present invention to the body gives it a system that utilizes artificial intelligence. It is possible.

[0434] [Broadcasting System] The GPU or computer according to one aspect of the present invention can be applied to a broadcasting system.

[0435] Figure 16(F) shows a schematic diagram of data transmission in a broadcasting system. FIG. 16(F) shows how radio waves (broadcast signals) transmitted from a broadcasting station 5680 are transmitted to television stations in each home. The TV 5600 is a receiving device. The broadcast signal received by the antenna 5650 is transmitted to the receiving device (not shown). The data is then sent to the TV5600 via the internet.

[0436] In FIG. 16(F), the antenna 5650 is a UHF (Ultra High Frequency) ncy) antenna is shown, but as antenna 5650, BS·110°CS antenna Antennas, CS antennas, etc. can also be applied.

[0437] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 receives them. The received radio wave 5675A is amplified and transmitted as radio wave 5675B. By receiving radio waves 5675B on 5650, you can watch terrestrial TV broadcasts on TV5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 16(F), but may be any other type of broadcasting system. It may also be satellite broadcasting using a satellite, data broadcasting via optical fiber lines, or the like.

[0438] The above-described broadcasting system uses a computer according to one aspect of the present invention and utilizes artificial intelligence. A broadcasting system may be configured in which broadcast data is transmitted from a broadcasting station 5680 to a TV 5600 in each home. When transmitting, the broadcast data is compressed by an encoder, and the antenna 5650 When broadcast data is received, the decoder of the receiving device included in the TV 5600 converts the broadcast data into By using artificial intelligence, for example, the encoder pressure In motion compensation prediction, which is one of the reduction methods, the display pattern contained in the displayed image is recognized. It is also possible to perform intra-frame prediction using artificial intelligence. For example, low-resolution broadcast data is received and the high-resolution TV 5600 displays the broadcast data. When displaying the data, the decoder restores the broadcast data, and the data is up-converted. Any image can be interpolated.

[0439] The AI-based broadcasting system described above is expected to be a key component of the ultra-high definition television broadcasting system, which will see an increase in the amount of broadcast data. It is suitable for HDTV (UHDTV: 4K, 8K) broadcasting.

[0440] In addition, as an application of artificial intelligence on the TV5600 side, for example, By configuring in this way, the recording device may be provided with By having AI learn user preferences, programs that match the user's preferences can be automatically recorded. It is possible.

[0441] <Parallel computer> A parallel computer is configured by forming a cluster using a plurality of computers according to one embodiment of the present invention. It is possible.

[0442] FIG. 17(A) illustrates a large-scale parallel computer 5400. In the example shown, a rack 5410 houses a plurality of rack-mounted computers 5420 .

[0443] The computer 5420 can have the configuration shown in the perspective view of FIG. In 7(B), a computer 5420 has a motherboard 5430, which includes: It has a plurality of slots 5431. A PC card 5421 is inserted into the slot 5431. In addition, the PC card 5421 has a connection terminal 5423, a connection terminal 5424, and a connection terminal Each of the controllers has a plurality of sub-controllers 5425 connected to a motherboard 5430 .

[0444] The PC card 5421 is a processing board equipped with a CPU, a GPU, a storage device, etc. For example, in FIG. 17C, a PC card 5421 has a board 5422. However, the connection terminal 5423, the connection terminal 5424, the connection terminal 5425, the chip 5426, 17(C) shows a configuration having a chip 5427 and a connection terminal 5428. Although chips other than chip 5426 and chip 5427 are shown in the figure, these chips For details of chips, please refer to the explanations of chips 5426 and 5427 below. .

[0445] The connection terminal 5428 has a shape that allows it to be inserted into a slot 5431 of a motherboard 5430. The connection terminal 5428 connects the PC card 5421 to the motherboard 5430. The standard for the connection terminal 5428 is, for example, For example, PCIe is one example.

[0446] The connection terminals 5423, 5424, and 5425 are, for example, a PC card 542 1, it can be used as an interface for supplying power, inputting signals, etc. In addition, for example, the interface for outputting signals calculated by the PC card 5421 is The connection terminal 5423, the connection terminal 5424, and the connection terminal 54 The 25 standards include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Compute r System Interface). Also, connection terminal 5423, When outputting video signals from connection terminals 5424 and 5425, the respective standards are Examples of such standards include HDMI (registered trademark).

[0447] The chip 5426 has a terminal (not shown) for inputting and outputting signals. By inserting the PC card 5421 into a socket (not shown), The chip 5426 can be electrically connected to the PC card 5421. For example, the processor may be the GPU described above.

[0448] The chip 5427 has a plurality of terminals, and the terminals are connected to the wiring of the PC card 5421. For example, by reflow soldering the wire, the chip 5427 and the PC card The chip 5427 can be electrically connected to the board 5421. Examples include memory devices, FPGAs, and CPUs.

[0449] The computer according to one embodiment of the present invention is a computer 54 of a parallel computer 5400 shown in FIG. 20, for example, to perform large-scale calculations required for AI learning and inference. It is possible.

[0450] <Servers and systems including servers> The computer according to one aspect of the present invention is applied to, for example, a server that functions on a network. This also makes it possible to configure a system that includes the server.

[0451] FIG. 18A shows an example of a server 5100 to which a computer according to one embodiment of the present invention is applied. and the information terminal 5500 and the desktop information terminal 5300 described above. 18(A) shows a schematic diagram of the communication. , communication 5110 is shown.

[0452] By configuring in this manner, the user can use the information terminal 5500, the desktop information terminal 5500, and the like. The server 5100 can be accessed from a terminal 5300 or the like. The user receives the information provided by the administrator of the server 5100 through communication 5110 via the Internet. Such services include, for example, e-mail, SN S (Social Networking Service), online software , cloud storage, navigation systems, translation systems, internet games , online shopping, financial transactions such as stocks, foreign exchange, and bonds, public facilities, commercial facilities, and accommodation Examples include making reservations at facilities and hospitals, and watching videos of internet programs, lectures, and other programs. can be.

[0453] In particular, by applying the computer according to one embodiment of the present invention to the server 5100, the above-described In some cases, artificial intelligence can be used in services such as navigation. By introducing artificial intelligence into the system, the system can detect road congestion, Depending on the vehicle operation information, etc., it may be possible to guide you to your destination flexibly. For example, by introducing artificial intelligence into a translation system, the system can In some cases, it may be possible to appropriately translate unique expressions such as language. By using artificial intelligence in the reservation system of a clinic, the system can Based on the symptoms and severity of the injury, we can refer you to an appropriate hospital or clinic. There is a match.

[0454] In addition, when a user wants to develop artificial intelligence, the user can access the server 5100 via the Internet. The development can be carried out on the server 5100 by accessing the The original information terminal 5500, desktop information terminal 5300, etc. do not have enough processing power. If this is not possible, a development environment can be constructed using the information terminal 5500 or the desktop information terminal 5300. This is suitable when there is no

[0455] In FIG. 18A, a system including a server is configured by an information terminal and a server 5100. However, as another example, it is possible to use an electronic device other than an information terminal. The system may be configured by the electronic device and the server 5100. As a form of IoT (Internet of Things) connected to the Internet good.

[0456] FIG. 18(B) shows, as an example, the electronic devices (electric refrigerator-freezer 5800, portable Communication is performed between the mobile game console 5200, the car 5700, and the TV 5600 and the server 5100. In FIG. 18(B), the communication is shown as follows. 5110 is shown.

[0457] When applying artificial intelligence to each electronic device described in FIG. 16, the following is shown in FIG. 18(B). The calculations required to operate the artificial intelligence can be executed by the server 5100. For example, input data required for calculation is transmitted to each electronic device via communication 5110. The server 5100 then sends the data to the server 5100, which then uses the artificial intelligence of the server 5100 to Output data is calculated based on the input data, and the output data is sent to the server via communication 5110. The data is transmitted from the server 5100 to one of the electronic devices. As a result, one of the electronic devices It can perform actions based on the input data.

[0458] The electronic device shown in FIG. 18(B) is an example, and electronic devices not shown in FIG. 18(B) are also supported. The communication device may be connected to a server 5100 and configured to communicate with each other in the same manner as described above.

[0459] The electronic devices described in the present embodiment, the functions of the electronic devices, application examples of artificial intelligence, and their effects, etc. These may be combined with descriptions of other electronic devices as appropriate.

[0460] (Embodiment 7) This embodiment mode will describe an application example of a memory device using the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can be used in various electronic devices (for example, Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video playback devices, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (for example, D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 19 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a flash memory and used in various storage devices and removable memory.

[0461] 19A is a schematic diagram of a USB memory. The USB memory 1100 is a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0462] Figure 19(B) is a schematic diagram of the external appearance of an SD card, and Figure 19(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 is a schematic diagram of the structure. The SD card 1110 comprises a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, the SD card 1110 The capacity can be increased. In addition, a wireless chip having a wireless communication function can be installed on the substrate 1113. This allows the host device and the SD card 1110 to communicate wirelessly. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0463] FIG. 19(D) is a schematic diagram of the external appearance of the SSD, and FIG. 19(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a memory The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DRAM chip may be used. A memory chip 1154 is also provided on the back side of the substrate 1153. By providing the memory chip 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0464] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done. [Explanation of symbols]

[0465] 100: Capacity, 100a: Capacity, 100A: Capacity, 100b: Capacity, 100B: Capacity, 1 10: conductor, 120: conductor, 130: insulator, 150: insulator, 160: conductor, 2 00:Transistor, 200a:Transistor, 200A:Transistor, 200b:Transistor Transistor, 200B: Transistor, 205: Conductor, 205A: Conductor, 205B: Conductor, 207: Insulator, 207a: Insulator, 207b: Insulator, 208: Conductor, 20 8a: conductor, 208A: conductor, 208b: conductor, 208B: conductor, 209: conductor body, 211: conductor, 211a: conductor, 211b: conductor, 214: insulator, 216: Insulator, 220: Insulator, 222: Insulator, 224: Insulator, 226: Insulator, 230: oxide, 230a: oxide, 230b: oxide, 230c: oxide, 239: region, 24 0: conductor, 242: conductor, 242a: conductor, 242b: conductor, 242c: conductor ,243: region, 243a: region, 243b: region, 243c: region, 244: insulator, 250: insulator, 260: conductor, 260a: conductor, 260A: conductor, 260b: conductor Conductor, 260B: Conductor, 270: Insulator, 271: Insulator, 272: Insulator, 273: Insulator, 274: Insulator, 275: Insulator, 280: Insulator, 281: Insulator, 282: Insulator, 300: transistor, 300a: transistor, 300A: transistor, 3 00b: transistor, 300B: transistor, 301: semiconductor layer, 311: substrate, 3 13: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 3 16: Conductor, 316A: Conductor, 316B: Conductor, 317: Insulator, 320: Insulator , 321: insulator, 322: insulator, 600: cell, 600A: memory cell, 600B: Memory cell, 1005: Wiring, 1100: USB memory, 1101: Housing, 1102: cap, 1103: USB connector, 1104: board, 1105: memory chip, 110 6: Controller chip, 1110: SD card, 1111: Housing, 1112: Connector , 1113: Substrate, 1114: Memory chip, 1115: Controller chip, 1150 :SSD, 1151:Housing, 1152:Connector, 1153:Board, 1154:Memory chip chip, 1155: memory chip, 1156: controller chip, 1400: DOSRA M, 1600: NOSRAM, 1610: memory cell array, 1611: memory cell,1 612: memory cell, 1613: memory cell, 1614: memory cell, 1615: memory Cell, 1615a: memory cell, 1615b: memory cell, 1640: controller, 1 650: row driver, 1651: row decoder, 1652: word line driver, 1660: Column driver, 1661: column decoder, 1662: driver, 1663: DAC, 1670 : Output driver, 1671: Selector, 1672: ADC, 1673: Output buffer, 2 000: CDMA, 4010: Calculation unit, 4011: Analog calculation circuit, 4012: DOS RAM, 4013: NOSRAM, 4014: FPGA, 4020: Control unit, 4021: CPU, 4022: GPU, 4023: PLL, 4024: SRAM, 4025: PRO M, 4026: Memory controller, 4027: Power supply circuit, 4028: PMU, 4030 : Input / output unit, 4031: External memory control circuit, 4032: Audio codec, 4033: Video Codec, 4034: General-purpose input / output module, 4035: Communication module, 4041: AI system, 4041A: AI system, 4041B: AI system, 4098: Bus Line, 4099: Network, 5100: Server, 5110: Communication, 5200: Mobile game System unit, 5201: Housing, 5202: Display unit, 5203: Buttons, 5300: Desktop Type information terminal, 5301: main body, 5302: display, 5303: keyboard, 540 0:Parallel computer, 5410:Rack, 5420:Computer, 5421:PC card, 542 2: Board, 5423: Connection terminal, 5424: Connection terminal, 5425: Connection terminal, 5426 : Chip, 5427: Chip, 5428: Connection terminal, 5430: Motherboard, 5431 : slot, 5432: connection terminal, 5433: connection terminal, 5500: information terminal, 5510 : Housing, 5511: Display, 5600: TV, 5650: Antenna, 5670: Radio tower, 5675A: Radio waves, 5675B: Radio waves, 5680: Broadcasting stations, 5700: Automobiles, 5701 : display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer Door, 7000: AI system IC, 7001: Lead, 7002: Printed circuit board, 70 03: Circuit section, 7004: Mounting board, 7031: Si transistor layer, 7032: Wiring layer ,7033:OS transistor layer

Claims

1. a first memory cell and a second memory cell; the first memory cell includes a first transistor and a second transistor; the second memory cell has a third transistor and a fourth transistor; one of a source or a drain of the first transistor, one of a source or a drain of the second transistor, one of a source or a drain of the third transistor, and one of a source or a drain of the fourth transistor are electrically connected to a bit line; a gate of the second transistor is electrically connected to the other of the source and the drain of the first transistor; a gate of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor; an oxide layer, a first conductor, a second conductor, and a third conductor; the oxide layer has a channel formation region of the first transistor and a channel formation region of the third transistor; the first conductor is disposed above and in contact with the oxide layer, and functions as one of a source electrode or a drain electrode of the first transistor and one of a source electrode or a drain electrode of the third transistor; the second conductor has a function of electrically connecting the bit line and the first conductor; the third conductor has a function of electrically connecting one of a source or a drain of the second transistor and one of a source or a drain of the fourth transistor to the second conductor; In a cross-sectional view taken along a channel width direction of the first transistor, the second conductor is disposed so as to straddle the first conductor and the oxide layer.

2. a first memory cell and a second memory cell; the first memory cell includes a first transistor and a second transistor; the second memory cell has a third transistor and a fourth transistor; one of a source or a drain of the first transistor, one of a source or a drain of the second transistor, one of a source or a drain of the third transistor, and one of a source or a drain of the fourth transistor are electrically connected to a bit line; a gate of the second transistor is electrically connected to the other of the source and the drain of the first transistor; a gate of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor; an oxide layer, a first conductor, a second conductor, and a third conductor; the oxide layer has a channel formation region of the first transistor and a channel formation region of the third transistor; the first conductor is disposed above and in contact with the oxide layer, and functions as one of a source electrode or a drain electrode of the first transistor and one of a source electrode or a drain electrode of the third transistor; the second conductor has a function of electrically connecting the bit line and the first conductor; the third conductor has a function of electrically connecting one of a source or a drain of the second transistor and one of a source or a drain of the fourth transistor to the second conductor; a fourth region in contact with the top surface of the first conductor, a fifth region in contact with a second side surface of the first conductor opposite to the first side surface, a sixth region in contact with a second side surface of the oxide layer opposite to the first side surface, and a seventh region separated from the first region and in contact with the top surface of the third conductor.

Images