A / d converter and a / d conversion method

Abstract

To obtain an A / D converter and an A / D conversion method capable of improving linearity of A / D conversion.SOLUTION: A control part CNTL controls a plurality of switches SW0 to SW7 to sample an analog signal at a lower-side common terminal LCT and an upper-side common terminal UCT, then performs binary search, and a comparator CMP outputs an A / D conversion result, thereby performing A / D conversion. The control part CNTL controls a capacitance value of a variable capacitor CC so that an output frequency of the A / D conversion result in which a lower bit is all 1 is equal to the output frequency of the A / D conversion result in which the lower bit is all 0. When the lower bit of the A / D conversion result is all 1 or all 0, the control part CNTL applies a voltage corresponding to the least significant bit or a negative number thereof as an offset to the sampled analog signal every other time from the next A / D conversion, subtracts a digital value corresponding to the applied offset from the A / D conversion result, and outputs the result as a digital signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to an A / D converter and an A / D conversion method. [Background technology]

[0002] In recent years, especially in CMOS process nodes of 0.18 μm and below, short channel effects have deteriorated saturation region characteristics (VDS-IDS characteristics) and lowered power supply voltages. These have been adverse effects on the design of analog circuits such as amplifiers. This impact is particularly significant in pipelined A / D converters that rely on amplification by amplifier circuits.

[0003] In contrast, successive approximation register analog-to-digital converters (SAR ADCs) do not require amplifiers and can be designed with comparators using switches and strong-arm latches. This results in a circuit configuration that is closer to the operation of digital circuits. As a result, they can benefit from miniaturization processes, giving them an advantage in terms of power efficiency.

[0004] Charge redistribution capacitive D / A converters (hereafter referred to as CDACs) contribute to improving the power efficiency of SAR ADCs. However, because CDACs are basically composed of capacitance elements weighted by a power of 2 (2N), the area required increases exponentially as the resolution improves. To address this area issue, a bridge capacitance C B Split-CDAC has been proposed, which combines the upper and lower bits to form a single CDAC (see, for example, Non-Patent Document 1). For example, in the case of 8-bit resolution, a normal CDAC requires 256C if the capacitance value of the unit capacitor is C. On the other hand, if the Split-CDAC is configured with 4 bits on the upper side and 4 bits on the lower side, the required capacitance is 15C + 16C + C. B =31C+C B Therefore, the unit capacity can be reduced to about 1 / 8.

[0005] In analog circuits, relative accuracy is generally obtained by the ratio of the number of identical physical patterns implemented. However, it is difficult to obtain accuracy when implementing elements with a non-integer ratio that cannot be expressed as the ratio of the number of implementation patterns when implementing elements. Also, C, which corresponds to the lower bits of the A / D converter, B The parasitic capacitance of the lower node makes the C B The capacitance value of this C B The difference between the theoretical value of the variable capacitance C and the capacitance value including the parasitic capacitance causes a differential non-linearity error (DNL). C It has been proposed to compensate for the error between the upper and lower CDACs by adjusting the capacitance values ​​of the CDACs (see, for example, Non-Patent Document 2). [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Institute of Electronics, Information and Communication Engineers "Knowledge Base: A / D Converter" [Non-patent document 2] X. Zhu et al., “A 9-bit 100MS / s SAR ADC with Digitally Assisted Background Calibration”, IEICE Tran. on Electronics 2012, E95 C. Summary of the Invention [Problem to be solved by the invention]

[0007] Bridge capacitance C B is connected between the upper CDAC and the lower CDAC, so when a carry occurs from the lower bit to the upper bit, C B affects the linearity of the A / D conversion. BTo the extent that this affects linearity, the analog signal must be uniformly distributed and not a "DC" voltage.

[0008] However, for example, Non-Patent Document 2 uses a method called Tri-Level CDAC with 9 bits D8 to D0, which causes missing codes or wide codes at "31" to "32," "63" to "64," "95" to "96," ... "479" to "480," where a carry occurs from the lower to the higher bits of the 512 gradations, impairing the linearity of the A / D conversion (see Figures 3 and 4 in Non-Patent Document 2). For example, if a "DC" voltage equivalent to "31" is continuously applied, it will not function properly.

[0009] Specifically, the output frequency at which the A / D conversion result (output code) becomes "31" is P 31 , the output frequency that becomes "30" is P 30 Then, C B >Optimal value for P 31 <P 30 In the method of Non-Patent Document 2, this is detected and C C Increase the C B By making it appear smaller, P 31 =P 30 For example, when a DC voltage equivalent to "31" is applied, P 31 >P 30 This is detected as P 31 C until B C to make it look smaller C As a result, a "chord drop" occurs where "31" is not output. B When a "DC" voltage in a range that affects linearity error was input, the corresponding digital signal was not output correctly, causing a problem with the linearity of the A / D conversion.

[0010] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide an A / D converter and an A / D conversion method that can improve the linearity of A / D conversion. [Means for solving the problem]

[0011] The A / D converter according to the present disclosure includes an input terminal to which an analog signal is input, a plurality of lower-side capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to a lower-side common terminal, a plurality of upper-side capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to an upper-side common terminal, a bridge capacitor connected between the lower-side common terminal and the upper-side common terminal, a plurality of switches connecting the other ends of the plurality of lower-side capacitors and the other ends of the plurality of upper-side capacitors to the input terminal, a reference voltage terminal, or a ground terminal, respectively, a comparator that compares a voltage of the upper-side common terminal with a reference voltage and outputs an A / D conversion result, a variable capacitor connected between the lower-side common terminal and the ground terminal, and a control unit that controls switching of the plurality of switches and the capacitance values ​​of the variable capacitors, A / D conversion is performed by a control unit controlling the plurality of switches to sample the analog signal to the lower common terminal and the upper common terminal, and then performing a binary search, and the comparator outputting the A / D conversion result, and the control unit controls the capacitance value of the variable capacitor so that the output frequency of the A / D conversion result whose lower bits are all 1 is the same as the output frequency of the A / D conversion result whose lower bits are all 0, and when the lower bits of the A / D conversion result are all 1 or all 0, the control unit applies a voltage equivalent to the least significant bit or its negative to the sampled analog signal as an offset every other A / D conversion from the next A / D conversion, and subtracts a digital value equivalent to the applied offset from the A / D conversion result to output the result as a digital signal. [Effects of the Invention]

[0012] The present disclosure makes it possible to improve the linearity of A / D conversion. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a diagram illustrating an optical transmission system according to an embodiment. [Figure 2] 1 is a circuit diagram illustrating an A / D converter according to an embodiment. [Figure 3] FIG. 2 is a timing diagram of the A / D converter according to the embodiment. [Figure 4] 4 is a flowchart of the operation of the A / D converter according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] 1 is a diagram showing an optical transmission system according to an embodiment. The optical transmission system includes a transmission signal processing circuit 1, a transmission optical module 2, a reception optical module 3, and a reception signal processing circuit 4. The transmission optical module 2 and the reception optical module 3 are connected by an optical fiber 5.

[0015] The transmission signal input to the transmission signal processing circuit 1 undergoes preliminary waveform compensation processing and error correction coding in the transmission digital signal processing circuit 6. The D / A converter 7 converts the output signal of the transmission digital signal processing circuit 6 into an analog electrical signal.

[0016] The transmitting optical module 2 converts the output signal of the D / A converter 7 into an optical signal using a laser diode and transmits it to the receiving side through the optical fiber 5. On the receiving side, the receiving optical module 3 converts the received optical signal into an analog electrical signal. The A / D converter 8 converts the output signal of the receiving optical module 3 into a digital electrical signal. The receiving digital signal processing circuit 9 performs chromatic dispersion compensation, polarization dispersion compensation, error correction, etc. on the output signal of the A / D converter 8.

[0017] Note that FIG. 1 shows how transmission data is separated into an X-polarized signal and a Y-polarized signal and transmitted from the transmitting side to the receiving side. However, the present disclosure is not limited to the above configuration and can also be applied to transmission using only one of the polarized waves. In that case, the polarization combining and polarization splitting circuits are not required. Furthermore, the present disclosure is not limited to optical communication shown in FIG. 1 and can also be applied to wireless communication or other types of communication.

[0018] 2 is a circuit diagram showing an A / D converter according to an embodiment. This A / D converter is a successive approximation register A / D converter (SAR ADC) having a charge redistribution type capacitive D / A converter (CDAC). The CDAC connects a 4-bit upper CDAC and a 4-bit lower CDAC via bridge capacitance C B The "successive approximation" type refers to a method in which a single comparator repeatedly performs magnitude comparisons.

[0019] One end of each of the plurality of lower-side capacitances C0 to C3 is connected in parallel to the lower-side common terminal LCT. The lower-side capacitances C0 to C3 have capacitance values ​​1C, 2C, 4C, and 8C, respectively, weighted by a binary ratio (C is a predetermined capacitance value). One end of each of the plurality of upper-side capacitances C4 to C7 is connected in parallel to the upper-side common terminal UCT. The upper-side capacitances C4 to C7 have capacitance values ​​1C, 2C, 4C, and 8C, respectively, weighted by a binary ratio. Bridge capacitance C B is connected between the lower common terminal LCT and the upper common terminal UCT. B The ideal value is (15 / 16)C, but in reality the capacitance value is slightly different.

[0020] A plurality of switches SW0 to SW7 connect the other ends of the lower-side capacitors C0 to C3 and the other ends of the upper-side capacitors C4 to C7 to the input terminals V in , reference voltage terminal V ref Connect to either the input terminal V or the ground terminal GND. in An analog signal is input to the reference voltage terminal V ref The reference voltage is applied to the common terminal UCT. The ground terminal GND is grounded. The voltage V of the common terminal UCT is applied to the negative input of the comparator CMP. CDAC is input, and the reference voltage is input to the + input of the comparator CMP. The comparator CMP detects the voltage V of the upper common terminal UCT. CDAC The A / D conversion result is output by comparing the voltage with the reference voltage.

[0021] Variable capacitance C C is connected between the lower common terminal LCT and the ground terminal GND. Offset capacitance C NOne end of the offset capacitance C is connected to the lower common terminal LCT. N has a capacitance of 1C, which corresponds to the least significant bit (LSB) of binary. N is the offset capacitance C N The other end of the reference voltage terminal V ref Or connect to the ground terminal GND.

[0022] The control unit CNTL controls the switching of the switches SW0 to SW7 by control signals D0 to D7, respectively, and controls the switching of the switches SW0 to SW7 by control signals Φ S ´Switch SW S1 ,SW S2 Controls the switching of the control signal D N The offset switch SW N The control unit CNTL controls the switching of the control signal D cal The variable capacitance C C The control unit CNTL is realized by a processing circuit such as a system LSI, but if the processing speed is slow, it can also be realized by a CPU that executes a program stored in memory.

[0023] Next, the operation of the A / D converter according to the embodiment will be described. Fig. 3 is a timing chart of the A / D converter according to the embodiment. Fig. 4 is a flowchart of the operation of the A / D converter according to the embodiment.

[0024] First, the control unit CNTL receives a control signal Φ S Set ´ to “H” and switch SW S1 ,SW S2 is turned on to connect the lower common terminal LCT and the upper common terminal UCT to the reference voltage, and the control signal D N The offset switch SW N Next, the control unit CNTL connects the switches SW7 to SW0 to the input terminal V in This causes analog signals to be applied to the capacitors C7 to C0. Next, the control unit CNTL connects the switch SW S1 ,SW S2When the control signal D is turned off, the analog signal is sampled at the lower common terminal LCT and the upper common terminal UCT (step S2). Next, the control unit CNTL connects the switches SW7 to SW0 to the ground terminal GND and turns off the control signal D N The offset switch SW N Reference voltage terminal V ref Next, the control unit CNTL sequentially connects the switches SW7 to SW0 to the reference voltage terminal V ref and performs a binary search in order from the most significant bit (step S4), and the comparator CMP outputs the A / D conversion result (output code) (step S5). In this way, the control unit CNTL controls the plurality of switches SW7 to SW0 to sample analog signals at the lower common terminal LCT and the upper common terminal UCT, and then performs a binary search, and the comparator CMP outputs the A / D conversion result, thereby performing A / D conversion.

[0025] Here, the bridge capacitance C B is connected between the 4th and 5th bits from the bottom of the CDAC. Therefore, when a carry occurs from the 4th bit from the bottom to the 5th bit, the bridge capacitance C B This affects the linearity of the A / D conversion. For example, the lower 4 bits of "15" are "1111" and the lower 4 bits of "16" are "0000", so when the analog signal is a voltage equivalent to "15" to "16", C B affects linearity.

[0026] Therefore, the control unit CNTL detects whether the A / D conversion result is "15" or "16" (step S6). If the result is not "15" or "16", the bridge capacitance C B does not affect the linearity, the control section CNTL is C The control loop is not executed, and the process returns to step S2 to sample the next analog signal.

[0027] When the control unit CNTL detects that the A / D conversion result is "15" or "16", it turns on the variable capacitor C CThe control circuit CNTL starts the control loop of the comparator CMP. 15 , the output frequency P becomes "16" 16 (Step S7). When the analog signal is uniformly distributed in the voltage range equivalent to "15" to "16", the bridge capacitance C B If the ideal value is (15 / 16)C, then P 15 =P 16 Therefore, the control unit CNTL 15 or P 16 The above A / D conversion is repeated until the count is 511 (step S8). 15 =P 16 The variable capacitance C C (Step S9) For example, the capacitance value of P 16 <P 15 In the case of C B <(15 / 16)C, so P 15 When the count reaches 511, the variable capacitance C C By reducing the capacitance value of B On the other hand, P 16 >P 15 In the case of C B >(15 / 16)C, so P 16 When the count reaches 511, the variable capacitance C C Increase the capacitance value of the bridge capacitance C B This makes the bridge capacitance C B The error from the ideal capacitance value (15 / 16)C is the variable capacitance C C Then, the capacitance value of P 15 and P 16 The count of the variable capacitance C is reset (step S10). Since it is probabilistic whether the A / D conversion result will be "15" or "16", one determination result is not enough to reset the count of the variable capacitance C C Therefore, as mentioned above, by collecting multiple judgment results and using a statistical method (actually majority vote), the variable capacitance C C The capacitance value of the capacitor is controlled.

[0028] However, if the output frequency of "15" and "16" is not uniform and there is a bias, for example, if a DC voltage equivalent to "15" or a sine wave with an upper limit of "15" is input as an analog signal, the variable capacitance C C Adjusting the capacitance value of 15 results in a worsening of differential nonlinearity between "15" and "16." Therefore, for the control loop to function properly, the analog signal must be uniformly distributed within that range, rather than being a "DC" voltage. Therefore, in this embodiment, when the lower bits of the A / D conversion result are all 1s or all 0s ("15" or "16"), a voltage equivalent to the least significant bit or its negative value (+1 LSB or -1 LSB) is applied as an offset to the sampled analog signal every other A / D conversion from the next A / D conversion onwards.

[0029] Specifically, when the lower 4 bits of the A / D conversion result are "1111", the control unit CNTL detects that the least significant bit is "1" and turns on the offset switch SW N is switched to the ground terminal GND (step S11), and the next analog signal is sampled (step S12). N Reference voltage terminal V ref (Step S13). As a result, a voltage equivalent to the least significant bit (+1LSB) is applied as an offset to the analog signal sampled by the CDAC. The comparator CMP A / D converts the analog signal Vin' after the offset is applied (Step S14). Therefore, the A / D conversion result becomes "16". The control unit CNTL 16 The process counts up, subtracts "1" from the A / D conversion result, and outputs "15" as the final digital signal (step S15). After that, the process returns to step S2 and performs the next A / D conversion without adding an offset to the analog signal.

[0030] On the other hand, if the lower 4 bits of the A / D conversion result are "0000", the control unit CNTL detects that the least significant bit is "0" and turns off the offset switch SW N Reference voltage terminal V refDuring binary search, the offset switch SW N is connected to the ground terminal GND. This applies a negative voltage (-1LSB) equivalent to the least significant bit as an offset to the analog signal sampled by the CDAC. As a result, the A / D conversion result of the comparator CMP becomes "15", and the control unit CNTL 15 The process counts up, adds "1" to the A / D conversion result, and outputs "16" as the final digital signal. After that, the process returns to step S2 and performs the next A / D conversion without adding an offset to the analog signal.

[0031] Since the offset is applied according to the least significant bit of the A / D conversion result, the offset is applied even if the next analog signal is not a voltage equivalent to "15" or "16". However, since the A / D conversion result is not "16" or "15", the control unit CNTL 15 or P 16 Therefore, the variable capacitance C C This does not affect the adjustment of

[0032] In addition, the control unit CNTL subtracts a digital value ("+1" or "-1") corresponding to the applied offset (+1LSB or -1LSB) from the A / D conversion result of the comparator CMP to generate the final digital signal D out This will result in a correct A / D conversion result that does not include offset.

[0033] As an example, we will explain the case where a voltage equivalent to "14" to "15" is input as an analog signal. If the least significant bit of the output of the comparator CMP is "0", it is judged as "14", and if the least significant bit is "1", it is judged as "15". If the output code of the comparator CMP is "15", +1LSB is applied to the next analog signal. As a result, the output code of the comparator CMP becomes "16", but the control unit CNTL subtracts "1" and outputs "15" as the final digital signal.

[0034] Next, let us consider the case where a voltage equivalent to "16" to "17" is input as an analog signal. If the least significant bit of the output of the comparator CMP is "0", it is judged as "16", and if the least significant bit is "1", it is judged as "17". If the output code of the comparator CMP is "16", -1LSB is applied to the next analog signal. As a result, the output code of the comparator CMP becomes "15", but the control unit CNTL adds "1" and outputs "16" as the final digital signal.

[0035] Here, an analog signal that is judged to be a "1" digital value has a voltage range equivalent to the least significant bit of "1," from the upper limit to the lower limit. For this reason, for example, if an analog signal close to the upper limit of "1" is input, subtracting the voltage equivalent to the least significant bit from it results in a voltage close to the upper limit of "0." When thermal noise is added to this, it is not necessarily judged to be a "0."

[0036] The voltage equivalent to the least significant bit is the offset capacitance C N When the conversion voltage range of an 8-bit A / D converter is 1V and the input capacitance of the CDAC is 4.1fF, the voltage equivalent to the least significant bit is 1 / (2 8 -1) ≒ 4mV. On the other hand, the thermal noise V n is generally V n 2 = kT / C, where k is the Boltzmann constant, k = 1.380649 × 10 -23 JK -1 For example, if C=4.1fF, V n =1mV. Therefore, the voltage equivalent to the least significant bit is accounted for by thermal noise at a high rate of 1 / 4, which is equivalent to 2σ. For this reason, even if the analog signal is at a voltage equivalent to the center of adjacent decision points, there is a probability of the least significant bit being judged as "1" or "0" being different from the original decision of about 5%. Therefore, even when a voltage equivalent to the least significant bit is applied, A / D conversion is performed as if a fluctuating signal, rather than a constant voltage, was input as an offset.

[0037] As explained above, the bridge capacitance C BIn order to compensate for the error from the ideal capacitance value, the output frequency P 15 and the output frequency P of the A / D conversion result "16" where the lower bits are all 0 16 The variable capacitance C C However, if a DC voltage equivalent to "15" or "16" is input, the A / D conversion result will be biased towards either "15" or "16", so the variable capacitance C C Therefore, in this embodiment, when the lower bits of the A / D conversion result are all 1 or all 0 (when it is "15" or "16"), a voltage equivalent to the least significant bit or its negative value (+1LSB or -1LSB) is applied as an offset to the sampled analog signal every other A / D conversion from the next A / D conversion. This causes the sampled analog signal to vary uniformly within the voltage range equivalent to "15" to "16", thereby reducing the voltage of the variable capacitance C C As a result, a digital signal corresponding to the input analog signal is correctly output without missing codes or wide codes, improving the linearity of the A / D conversion.

[0038] Furthermore, if the offset has periodicity, spurious (unwanted frequency components) will occur at the corresponding frequency. To prevent this, if random numbers are generated using a random number generating circuit such as PN (Pseudo Random Noise), the circuit size will increase, resulting in higher costs. In contrast, in this embodiment, an offset capacitance C N Using this, a voltage equivalent to the least significant bit or its negative value is applied to the analog signal as an offset. Since the voltage equivalent to the least significant bit is highly dominated by thermal noise, it behaves as a non-periodic random number that follows a Gaussian distribution. This makes it possible to prevent spurious signals from occurring without using a random number generation circuit. Since a random number generation circuit is not required, costs can be reduced. [Explanation of symbols]

[0039] C0 to C3 lower side capacitance, C4 to C7 upper side capacitance, C B Bridge capacitance, C C Variable capacitance, C N Offset capacitance, CMP comparator, CNTL control section, GND ground terminal, LCT lower common terminal, SW0 to SW7 switches, SW N Offset switch, UCT Upper common terminal, V in Input terminal, V ref Reference Voltage Terminal

Claims

1. an input terminal to which an analog signal is input; a plurality of lower-side capacitors having capacitance values ​​weighted by a binary ratio and one end of which is connected in parallel to a lower-side common terminal; a plurality of upper side capacitors each having a capacitance value weighted by a binary ratio and one end of which is connected in parallel to the upper side common terminal; a bridge capacitor connected between the lower common terminal and the upper common terminal; a plurality of switches that connect the other ends of the plurality of lower-side capacitors and the other ends of the plurality of upper-side capacitors to any one of the input terminal, the reference voltage terminal, and the ground terminal; a comparator that compares the voltage of the upper common terminal with a reference voltage and outputs an A / D conversion result; a variable capacitor connected between the lower common terminal and the ground terminal; a control unit that controls switching of the plurality of switches and a capacitance value of the variable capacitor, the control unit controls the plurality of switches to sample the analog signal at the lower common terminal and the upper common terminal, and then performs a binary search; and the comparator outputs the A / D conversion result, thereby performing A / D conversion; the control unit controls a capacitance value of the variable capacitor so that an output frequency of the A / D conversion result in which the lower bits are all 1 is equal to an output frequency of the A / D conversion result in which the lower bits are all 0; an A / D converter characterized in that, when the lower bits of the A / D conversion result are all 1s or all 0s, the control unit applies a voltage equivalent to the least significant bit or its negative value as an offset to the sampled analog signal every other A / D conversion from the next A / D conversion, subtracts a digital value equivalent to the applied offset from the A / D conversion result, and outputs the result as a digital signal.

2. 2. The A / D converter according to claim 1, wherein the control unit applies a voltage equivalent to the least significant bit to the sampled analog signal as the offset when the lower bits of the A / D conversion result are all 1's, and applies a negative number of the voltage equivalent to the least significant bit to the sampled analog signal as the offset when the lower bits of the A / D conversion result are all 0's.

3. an offset capacitor having a capacitance value corresponding to the least significant bit of the binary and one end connected to the lower common terminal; an offset switch that connects the other end of the offset capacitor to the reference voltage terminal or the ground terminal, 3. The A / D converter according to claim 2, wherein the control unit applies the offset to the sampled analog signal by controlling the offset switch.

4. an A / D conversion method using an A / D converter including: an input terminal for inputting an analog signal; a plurality of lower-side capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to a lower-side common terminal; a plurality of upper-side capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to an upper-side common terminal; a bridge capacitor connected between the lower-side common terminal and the upper-side common terminal; a plurality of switches connecting the other ends of the plurality of lower-side capacitors and the other ends of the plurality of upper-side capacitors to the input terminal, a reference voltage terminal, or a ground terminal, respectively; a comparator that compares a voltage of the upper-side common terminal with a reference voltage and outputs an A / D conversion result; a variable capacitor connected between the lower-side common terminal and the ground terminal; and a control unit that controls switching of the plurality of switches and the capacitance values ​​of the variable capacitors, a step of performing A / D conversion by the control unit controlling the plurality of switches to sample the analog signal at the lower common terminal and the upper common terminal, and then performing a binary search, and the comparator outputting the A / D conversion result; a step in which the control unit controls a capacitance value of the variable capacitor so that an output frequency of the A / D conversion result in which the lower bits are all 1 is equal to an output frequency of the A / D conversion result in which the lower bits are all 0; and if the lower bits of the A / D conversion result are all 1s or all 0s, the control unit applies a voltage equivalent to the least significant bit or its negative value as an offset to the sampled analog signal every other A / D conversion from the next A / D conversion, subtracts a digital value equivalent to the applied offset from the A / D conversion result, and outputs the result as a digital signal.

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