Semiconductor device manufacturing method

Abstract

To provide a semiconductor device manufacturing method capable of suppressing the occurrence of defects.SOLUTION: A semiconductor device manufacturing method according to an embodiment includes forming a recess on the second surface of a wafer having a first surface on which a semiconductor element is provided and a second surface opposite the first surface, thereby forming a thin plate portion and an annular protrusion portion surrounding the thin plate portion on the second surface. The manufacturing method also includes forming a first film on the second surface. The manufacturing method also includes removing a portion of the first film so that at least a portion of the first film remains at the boundary between the thin plate portion and the annular protrusion portion.SELECTED DRAWING: Figure 1C

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In the manufacturing process of semiconductor devices (such as IGBTs (Insulated Gate Bipolar Transistors) and LV-MOSs (Low-Voltage Metal-Oxide-Semiconductors)), the TAIKO (registered trademark) process involves leaving a ring-shaped thick film (rim) on the outer periphery of the wafer and grinding the inside of the rim to thin the wafer (e.g., silicon thickness). In recent years, the need for further thinning of wafers has increased due to demands for improved device characteristics. However, as wafer thickness continues to decrease, the stress load on the boundary between the rim and the membrane (the ground thin film) can increase. In particular, cracks can develop from this boundary after backside electrode formation or after plating on the frontside electrode, resulting in defects such as wafer breakage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-94661 [Patent Document 2] Patent Publication No. 2021-129000 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-98529 [Patent Document 4] Japanese Patent Application Laid-Open No. 2014-53549 Summary of the Invention [Problem to be solved by the invention]

[0004] A method for manufacturing a semiconductor device that can suppress the occurrence of defects is provided. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to the present embodiment includes forming a recess on a second surface of a wafer having a first surface on which a semiconductor element is provided and a second surface opposite the first surface, thereby forming a thin plate portion and an annular protrusion portion surrounding the thin plate portion on the second surface. The method also includes forming a first film on the second surface. The method also includes removing a portion of the first film so that at least a portion of the first film remains at the boundary between the thin plate portion and the annular protrusion. [Brief explanation of the drawings]

[0006] [Figure 1A] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 1B] 1B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. 1A. [Figure 1C] 1C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. 1B. [Figure 1D] 1D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 1C. [Figure 1E] 1D, a cross-sectional view showing an example of a method for manufacturing a semiconductor device. [Figure 2] 1 is a top view showing an example of the configuration of a semiconductor wafer according to a first embodiment. [Figure 3] 1 is a cross-sectional view showing an example of the configuration of a semiconductor wafer according to a first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a stress simulation according to the first embodiment. [Figure 5A] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 5B] 5B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 5B. [Figure 5D] 5D is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 5C. [Figure 6]FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor wafer according to a second embodiment. [Figure 7A] 10A to 10C are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the third embodiment. [Figure 7B] 7B is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 7A. FIG. [Figure 7C] FIG. 7C is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 7B. [Figure 8] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor wafer according to a third embodiment. [Figure 9A] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 9B] 9B is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 9A. FIG. [Figure 9C] 9C is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 9B. [Figure 9D] 9D is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 9C. [Figure 9E] FIG. 9D is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, following FIG. 9D. [Figure 10] FIG. 10 is a top view showing an example of the configuration of a semiconductor wafer according to a fourth embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor wafer according to a fourth embodiment. [Figure 12] FIG. 10 is a diagram illustrating an example of a stress simulation according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual, and the proportions of the various parts are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] (First embodiment) 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a first embodiment.

[0009] The semiconductor wafer W has a first surface F1 and a second surface F2 opposite to the first surface. A semiconductor element E is provided on the first surface F1. Prior to the step shown in FIG. 1A, a protective film (not shown) for protecting the semiconductor element E is formed on the first surface F1.

[0010] First, as shown in FIG. 1A, a recess R is formed on the second surface F2 of the semiconductor wafer W, thereby forming a thin plate portion F2a (membrane portion) and an annular protrusion F2b (rim portion) on the second surface F2. The rim portion F2b is formed so as to surround the membrane portion F2a on the outer periphery of the semiconductor wafer W. The recess R is formed in a central region of the second surface F2 that overlaps with at least the semiconductor element E when viewed from a direction substantially perpendicular to the semiconductor wafer W. The recess R has, for example, a substantially circular shape when viewed from the second surface F2 side (see FIG. 2).

[0011] Next, as shown in FIG. 1B, a first film 10 is formed on the second surface F2. More specifically, an inorganic insulating film 11 is formed on the second surface F2. That is, the first film 10 according to the first embodiment is a single layer of the inorganic insulating film 11. The inorganic insulating film 11 is, for example, a silicon oxide film (SiO2), but may also be a silicon nitride film (SiN). The silicon oxide film is formed by, for example, low-temperature CVD (Chemical Vapor Deposition), sputtering (PVD (Physical Vapor Deposition)), or coating.

[0012] Next, as shown in FIG. 1C, a portion of the first film 10 is removed so that at least a portion of the first film 10 remains at the boundary B between the membrane portion F2a and the rim portion F2b. More specifically, the first film 10 is removed by anisotropic etching until the membrane portion F2a is exposed. That is, etch-back is performed by RIE (Reactive Ion Etching) on ​​the entire surface.

[0013] Fig. 2 is a top view showing an example of the configuration of the semiconductor wafer W according to the first embodiment, as viewed from the second surface F2 side of the semiconductor wafer W in the step shown in Fig. 1C.

[0014] The first film 10 is provided at the boundary B between the rim portion F2b and the membrane portion F2a when viewed from the second surface F2 side. The first film 10 functions as a reinforcing material, which can suppress the occurrence of defects such as cracks or chips in the semiconductor wafer W during the manufacturing process.

[0015] 1D, a metal film 20 is formed on the first film 10 remaining in the boundary portion B and on the second surface F2. The metal film 20 is formed by, for example, sputtering.

[0016] Fig. 3 is a cross-sectional view showing an example of the configuration of the semiconductor wafer W according to the first embodiment. Fig. 3 is an enlarged cross-sectional view of the semiconductor wafer W in the vicinity of the boundary B shown in Fig. 1D.

[0017] Corner portion C is a corner portion where the surface of membrane portion F2a and the inner surface of rim portion F2b intersect, and is included in boundary portion B.

[0018] Next, as shown in FIG. 1E, the first film 10 is removed. As a result, the metal film 20 on the first film 10 is also removed (lifted off). The silicon oxide film, which is the first film 10 (inorganic insulating film 11), is removed by, for example, HF-based wet etching. For example, the first film 10 is removed by a chemical solution penetrating through gaps in the metal film 20, not shown in FIG. 3.

[0019] Next, the rim portion F2b is removed from the semiconductor wafer W. The rim portion F2b is removed by cutting the region where the first film 10 and the metal film 20 on the first film 10 have been removed into a ring shape. This reduces the burden on the semiconductor wafer W caused by cutting the metal film 20. Next, the semiconductor wafer W is divided into multiple chips by dicing. The metal film 20 functions as a back electrode. In this case, the semiconductor device is, for example, a device in which current flows in the vertical direction of the paper surface of FIG. 3.

[0020] 1E may be omitted. In this case, the rim portion F2b is removed by cutting the inside of the first film 10 in a ring shape.

[0021] Next, the results of the stress simulation will be explained. The stress explained below is the stress applied to the corner C in FIGS.

[0022] 4 is a diagram showing an example of a stress simulation according to the first embodiment. The distribution of stress (Pa) near the corner C is shown by contour lines. The vertical axis of the graph represents the X coordinate, and the horizontal axis of the graph represents the Y coordinate.

[0023] 4(a) shows a case where the first film 10 is not formed (comparative example). FIG. 4(b) shows a case where a 2 μm inorganic insulating film 11 (TEOS (Tetra-ethoxy silane) film) is formed (first embodiment). The inorganic insulating film 11 is formed in the range of ±50 μm from the corner C in the Y-axis direction in FIG. 4. The metal film 20 is a laminated film including an aluminum (Al) film, a titanium (Ti) film, and a nickel (Ni) film.

[0024] In FIG. 4(a), the position of high stress is close to corner C. In FIG. 4(b), the position of high stress is farther from corner C than in FIG. 4(a).

[0025] In Figure 4(a), the stress σ acting on the X-plane in the X-direction XX is 1.787 x 10 8 (Pa), and the stress acting on the Y surface in the Y direction σ YY is 1.318 x 10 8 (Pa), and the stress σ acting on the X surface in the Y direction XY is -7.813 x 10 6 (Pa). In FIG. 4(b), the stress σ acting on the X-plane in the X-direction XX is 1.117 x 10 7 (Pa), and the stress acting on the Y surface in the Y direction σ YY is -2.270 x 107 (Pa), and the stress σ acting on the X surface in the Y direction XY is -1.639 x 10 7 (Pa). Therefore, the inorganic insulating film 11 reduces the stress (stress σ XX ) can be reduced by an order of magnitude.

[0026] As described above, according to the first embodiment, by forming recesses R on the second surface F2 of the semiconductor wafer W, a membrane portion F2a and a rim portion F2b are formed on the second surface F2. A first film 10 is then formed on the second surface F2. A portion of the first film 10 is then removed so that at least a portion of the first film 10 remains at the boundary portion B. This reinforces the boundary portion B between the rim portion F2b and the membrane portion F2a. As a result, the inside of the rim portion F2b is reinforced, and defects such as cracks or chips in the semiconductor wafer W during the manufacturing process can be suppressed. Therefore, the wafer breakage yield can be improved.

[0027] As shown in Figure 3, the inner surface of the rim portion F2b has a sloped shape. However, the first embodiment is also applicable to other shapes of the rim portion F2b, such as when the inner surface of the rim portion does not have a sloped shape.

[0028] One possible method for reinforcing the boundary B between the rim portion F2b and the membrane portion F2a is to slope the shape of the rim portion F2b and make the slope angle gentler. However, if the rim top width Wt remains unchanged, the rim bottom width Wb increases due to the gentle slope angle, increasing the dead area around the wafer's periphery and reducing chip gross (yield of chips per wafer). On the other hand, if the chip gross is maintained without changing the rim bottom width Wb, the rim top width Wt narrows, degrading the rigidity of the semiconductor wafer W and raising concerns about damage during transport in manufacturing equipment that clamps the wafer's periphery for transport and processing.

[0029] In contrast to this, in the first embodiment, the first film 10 that functions as a reinforcing material is formed without changing the slope angle, rim top width, and rim bottom width Wb. This allows the chip gloss to be maintained and the boundary portion B between the rim portion F2b and the membrane portion F2a to be reinforced so as not to impair the rigidity of the semiconductor wafer W.

[0030] (Second embodiment) 5A to 5D are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to Embodiment 2. The step shown in Fig. 5A is carried out after the same steps as those shown in Figs. 1A and 1B.

[0031] The second embodiment differs from the first embodiment in that the part of the first film 10 remaining in the boundary portion B is removed by resist patterning and wet etching instead of the full-surface RIE etch-back.

[0032] After the inorganic insulating film 11 is formed on the second surface F2 (see FIG. 1B), a resist 30 is applied onto the inorganic insulating film 11 as shown in FIG. 5A.

[0033] 5B, resist 30 is patterned so as to cover boundary portion B between rim portion F2b and membrane portion F2a. That is, a pattern corresponding to boundary portion B is formed in resist 30.

[0034] Next, as shown in Fig. 5C, the inorganic insulating film 11 is etched and the resist 30 is peeled off. That is, the inorganic insulating film 11 is removed using the resist 30 having the pattern shown in Fig. 5B as a mask. The silicon oxide film, which is the inorganic insulating film 11, is etched by, for example, HF-based wet etching.

[0035] Next, as shown in Fig. 5D, a metal film 20 is formed on the remaining first film 10 and on the second surface F2. The process shown in Fig. 5D is the same as the process shown in Fig. 1D.

[0036] Fig. 6 is a cross-sectional view showing an example of the configuration of the semiconductor wafer W according to the second embodiment. Fig. 6 is an enlarged cross-sectional view of the semiconductor wafer W in the vicinity of the boundary B shown in Fig. 5D.

[0037] Thereafter, the same steps as those shown in FIG. 1E and subsequent steps are carried out.

[0038] As in the second embodiment, the method for partially removing the first film 10 may be changed. The method for manufacturing a semiconductor device according to the second embodiment can obtain the same effects as the first embodiment.

[0039] (Third embodiment) 7A to 7C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to Embodiment 3. The step shown in Fig. 7A is carried out after the same steps as those shown in Figs. 1A and 1B.

[0040] The third embodiment differs from the first embodiment in that the first film 10 is a laminated film.

[0041] After forming the inorganic insulating film 11 on the second surface F2 (see FIG. 1B), an inorganic insulating film 12 is formed on the inorganic insulating film 11 as shown in FIG. 7. The first film 10 according to the third embodiment is a laminated film including a plurality of inorganic insulating films 11 and 12. In the third embodiment, for example, the silicon oxide film that is the inorganic insulating film 11 is formed by coating, and the silicon oxide film that is the inorganic insulating film 12 is formed by coating or CVD, for example.

[0042] The thickness of the silicon oxide film that can be formed at one time is, for example, several μm. If the stress on the boundary portion B cannot be reduced to the desired strength level, reinforcement is possible by stacking multiple layers to thicken the first film 10.

[0043] The laminated film is not limited to two layers, but may be three or more layers. The inorganic insulating films 11 and 12 and the films further laminated thereon may be made of different materials.

[0044] Next, as shown in Fig. 7B, a portion of the first film 10 is removed so that at least a portion of the first film 10 remains at the boundary portion B. The step shown in Fig. 7B is the same as the step shown in Fig. 1C.

[0045] Next, as shown in Fig. 7C, a metal film 20 is formed on the remaining first film 10 and on the second surface F2. The step shown in Fig. 7C is the same as the step shown in Fig. 1D.

[0046] Fig. 8 is a cross-sectional view showing an example of the configuration of the semiconductor wafer W according to the third embodiment. Fig. 8 is an enlarged cross-sectional view of the semiconductor wafer W near the boundary B shown in Fig. 7C.

[0047] Thereafter, the same steps as those shown in FIG. 1E and subsequent steps are carried out.

[0048] As in the third embodiment, the first film 10 may be a laminated film. The semiconductor device manufacturing method according to the third embodiment can obtain the same effects as the first embodiment. Moreover, the semiconductor device manufacturing method according to the third embodiment may be combined with the second embodiment.

[0049] (Fourth embodiment) 9A to 9E are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the fourth embodiment. The step shown in FIG. 9A is performed after the same steps as those shown in FIGS. 1A and 1B. In the fourth embodiment, resist patterning and wet etching are performed as in the second embodiment. However, RIE etchback may also be performed on the entire surface.

[0050] The fourth embodiment differs from the third embodiment in that the first film 10 is a laminated film including an organic insulating film 13.

[0051] After the inorganic insulating film 11 is formed on the second surface F2 (see FIG. 1B), an organic insulating film 13 is formed on the inorganic insulating film 11 as shown in FIG. 9A. The first film according to the fourth embodiment is a laminated film including the inorganic insulating film 11 and the organic insulating film 13. The organic insulating film 13 is, for example, a polyimide film. The laminated film may be a laminated film of the inorganic insulating film 11, the organic insulating film 13, or a combination thereof.

[0052] Next, as shown in Fig. 9B, a resist 30 is applied onto the organic insulating film 13. The step shown in Fig. 9B is the same as the step shown in Fig. 5A.

[0053] Next, as shown in Fig. 9C, a resist 30 is patterned so as to cover the boundary B between the rim portion F2b and the membrane portion F2a. The step shown in Fig. 9C is the same as the step shown in Fig. 5B.

[0054] 9D, the organic insulating film 13 is patterned and the inorganic insulating film 11 is wet-etched. The silicon oxide film, which is the inorganic insulating film 11, is etched by, for example, HF-based wet etching.

[0055] Fig. 10 is a top view showing an example of the configuration of the semiconductor wafer W according to the fourth embodiment, as viewed from the second surface F2 side of the semiconductor wafer W in the step shown in Fig. 9D.

[0056] The first film 10, which includes the inorganic insulating film 11 and the organic insulating film 13, is provided at the boundary B between the rim portion F2b and the membrane portion F2a when viewed from a direction substantially perpendicular to the semiconductor wafer W.

[0057] Next, as shown in Fig. 9E, a metal film 20 is formed on the remaining first film 10 and the second surface F2. The step shown in Fig. 9E is the same as the step shown in Fig. 1D.

[0058] Fig. 11 is a cross-sectional view showing an example of the configuration of the semiconductor wafer W according to the fourth embodiment, and is an enlarged cross-sectional view of the semiconductor wafer W in the vicinity of the boundary B shown in Fig. 9E.

[0059] Thereafter, the same steps as those shown in FIG. 1E and subsequent steps are carried out.

[0060] Next, the results of the stress simulation will be explained. The stress explained below is the stress applied to the corner C in FIGS.

[0061] 12 is a diagram showing an example of a stress simulation according to the second embodiment. The distribution of stress (Pa) near the corner C is shown by contour lines. The vertical axis of the graph represents the X coordinate, and the horizontal axis of the graph represents the Y coordinate.

[0062] 12 shows a case where a 2 μm inorganic insulating film 11 and a 10 μm organic insulating film 13 are formed. The inorganic insulating film 11 and the organic insulating film 13 are formed in a range of 50 μm from the corner C in the Y-axis direction in FIG. 12. The metal film 20 is a laminated film including an aluminum (Al) film, a titanium (Ti) film, and a nickel (Ni) film.

[0063] In Figure 12, the stress σ acting on the X plane in the X direction XX is -1.003 x 10 6 (Pa), and the stress acting on the Y surface in the Y direction σ YY is 1.296 x 10 7 (Pa), and the stress σ acting on the X surface in the Y direction XY is 1.2196×10 7 (Pa). Therefore, the organic insulating film 13 reduces the stress (stress σ XX ) can be reduced by an order of magnitude.

[0064] If the organic insulating film 13 has photosensitivity, the organic insulating film 13 may be patterned without using the resist 30 .

[0065] As in the fourth embodiment, the first film 10 may be a laminated film including an organic insulating film 13. The method for manufacturing a semiconductor device according to the fourth embodiment can obtain the same effects as those of the third embodiment.

[0066] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0067] 10 first film, 11 inorganic insulating film, 12 inorganic insulating film, 13 organic insulating film, 20 metal film, 30 resist, B boundary portion, C corner portion, E semiconductor element, F1 first surface, F2 second surface, F2a membrane portion, F2b rim portion, R recess, W semiconductor wafer

Claims

1. a wafer having a first surface on which a semiconductor element is provided and a second surface opposite to the first surface, and a recess is formed in the second surface to form a thin plate portion and an annular protrusion portion surrounding the thin plate portion on the second surface; forming a first film on the second surface; removing a portion of the first film so that at least a portion of the first film remains at a boundary between the thin plate portion and the annular convex portion; A method for manufacturing a semiconductor device, comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein removing the portion of the first film includes removing the first film by anisotropic etching until the thin plate portion is exposed.

3. Removing the portion of the first film includes: forming a mask material on the first film; forming a pattern on the mask material according to the boundary portion; removing the first film using the mask material of the pattern as a mask; The method for manufacturing a semiconductor device according to claim 1 , comprising:

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first film is a single-layer film.

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the single layer film is an inorganic insulating film or an organic insulating film.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the first film is a laminated film.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the laminated film is an inorganic insulating film, an organic insulating film, or a laminated film made of a combination thereof.

8. the inorganic insulating film is at least one of a silicon oxide film and a silicon nitride film, 8. The method for manufacturing a semiconductor device according to claim 5, wherein the organic insulating film is a polyimide film.

9. After removing a portion of the first film, forming a metal film on the first film remaining at the boundary and on the second surface; removing the first film; removing the annular protrusion from the wafer; Singulating the wafer into a plurality of chips; The method for manufacturing a semiconductor device according to claim 1 , further comprising:

10. The method for manufacturing a semiconductor device according to claim 1 , wherein the boundary portion is a corner portion where a surface of the thin plate portion intersects with an inner side surface of the annular protrusion.

11. 2. The method for manufacturing a semiconductor device according to claim 1, wherein forming the recess includes grinding a central portion of the second surface that overlaps with the semiconductor element when viewed from a direction substantially perpendicular to the wafer.

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