Indication device

Abstract

To solve a problem of a physical limit of thinning of a gate insulation layer when the gate insulation layer is a single layer of a silicon oxide film due to increase in tunnel current, that is, gate leakage current although a minute transistor requires thinning of the gate insulation layer.SOLUTION: In a semiconductor device, gate leakage current of a minute transistor is reduced by using a high-k film having a dielectric constant of 10 and more for a gate insulation layer. By using the high-k film as a first insulation layer having a dielectric constant higher than that of a second insulation layer which contacts an oxide semiconductor layer, the gate insulation layer can be thinned to a further degree than a gate insulation layer in the case of being converted to a silicon oxide film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] A semiconductor device having a transistor using an oxide semiconductor and an integrated circuit including the transistor For example, the present invention relates to an electronic device that includes a semiconductor integrated circuit as a component, and a method for manufacturing the same. Regarding child devices.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to all semiconductor devices, including display devices, electro-optical devices, semiconductor circuits, electronic components, and electronic equipment. It is a conductor device. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and silicon wafers, glass substrates, etc. are used depending on the application. Various types of semiconductor devices are manufactured.

[0004] For example, in the case of a liquid crystal display device, transistors and wiring are formed on a glass substrate. The I / O, CPU, and memory are all semiconductor integrated circuits (at least transistors) separated from the semiconductor wafer. It is an assembly of semiconductor elements having a plurality of electrodes (transistors and memories) and a connection terminal. do.

[0005] The semiconductor device can include a transistor as a part of its components. Silicon-based semiconductor materials are well known as applicable semiconductor thin films, but oxide semiconductor materials are also suitable. It is attracting attention.

[0006] As an oxide semiconductor material, one containing zinc oxide is known. Transistors formed from semiconductors using zinc have been disclosed (Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165527 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-165529 Summary of the Invention [Problem to be solved by the invention]

[0008] In semiconductor devices, not only the power consumption during operation but also the power consumption during standby is considered important. In particular, portable semiconductor devices are battery-powered and therefore require limited power. In addition, the leakage current of semiconductor devices in vehicles is large during standby. For example, in the case of electric vehicles, The leakage current of the semiconductor device reduces the distance traveled per a certain amount of charge.

[0009] In order to reduce power consumption, it is necessary to reduce not only the power consumption during operation but also the leakage current during standby. It is effective to reduce the leakage current of each transistor. An LSI has millions of transistors, and the total leakage current of these transistors is: Such leakage currents are a major factor in the power consumption of semiconductor devices during standby. There are various causes of leakage current, but the main If the peak current can be reduced, the power consumed by the drive circuit etc. can be reduced. The power consumption of the semiconductor device can be reduced. The leakage current of the semiconductor device during standby can be reduced. One of the goals is to reduce this.

[0010] Furthermore, since miniaturization of semiconductor devices is required, transistors, which are components of semiconductor devices, It is inevitable that miniaturization is also required for transistors. However, if the thickness of the gate insulating layer is less than 1 nm, the tunnel current increases. The probability of pinholes occurring in the gate insulating layer also increases sharply. Therefore, when the gate insulating layer is a single layer of silicon oxide film, the gate leakage current increases. There is a physical limit to how thin the gate insulating layer can be. The first problem is to miniaturize transistors and further miniaturize the entire semiconductor device. This is one of the challenges. [Means for solving the problem]

[0011] By removing impurities such as water or hydrogen that form donor levels in the oxide semiconductor, A semiconductor that is essentially intrinsic or has a larger energy gap than a silicon semiconductor. A transistor in which a channel region is formed using a thin oxide semiconductor is used, and fabricate semiconductor devices, semiconductor circuits, electronic components, and electronic equipment.

[0012] Impurities such as hydrogen contained in oxide semiconductors can be removed by heat treatment at temperatures above 400°C and below the distortion point of the substrate. The hydrogen concentration in the oxide semiconductor is sufficiently reduced to obtain a highly purified oxide. By using a semiconductor layer, the off-state current of a transistor can be reduced.

[0013] The oxide semiconductor has the chemical formula InMO3(ZnO) m Thin (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. For example, M may represent Ga, Ga and Al, Ga and Mn, or Examples of the elements include Ga and Co.

[0014] By using a high-k film with a relative dielectric constant of 10 or more for the gate insulating layer, This makes it possible to reduce the gate leakage current of transistors, thereby realizing power savings in semiconductor devices. High-k films with high dielectric constants include hafnium oxide (HfO2, etc.) and hafnium silicate. HfSi x O y ;where x>0, y>0), hafnium oxynitride silicate Hafnium oxide (HfSiON), hafnium aluminate (HfAl x O y ;where x>0, y> 0) can be used. Other high-k films include zirconium oxide (ZrO2, etc.), tantalum oxide (Ta2O5, etc.), aluminum zirconium oxide (Zr Al x O y ; where x>0, y>0)) can also be mentioned, and among these materials A layer consisting of any one of these and the insulating film containing hafnium is used as the gate insulating layer. In addition, when wet etching is used for the insulating film containing hafnium, In addition, since it is hardly etched, the etching that protects the electrodes and substrate provided below is It can also function as a gas stopper membrane.

[0015] In addition, by using a high-k film with a relative dielectric constant of 10 or more for the gate insulating layer, The same effect as a gate insulating layer with a thickness of 0.8 nm or less formed alone can be achieved with a thickness of 2 nm or more (specifically Specifically, the thickness of the gate insulating layer is 2 nm to 10 nm. The insulating layer is made of a high-k film with a relative dielectric constant of 10 or more (specifically, a thickness of 2 nm to 10 nm). By using a gate insulating film (below), the thickness of the gate insulating film is reduced compared to the gate insulating film converted into a silicon oxide film. In addition, the gate insulating layer is free of pinholes and has a uniform dielectric strength. A transistor can be realized.

[0016] One aspect of the present invention disclosed in this specification is a first insulating film provided in contact with a gate electrode. a second insulating layer made of a metal oxide provided in contact with the first insulating layer; an oxide semiconductor layer provided in contact with the insulating layer; a third insulating layer formed between the second insulating layer and the third insulating layer; and an oxide semiconductor layer formed between the second insulating layer and the third insulating layer. a semiconductor device including: a first insulating layer having a higher dielectric constant than a second insulating layer; is.

[0017] The above configuration solves at least one of the above problems.

[0018] For example, the first insulating layer having a higher dielectric constant than the second insulating layer in contact with the oxide semiconductor layer may be By using an insulating film containing hafnium (specifically, a thickness of 2 nm to 10 nm), The gate insulating film can be made thinner than the gate insulating layer when converted into a silicon nitride film, This allows for miniaturization of the capacitor.

[0019] In the above structure, the second insulating layer, the third insulating layer, and the oxide semiconductor layer are formed by a sputtering method. The second insulating layer and the third insulating layer are preferably formed by adding hydrogen, hydroxide, or the like to the oxide semiconductor layer. In order to minimize the amount of base and moisture contained in the film, the remaining moisture in the film formation chamber is removed while the water is being It is preferable to carry out film formation by introducing a sputtering gas from which oxygen and moisture have been removed.

[0020] A method for manufacturing a bottom-gate transistor is also one aspect of the present invention. The structure is such that a gate electrode is formed on a substrate having an insulating surface, and a first insulating film covering the gate electrode is formed on the substrate. An edge layer is formed by sputtering, and a second insulating layer is formed on the first insulating layer by sputtering. an oxide semiconductor layer is formed over the second insulating layer, and the oxide semiconductor layer is then heated in an atmosphere containing nitrogen, oxygen, or a rare gas. The substrate is subjected to a heat treatment at a temperature of 400°C or higher and lower than the strain point of the substrate to remove the moisture contained in the oxide semiconductor layer. The third insulating layer is formed on the oxide semiconductor layer by sputtering, and the first insulating layer is formed on the oxide semiconductor layer by sputtering. The method for manufacturing a semiconductor device includes the step of forming an insulating layer having a higher dielectric constant than the second insulating layer.

[0021] In addition, the second insulating layer and the third insulating layer are layers that are in contact with the oxide semiconductor layer, and therefore, are made of silicon oxide. In particular, the insulating layer formed after the formation of the oxide semiconductor layer is preferably an oxide insulating layer such as a silicon oxide layer. The insulating layer 3 is formed by heat treatment at 400° C. or higher and lower than the distortion point of the substrate to remove impurities in the oxide semiconductor layer. The oxide semiconductor that is reduced at the same time by the process of removing impurities (such as moisture) It is also possible to supply oxygen, which is one of the materials that make up an oxide semiconductor. By supplying oxygen, the oxide semiconductor layer is highly purified and electrically becomes I-type (intrinsic). It can be made into

[0022] The first insulating layer is made of a high-k film having a relative dielectric constant of 10 or more, such as hafnium. When an insulating film containing the compound is used, wet etching can be used to pattern the oxide semiconductor layer. Even if a thin film of the second insulating layer is removed, it is hardly etched. It functions as an etching stopper film to protect the gate electrode and substrate underneath. It is also possible.

[0023] The semiconductor device also has two gate electrodes arranged above and below the channel region with a gate insulating layer interposed therebetween. The structure of a dual gate type transistor is also one aspect of the present invention, and its configuration is as follows: a first insulating layer provided in contact with the port electrode; a second insulating layer formed on the oxide semiconductor layer; an oxide semiconductor layer provided in contact with the second insulating layer; a third insulating layer provided in contact with the semiconductor layer; A fourth insulating layer having a higher dielectric constant and a second gate electrode overlapping the first gate electrode are formed as a fourth insulating layer. the oxide semiconductor layer is in contact with the second insulating layer and the third insulating layer, and the first insulating layer has a higher dielectric constant than the second insulating layer. It is a body device.

[0024] The above configuration solves at least one of the above problems.

[0025] For example, an insulating film containing hafnium is used as the first insulating layer having a higher dielectric constant than the second insulating layer. and a fourth insulating layer having a higher dielectric constant than the third insulating layer is made of an insulating film containing hafnium. This allows the thickness of the gate insulating layer of a dual-gate transistor to be reduced. This makes it possible to miniaturize dual-gate transistors.

[0026] In the above structure, the oxide semiconductor layer is a semiconductor layer including a channel formation region of the transistor. When using this, the threshold voltage of the transistor may become negative depending on the manufacturing process of the semiconductor device. Therefore, the semiconductor including the channel formation region In a transistor using an oxide semiconductor for a layer, the threshold voltage can be controlled. By controlling the potential of the first gate electrode or the second gate electrode, The threshold voltage can also be controlled to a desired value. [Effects of the Invention]

[0027] A transistor using an oxide semiconductor layer that is highly purified by sufficiently reducing the hydrogen concentration is A semiconductor device with low power consumption due to a low current can be realized.

[0028] In addition, transistors with gate insulating layers using excellent high-k films with low gate leakage current are also available. This makes it possible to realize a transistor.

[0029] Furthermore, a transistor using an oxide semiconductor layer that is highly purified by sufficiently reducing the hydrogen concentration can be formed on a glass substrate, and displays, LSIs, and CPUs can be mounted on the glass substrate. By using a large-area glass substrate, manufacturing costs can be reduced. can be reduced. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 5] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 7] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 8] 1A and 1B are diagrams illustrating examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0032] (Embodiment 1) In this embodiment, an example of a transistor that can be applied to the semiconductor device disclosed in this specification will be described. The structure of a transistor that can be applied to the semiconductor device disclosed in this specification is not particularly limited. For example, a gate electrode may be formed as a top gate electrode, which is disposed above an oxide semiconductor layer via a gate insulating layer. A gate electrode is disposed below the oxide semiconductor layer via a gate insulating layer. A staggered type or planar type with a bottom gate structure can be used. The transistor has a single gate structure in which one channel formation region is formed, and two gate structures in which It may be a blue gate structure or a triple gate structure in which three gates are formed. Dual gate electrodes are arranged above and below the panel region via a gate insulating layer. A gate type may also be used.

[0033] Note that examples of cross-sectional structures of transistors are shown in FIGS. 1A to 1D. The transistors shown in (A) to (D) each use an oxide semiconductor as a semiconductor. The advantage of using compound semiconductors is that the field effect mobility of the transistor in the on state is Maximum value (5cm 2 / Vsec or more, preferably 10cm 2 / Vsec or more 150cm 2 / Vsec or less) and a low off-state voltage in the off state of the transistor. current (less than 1 aA / μm, more preferably less than 10 zA / μm, and 100 at 85°C) zA / μm) can be obtained.

[0034] The transistor 410 shown in FIG. 1A is a bottom-gate transistor. , also called an inverted staggered transistor.

[0035] The transistor 410 includes a gate electrode 401, a first gate electrode 402, a second gate electrode 403, a first gate electrode 404, a second gate electrode 405, a first gate electrode 406, a second gate electrode 407, a second gate electrode 408, a second gate electrode 409, a second gate electrode 410, a second gate electrode 411, a second gate electrode 412, a second gate electrode 413, a second gate electrode a gate insulating layer 402a, a second gate insulating layer 402b, an oxide semiconductor layer 403, a source electrode The transistor 410 includes a gate electrode 405a and a drain electrode 405b. An insulating film 407 is provided on the semiconductor layer 403. A protective insulating layer 409 is formed.

[0036] The transistor 420 illustrated in FIG. 1B is a channel-protective transistor (also called a channel-stop transistor). ) and is also called an inverted staggered transistor.

[0037] The transistor 420 includes a gate electrode 401, a first gate electrode 402, a second gate electrode 403, a first gate electrode 404, a second gate electrode 405, a first gate electrode 406, a second gate electrode 407, a second gate electrode 408, a second gate electrode 409, a second gate electrode 410, a second gate electrode 411, a second gate electrode 412, a second gate electrode 413, a second gate electrode a gate insulating layer 402a, a second gate insulating layer 402b, an oxide semiconductor layer 403, an oxide semiconductor layer An insulating layer 427 which functions as a channel protection layer covering the channel formation region of the semiconductor layer 403; The transistor 420 includes a source electrode 405a and a drain electrode 405b. A protective insulating layer 409 is formed.

[0038] The transistor 430 shown in FIG. 1C is a bottom-gate transistor. A gate electrode 401, a first gate insulating layer 402a, a second gate insulating layer 402b, a third gate insulating layer 402c, a fourth gate insulating layer 402d, a fourth gate insulating layer 402e, a fifth gate insulating layer 402f, a sixth gate insulating layer 402g, a sixth gate insulating layer 402h ... The second gate insulating layer 402b, the source electrode 405a, the drain electrode 405b, and the oxide semiconductor The conductive layer 403 covers the transistor 430 and is in contact with the oxide semiconductor layer 403. An insulating film 407 is provided. A protective insulating layer 409 is further formed on the insulating film 407. are.

[0039] In the transistor 430, the first gate insulating layer 402a is insulated from the substrate 400 and the gate electrode. The source electrode 405a and the drain electrode 405b are provided on the second gate electrode 401 in contact with each other. The second gate insulating layer 402b is provided on the first gate insulating layer 402b. An oxide semiconductor layer 403 is provided over the source electrode 405a and the drain electrode 405b. There are.

[0040] The transistor 440 shown in FIG. 1D is a top-gate transistor. The transistor 440 is formed on a substrate 400 having an insulating surface, an insulating layer 437, an oxide semiconductor layer 438, and a gate insulating layer 439. The gate insulating layer 403, the source electrode 405a, the drain electrode 405b, and the second gate insulating layer 40 2b, a first gate insulating layer 402a, a gate electrode 401, a source electrode 405a, a drain electrode 405b, a drain electrode 406a, a drain electrode 406b, a drain electrode 406c, a drain electrode 406d, a drain electrode 406e, a drain electrode 406f, a drain electrode 406g, a drain electrode 406h, a drain electrode 406i, a drain electrode 4 The wiring layers 436a and 436b are provided in contact with the rain electrode 405b, respectively, and electrically is connected to.

[0041] In this embodiment, as described above, the oxide semiconductor layer 403 is used as the semiconductor layer. The oxide semiconductor used for the compound semiconductor layer 403 is a quaternary metal oxide, In-Sn- Ga-Zn-O oxide semiconductors and In-Ga-Zn-O oxides, which are ternary metal oxides Compound semiconductors, In-Sn-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors , Sn-Ga-Zn-O based oxide semiconductor, Al-Ga-Zn-O based oxide semiconductor, Sn- Al-Zn-O oxide semiconductors and In-Zn-O oxide semiconductors, which are binary metal oxides, body, Sn-Zn-O oxide semiconductor, Al-Zn-O oxide semiconductor, Zn-Mg-O Oxide semiconductors, Sn-Mg-O oxide semiconductors, In-Mg-O oxide semiconductors, and mono- In-O based oxide semiconductors, Sn-O based oxide semiconductors, Zn-O based oxide semiconductors, The oxide semiconductor may contain SiO2. Here, for example, the In-Ga-Zn-O-based oxide semiconductor is a semiconductor containing indium (In), gallium (Ga), and zinc (Zn). It means an oxide film containing sodium (Ga) and zinc (Zn), and the stoichiometric ratio is There is no particular restriction on the type of element, and elements other than In, Ga, and Zn may also be included.

[0042] The transistors 410, 420, 430, and 440 including the oxide semiconductor layer 403 are in an off state. This allows the current value (off-state current value) in this state to be reduced.

[0043] The transistors 410, 420, 430, and 440 including the oxide semiconductor layer 403 are Since a relatively high field-effect mobility can be obtained, high-speed operation is possible.

[0044] The first gate insulating layer 402a is obtained by using a plasma CVD method, a sputtering method, or the like. High-k films containing hafnium, such as hafnium oxide films, hafnium silicate films, and silica Hafnium oxynitride film and hafnium aluminate film are formed as a single layer or laminated layers. It can be achieved.

[0045] The second gate insulating layer 402b is a silicon oxide layer (SiO x (x>2)), nitride silicon Silicon layer, silicon oxynitride layer, silicon nitride oxide layer are formed as a single layer or in a laminated form. For example, the first gate insulating layer 402a can be formed by sputtering to a thickness of 5 nm or more. A hafnium oxide layer of 100 nm or less is formed, and a second gate insulating layer is formed on the first gate insulating layer. The layer 402b is a silicon oxide layer (S iO x (x>2)) are stacked to form a gate insulating layer with a total thickness of 100 nm or less. The thickness of the first gate insulating layer 402a is set to be thicker than that of the second gate insulating layer 402b. It is preferable to set

[0046] In the top-gate transistor 440, the first gate electrode on and in contact with the oxide semiconductor layer 403 The order in which the second gate insulating layer 402b is formed and then the first gate insulating layer 402a is formed. Let's say.

[0047] In the bottom-gate transistors 410, 420, and 430, an insulating film serving as a base film The base film may be provided between the substrate and the gate electrode. The base film prevents the diffusion of impurity elements from the substrate. The silicon nitride film, silicon oxide film, silicon nitride oxide film, or oxynitride film has a function of forming a silicon nitride film. The insulating film can be formed by a laminated structure of one or more films selected from silicon films.

[0048] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. A glass substrate such as borosilicate glass or aluminoborosilicate glass is used.

[0049] The material of the gate electrode 401 is Mo, Ti, Cr, Ta, W, Al, Cu, Nd, Sc, etc. It is formed by using a metal material or an alloy material containing these as the main component, in a single layer or in a laminated form. It is possible.

[0050] The conductive film used for the source electrode 405a and the drain electrode 405b is, for example, Al, C A metal film containing an element selected from the group consisting of r, Cu, Ta, Ti, Mo, and W, or a metal film containing the above-mentioned elements Metal nitride films containing titanium nitride as a component (titanium nitride film, molybdenum nitride film, tungsten nitride film) Also, one or both of the upper and lower sides of a metal film such as Al or Cu can be used. On the other hand, high melting point metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film, nitride film) Alternatively, a structure in which a molybdenum nitride film, a molybdenum nitride film, or a tungsten nitride film is laminated may be used.

[0051] In addition, the source electrode 405a and the drain electrode 405b (the wiring layer formed in the same layer as these) The conductive film may be made of a conductive metal oxide. Examples include indium oxide (In2O3, etc.), tin oxide (SnO2, etc.), and zinc oxide (ZnO, etc.). ), indium oxide tin oxide alloy (In2O3-SnO2, etc., abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO, etc.) or oxides of these metal oxide materials Silicon-containing materials can be used.

[0052] The insulating films 407 and 427 provided above the oxide semiconductor layers are typically silicon oxide films. , an inorganic film such as a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film The insulating layer 437 provided under the oxide semiconductor layer can be formed using an insulating film. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an oxynitride film An inorganic insulating film such as an aluminum oxide film can be used.

[0053] The protective insulating layer 409 provided over the oxide semiconductor layer is formed of a silicon nitride film, an aluminum nitride film, or the like. Aluminum film, aluminum oxide nitride film, high-k film containing hafnium, etc. Examples of high-k films containing hafnium include hafnium oxide films and silicon dioxide films. Hafnium oxide film, hafnium silicate oxynitride film, hafnium aluminate film, etc. can be used.

[0054] As described above, in this embodiment, an oxide semiconductor having a high field-effect mobility and a low off-state current value is used. A transistor including a conductor layer is used, and the first gate insulating layer 402a includes hafnium. By using high-k film, we have provided a semiconductor device with low power consumption due to leakage current. It can be provided.

[0055] (Embodiment 2) In this embodiment, an example of a transistor including an oxide semiconductor layer and a manufacturing method thereof will be described with reference to FIGS. The same parts as those in the above embodiment or parts and steps having similar functions are described below. This can be done in the same way as in the above embodiment, and the repeated explanation will be omitted. Detailed explanation will be omitted.

[0056] 2A to 2E show examples of cross-sectional structures of transistors. The transistor 510 shown in FIG. 1A is a bottom-gate transistor similar to the transistor 410 shown in FIG. It is an inverted staggered transistor with a structure.

[0057] Hereinafter, a process of manufacturing a transistor 510 over a substrate 505 will be described with reference to FIGS. 2A to 2E. Explain.

[0058] First, a conductive film is formed on a substrate 505 having an insulating surface, and then a first photolithography is performed. A gate electrode 511 is formed by the process. If the resist mask is formed by an inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0059] The substrate 505 having an insulating surface is the same as the substrate 400 shown in Embodiment 1. In this embodiment mode, a glass substrate is used as the substrate 505.

[0060] An insulating film serving as a base film may be provided between the substrate 505 and the gate electrode 511. It has the function of preventing the diffusion of impurity elements from the substrate 505, and is a silicon nitride film, a silicon oxide film, The insulating film is made of one or more films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It can be formed in a laminated structure.

[0061] The material of the gate electrode 511 is Mo, Ti, Cr, Ta, W, Al, Cu, Nd, S It is formed in a single layer or laminated form using metal materials such as c or alloy materials whose main components are these. It is possible.

[0062] Next, a first gate insulating layer 507a is formed on the gate electrode 511. The edge layer 507a is formed by depositing a high-k film using a plasma CVD method, a sputtering method, or the like. Form.

[0063] In this embodiment, a metal oxide target made of hafnium oxide is used, and the RF power supply 1kw, pressure 3mTorr, distance between substrate and target (TS distance) 150m The film formation temperature was room temperature, the argon flow rate was 5 sccm, and the oxygen flow rate was 5 sccm. A hafnium oxide film of 100 nm was formed under the above film formation conditions. The relative dielectric constant of the fluorine film was 15. The dielectric constant of vacuum, ε0, was 8.84 × 10 -1 2 F / m, electrode pad area 0.7854mm 2 The relative dielectric constant was calculated using the following formula: After forming the fluorine film, the film was heat treated in a nitrogen atmosphere at 550°C for 1 hour, and the results were as follows: The relative dielectric constant of the hafnium oxide film was 15.2, which was almost the same value as immediately after the film formation. Hafnium oxide films are almost impossible to etch with wet etching using chemicals. When etching, BCl3 gas, Cl2 gas, CHF3 gas, or a mixture of these gases is used. Dry etching was used.

[0064] In a later step, the hafnium oxide film is selectively etched to form a contact that reaches the gate electrode 511. When forming a gate hole, if a mixture of BCl3 gas and Cl2 gas is used, If the gate electrode 511 is a Ti film or an Al film, it will be etched together with the Ti film or the Al film. The top layer of 511 is preferably a W film.

[0065] Next, a second gate insulating layer 507b is formed on the first gate insulating layer 507a. The gate insulating layer 507b is formed by depositing an oxide film using a plasma CVD method, a sputtering method, or the like. Silicon layer, silicon nitride layer, silicon oxynitride layer, silicon nitride oxide layer, single layer or stacked layers In this embodiment, the second gate insulating layer 507a can be formed on the first gate insulating layer 507a. The gate insulating layer 507b is formed by sputtering a silicon oxide film having a thickness of 5 nm to 100 nm. The SiO layer x (x>2)) are stacked to form a gate insulating layer with a total thickness of 100 nm or less. do.

[0066] The oxide semiconductor of this embodiment is an oxide semiconductor obtained by removing impurities and becoming i-type or substantially i-type. In the technical concept of the present invention, an oxide that is I-type or substantially I-type is used. A semiconductor is a material with a carrier density of 1×10 12 cm -3 less than, more preferably below the measurement limit 1.45 x 10 10 cm -3 This refers to oxide semiconductors with a purity of less than 100%. Since the oxide semiconductor is highly sensitive to the interface state density and the interface charge, The interface between the semiconductor layer and the gate insulating layer is important. The second gate insulating layer 507b in contact therewith is required to have high quality.

[0067] For example, high density plasma CVD using microwaves (for example, frequency 2.45 GHz) produces dense This is preferable because it allows the formation of a high-quality insulating layer with high dielectric strength. The high-quality second gate insulating layer 507b is in close contact with the first gate insulating layer 507a, thereby reducing the interface state density. This is because the interface characteristics can be improved.

[0068] Of course, if a good insulating layer can be formed as the second gate insulating layer 507b, Other film formation methods such as sputtering can also be applied. This improves the film quality of the second gate insulating layer 507b and the interface characteristics with the oxide semiconductor. In any case, the film quality of the second gate insulating layer 507b is good. In addition, it is possible to reduce the interface state density with the oxide semiconductor and form a good interface. It's fine as long as it's something that works.

[0069] In addition, the first gate insulating layer 507a, the second gate insulating layer 507b, and the oxide semiconductor film In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film 530 as much as possible, As a pretreatment for forming the film 530, the gate electrode 511 is formed in the preheating chamber of the sputtering device. The substrate 505, the first gate insulating layer 507a, or the second gate insulating layer 507b. The substrate 505 on which the film is formed is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 505. It is preferable to desorb and exhaust the gas. The exhaust means provided in the preheating chamber is a cryopump. It is preferable that the preheating step is omitted. Before forming the insulating layer 516, the source electrode 515a and the drain electrode 515b are formed. The same process may be carried out on the substrate 505 .

[0070] Next, a thin film having a thickness of 2 nm to 200 nm, preferably An oxide semiconductor film 530 having a thickness of 5 nm to 30 nm is formed (see FIG. 2A).

[0071] Note that before the oxide semiconductor film 530 is formed by a sputtering method, argon gas is introduced. The reverse sputtering is performed by introducing the silicon dioxide into the silicon dioxide to generate plasma, and the silicon dioxide is deposited on the surface of the second gate insulating layer 507b. It is preferable to remove any powdery material (also called particles or dust) adhering to the surface. The target is not voltage-applied, but an RF power source is used on the substrate side in an argon atmosphere. This is a method of modifying the surface by applying a voltage to generate plasma near the substrate. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used.

[0072] The oxide semiconductor used for the oxide semiconductor film 530 is the oxide semiconductor described in Embodiment 1. The oxide semiconductor may contain SiO2. The oxide semiconductor film 530 was formed using an In—Ga—Zn—O-based metal oxide target. The film is formed by sputtering. The cross section at this stage corresponds to Figure 2(A). The oxide semiconductor film 530 is grown under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or The film can be formed by sputtering in a mixed atmosphere of rare gas and oxygen.

[0073] Examples of targets for forming the oxide semiconductor film 530 by a sputtering method include The composition ratio of the metal oxide was In2O3:Ga2O3:ZnO=1:1:1 [molar ratio]. An In-Ga-Zn-O film is formed using an In-Ga-Zn-O target. The material and composition are not limited, for example, In2O3:Ga2O3:ZnO=1:1:2 [mo A metal oxide target having a ratio of [1 / 2] may also be used.

[0074] The relative density of the metal oxide target is 90% or more and 100% or less, preferably 95% or more. By using a metal oxide target with a high relative density, The deposited oxide semiconductor film can be a dense film.

[0075] The oxide semiconductor film 530 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. It is preferable to use a high-purity gas from which impurities such as oxides have been removed.

[0076] The substrate is held in a film-forming chamber maintained in a reduced pressure state, and the substrate temperature is preferably set to 100°C or more and 600°C or less. The temperature is preferably 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. Damage caused by coating is reduced. The removed sputtering gas is introduced, and an oxide semiconductor is deposited on the substrate 505 using the target. To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, e.g. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means is preferably a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may contain, for example, hydrogen atoms, water (H2O), Compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) are exhausted. Therefore, the impurity concentration in the oxide semiconductor film formed in the deposition chamber can be reduced.

[0077] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed DC power supply is used, powdery substances (particles, etc.) generated during film formation are This is preferable because it can reduce the thickness (also called "slippage") and make the film thickness distribution uniform.

[0078] Next, the oxide semiconductor film 530 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the substrate. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0079] In addition, contact holes are formed in the first gate insulating layer 507a and the second gate insulating layer 507b. In this case, the step of forming the oxide semiconductor film 530 can be performed simultaneously with the processing of the oxide semiconductor film 530.

[0080] The etching of the oxide semiconductor film 530 here can be performed by dry etching or wet etching. For example, wet etching of the oxide semiconductor film 530 may be used. The etching solution used for etching is a mixture of phosphoric acid, acetic acid, and nitric acid, or ITO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0081] Next, the oxide semiconductor layer is subjected to first heat treatment. The conductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C. The temperature is set to 750°C or higher, or 400°C or higher but lower than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the facilities, and the oxide semiconductor layer was heated to 450°C in a nitrogen atmosphere. After the heat treatment for 1 hour, the oxide semiconductor layer was cooled to room temperature and then cooled to room temperature without being exposed to the air. The recontamination of elements is prevented, and an oxide semiconductor layer 531 is obtained (see FIG. 2B).

[0082] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Tank Apparatus) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0083] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. You may also perform a GRTA.

[0084] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0085] After the oxide semiconductor layer is heated by the first heat treatment, high-purity oxygen gas, high-purity SiO 2 gas, and Introduce high-temperature N2O gas or ultra-dry air (dew point below -40°C, preferably below -60°C). It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment device is preferably 6N or more. or 7N or more (i.e., the impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably It is preferable to set the concentration of the oxygen gas or N2O gas to 0.1 ppm or less. The process of removing impurities by dehydration or dehydrogenation treatment simultaneously reduces By supplying oxygen, which is one of the materials that make up oxide semiconductors, The layer is purified and electrically made to be type I (intrinsic).

[0086] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The same can be done for the semiconductor film 530. In that case, after the first heat treatment, The substrate is then removed and subjected to a photolithography process.

[0087] In addition to the above, the first heat treatment may be performed after the oxide semiconductor layer is formed. After the source electrode and the drain electrode are laminated on the layer, or Either of these may be performed after forming an insulating layer on the electrode.

[0088] In addition, contact holes are formed in the first gate insulating layer 507a and the second gate insulating layer 507b. In this case, the step of forming the oxide semiconductor film 530 may be performed before the first heat treatment. It's fine if it's later.

[0089] In addition, the oxide semiconductor layer is formed in two separate steps and heat-treated in two separate steps. Regardless of the material of the component, such as oxide, nitride, or metal, the thick crystalline region, i.e., the film An oxide semiconductor layer having a crystal region whose c-axis is oriented perpendicular to the surface may be formed. For example, a first oxide semiconductor film having a thickness of 3 nm to 15 nm; In a dry air atmosphere, 450°C to 850°C, preferably 550°C to 750°C The first heat treatment is performed to obtain a first crystal having a crystalline region (including plate-like crystals) in a region including the surface. Then, a second oxide semiconductor film that is thicker than the first oxide semiconductor film is formed. a second film is formed at 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. heat treatment is performed to grow crystals upward using the first oxide semiconductor film as a seed for crystal growth; The second oxide semiconductor film is crystallized to form an oxide semiconductor film having a thick crystalline region. A body layer may be formed.

[0090] Next, a source electrode and a A conductive film is formed to become the drain electrode (including wiring formed in the same layer). The conductive film used for the source electrode 40 shown in the first embodiment is used as the conductive film for the drain electrode. 5a, the same materials as those used for the drain electrode 405b can be used.

[0091] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode 515a and the drain electrode 515b by etching, a resist mask is Remove the crust (see Figure 2(C)).

[0092] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrodes adjacent to each other on the oxide semiconductor layer 531 may be formed by using a laser beam or an ArF laser beam. The width of the gap between the bottom end of the drain electrode and the bottom end of the transistor to be formed later is The channel length L is determined. When exposure is performed for a channel length L of less than 25 nm, the third The exposure during resist mask formation in the photolithography process is extremely small, ranging from several nm to several tens of nm. Extreme ultraviolet light with a short wavelength is recommended. Exposure by ultraviolet light has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. Speed ​​can be increased.

[0093] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. A single multi-tone mask can produce patterns corresponding to at least two different types of patterns. Therefore, the number of exposure masks can be reduced, and This also reduces the number of photolithography steps required, making it possible to simplify the process.

[0094] Note that when the conductive film is etched, the oxide semiconductor layer 531 is etched and divided. It is desirable to optimize the etching conditions so as not to cause this problem. It is difficult to obtain conditions for etching only the conductive film without etching the layer 531 at all. When the conductive film is etched, the oxide semiconductor layer 531 is partially etched, forming a groove (a recess). In some cases, the oxide semiconductor layer has the following structure.

[0095] In this embodiment, a Ti film is used as the conductive film, and an In—Ga— Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (3 A mixture of 1% by weight hydrogen peroxide water, 28% by weight ammonia water, and water (5:2:2) is used.

[0096] Next, plasma treatment is performed using gases such as N2O, N2, or Ar to remove the exposed The plasma treatment may be performed to remove adsorbed water or the like attached to the surface of the oxide semiconductor layer. In this case, after the plasma treatment, the protective insulating film in contact with a part of the oxide semiconductor layer is removed without being exposed to the air. An insulating layer 516 is formed to serve as an insulating film.

[0097] The insulating layer 516 has a thickness of at least 1 nm, and is formed by a method such as sputtering. The insulating layer 516 can be formed by appropriately using a method that does not mix impurities such as hydrogen. When hydrogen is contained in the oxide semiconductor layer, the hydrogen penetrates into the oxide semiconductor layer, or the oxide semiconductor layer is deformed by the hydrogen. The oxygen in the layer is extracted, and the back channel of the oxide semiconductor layer becomes low resistance (N-type). Therefore, the insulating layer 516 should be as thin as possible. It is important that the deposition process does not use hydrogen, resulting in a hydrogen-free film.

[0098] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed as the insulating layer 516 by sputtering. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas (typically In an atmosphere of oxygen, or a mixture of rare gases and oxygen, In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used in an oxygen-containing atmosphere. Silicon oxide can be formed in contact with the oxide semiconductor layer by sputtering. The insulating layer 516 formed by the insulating layer 516 is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as It uses an inorganic insulating film that blocks external penetration, typically a silicon oxide film or an acid A silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0099] As in the case of forming the oxide semiconductor film 530, residual moisture in the deposition chamber for the insulating layer 516 is removed. To achieve this, it is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating layer 516 formed in a deposition chamber evacuated using an opto-pump was reduced. In addition, the following exhaust means can be used to remove residual moisture in the deposition chamber for the insulating layer 516: A turbo pump with a cold trap may also be used.

[0100] The insulating layer 516 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is preferable to use a high-purity gas from which impurities have been removed.

[0101] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. A part of the body layer (channel forming region) is heated while being in contact with the insulating layer 516 .

[0102] The first heat treatment (hydrogen, moisture, hydroxyl group, or hydride (hydrogen)) is performed on the oxide semiconductor film. a process for intentionally removing impurities such as oxide semiconductor compounds from the oxide semiconductor layer At the same time, oxygen, one of the materials that make up oxide semiconductors, is reduced. Therefore, the oxide semiconductor layer can be supplied with the Highly purified and electrically made into type I (intrinsic).

[0103] Through the above steps, a transistor 510 is formed (see FIG. 2D).

[0104] Furthermore, when a silicon oxide layer containing many defects is used as the insulating layer 516, after the silicon oxide layer is formed, The heat treatment reduces hydrogen, moisture, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer. The impurities are diffused into the insulating layer, and the impurities contained in the oxide semiconductor layer are further reduced. Play.

[0105] A protective insulating layer 506 may be further formed on the insulating layer 516. For example, the protective insulating layer 506 may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a silicon nitride film. This is a preferable film formation method. The protective insulating layer does not contain impurities such as moisture, and these impurities are easily absorbed from the outside. Inorganic insulating films such as silicon nitride and aluminum nitride are used to block the penetration of In this embodiment, the protective insulating layer 506 is formed using a silicon nitride film. (See Figure 2(E)).

[0106] In this embodiment, the substrate 505 on which the insulating layer 516 is formed is used as the protective insulating layer 506. It is heated to a temperature of 100℃ to 400℃ and then heated with a sputter containing high-purity nitrogen from which hydrogen and moisture have been removed. A silicon nitride film is formed by introducing a target of silicon semiconductor. In this case, similar to the insulating layer 516, the protective insulating layer 5 is removed while removing the remaining moisture in the processing chamber. It is preferable to deposit 06.

[0107] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then reduced from the heating temperature to room temperature. The temperature drop at this temperature may be repeated several times.

[0108] In this manner, the transistor including the highly purified oxide semiconductor layer manufactured according to this embodiment The transistor has high field-effect mobility, allowing for high-speed operation. By using hafnium oxide as an insulating layer, the gate leakage current of the transistor is reduced. This makes it possible to reduce the power consumption of the semiconductor device.

[0109] In addition, by using a hafnium oxide film as the first gate insulating layer, it is possible to form a silicon oxide film alone. The same effect as a gate insulating layer with a thickness of 0.8 nm or less can be achieved with a layer with a thickness of 2 nm or more (specifically, This is achieved with a gate insulating layer having a thickness of 2 nm to 10 nm.

[0110] This embodiment mode can be freely combined with Embodiment Mode 1.

[0111] (Embodiment 3) In this embodiment, two gates are arranged above and below the channel region via a gate insulating layer. An example of fabricating a dual-gate transistor having electrodes will be described below.

[0112] Since the steps in between are the same as those in the second embodiment, the same reference numerals are used for the same parts. Reveal.

[0113] 3A to 3C show examples of cross-sectional structures of transistors. ) First, the state shown in FIG. 3(A) is obtained according to the second embodiment.

[0114] Next, in the same manner as in the second embodiment, an insulating layer 5 which will be a protective insulating film in contact with a part of the oxide semiconductor layer is formed. In this embodiment, a second gate electrode 16 is formed in a subsequent step. An insulating film is formed of the same material and with the same thickness as the second gate insulating layer 507b.

[0115] Next, as shown in FIG. 3(B), a dielectric film having a higher dielectric constant than the insulating layer 516 is formed on the insulating layer 516. The insulating layer 526 is made of the same material as the first gate insulating layer 507a. A hafnium oxide film is formed as an insulating film with the same thickness of 20 nm.

[0116] Next, a second gate electrode 508 is formed on the insulating layer 526. The material is a metal material such as Mo, Ti, Cr, Ta, W, Al, Cu, Nd, Sc, or The alloy material containing these as main components can be used to form a single layer or a laminated layer.

[0117] Through the above steps, a transistor 520 illustrated in FIG. 3C can be manufactured.

[0118] The insulating layer 526 made of hafnium oxide is hardly etched by wet etching. Since the second gate electrode 508 is not patterned, wet etching is used. When the insulating layer 526 has a thickness of 2 nm or more and 10 nm or less, it functions as an etching stopper film. Even if the insulating layer 526 is less than 100 μm, there are no pinholes in the insulating layer 526 and the transformer has a uniform dielectric strength. It is possible to achieve a 520.

[0119] An insulating film containing hafnium is used as the first insulating layer having a higher dielectric constant than the second insulating layer, The fourth insulating layer has a higher dielectric constant than the third insulating layer, and the insulating layer contains hafnium. As a result, the gate insulating layer of this embodiment is thicker than the gate insulating layer when converted into a silicon oxide film. It is possible to make the film thinner.

[0120] When an oxide semiconductor layer is used as a semiconductor layer including a channel formation region of a transistor, Depending on the manufacturing process of the device, the threshold voltage of the transistor may be negative or positive. Therefore, when an oxide semiconductor is used in a semiconductor layer including a channel formation region, The transistor used has a dual gate structure, like transistor 520. A configuration that allows the threshold voltage to be controlled is preferable. By controlling the potential of the second gate electrode 508, the threshold voltage can be controlled to a desired value. It is also possible to do so.

[0121] This embodiment mode can be freely combined with Embodiment Mode 1 or 2.

[0122] (Fourth embodiment) The oxide semiconductor layer is easily affected by the electric field generated during the manufacturing process. When a top-gate transistor as shown in FIG. 1(D) of the first embodiment is fabricated, the oxide This reduces the influence of electric fields that occur when forming a gate insulating layer on a semiconductor layer by sputtering. The film formation device used for this purpose is shown in Figure 4.

[0123] In this embodiment, the hafnium oxide film is formed using the film forming apparatus shown in FIGS. 4(A) and 4(B). Here is an example:

[0124] The chamber 301 is evacuated, and a mixture of O2 gas and Ar gas is introduced as a raw material gas. or Ar gas is flowed, and an electrode 302 connected to an RF power supply 304 faces an electrode 303. The electrodes 302 and 303 are provided with hafnium oxide targets 308 and 309, respectively. 9 are fixed.

[0125] 4(A) is a schematic top view of the chamber 301, and FIG. 4(B) is a schematic top view of the chamber 301. FIG. 3 is a cross-sectional view of the chamber 301.

[0126] In order to accommodate large-area substrates, the substrate 305 is placed vertically and sputtering is performed. Hafnium targets 308 and 309 face each other, and a substrate 305 is placed between them. By preventing the substrate 305 from being exposed to the plasma, the substrate 305 is hardly exposed to the plasma. 05 is provided with an oxide semiconductor layer covered with an insulating film, as shown in FIGS. 4A and 4B. By using the device shown in FIG. 1, damage to the oxide semiconductor layer (plasma damage) that does not cause practical problems can be prevented. The hafnium oxide film can be formed without giving any damage (image, etc.). A hafnium oxide film is formed on the surface of the substrate 305 fixed by the holder 307. The film formation on the substrate is stopped by shutter 306 until the speed stabilizes. 4(A) and 4(B), the shutter 306 is Although a sliding shutter is illustrated, the present invention is not limited thereto.

[0127] In FIG. 4(A), the substrate surface is shown perpendicular to the bottom surface of the chamber, but this is not particularly limited. The substrate may be placed in the holder 307 so that the substrate surface is inclined relative to the bottom surface of the chamber. The heater 307 is provided with a heater, and the film can be formed while heating the substrate 305. can.

[0128] The heater of the holder 307 is used to heat the substrate 30 in the chamber 301, which is kept in a reduced pressure state. 5, and the temperature of the substrate 305 is maintained at 100°C or higher but lower than 550°C, preferably 200°C or higher. The oxide semiconductor layer over the substrate 305 can be heated to a temperature of 0° C. or lower. While removing moisture from the chamber 301, the sputtering gas (oxygen) from which hydrogen, water, etc. have been removed is or argon) is introduced, and a hafnium oxide film is formed using the above target. The hafnium oxide film is formed while the substrate 305 is heated using the heater of the heater 307. This also reduces damage caused by sputtering.

[0129] To remove moisture from the chamber 301, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. Alternatively, a turbo pump with a cold trap may be used. Hydrogen and water can be removed from the processing chamber by evacuating using a cryopump or similar device. can be done.

[0130] In addition, in this embodiment, the hafnium oxide film has been described as an example, but it is not particularly limited thereto. The deposition system shown in Figure 4 is used to deposit insulating films that can be used as edge layers and other high-k films. The film formation apparatus shown in FIG. 4 can be used for forming an insulating film in contact with an oxide semiconductor layer. It can also be used in membranes.

[0131] (Embodiment 5) In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described. 5A and 5C show transistors 4010 and 40 11 and a liquid crystal element 4013 are sealed between the first substrate 4001 and the second substrate 4006. 5(A) and 5(B) are plan views of the panel sealed with sealing material 4005. corresponds to the cross section at MN in FIG. 5(C).

[0132] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0133] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. This is an example of mounting the signal line driver circuit 4003 by the COG method, and FIG. 5(C) is an example of mounting the signal line driver circuit 4003 by the TAB method. This is an example in which the signal line driver circuit 4003 is mounted by the method.

[0134] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. The pixel portion 4002 has a plurality of transistors. 4004 and a transistor 4010 included in the scanning line driver circuit 4004. The transistor 4011 has a first gate insulating layer 4020a, a second gate insulating layer 40 20b, and the first gate insulating layer 402a and the second gate insulating layer 202b shown in the second embodiment A high-k film can be used as the first gate insulating layer 402a. This allows the transistor to have a low gate leakage current. On the stanchions 4010 and 4011, insulating layers 4041, 4042 and 4021 are provided.

[0135] The transistors 4010 and 4011 are transistors with low gate leakage current shown in the first embodiment. A transistor can be applied. The transistor 4010 may be any of the transistors 410, 420, and 43 shown in Embodiment 1. In this embodiment, transistors 4010 and 40 11 is an n-channel transistor.

[0136] The oxide semiconductor layer of the transistor 4011 for the driver circuit is formed over the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping the panel formation region. By placing it at a position that overlaps with the channel formation region of the semiconductor layer, The amount of change in the threshold voltage of the transistor 4011 can be reduced. The potential of the gate electrode of the transistor 4011 may be the same as or different from the potential of the gate electrode of the transistor 4011. The conductive layer 4040 may function as a second gate electrode. The potential may be GND, 0V, or floating.

[0137] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 and the counter electrode 4031 are formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. The liquid crystal layer 4008 is sandwiched between layers 4032 and 4033 .

[0138] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. It can be used on plastics such as polyester film or acrylic resin film, or glass. or ceramics can be used.

[0139] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the transistor 4010. The common connection portion is used to connect the opposing electrode layer 4031 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 4005 to the common potential line. Contains.

[0140] Furthermore, a liquid crystal that exhibits a blue phase without using an alignment film may be used, in which case it is considered to be a horizontal electric field type. For this reason, the electrode arrangement is different from that shown in Fig. 5. For example, a pixel electrode layer is formed on the same insulating layer. The blue phase is a type of liquid crystal phase. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small.

[0141] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0142] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In this example, the polarizing plate is provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment, and the materials of the polarizing plate and the colored layer and The conditions may be appropriately set depending on the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0143] An insulating layer 4041 is formed in contact with an oxide semiconductor layer over the transistors 4011 and 4010. The insulating layer 4041 is formed using the same material and method as the insulating film 407 shown in the first embodiment. Here, the insulating layer 4041 is formed by the deposition apparatus of Embodiment 4. A silicon oxide film is formed by sputtering. A protective insulating layer 4041 is formed on the insulating layer 4041. The insulating layer 4042 is formed in the same manner as the protective insulating layer 409 described in Embodiment 1. In addition, in order to reduce the surface unevenness of the transistor, The edge layer 4042 is covered with an insulating layer 4021 that functions as a planarizing insulating film.

[0144] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0145] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a baking machine. By using both, it becomes possible to manufacture a semiconductor device efficiently.

[0146] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0147] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0148] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source and drain electrodes of the transistors 4010 and 4011. It is made of the same conductive film as the rain electrode.

[0149] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0150] In FIG. 5, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. The example shown is an example in which a scanning line driving circuit is formed separately and mounted. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. You can also wear it.

[0151] (Sixth embodiment) In this embodiment, an example of electronic paper will be shown as one mode of a semiconductor device.

[0152] The transistor including the gate insulating layer of the stack obtained by the method described in Embodiment 2 is Electronic paper that uses elements electrically connected to etching elements to drive electronic ink. Electronic paper is also called an electrophoretic display. It has the same readability as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0153] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0154] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0155] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0156] Furthermore, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, a display can be performed. For example, the transistor of the second embodiment An active matrix substrate obtained by the above method can be used.

[0157] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0158] FIG. 6 shows an active matrix electronic paper as an example of a semiconductor device. The transistor 581 used in the device is the same as the transistor described in Embodiment 2. This transistor can be fabricated and has low gate leakage current.

[0159] The electronic paper in Figure 6 is an example of a display device that uses the twist ball display method. The ball display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of the spherical particles that are generated.

[0160] The transistor 581 is a bottom-gate transistor, and the first gate insulating layer 58 2a, an oxide semiconductor layer is provided on and in contact with a second gate insulating layer 582b, The first gate insulating layer 582a is covered with an insulating layer 583 that is in contact with the conductor layer. The insulating film is an insulating film containing ammonium and has a higher dielectric constant than the second gate insulating layer 582b. are.

[0161] The source electrode or the drain electrode of the transistor 581 is formed by the first electrode layer 587 and the insulating layer 588. The first electrode 83, 584, and 585 are in contact with each other through openings formed therein and are electrically connected. Between the layer 587 and the second electrode layer 588 there are black areas 590a and white areas 590b. A spherical particle 589 surrounded by a liquid is provided between a pair of substrates 580 and 596. The spherical particles 589 are filled with a filler 595 such as resin (see FIG. 6). .

[0162] The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential line provided over the same substrate as the transistor 581. The common connection is used to connect the conductive layers disposed between the pair of substrates 580, 596. The second electrode layer 588 can be electrically connected to a common potential line via conductive particles.

[0163] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0164] Through the above process, a power-saving electronic device having a transistor with low gate leakage current is obtained. Paper can be made.

[0165] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0166] (Embodiment 7) In this embodiment, a transistor using an oxide semiconductor and a transistor using a material other than an oxide semiconductor are described. An example in which a transistor having a gate electrode and a gate insulating film are formed over the same substrate will be described below.

[0167] FIG. 7 shows an example of the configuration of a semiconductor device. FIG. 7(A) shows a cross section of the semiconductor device, and FIG. 7B) shows a plan view of the semiconductor device. Here, FIG. 7A shows the A of FIG. 7B. 7(A) and 7(B) correspond to the cross sections taken along lines 1-A2 and B1-B2. The semiconductor device has a transistor 160 using a first semiconductor material in the lower part and a The first semiconductor material is used as the transistor 162. The first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material is an oxide semiconductor. Transistors using materials other than oxide semiconductors can easily operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charge for a long time due to its characteristics. It is possible.

[0168] The transistor 160 in FIG. 7 is formed on a substrate 100 that includes a semiconductor material (e.g., silicon). 00 and the channel forming region 116 provided in between. The impurity region 120 is formed by the metal compound region 124 in contact with the impurity region 120, and the channel A gate insulating layer 108 is provided on the gate forming region 116, and a and a gate electrode 110 formed thereon.

[0169] The substrate 100 containing the semiconductor material may be a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, or a The substrates used include crystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates. Generally, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification, it refers to a substrate having a structure in which a material other than silicon is formed on an insulating surface. The term "SOI substrate" also includes a substrate with a semiconductor layer formed thereon. The semiconductor layer of the SOI substrate is not limited to a silicon semiconductor layer. This includes a configuration in which a semiconductor layer is provided on an insulating substrate such as a silicon substrate via an insulating layer. Let's say.

[0170] An electrode 126 is connected to a portion of the metal compound region 124 of the transistor 160 . Here, the electrode 126 functions as a source electrode or a drain electrode of the transistor 160. In addition, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. The transistor 160 is covered with an insulating layer 128 and an insulating layer 130. In order to achieve high integration, the transistor 160 is It is preferable to have a structure without a sidewall insulating layer. When the characteristics of 0 are important, a sidewall insulating layer is provided on the side of the gate electrode 110, Impurity regions 120 including regions with different impurity concentrations may be provided.

[0171] The transistor 160 can be fabricated using known techniques. The transistor 160 has the feature of being capable of high-speed operation. By using it as a readout transistor, information can be read out at high speed. do.

[0172] After forming the transistor 160, but before forming the transistor 162 and the capacitor element 164 As a process, the insulating layer 128 and the insulating layer 130 are subjected to CMP processing, and the gate electrode 110 and The upper surfaces of the gate electrode 110 and the electrode 126 are exposed. In addition to the CMP process, etching or the like can also be applied as a process to be performed. The etching process may be combined with the CMP process. To improve the performance, the surfaces of the insulating layer 128 and the insulating layer 130 are made as flat as possible. It is desirable.

[0173] Next, a conductive layer is formed on the gate electrode 110, the electrode 126, the insulating layer 128, the insulating layer 130, etc. The conductive layer is selectively etched to form a source electrode or a drain electrode 142a. The source or drain electrode 142b is formed.

[0174] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using Al, Cr, Cu, Ta, T It is possible to use elements selected from I, Mo, and W, or alloys containing the above elements. Mn, Mg, Zr, Be, Nd, Sc, or a combination of these elements Materials that have been modified may also be used.

[0175] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The source or drain electrode 142a and the source or drain electrode 142 It has the advantage of being easy to process into b.

[0176] The channel length (L) of the upper transistor 162 is a and the distance between the bottom ends of the source or drain electrodes 142b. The mask shape used when forming a transistor with a channel length (L) of less than 25 nm When performing exposure for the composition, it is desirable to use extreme ultraviolet light with a short wavelength of several nm to several tens of nm. .

[0177] Next, an insulating layer 143a is formed on the source or drain electrode 142a. An insulating layer 143b is formed on the drain electrode 142b. The insulating layer 143b is formed on the source or drain electrode 142a and the insulating layer 143b. After forming an insulating layer covering the rain electrode 142b, the insulating layer is selectively etched. The insulating layer 143a and the insulating layer 143b can be formed by the gate insulating layer 143a and the gate insulating layer 143b. By providing such an insulating layer, the gate electrode is It is possible to reduce the capacitance between the gate electrode and the source or drain electrode.

[0178] The insulating layer 143a and the insulating layer 143b are made of silicon oxide, silicon oxynitride, silicon nitride, or silicon oxide. The insulating film can be formed using a material containing an inorganic insulating material such as aluminum chloride.

[0179] In addition, in order to reduce the capacitance between the gate electrode and the source electrode or the drain electrode, In this case, it is preferable to form the insulating layer 143a and the insulating layer 143b. It is also possible to configure it without providing it.

[0180] Next, the source or drain electrode 142a and the source or drain electrode 142b are After forming an oxide semiconductor layer so as to cover 42b, the oxide semiconductor layer is selectively etched. The oxide semiconductor layer 144 is formed by etching.

[0181] The oxide semiconductor layer is formed using the material and the formation process described in Embodiment 2.

[0182] After that, the oxide semiconductor layer is preferably subjected to heat treatment (first heat treatment). Excess hydrogen (including water and a hydroxyl group) in the oxide semiconductor layer is removed by first heat treatment; The structure of the oxide semiconductor layer can be adjusted to reduce the density of defect states in the energy gap. The temperature of the first heat treatment can be, for example, 300°C or higher and lower than 550°C, or 400°C or higher and lower than 550°C. The temperature should be 500°C or less.

[0183] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, and heating the object in a nitrogen atmosphere. The process can be carried out under the conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the air. The first heat treatment reduces impurities and makes the I-type By forming an oxide semiconductor layer that is as close to intrinsic or i-type as possible, extremely excellent characteristics can be achieved. It is possible to realize a transistor of the above type.

[0184] Next, a first gate insulating layer 146a is formed in contact with the oxide semiconductor layer 144, and a second gate insulating layer 146b is formed thereon. A second gate insulating layer 146b is formed.

[0185] The first gate insulating layer 146a is formed by depositing silicon oxide using a sputtering method or a plasma CVD method. Silicon nitride, silicon oxynitride, etc. are used.

[0186] The second gate insulating layer 146b is made of a high dielectric constant material having a dielectric constant of 10 or more as shown in the second embodiment. By using high-k film, the gate insulation layer can be made thinner. This suppresses an increase in the leakage current, and allows the semiconductor device to be miniaturized. The total thickness of the edge layer 146a and the second gate insulating layer 146b is 2 nm or more and 100 nm or less. Preferably, the thickness is 10 nm or more and 50 nm or less.

[0187] Next, a gate insulating layer 146b is formed in a region overlapping with the oxide semiconductor layer 144. A source electrode 148a is formed, and an electrode is formed in a region overlapping with the source electrode or drain electrode 142a. forming pole 148b.

[0188] After the first gate insulating layer 146a or the second gate insulating layer 146b is formed, an inactive The second heat treatment is preferably carried out in a gas atmosphere or an oxygen atmosphere. The temperature is 200°C or higher and 450°C or lower, preferably 250°C or higher and 350°C or lower. The second heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. This can reduce variations in the electrical characteristics of the transistor. Since the insulating layer 146a or the second gate insulating layer 146b contains oxygen, the oxide semiconductor layer 1 Oxygen is supplied to the oxide semiconductor layer 44 to compensate for oxygen vacancies in the oxide semiconductor layer 144, thereby forming an I-type (intrinsic) or Alternatively, an oxide semiconductor layer that is as close to i-type as possible can be formed.

[0189] The timing of the second heat treatment is not limited to this. For example, after the gate electrode is formed, A second heat treatment may be performed. Alternatively, the second heat treatment may be performed following the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's okay to let them cum.

[0190] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide The semiconductor layer 144 is highly purified so that it contains as few impurities as possible other than its main components. can.

[0191] The gate electrode 148a and the electrode 148b are formed by forming a conductive layer on the second gate insulating layer 146b. After forming the conductive layer, the conductive layer can be selectively etched.

[0192] Next, an insulating layer is formed on the second gate insulating layer 146b, the gate electrode 148a, and the electrode 148b. The insulating layer 150 and the insulating layer 152 are formed by sputtering. It can be formed by using a deposition method, a CVD method, etc. Also, silicon oxide, silicon oxynitride, etc. The material used is an inorganic insulating material such as silicon nitride, hafnium oxide, or aluminum oxide. It can be formed by

[0193] Next, the first gate insulating layer 146a, the second gate insulating layer 146b, the insulating layer 150, and An opening is formed in the insulating layer 152 so as to reach the source or drain electrode 142b. The opening is formed by selective etching using a mask or the like.

[0194] Here, it is desirable that the opening be formed in a region that overlaps with the electrode 126. By forming openings in the appropriate areas, the increase in element area due to the electrode contact area is suppressed. In other words, the degree of integration of the semiconductor device can be increased.

[0195] Thereafter, an electrode 154 is formed in the opening, and a wiring 15 in contact with the electrode 154 is formed on the insulating layer 152. Form 6.

[0196] The electrode 154 is formed by forming a conductive layer in the region including the opening using, for example, a PVD method or a CVD method. Then, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by the following.

[0197] The wiring 156 is formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. After forming a conductive layer using the above, the conductive layer is patterned to form the conductive layer. The conductive layer is made of an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The elements and alloys containing the above elements can be used. Mn, Mg, Zr, Be , Nd, Sc, or a combination of these materials may be used. , the source electrode or the drain electrode 142a, etc.

[0198] As a result of the above, the transistor 162 including the highly purified oxide semiconductor layer 144 and The capacitor element 164 is completed. The capacitor element 164 is formed by forming a source electrode or a drain electrode 142a , an oxide semiconductor layer 144, a first gate insulating layer 146a and a second gate insulating layer 146b, and electrode 148b.

[0199] In the capacitor 164 of FIG. 7, the oxide semiconductor layer 144 and the first gate insulating layer 146a and the second gate insulating layer 146b are laminated to form a source electrode or a drain electrode. This ensures sufficient insulation between the electrode 142a and the electrode 148b. In order to ensure sufficient capacitance, the capacitor 164 does not include the oxide semiconductor layer 144. In addition, a capacitor element having an insulating layer formed in the same manner as the insulating layer 143a may be used. Furthermore, if capacitance is not required, a configuration without the capacitor element 164 may be adopted. It is also possible to do so.

[0200] By using the highly purified and intrinsic oxide semiconductor layer 144, the off-state of the transistor can be The current can be sufficiently reduced. By using such a transistor, A semiconductor device capable of retaining stored contents for an extremely long period of time can be obtained.

[0201] In addition, in the semiconductor device shown in this embodiment mode, wiring is shared, so that the degree of integration is high. A sufficiently enhanced semiconductor device is realized. By forming it in this way, the increase in the element area due to the electrode contact region can be suppressed, and This allows for even higher integration.

[0202] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0203] (Embodiment 8) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples include:

[0204] In this embodiment, the gate leakage current reduction obtained in any one of the first to third embodiments is An example of an electronic device incorporating a small transistor will be described with reference to FIG.

[0205] FIG. 8(A) shows a notebook-type personal computer manufactured by mounting at least a display device as a component. It is a personal computer, and it has a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, and a 004, etc. In addition, the gate leakage current shown in the fifth embodiment is small. A notebook personal computer has a display device with a low power consumption and a transistor. It has.

[0206] FIG. 8(B) shows a portable information terminal (P DA), and the main body 3021 includes a display unit 3023, an external interface 3025, Operation buttons 3024 and the like are provided. A stylus 3022 is also provided as an accessory for operation. Note that the power-saving transistor having a low gate leakage current shown in Embodiment 5 is used. The portable information terminal has a display device that is powered by the display.

[0207] FIG. 8C shows a power-saving transistor having a low gate leakage current, which is shown in Embodiment 6. This is an electronic book that was created by implementing the powered electronic paper as a component. 27 shows an example of an electronic book. For example, the electronic book 2700 includes a housing 2701 and a housing The housing 2701 and the housing 2703 are connected by a shaft 27 11, and opening and closing operations can be performed with the shaft portion 2711 as an axis. This configuration allows the device to operate like a paper book.

[0208] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 8C), and a An image can be displayed on a display unit (display unit 2707 in FIG. 8C).

[0209] FIG. 8C shows an example in which an operation unit and the like are provided on the housing 2701. The body 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The device may be configured to include a keyboard, a pointing device, etc. or on the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. You may do so.

[0210] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0211] FIG. 8D shows a transistor having a small gate leakage current according to the fifth embodiment. This is a mobile phone manufactured by mounting a powered display device as a single component, and the housing 2800 and The display panel 2802 is configured as a display panel. , a speaker 2803, a microphone 2804, a pointing device 2806, The camera lens 2807 and the external connection terminal 2808 are also provided. The solar cell 2810 that charges the portable information terminal, the external memory slot 2811, etc. The antenna is built into the housing 2801.

[0212] The display panel 2802 is equipped with a touch panel, and in FIG. 8(D) an image is displayed. The multiple operation keys 2805 are indicated by dotted lines. A boost circuit is also implemented to boost the voltage required for each circuit.

[0213] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the lens 2802, allowing video calls. The speaker 2803 and microphone 2804 are not limited to voice calls, but can also be used for video calls. Furthermore, the housing 2800 and the housing 2801 can be slid apart, As shown in Figure 8(D), it can be folded from the unfolded state to the folded state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0214] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. The semiconductor device described in Embodiment 6 can be used as the recording medium. According to [6], by using a transistor that can sufficiently reduce the off-state current, This provides a semiconductor device capable of retaining stored data for a long period of time.

[0215] In addition to the above functions, it also has infrared communication functions, TV reception functions, etc. Good too.

[0216] FIG. 8E shows a power-saving transistor having a low gate leakage current as shown in Embodiment 5. The digital camera is manufactured by mounting an enhanced display device as a single component, and the main body 305 1, display unit (A) 3057, eyepiece unit 3053, operation switch 3054, display unit (B) 30 55, battery 3056, etc.

[0217] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 6. [Explanation of symbols]

[0218] 100 boards 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 116 Channel formation region 120 Impurity region 124 Metal compound area 126 electrode 128 Insulating Layer 130 Insulating layer 142a Drain electrode 142b Drain electrode 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 146a Gate insulating layer 146b Gate insulating layer 148a Gate electrode 148b Electrode 150 insulating layer 152 Insulating layer 154 Electrode 156 Wiring 160 transistors 162 transistors 164 Capacitor 301 Chamber 302 Electrode 303 Electrode 304 RF power supply 305 Substrate 306 Shutter 307 Holder 308 Target 400 boards 401 Gate electrode 402a First gate insulating layer 402b Second gate insulating layer 403 Oxide semiconductor layer 405a Source electrode 405b Drain electrode 407 Insulating Film 409 Protective Insulation Layer 410 Transistor 420 transistors 427 Insulating Layer 430 transistors 436a Wiring layer 436b wiring layer 437 Insulating Layer 440 transistors 505 board 506 Protective insulation layer 507a Gate insulating layer 507b Gate insulating layer 510 Transistor 511 Gate electrode 515a Source electrode 515b Drain electrode 516 Insulating Layer 520 transistor 526 Insulating Layer 530 Oxide semiconductor film 531 Oxide semiconductor layer 580 board 581 Transistor 582a Gate insulating layer 582b Gate insulating layer 583 Insulating Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 595 Filling material 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 External Memory Slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020a Gate insulating layer 4020b Gate insulating layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4041 Insulation layer 4042 Insulation layer

Claims

1. a first transistor, a second transistor, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a silicon layer having a channel formation region of the first transistor and an impurity region; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the first insulating layer and a region in contact with an upper surface of the first conductive layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one electrode of the capacitor; a third conductive layer electrically connected to an impurity region of the first transistor and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a fifth conductive layer having a region overlapping with a channel formation region of the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the oxide semiconductor layer, the fourth conductive layer and the fifth conductive layer have the same material; the third conductive layer is electrically connected to the sixth conductive layer; a seventh conductive layer having a region in contact with the upper surface of the sixth conductive layer; the seventh conductive layer has a region overlapping with the first conductive layer, the seventh conductive layer has an area overlapping with the second conductive layer, the seventh conductive layer has an area overlapping with the fourth conductive layer, the seventh conductive layer has a region overlapping with a channel formation region of the first transistor, a channel formation region of the first transistor not overlapping with the fifth conductive layer;

2. a first transistor, a second transistor, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a silicon layer having a channel formation region of the first transistor and an impurity region; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the first insulating layer and a region in contact with an upper surface of the first conductive layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one electrode of the capacitor; a third conductive layer electrically connected to an impurity region of the first transistor and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a fifth conductive layer having a region overlapping with a channel formation region of the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the oxide semiconductor layer, the fourth conductive layer and the fifth conductive layer have the same material; the third conductive layer is electrically connected to the sixth conductive layer; a seventh conductive layer having a region in contact with the upper surface of the sixth conductive layer; the seventh conductive layer has a region overlapping with the first conductive layer, the seventh conductive layer has an area overlapping with the second conductive layer, the seventh conductive layer has an area overlapping with the fourth conductive layer, the seventh conductive layer has a region overlapping with a channel formation region of the first transistor, a channel formation region of the first transistor does not overlap with the fifth conductive layer; the fourth conductive layer has a region overlapping with the first conductive layer, The display device, wherein the fourth conductive layer is provided in the same layer as the fifth conductive layer.

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