Semiconductor element, semiconductor circuit, semiconductor device, motor system, electric apparatus, and printer

Abstract

To provide a semiconductor element capable of suppressing occurrence of latch-up at current off operation while suppressing increase in mounting area by layout improvement.SOLUTION: A semiconductor element includes: first to fourth transistor formation regions (1, 2, 3, 4) formed mutually apart on a semiconductor substrate (S1) of a first conductivity type; a first impurity region (R1) of the first conductivity type with higher impurity concentration than the semiconductor substrate and formed between the first transistor formation region (2) and the second transistor formation region (3); and a second impurity region of the first conductivity type with higher impurity concentration than the semiconductor substrate and formed between the third transistor formation region (4) and the fourth transistor formation region (1), wherein the first to fourth transistor formation regions are arranged in line along a first direction (X direction).SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a semiconductor element, a semiconductor circuit, a semiconductor device, a motor system, an electric device, and a printer. [Background technology]

[0002] Motor drive circuits that use a bridge output stage to generate a drive current for a motor have been used in a variety of applications. Bridge output stages provided in motor drive circuits include H-bridge output stages and three-phase bridge output stages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-189066 Summary of the Invention [Problem to be solved by the invention]

[0004] In a typical motor drive circuit, there is a risk of unintended latch-up occurring during a current-off operation in which the drive current flowing through the motor's excitation coil is switched from an on state to an off state.

[0005] Paragraph 0076 of Patent Document 1 gives examples of layout solutions to prevent latch-up, including (i) a layout that widens the distance between the first-phase high-side transistor and the second-phase low-side transistor, (ii) a layout that embeds an isolation section between the first-phase high-side transistor and the second-phase low-side transistor, and (iii) a layout that forms an n-type well to which a power supply voltage is applied and a p-type well to which a ground voltage is applied, thereby making the second-phase low-side transistor a floating structure. However, the above latch-up solutions (i) to (iii) have the disadvantage of increasing the mounting area.

[0006] The motor drive circuit disclosed in this specification includes a first-phase half-bridge circuit and a second-phase half-bridge circuit. The first-phase half-bridge circuit includes a first-phase high-side FET configured to receive a first voltage at a first terminal thereof, and a first-phase low-side FET configured to have a second terminal of the first-phase high-side FET connected to its first terminal and to receive a second voltage lower than the first voltage at its second terminal thereof. The second-phase half-bridge circuit includes a second-phase high-side FET configured to receive the first voltage at its first terminal thereof, and a second-phase low-side FET configured to have a second terminal of the second-phase high-side FET connected to its first terminal thereof and to receive the second voltage at its second terminal thereof. The first-phase low-side FET or the second-phase high-side FET is disposed between the first-phase high-side FET and the second-phase low-side FET. The second-phase low-side FET or the first-phase high-side FET is disposed between the first-phase low-side FET and the second-phase high-side FET.

[0007] The motor system disclosed in this specification includes a motor and a motor drive circuit configured to drive the motor.

[0008] The electric device disclosed in this specification includes a motor system having the above-described configuration. [Effects of the Invention]

[0009] According to the motor drive circuit, motor system, and electrical equipment disclosed in this specification, by devising a layout, it is possible to suppress an increase in mounting area while suppressing the occurrence of latch-up during current-off operation. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the configuration of a motor drive circuit according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the vertical structures of an N-channel FET and a P-channel FET. [Figure 3]FIG. 3 is a diagram showing a thyristor formed by a parasitic PNP transistor Q1 and a parasitic NPN transistor Q2. [Figure 4] FIG. 4 is a diagram showing a first layout example of a P-channel FET and an N-channel FET. [Figure 5] FIG. 5 is a diagram showing an example of a wiring pattern in the first layout example. [Figure 6] FIG. 6 is a diagram showing another example of the wiring pattern in the first layout example. [Figure 7] FIG. 7 is a diagram showing a second layout example of the P-channel FET and the N-channel FET. [Figure 8] FIG. 8 is a diagram showing a third layout example of the P-channel FET and the N-channel FET. [Figure 9] FIG. 9 is a diagram showing a fourth layout example of the P-channel FET and the N-channel FET. [Figure 10] FIG. 10 is a diagram showing the configuration of a motor drive circuit according to the second embodiment. [Figure 11] FIG. 11 is a diagram showing the vertical structure of an N-channel FET. [Figure 12] FIG. 12 is a block diagram of the motor system. [Figure 13] FIG. 13 is a perspective view of the printer. [Figure 14] FIG. 14 is a diagram showing the configuration of a motor drive circuit according to a modified example. [Figure 15] FIG. 15 is a diagram showing an example of the layout of a P-channel FET and an N-channel FET. DETAILED DESCRIPTION OF THE INVENTION

[0011] First Embodiment FIG. 1 is a diagram showing the configuration of a motor drive circuit 10 (hereinafter referred to as "motor drive circuit 10") according to the first embodiment.

[0012] The motor drive circuit 10 includes a first-phase half-bridge circuit HB1 and a second-phase half-bridge circuit HB2.

[0013] The first-phase half-bridge circuit HB1 includes a P-channel FET (Field Effect Transistor) 1 and an N-channel FET 2. The P-channel FET 1 is a first-phase high-side FET, and the N-channel FET 2 is a first-phase low-side FET.

[0014] A power supply voltage VCC is applied to the source and back gate of the P-channel FET 1 .

[0015] The drain of the N-channel FET 2 is connected to the drain of the P-channel FET 1. A ground voltage is applied to the source and back gate of the N-channel FET 2. The ground voltage is lower than the power supply voltage VCC.

[0016] A parasitic diode D1 is formed in the P-channel FET1. The anode of the parasitic diode D1 is connected to the drain of the P-channel FET1, and the cathode of the parasitic diode D1 is connected to the source and back gate of the P-channel FET1. A parasitic diode D2 is formed in the N-channel FET2. The anode of the parasitic diode D2 is connected to the source and back gate of the N-channel FET1, and the cathode of the parasitic diode D2 is connected to the drain of the N-channel FET1.

[0017] The second-phase half-bridge circuit HB2 includes a P-channel FET 3 and an N-channel FET 4. The P-channel FET 3 is a second-phase high-side FET, and the N-channel FET 4 is a second-phase low-side FET.

[0018] A power supply voltage VCC is applied to the source and back gate of the P-channel FET 3 .

[0019] The drain of the N-channel FET 4 is connected to the drain of the P-channel FET 3. The source and back gate of the N-channel FET 4 are applied with a ground voltage.

[0020] A parasitic diode D3 is formed in the P-channel FET 3. The anode of the parasitic diode D3 is connected to the drain of the P-channel FET 3, and the cathode of the parasitic diode D3 is connected to the source and back gate of the P-channel FET 3. A parasitic diode D4 is formed in the N-channel FET 4. The anode of the parasitic diode D4 is connected to the source and back gate of the N-channel FET 4, and the cathode of the parasitic diode D4 is connected to the drain of the N-channel FET 4.

[0021] The connection node N1 is a connection node between the drain of the P-channel FET 1 and the drain of the N-channel FET 2. The connection node N2 is a connection node between the drain of the P-channel FET 3 and the drain of the N-channel FET 4. A stepping motor 20 is provided between the connection nodes N1 and N2. More specifically, the stepping motor 20 includes a first excitation coil and a second excitation coil, with a first end of the first excitation coil connected to the connection node N1 and a second end of the first excitation coil connected to the connection node N2.

[0022] When P-channel FET1 and N-channel FET4 are on and P-channel FET3 and N-channel FET2 are off, a drive current flows through the first excitation coil in the direction from connection node N1 to connection node N2. If P-channel FET1 and FET3 and N-channel FET2 and N-channel FET4 are turned off from this state, the first excitation coil attempts to continue to pass the drive current in the same direction. Therefore, as shown by the dashed arrow in Figure 1, the drive current flows through a current path from the ground application terminal through parasitic diode D2, the first excitation coil, and parasitic diode D3 to the power supply voltage VCC application terminal.

[0023] Fig. 2 is a diagram showing the vertical structure of the N-channel FET 2 and the P-channel FET 3. Note that Fig. 2 shows parts related to the parasitic diodes and parasitic transistors, and omits parts unrelated to the parasitic diodes and parasitic transistors.

[0024] The N-channel FET 2 and the P-channel FET 3 are formed on a P-type semiconductor substrate S1. A heavily doped P-type region R1 is also formed on the P-type semiconductor substrate S1. The heavily doped P-type region R1 is an application terminal for the ground voltage.

[0025] The N-channel FET 2 includes an N-type region 21, a P-type region 22, a heavily doped P-type region 23, and a heavily doped N-type region 24. The heavily doped P-type region 23 is the back gate of the N-channel FET 2, and the heavily doped N-type region 24 is the drain of the N-channel FET 2.

[0026] The P-channel FET 3 includes an N-type region 31, a P-type region 32, a heavily doped P-type region 33, and a heavily doped N-type region 34. The heavily doped P-type region 33 is the drain of the P-channel FET 3, and the heavily doped N-type region 34 is the back gate of the P-channel FET 3.

[0027] A parasitic diode D2 is formed by the P-type semiconductor substrate S1, the P-type region 22, and the N-type region 21, and a parasitic diode D3 is formed by the P-type region 32 and the N-type region 31. A parasitic PNP transistor Q1 is formed by the P-type region 32, the N-type region 31, and the P-type semiconductor substrate S1, and a parasitic NPN transistor Q2 is formed by the N-type region 31, the P-type semiconductor substrate S1, and the N-type region 21.

[0028] When the drive current indicated by the dashed arrow in Fig. 1 flows, the current indicated by the dashed arrow in Fig. 2 flows. In other words, when the drive current indicated by the dashed arrow in Fig. 1 flows, a current also flows through the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2. The parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 form a thyristor as shown in Fig. 3. Therefore, if the gain of the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 is high, the thyristor formed by the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 turns on during current-off operation, causing latch-up.

[0029] On the other hand, when P-channel FET1 and N-channel FET4 are off and P-channel FET3 and N-channel FET2 are on, a drive current flows from connection node N2 to connection node N1 through the first excitation coil. If P-channel FET1 and FET3 and N-channel FET2 and N-channel FET4 are turned off in this state, the first excitation coil attempts to continue to pass the drive current in the same direction. Therefore, the drive current flows through a current path from the ground application terminal through parasitic diode D4, the first excitation coil, and parasitic diode D1 to the power supply voltage VCC application terminal.

[0030] Therefore, similar to the N-channel FET 2 and P-channel FET 3 described above, latch-up also occurs in the P-channel FET 1 and N-channel FET 4 when the gain of the parasitic transistor is high.

[0031] In addition to the H-bridge (first-phase half-bridge circuit HB1 and second-phase half-bridge circuit HB2) for passing a drive current to the first excitation coil of the stepping motor 20, the motor drive circuit 10 also includes an H-bridge for passing a drive current to the second excitation coil of the stepping motor 20.

[0032] The H-bridge for passing a drive current through the second excitation coil of the stepping motor 20 has the same configuration as the H-bridge for passing a drive current through the first excitation coil of the stepping motor 20. In addition, each layout example described below may also be applied to the H-bridge for passing a drive current through the second excitation coil of the stepping motor 20.

[0033] <First layout example> Fig. 4 is a diagram showing a first layout example of the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4. Fig. 4 is a top view of the main part of a semiconductor chip on which the motor drive circuit 10 is mounted.

[0034] In the first layout example, a second-phase low-side FET 4 is placed between an N-channel FET 2, which is a first-phase low-side FET, and a P-channel FET 3, which is a second-phase high-side FET. This makes it possible to reduce the gain of the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 shown in FIG. 2 without providing a dead space as in Patent Document 1.

[0035] In the first layout example, an N-channel FET 2, which is a first-phase low-side FET, is placed between a P-channel FET 1, which is a first-phase high-side FET, and an N-channel FET 4, which is a second-phase low-side FET. This makes it possible to reduce the gain of the parasitic transistor without providing a dead space as in Patent Document 1.

[0036] Therefore, according to the first layout example, it is possible to suppress the occurrence of latch-up during the current-off operation while suppressing an increase in the mounting area.

[0037] Furthermore, in the first layout example and the fourth layout described later, unlike the second and third layout examples described later, the P-channel FET 1, which is the first-phase high-side FET, and the N-channel FET 2, which is the first-phase low-side FET, are adjacent to each other, eliminating the need to route a wiring pattern connecting the drain of the P-channel FET 1 and the drain of the N-channel FET 2. Similarly, in the first layout example and the fourth layout described later, unlike the second and third layout examples described later, the P-channel FET 3, which is the second-phase high-side FET, and the N-channel FET 4, which is the second-phase low-side FET, are adjacent to each other, eliminating the need to route a wiring pattern connecting the drain of the P-channel FET 3 and the drain of the N-channel FET 4.

[0038] It is desirable that the length W1 of each of the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4 in the direction in which the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4 are arranged (X direction) be shorter than the length L1 in the direction perpendicular to the X direction and the thickness direction of the substrate (in this embodiment, a P-type semiconductor substrate S1) on which the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4 are formed (Y direction). This prevents the mounting area of ​​the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4 from being extremely elongated in the X direction. The lengths W1 of the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4 may all be the same, or at least one may be different from the others. The lengths L1 of the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4 may all be the same, or at least one may be different from the others. The thickness direction of the substrate described above can be defined, for example, as the direction perpendicular to the surface of the impurity regions (P-type regions, N-type regions) formed in the substrate that are exposed to the outside of the substrate.

[0039] Fig. 5 is a diagram showing an example of a wiring pattern in the first layout example, and Fig. 6 is a diagram showing another example of a wiring pattern in the first layout example.

[0040] The first conductor portion C1 is connected to the source 1A of the P-channel FET 1 and the source 3A of the P-channel FET 3. The first conductor portion C1 is separated into a first region connected to the source 1A of the P-channel FET 1 and a second region connected to the source 3A of the P-channel FET 3, and the first and second regions are electrically connected to each other by a connecting wiring pattern (not shown). The connecting wiring pattern is located, for example, on one side of the first and second regions in the Y direction or on the other side of the first and second regions in the Y direction and extends along the X direction. The second conductor portion C2 is connected to the drain 1B of the P-channel FET 1 and the drain 2A of the N-channel FET 2. The third conductor portion C3 is connected to the source 2B of the N-channel FET 2 and the source 4B of the N-channel FET 4. The fourth conductor portion C4 is connected to the drain 3B of the P-channel FET 3 and the drain 4A of the N-channel FET 4.

[0041] 5, the first to fourth conductor portions C1 to C4 do not overlap when viewed from a direction (Y direction) perpendicular to the direction in which the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4 are lined up (X direction) and the thickness direction of the base material (P-type semiconductor substrate S1 in this embodiment) on which the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4 are formed. This wiring pattern makes it easy to arrange the source and drain of each FET along the X direction.

[0042] 6, when viewed from the Y direction, the second conductor portion C2 overlaps with the first conductor portion C1 and the third conductor portion C3, the fourth conductor portion C4 overlaps with the first conductor portion C1 and the third conductor portion C3, and the second conductor portion C2 and the fourth conductor portion C4 do not overlap with each other. This wiring pattern makes it easy to arrange the source and drain of each FET along the Y direction.

[0043] <Layout examples 2 to 4> 7 to 9 are diagrams showing second to fourth layout examples of the P-channel FETs 1 and 3 and the N-channel FETs 2 and 4. FIG.

[0044] In the second layout example shown in FIG. 7, a P-channel FET 3 serving as a second-phase high-side FET is placed between a P-channel FET 1 serving as a first-phase high-side FET and an N-channel FET 4 serving as a second-phase low-side FET.

[0045] In addition, an N-channel FET 4 serving as a second-phase low-side FET is disposed between an N-channel FET 2 serving as a first-phase low-side FET and a P-channel FET 3 serving as a second-phase high-side FET.

[0046] According to the second layout example, similar to the first layout example, it is possible to suppress an increase in the mounting area and also to suppress the occurrence of latch-up during the current-off operation.

[0047] In the third layout example shown in FIG. 8, an N-channel FET 2 serving as a first-phase low-side FET is placed between a P-channel FET 1 serving as a first-phase high-side FET and an N-channel FET 4 serving as a second-phase low-side FET.

[0048] In the third layout example shown in FIG. 8, a P-channel FET 1 serving as a first-phase high-side FET is placed between an N-channel FET 2 serving as a first-phase low-side FET and a P-channel FET 3 serving as a second-phase high-side FET.

[0049] According to the third layout example, similar to the first layout example, it is possible to suppress an increase in the mounting area and also to suppress the occurrence of latch-up during the current-off operation.

[0050] In the fourth layout example shown in FIG. 9, a P-channel FET 3 serving as a second-phase high-side FET is placed between a P-channel FET 1 serving as a first-phase high-side FET and an N-channel FET 4 serving as a second-phase low-side FET.

[0051] In addition, in the fourth layout example shown in FIG. 9, a P-channel FET 1 which is the first-phase high-side FET is arranged between an N-channel FET 2 which is the first-phase low-side FET and a P-channel FET 3 which is the second-phase high-side FET.

[0052] According to the fourth layout example, similar to the first layout example, it is possible to suppress an increase in the mounting area and also to suppress the occurrence of latch-up during the current-off operation.

[0053] Second Embodiment FIG. 10 is a diagram showing the configuration of a motor drive circuit 10' according to the second embodiment (hereinafter referred to as "motor drive circuit 10'").

[0054] Motor drive circuit 10′ differs from motor drive circuit 10 in that it uses an N-channel FET 1′ as the first-phase high-side FET and an N-channel FET 3′ as the second-phase high-side FET, but is otherwise similar to motor drive circuit 10.

[0055] Fig. 11 is a diagram showing the vertical structure of N-channel FETs 2 and 3'. Note that Fig. 11 shows parts related to parasitic diodes and parasitic transistors, and omits parts unrelated to the parasitic diodes and parasitic transistors.

[0056] In the motor drive circuit 10', a parasitic transistor similar to that in the motor drive circuit 10 is formed, and therefore by using a layout of each FET similar to that in the motor drive circuit 10, it is possible to suppress an increase in the mounting area while suppressing the occurrence of latch-up during current-off operation.

[0057] <Motor system> Fig. 12 is a block diagram of a motor system. The motor system 100 shown in Fig. 12 includes a stepping motor 20, a motor drive circuit 10 configured to drive the stepping motor 20, and a control unit 30 configured to control the switching of each FET in the motor drive circuit 10. Naturally, a motor drive circuit 10' may be used in place of the motor drive circuit 10.

[0058] <Electrical equipment> The above-described motor system 100 is built into, for example, a printer 200 shown in Fig. 13 and is used as part of a paper feed mechanism. Naturally, the above-described motor system 100 may also be mounted on electrical equipment other than a printer.

[0059] <Points to note> In addition to the above-described embodiments, various modifications can be made to the configuration of the present invention without departing from the spirit of the invention. The above-described embodiments are illustrative in all respects and should be considered not to be limiting. The technical scope of the present invention is defined by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0060] In the above-described embodiment, the motor drive circuit drives a stepping motor including a first excitation coil and a second excitation coil, but the motor drive circuit may drive a motor other than a stepping motor.

[0061] A motor drive circuit 10" according to a modified example shown in FIG. 14 drives a three-phase brushless motor 40. The motor drive circuit 10" according to the modified example includes a third-phase half-bridge circuit HB3 in addition to a first-phase half-bridge circuit HB1 and a second-phase half-bridge circuit HB2. The third-phase half-bridge circuit HB3 includes a P-channel FET5 and an N-channel FET6. The P-channel FET5 is a third-phase high-side FET, and the N-channel FET6 is a third-phase low-side FET.

[0062] A parasitic diode D5 is formed in the P-channel FET 5. A parasitic diode D6 is formed in the N-channel FET 6.

[0063] In a motor drive circuit 10" according to a modified example, as shown in FIG. 15, for example, the first-phase high-side FET, first-phase low-side FET, second-phase high-side FET, and second-phase low-side FET may be arranged in the same manner as in the first layout example described above, and further, a P-channel FET 5 serving as a third-phase high-side FET may be arranged between a P-channel FET 3 serving as a second-phase high-side FET and an N-channel FET 6 serving as a third-phase low-side FET.

[0064] The motor drive circuit (10, 10', 10") described above includes a first-phase half-bridge circuit (HB1) and a second-phase half-bridge circuit (HB2), the first-phase half-bridge circuit includes a first-phase high-side FET (1, 1') configured to have a first voltage applied to a first terminal, and a first-phase low-side FET (2) configured to have a second terminal of the first-phase high-side FET connected to the first terminal and to have a second voltage lower than the first voltage applied to a second terminal, and the second-phase half-bridge circuit includes a first-phase high-side FET (1, 1') configured to have a first terminal of the first-phase high-side FET connected to the first terminal and to have a second voltage lower than the first voltage applied to a second terminal. and a second-phase low-side FET (4) having a first end to which a second end of the second-phase high-side FET is connected and having the second voltage applied to a second end, wherein the first-phase low-side FET or the second-phase high-side FET is arranged between the first-phase high-side FET and the second-phase low-side FET, and the second-phase low-side FET or the first-phase high-side FET is arranged between the first-phase low-side FET and the second-phase high-side FET.

[0065] The motor drive circuit having the first configuration can suppress the occurrence of latch-up during the current-off operation while suppressing an increase in the mounting area.

[0066] The motor drive circuit having the first configuration may have a configuration (second configuration) in which the first-phase low-side FET is disposed between the first-phase high-side FET and the second-phase low-side FET.

[0067] The motor drive circuit having the second configuration described above eliminates the need to route a wiring pattern connecting the drain of the first-phase high-side FET and the drain of the first-phase low-side FET, and eliminates the need to route a wiring pattern connecting the drain of the second-phase high-side FET and the drain of the second-phase low-side FET.

[0068] The motor drive circuit having the second configuration may further include a first conductor configured to be connected to a first end of the first-phase high-side FET and a first end of the second-phase high-side FET, a second conductor configured to be connected to a second end of the first-phase high-side FET and a first end of the first-phase low-side FET, a third conductor configured to be connected to the second end of the first-phase low-side FET and a second end of the second-phase low-side FET, and a fourth conductor configured to be connected to the second end of the second-phase high-side FET and a first end of the second-phase low-side FET, wherein the first conductor, the second conductor, the third conductor, and the fourth conductor do not overlap when viewed in a direction perpendicular to an arrangement direction of the first-phase high-side FET, the first-phase low-side FET, the second-phase low-side FET, and the second-phase high-side FET and a thickness direction of a substrate on which the first-phase high-side FET, the first-phase low-side FET, the second-phase low-side FET, and the second-phase high-side FET are formed (third configuration).

[0069] In the motor drive circuit having the third configuration, the first and second ends of each FET can be easily arranged along the direction in which the FETs are lined up.

[0070] The motor drive circuit having the second configuration described above includes a first conductor configured to be connected to a first end of the first-phase high-side FET and a first end of the second-phase high-side FET, a second conductor configured to be connected to a second end of the first-phase high-side FET and a first end of the first-phase low-side FET, a third conductor configured to be connected to a second end of the first-phase low-side FET and a second end of the second-phase low-side FET, and a fourth conductor configured to be connected to a second end of the second-phase high-side FET and a first end of the second-phase low-side FET. Alternatively, when viewed from a direction perpendicular to a direction in which the first phase high-side FET, the first phase low-side FET, the second phase low-side FET, and the second phase high-side FET are arranged and a thickness direction of a substrate on which the first phase high-side FET, the first phase low-side FET, the second phase low-side FET, and the second phase high-side FET are formed, the second conductor overlaps with the first conductor and the third conductor, the fourth conductor overlaps with the first conductor and the third conductor, and the second conductor and the fourth conductor do not overlap with each other (fourth configuration).

[0071] In the motor drive circuit having the fourth configuration, the first and second ends of each FET can be easily arranged along a direction perpendicular to the direction in which the FETs are lined up.

[0072] In the motor drive circuit having any of the first to fourth configurations, the first phase high-side FET, the first phase low-side FET, the second phase high-side FET, and the second phase low-side FET may each have a length in a direction in which the first phase high-side FET, the first phase low-side FET, the second phase high-side FET, and the second phase low-side FET are arranged that is shorter than a length in a direction perpendicular to the direction in which the first phase high-side FET, the first phase low-side FET, the second phase high-side FET, and the second phase low-side FET are arranged and to a thickness direction of a base material on which the first phase high-side FET, the first phase low-side FET, the second phase high-side FET, and the second phase low-side FET are formed (fifth configuration).

[0073] The motor drive circuit having the fifth configuration can prevent the mounting area of ​​the first-phase high-side FET, the first-phase low-side FET, the second-phase high-side FET, and the second-phase low-side FET from becoming extremely elongated in the direction in which the first-phase high-side FET, the first-phase low-side FET, the second-phase high-side FET, and the second-phase low-side FET are arranged.

[0074] The motor system (100) described above has a configuration (sixth configuration) including a motor (20) and a motor drive circuit having any one of the first to fifth configurations configured to drive the motor.

[0075] The motor system having the sixth configuration can suppress the occurrence of latch-up during the current-off operation while suppressing an increase in the mounting area of ​​the motor drive circuit.

[0076] The electric device (200) described above has a configuration (seventh configuration) including the motor system of the sixth configuration.

[0077] The electric device having the seventh configuration can suppress the occurrence of latch-up during the current-off operation while suppressing an increase in the mounting area of ​​the motor drive circuit. [Explanation of symbols]

[0078] 1, 3 P-channel FET 1A, 3A P-channel FET source 1B, 3B P-channel FET drain 2, 4, 1', 3' N-channel FET 2A, 2A N-channel FET drain 2B, 2B N-channel FET source 10 Motor drive circuit according to the first embodiment 10' Motor drive circuit according to the second embodiment 20 Stepping motor 21, 31 N-type region 22, 32 P-type region 23, 33 Highly concentrated P-type region 24, 34 Highly concentrated N-type region 30 Control Unit 40 Three-phase brushless motor 100 Motor System 200 printers C1~C4 1st~4th conductor part D1~D4 Parasitic diodes HB1~HB3 1st to 3rd phase half-bridge circuits Q1 Parasitic PNP transistor Q2 Parasitic NPN transistor R1 High concentration P type region S1 P-type semiconductor substrate

Claims

1. first to fourth transistor formation regions formed spaced apart from one another on a semiconductor substrate of a first conductivity type; a first impurity region of a first conductivity type formed between the first transistor forming region and the second transistor forming region and having an impurity concentration higher than that of the semiconductor substrate; a second impurity region of the first conductivity type formed between the third transistor forming region and the fourth transistor forming region and having an impurity concentration higher than that of the semiconductor substrate, The first to fourth transistor forming regions are arranged side by side in a first direction.

2. 2. The semiconductor device according to claim 1, wherein either the third transistor forming region or the fourth transistor forming region is disposed between the first transistor forming region and the second transistor forming region.

3. The semiconductor device according to claim 1 , wherein the first impurity region and the second impurity region are terminals to which a ground voltage is applied.

4. 4. The semiconductor device according to claim 3, wherein each of the first to fourth transistor forming regions includes a second region of a second conductivity type and a first region of a first conductivity type formed within the second region.

5. The semiconductor device according to claim 1 , further comprising: a first electrode formed on the second region of each of the first to fourth transistor forming regions; and a second electrode formed on the second region.

6. 6. The semiconductor device according to claim 5, wherein the first electrode of the second transistor forming region and the second electrode of the first transistor forming region are configured to be connectable to a load.

7. 6. The semiconductor device according to claim 5, wherein the second electrode of the second transistor forming region is a terminal to which a power supply voltage is applied, and the first electrode of the first transistor forming region is a terminal to which a ground voltage is applied.

8. 6. The semiconductor device according to claim 5, wherein the first electrode of the third transistor forming region and the second electrode of the fourth transistor forming region are configured to be connectable to a load.

9. 6. The semiconductor device according to claim 5, wherein the second electrode of the third transistor forming region is a terminal to which a power supply voltage is applied, and the first electrode of the fourth transistor forming region is a terminal to which a ground voltage is applied.

10. A first-phase half-bridge circuit and a second-phase half-bridge circuit are included. A semiconductor circuit, wherein the first-phase half-bridge circuit and the second-phase half-bridge circuit are configured with the semiconductor elements according to claim 1 .

11. 11. The semiconductor circuit according to claim 10, wherein the first-phase half-bridge circuit is composed of FETs formed in the first transistor forming region and the fourth transistor forming region, and the second-phase half-bridge circuit is composed of FETs formed in the second transistor forming region and the third transistor forming region.

12. A control unit; The semiconductor circuit according to claim 10, configured to be controlled by the control unit. A semiconductor device comprising:

13. A motor; The semiconductor device according to claim 12 configured to drive the motor; A motor system comprising:

14. An electric machine comprising the motor system according to claim 13.

15. A printer comprising the motor system of claim 13.

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