Manufacturing method of semiconductor device

Abstract

To accurately forme each trench when a plurality of trenches are formed on a surface of a semiconductor wafer by etching.SOLUTION: A manufacturing method of a semiconductor device, comprises the steps of: forming a deposit of powder composed of a substance scattered from a dummy wafer on a surface of a stage around the dummy wafer by performing sputtering etching on the dummy wafer in a state where the dummy wafer is placed on the stage; and forming a plurality of trenches in a semiconductor wafer by dry etching the semiconductor wafer through a mask in a state where the semiconductor wafer having a surface provided with the mask having a plurality of openings is placed on the stage. In the step of forming the trench, the deposit is dry-etched together with the semiconductor wafer.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

[0002] A technique for forming multiple trenches on the surface of a semiconductor wafer by dry etching the surface of the semiconductor wafer through a mask is known. When forming multiple trenches in this manner, the trenches may be deeper at the periphery of the semiconductor wafer (i.e., the area surrounding the center) than at the center. This phenomenon is thought to occur because the etching environment is different between the center and the periphery of the semiconductor wafer. In other words, because there is no material to be etched on the periphery side of the semiconductor wafer, the concentration of activated species is higher at the periphery of the semiconductor wafer than at the center. As a result, the etching rate is higher at the periphery than at the center, and the trenches are thought to be deeper at the periphery than at the center.

[0003] Patent Document 1 discloses a technique for suppressing variations in trench depth between the center and periphery of a semiconductor wafer. In this technique, a semiconductor wafer and a dummy wafer are placed on a stage so that a dummy wafer made of the same material as the semiconductor wafer is exposed around the periphery of the semiconductor wafer, and the semiconductor wafer is dry-etched in this state. If a dummy wafer made of the same material as the semiconductor wafer is exposed around the periphery of the semiconductor wafer, the environment during etching is made uniform between the center and periphery of the semiconductor wafer, making it possible to make the trench depth uniform between the center and periphery. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-264227 Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology of Patent Document 1, a semiconductor wafer and a dummy wafer are placed one on top of the other on a stage. During etching, the semiconductor wafer is cooled by the stage. If a dummy wafer is placed on top of the semiconductor wafer, it becomes difficult to control the temperature of the semiconductor wafer, and the etching rate becomes unstable. This specification proposes a technology for accurately forming each trench when forming multiple trenches by etching on the surface of a semiconductor wafer. [Means for solving the problem]

[0006] The present specification discloses a method for manufacturing a semiconductor device, comprising the steps of: sputter-etching a dummy wafer placed on a stage to form a powder deposit composed of material scattered from the dummy wafer on the surface of the stage around the dummy wafer; and dry-etching a semiconductor wafer having a mask with a plurality of openings on its surface, placed on the stage, to form a plurality of trenches in the semiconductor wafer through the mask. In the step of forming the trenches, the deposit is dry-etched together with the semiconductor wafer.

[0007] In this manufacturing method, a powder deposit is formed on a stage by sputter etching a dummy wafer. Therefore, during the process of dry etching a semiconductor wafer, the powder deposit is present on the stage around the semiconductor wafer. During the process of dry etching a semiconductor wafer, the deposit is dry etched along with the semiconductor wafer. Because the activated species of the etching gas are consumed by the deposit, differences in the concentration of activated species are unlikely to occur between the center and periphery of the semiconductor wafer. Therefore, differences in trench depth are unlikely to occur between the center and periphery of the semiconductor wafer. Furthermore, because the powder deposit has a small heat capacity, it has almost no effect on the temperature distribution on the stage. Therefore, the temperature of the semiconductor wafer can be accurately controlled. Therefore, this manufacturing method allows for a stable etching rate and accurate trench formation. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. [Figure 2] 1 is a cross-sectional view of a semiconductor wafer and a mask. [Figure 3] FIG. 10 is a cross-sectional view of the stage in a first preparation step. [Figure 4] FIG. [Figure 5] FIG. [Figure 6] FIG. [Figure 7] Cross section of a MOSFET. DETAILED DESCRIPTION OF THE INVENTION

[0009] FIG. 1 shows a semiconductor wafer 10 to be processed by the manufacturing method of the embodiment. The semiconductor wafer 10 is made of silicon carbide (i.e., SiC). In FIG. 1, dashed lines indicate dicing lines 12. The semiconductor wafer 10 will be cut along the dicing lines 12 in a later process and divided into multiple chips. Note that the dicing lines 12 are cutting positions in design, and no lines corresponding to the dicing lines 12 are drawn on the surface of the semiconductor wafer 10. Furthermore, element regions 14 surrounded by the dicing lines 12 are regions that will become semiconductor devices after dicing. In FIG. 1, the hatched region is an outer periphery 22 of the semiconductor wafer 10, and the non-hatched region is a central portion 20 of the semiconductor wafer 10. The outer periphery 22 is the area surrounding the central portion 20. Element regions 14 exist in both the central portion 20 and the outer periphery 22. Hereinafter, the element region 14 in the central portion 20 will be referred to as element region 14a, and the element region 14 in the outer periphery 22 will be referred to as element region 14b. The region of the outer peripheral portion 22 that is outside the element region 14b is referred to as the peripheral region 15. In this embodiment, a semiconductor device is manufactured by forming a plurality of trenches in each element region 14. In the following, a direction along the top surface of the semiconductor wafer 10 is referred to as the x-direction, and a direction along the top surface of the semiconductor wafer 10 and perpendicular to the x-direction is referred to as the y-direction.

[0010] First, as shown in FIG. 2, a mask 30 is formed on the upper surface 18 of the semiconductor wafer 10. The mask 30 is made of silicon oxide and has a plurality of openings 32. A plurality of openings 32 are provided in each of the element regions 14. Each opening 32 extends elongatedly along the y direction. In each element region 14, the openings 32 are arranged at intervals in the x direction. No openings 32 are provided in the peripheral region 15. The mask 30 is formed, for example, by depositing a silicon oxide layer and then patterning the silicon oxide layer by photolithography.

[0011] Next, a trench formation process is performed. The trench formation process includes a first preparation process, a second preparation process, and a dry etching process. The first preparation process is a process of cleaning the stage of the etching device. The second preparation process is a process of forming a deposit on the stage of the etching device. The dry etching process is a process of etching the semiconductor wafer 10 using the etching device. The etching device mass-produces semiconductor devices by repeatedly performing a set of the first preparation process, the second preparation process, and the dry etching process. These processes are described below.

[0012] FIG. 3 is an enlarged cross-sectional view of a portion of a stage 90 of an etching apparatus, including the outer periphery. The stage 90 is disposed within a chamber of the etching apparatus. The stage 90 includes a stage body 92 and a focus ring 94. The stage body 92 is disk-shaped. Although not shown, a flow path through which a coolant flows is provided inside the stage body 92. The stage body 92 is capable of cooling a wafer placed on the stage body 92. The focus ring 94 is ring-shaped. The focus ring 94 is fixed to the upper surface of the stage body 92 and extends along the outer periphery of the stage body 92. The focus ring 94 forms the outer periphery of the stage 90. The focus ring 94 is made of a material that is difficult to etch (e.g., quartz).

[0013] As described above, in the etching apparatus, a set of the first preparation step, the second preparation step, and the dry etching step is repeatedly performed. Also, as described above, in the second preparation step, deposits are formed on the stage 90 of the etching apparatus. Therefore, as shown in FIG. 3, before the start of the first preparation step, deposits 80 are attached to the surface of the stage 90. The deposits 80 are formed by the accumulation of silicon oxide particles. The deposits 80 are attached to the surface of the focus ring 94.

[0014] In the first preparation step, the deposit 80 is etched by supplying an etching gas capable of etching silicon oxide to the surface of the stage 90. As a result, the deposit 80 is removed as shown in FIG.

[0015] In the second preparation step, as shown in FIG. 4 , a dummy wafer 82 is placed on a stage 90. The dummy wafer 82 has a silicon layer 84 and a silicon oxide layer 86 covering the surface of the silicon layer 84. Here, the dummy wafer 82 is placed on the stage body 92 with the silicon oxide layer 86 facing upward. Therefore, a focus ring 94 is present on the outer periphery of the dummy wafer 82. In the second preparation step, sputtering is performed using the silicon oxide layer 86 of the dummy wafer 82 as a target. That is, sputter etching is performed on the silicon oxide layer 86. Note that argon, for example, can be used as an inert gas for sputtering. During sputtering, argon ions collide with the silicon oxide layer 86 of the dummy wafer 82. This causes silicon oxide particles to scatter from the silicon oxide layer 86. The scattered silicon oxide particles accumulate on the surface of the focus ring 94, forming a deposit 80. In this way, the deposit 80 is formed by the accumulation of silicon oxide particles, so the deposit 80 has a structure in which powder is layered. Therefore, the deposit 80 has voids inside and a large surface area. The amount of deposit 80 can be controlled by the execution time of sputtering. After the deposit 80 is formed, the dummy wafer 82 is removed from the etching device.

[0016] In the etching process, as shown in FIG. 5, the semiconductor wafer 10 is placed on a stage 90. Here, the semiconductor wafer 10 is placed on a stage body 92 with the mask 30 facing upward. Therefore, a focus ring 94 is located on the outer periphery of the semiconductor wafer 10. The surface of the focus ring 94 is covered with powder deposits 80. In the etching process, the upper surface 18 of the semiconductor wafer 10 is etched through the mask 30 by dry etching such as reactive ion etching. For example, dry etching can be performed by introducing an etching gas, an inert gas, and an oxidizing gas into the chamber of an etching apparatus and generating plasma in the chamber. For example, CF4 can be used as the etching gas. He or Ar can also be used as the inert gas. O2 can also be used as the oxidizing gas. The generation of plasma generates fluorine radicals as active species from the etching gas. The semiconductor wafer 10 (i.e., SiC) reacts with the fluorine radicals and the oxidizing gas to decompose into SiF4 and CO2. In other words, the semiconductor wafer 10 is chemically etched. Furthermore, the semiconductor wafer 10 is physically etched as the inert gas ions collide with the semiconductor wafer 10. Thus, the semiconductor wafer 10 is efficiently etched by chemical and physical etching performed in parallel. Furthermore, because the mask 30 is made of dense silicon oxide, the mask 30 is hardly etched. Therefore, as shown in FIG. 6 , the upper surface 18 of the semiconductor wafer 10 is etched within each opening 32, forming multiple trenches 28 in the upper surface 18. Furthermore, the deposit 80 is made of the same silicon oxide as the mask 30, but is a powder deposit and has a large surface area, so it is etched at a relatively fast rate. The deposit 80 (i.e., SiO2) reacts with the fluorine radicals and the oxidizing gas to decompose into SiF4 and SiOF.

[0017] As shown in FIG. 1, the element region 14a in the central portion 20 is surrounded by other element regions 14. Therefore, openings 32 are present at a high density in the element region 14a and its surroundings, and fluorine radicals are consumed in each opening 32. That is, in the element region 14a, fluorine radicals are supplied to the element region 14a and the surrounding element regions 14 in a dispersed manner. On the other hand, the element region 14b in the outer periphery 22 is adjacent to the peripheral region 15. Since no openings 32 are provided in the peripheral region 15, fluorine radicals are not consumed in the peripheral region 15. However, as shown in FIG. 6, fluorine radicals are consumed in the deposits 80 provided on the outer periphery side of the semiconductor wafer 10. In this way, fluorine radicals are supplied to the element region 14b and the deposits 80 in the outer periphery 22 in a dispersed manner. Therefore, the density of fluorine radicals supplied to each opening 32 in the element region 14a and the density of fluorine radicals supplied to each opening 32 in the element region 14b are uniform. In other words, the consumption of fluorine radicals by the deposits 80 prevents the supply density of fluorine radicals from becoming locally high in the element region 14b in the outer peripheral portion 22. Therefore, the etching rate of the semiconductor wafer 10 is made uniform between the element region 14a and the element region 14b. This makes it difficult for differences in the depth of the trenches 28 to occur between the central portion 20 and the outer peripheral portion 22. In this way, the etching process can form trenches 28 of approximately uniform depth in the central portion 20 and the outer peripheral portion 22.

[0018] Furthermore, in the etching process, in order to prevent the semiconductor wafer 10 from excessively increasing in temperature, the semiconductor wafer 10 is cooled by flowing a coolant through a channel inside the stage 90. The deposits 80 are made up of accumulated silicon oxide particles and have an extremely small heat capacity. Therefore, the deposits 80 do not affect the temperature of the stage 90 or the semiconductor wafer 10. Therefore, in the etching process, the temperature of the semiconductor wafer 10 can be accurately controlled, and the etching rate over the entire semiconductor wafer 10 can be accurately controlled. Therefore, the depth of each trench 28 can be accurately controlled.

[0019] After forming the trenches 28, electrodes, insulating films, etc. are formed in each element region 14. Thereafter, the semiconductor wafer 10 is cut along the dicing lines 12, and each element region 14 becomes a semiconductor device.

[0020] As described above, this trench formation process can suppress variations in the depth of the trenches 28 within the semiconductor wafer 10. In particular, because the deposit 80 is removed in the first preparation process and then formed in the second preparation process, the amount of deposit 80 can be accurately controlled, and variations in the depth of the trenches 28 within the semiconductor wafer 10 can be more appropriately suppressed. Furthermore, because the temperature of the semiconductor wafer 10 can be accurately controlled in the etching process, the depth of each trench 28 can be accurately controlled. Therefore, when this manufacturing method is repeatedly performed, manufacturing errors in the depth of the trenches 28 that occur in each trench formation process can be reduced.

[0021] FIG. 7 shows a trench-gate metal-oxide-semiconductor field effect transistor (MOSFET) 100 that can be manufactured by the manufacturing method of this embodiment. The MOSFET 100 has a gate electrode 110 formed in a trench 28. Each trench 28 is formed by the trench formation process of this embodiment. The MOSFET 100 has a superjunction structure 160 in which n-type pillar layers 140 and p-type pillar layers 150 are arranged alternately in the lateral direction. An epitaxial layer 170 is provided on top of the superjunction structure 160. A source layer, a body layer, and the like are formed in the epitaxial layer 170. The epitaxial layer 170 forms the upper surface 18 of the semiconductor wafer 10. A trench 28 is provided in the epitaxial layer 170. If the trench 28 penetrates the epitaxial layer 170, the breakdown voltage of the MOSFET 100 decreases. Therefore, if the depth of the trenches 28 varies greatly within the semiconductor wafer 10, the epitaxial layer 170 needs to be thickened to match the deepest trench 28, which increases manufacturing costs. According to the manufacturing method of the embodiment, it is possible to suppress the variation in the depth of the trenches 28 within the semiconductor wafer 10, and therefore it is possible to reduce the thickness of the epitaxial layer 170. Therefore, according to the manufacturing method of the embodiment, it is possible to manufacture the MOSFET 100 at low cost.

[0022] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A method for manufacturing a semiconductor device, comprising: a step of sputter-etching a dummy wafer placed on a stage, thereby forming a powder deposit made of material scattered from the dummy wafer on the surface of the stage around the dummy wafer; a step of forming a plurality of trenches in the semiconductor wafer by dry etching the semiconductor wafer through a mask having a plurality of openings on its surface while the semiconductor wafer is placed on the stage; and The manufacturing method, wherein the step of forming the trench includes dry etching the deposit together with the semiconductor wafer. (Configuration 2) the dummy wafer has a silicon oxide layer, The step of forming the deposit includes sputter etching the silicon oxide layer. The manufacturing method according to configuration 1. (Configuration 3) 3. The method of claim 1, wherein the mask is made of silicon oxide. (Configuration 4) 4. The manufacturing method according to any one of aspects 1 to 3, wherein the semiconductor wafer is made of silicon carbide. (Configuration 5) Repeating a set of the steps of forming the deposit and forming the trench; 5. The manufacturing method according to any one of configurations 1 to 4, wherein the set further comprises a step of removing the deposit on the stage before the step of forming the deposit.

[0023] According to the first configuration, each trench can be formed accurately. Furthermore, in the technique of simultaneously dry-etching a semiconductor wafer and a dummy wafer as in Patent Document 1, the area of ​​the etched region of the dummy wafer must be designed to match the aperture ratio of the mask on the semiconductor wafer. In other words, in Patent Document 1, a dummy wafer must be designed for each type of semiconductor device to be manufactured. Furthermore, since dummy wafers are consumables, it is necessary to manage the wear of the dummy wafers provided for each type of semiconductor device and replace the dummy wafers as necessary. This results in high costs for managing the dummy wafers. In contrast, according to the first configuration, the amount of deposit can be controlled by the sputter etching conditions (e.g., time), allowing for the manufacture of a wide variety of semiconductor devices at low cost.

[0024] According to configuration 2, the dummy wafer and the deposit are made of silicon oxide, which is commonly used in the manufacture of semiconductor devices, and therefore contamination of the etching equipment can be prevented. The dummy wafer may be made of only a silicon oxide layer, or may have a silicon oxide layer and a layer of another material.

[0025] According to configuration 5, the deposit is formed on the stage after the deposit is first removed from the stage, so the amount of deposit can be accurately controlled.

[0026] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0027] 10: semiconductor wafer, 20: center portion, 22: outer periphery portion, 28: trench, 30: mask, 80: deposit, 82: dummy wafer, 90: stage

Claims

1. A method for manufacturing a semiconductor device, comprising: a step of sputter-etching a dummy wafer placed on a stage, thereby forming a powder deposit made of material scattered from the dummy wafer on the surface of the stage around the dummy wafer; a step of forming a plurality of trenches in the semiconductor wafer by dry etching the semiconductor wafer through a mask having a plurality of openings on its surface while the semiconductor wafer is placed on the stage; and The manufacturing method, wherein the step of forming the trench includes dry etching the deposit together with the semiconductor wafer.

2. the dummy wafer has a silicon oxide layer, The step of forming the deposit includes sputter etching the silicon oxide layer. The method of claim 1.

3. 3. The manufacturing method according to claim 1, wherein the mask is made of silicon oxide.

4. 3. The manufacturing method according to claim 1, wherein the semiconductor wafer is made of silicon carbide.

5. Repeating a set of the steps of forming the deposit and forming the trench; The manufacturing method according to claim 1 or 2, wherein the set further comprises a step of removing the deposit on the stage before the step of forming the deposit.

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