Antenna array architecture with electrically conductive columns between substrates

Abstract

To provide an electrical interconnection between substrates having, respectively, different coefficients of thermal expansion.SOLUTION: An antenna apparatus 100 includes: an antenna substrate 120 having a first surface 131 and a second surface 139 that face each other; and a PCB 140 having a top surface 149 and a bottom surface 141 that face each other. Antenna elements 125 are disposed on a first surface of the antenna substrate 120. A plurality of electrically conductive columns 122 each having a first end attached to the bottom surface of the PCB 140 and a second end attached to the second surface of the antenna substrate, secure the PCB to the antenna substrate, and provide an electrical interconnect between the PCB and the antenna substrate. Each of a plurality of RFIC chips 126 is attached to the second surface of the antenna substrate and coupled to the antennal elements. At least one FPGA 142 is attached to the top surface of the PCB, and electrically coupled to at least one of the RFIC chips through at least one of the electrically conductive columns 122.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates generally to a compact architecture for radio frequency integrated circuit chip (RFIC) integrated antenna arrays. [Background technology]

[0002] Antenna arrays are deployed in a variety of applications at microwave and millimeter-wave frequencies, for example, in aircraft, satellites, vehicles, and general-purpose ground-based communications base stations. Such antenna arrays typically comprise microstrip radiating elements driven by phase-shifting beamforming circuits to produce a beam-steerable phased array. It is typically desirable for the overall antenna system, including the antenna array and beamforming circuits, to be thin and occupy minimal space while meeting required performance metrics over a range of environmental conditions.

[0003] A low-profile antenna array device can consist of antenna elements integrated with RFICs (e.g., MMICs) in a compact structure. The antenna array device may have a sandwich-type configuration in which the antenna elements are disposed on an exterior component layer and the RFICs are distributed across the effective antenna aperture in an adjacent parallel component layer behind the antenna element layer. The RFIC may include an RF power amplifier (PA) for transmit operation, a low-noise amplifier (LNA) for receive operation, and / or a phase shifter / amplitude adjuster for beam steering. Distributing the PA / LNA in this manner can achieve high efficiency during transmit and / or low-noise performance during receive. A complex connection layout can route DC bias voltages to the amplifiers and beam steering control signals to the phase shifters. A typical antenna array device producing a narrow beamwidth of only a few degrees may each include hundreds or even thousands of RFIC chips, antenna elements, and control lines. Such complex arrangements present design challenges for producing a low-profile design that operates well in a wide range of environments. Summary of the Invention

[0004] In one aspect of the present disclosure, an antenna device includes an antenna substrate having opposing first and second surfaces and a printed circuit board (PCB) having opposing first and second surfaces. A plurality of antenna elements are disposed on the first surface of the antenna substrate. A plurality of conductive posts, each having a first end attached to the second surface of the PCB and a second end attached to the second surface of the antenna substrate, secure the PCB to the antenna substrate and provide electrical interconnections between the PCB and the antenna substrate. A plurality of radio frequency integrated circuit (RFIC) chips are respectively attached to the second surface of the antenna substrate and coupled to the plurality of antenna elements. At least one circuit element is attached to the first surface of the PCB and electrically coupled to at least one of the RFIC chips via at least one of the conductive posts.

[0005] In various examples, the electrical interconnects may be RF interconnects for communicating RF signals, DC interconnects for communicating DC signals, or data control signal interconnects for communicating data control signals. The PCB and antenna substrate may have different coefficients of thermal expansion (CTE), and the posts may be deflected, bent, or compressed to provide stress relief due to the different CTEs.

[0006] In another aspect, an interconnect structure for an electronic device includes a substrate having a top surface, a PCB having a top surface and a bottom surface, and a plurality of conductive posts attached between the bottom surface of the PCB and the top surface of the substrate. The posts secure the PCB to the substrate and provide electrical interconnections between the PCB and the substrate. A plurality of IC chips are attached to the top surface of the substrate. At least one circuit element is attached to at least one of the top and bottom surfaces of the PCB and is electrically coupled to at least one of the IC chips via at least one of the conductive posts. [Brief explanation of the drawings]

[0007] The above and other aspects and features of the disclosed technology will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters indicate like elements or features. Various elements of the same or similar type may be distinguished by appending a reference label with an underscore / dash and a second label that distinguishes among the same / similar elements (e.g., _1, _2), or by appending the reference label directly with the second label. However, if a given description uses only a first reference label, this label is applicable to any one of the same / similar elements having the same first reference label, regardless of the second label. Elements and features may not be drawn to scale in the drawings.

[0008] [Figure 1] FIG. 1 is an exploded perspective view of an exemplary antenna apparatus according to one embodiment. [Figure 2] FIG. 2 is an exemplary cross-sectional view of a portion of the antenna apparatus of FIG. 1 according to one embodiment. [Figure 3A] FIG. 3A shows an exemplary interconnect structure for region "A" of FIG. 2, in which conductive posts are conductively attached to a first metal layer of the antenna substrate. [Figure 3B] FIG. 3B illustrates another exemplary interconnect structure for region "A" of FIG. 2A, in which conductive posts are conductively attached to a second metal layer of the antenna substrate. [Figure 4] FIG. 4 shows an exemplary interconnect structure for region "B" of FIG. 2, in which conductive posts are conductively attached to a transmission line layer of the antenna substrate. [Figure 5A] FIG. 5A is an exemplary cross-sectional view of a portion of the antenna apparatus of FIG. 1 according to another embodiment. [Figure 5B] FIG. 5B is a cross-sectional view of an exemplary structure in region "C" of FIG. 5A. [Figure 6] FIG. 6 is an exemplary view taken along line 6-6 of FIG. 5A, showing the layout of the IC chip and PCB portion mounted on the surface of the antenna substrate. [Figure 7] FIG. 7 is an exemplary cross-sectional view of a portion of the antenna apparatus of FIG. 1 according to a further embodiment. [Figure 8] FIG. 8 is a flow chart illustrating an exemplary method for manufacturing an antenna device according to one embodiment. [Figure 9A] FIG. 9A shows an antenna substrate assembly of an antenna device, the antenna substrate assembly having a conductive mast partially formed thereon. [Figure 9B] FIG. 9B shows an antenna substrate assembly with the mast fully formed thereon. [Figure 9C] FIG. 9C shows an antenna substrate assembly with a pre-formed mast attached thereto. DETAILED DESCRIPTION OF THE INVENTION

[0009] For purposes of explanation, the following description is provided with reference to the accompanying drawings to facilitate a comprehensive understanding of certain exemplary embodiments of the technology disclosed herein. Although the description includes various specific details to help those skilled in the art understand the technology, these details should be considered merely exemplary. For purposes of simplicity and clarity, descriptions of well-known functions and structures may be omitted if their inclusion may obscure the understanding of the technology by those skilled in the art.

[0010] 1 is an exploded perspective view of an exemplary antenna device 100 according to one embodiment. The antenna device 100 has a compact arrangement including a planar antenna substrate 120 secured to a printed circuit board (PCB) 140 by a plurality of conductive posts 122. A plurality of antenna elements 125 are disposed on a first major surface 131 (in the x-y plane) of the antenna substrate 120. A plurality of radio frequency integrated circuit (RFIC) chips 126 are respectively mounted on a second, opposite major surface 139 of the antenna substrate 120 and coupled to the antenna elements 125. At least one circuit element, such as a field programmable gate array (FPGA) 142, a DC connector 146, and / or an RF connector 144, is mounted on the first major surface 149 of the PCB 140. Each of the posts 122 may provide electrical interconnection between the circuit element secured to the PCB 140 and the RFIC chip 126 via a conductive layer in the antenna substrate 120.

[0011] To provide electrical interconnection, each of the pillars 122 may have a first end 151 attached to the second side 139 of the antenna substrate 120 and a second end 159 attached to the second side 141 of the PCB 140. The antenna substrate 120 and the PCB 140 may have different coefficients of thermal expansion (CTE). The structure and materials of the pillars 122 may be designed to enable stress relief by allowing the antenna device 100 (hereinafter interchangeably referred to as "antenna 100") to accommodate the CTE mismatch between the antenna substrate 120 and the PCB 140. To this end, the pillar 122 configuration allows the pillars to deform by bending, compressing, or stretching as the PCB and the antenna substrate expand at different rates over temperature while maintaining electrical connection. This is in contrast to solder balls, which may break when subjected to the same stresses. For example, each of the posts 122 may be configured as a solid cylinder, a solid cylinder with a spiral skin of a different material, a spring, a flexible solid structure, or a section of a micro-coaxial cable. The posts 122 may be configured as solder (e.g., a Pb / Sn alloy) or other conductive material. In one example, the posts 122 are column grid array (CGA) type posts with a Pb / Sn alloy inner cylinder and a copper spiral-wrapped skin for improved thermal conduction and reliability. For simplicity of illustration, only a few posts 122, RFIC chips 126, antenna elements 125, etc. are shown in FIG. 1 . In a typical embodiment of the antenna 100, there may be hundreds or thousands of antenna elements 125, RFIC chips 126, and posts 122. Additionally, multiple FGPAs 142, multiple DC connectors 146, and / or multiple RF connectors 144 may be included in the antenna 100 and attached to the PCB 140. The overall mechanical support for the attachment of the PCB 140 to the antenna substrate 120 may be provided by posts 122 .

[0012] For example, the pillars 122 may be formed as solid solder pillars by a process of incrementally building up the pillars in layers of solder. An exemplary process may first form the bottom layer of all pillars 122 against solder pads on the second side 139 of the antenna substrate or the second side 141 of the PCB 140. The lowest layers may be formed sequentially using a computer-controlled solder tool that moves from pillar to pillar. The process may be repeated layer by layer to incrementally build the height of the pillars (in the z-plane) until the desired height is reached on all pillars 122. The final solder layer may be comprised of a lower temperature solder than the solder on the other layers of pillars 122. For example, if the pillars 122 are built up from the surface of the antenna substrate 120, the final attachment step may include placing the PCB 140 on top of the pillars 122 by aligning the low-temperature solder pads on the second side 141 of the PCB 140 with the pillars 122. The entire antenna assembly may then be heated to a temperature sufficient to melt only the low temperature solder to complete the attachment process of PCB 140 to antenna substrate 120.

[0013] For example, PCB 140 may have one or more FPGAs 142, DC connector 146, and RF connector 144 mounted on its first surface 149, and these circuit elements may be electrically connected to signal and / or ground lines formed in antenna substrate 120 via posts such as 122a, 122b, and 122c. Antenna substrate 120 may have multiple thin metal layers formed therein, which may be patterned to form DC bias lines, control signal lines, ground lines, and RF transmission lines. For example, post 122b may be a DC interconnect that couples DC connector 146 to DC lines in antenna substrate 120 to communicate DC signals. The DC signals may bias amplifiers in RFIC chip 126. Post 122c may be a data control signal interconnect that couples FPGA 142 to control signal lines in antenna substrate 120 to communicate data control signals. The data control signals may be provided to RFIC chip 126 and / or other IC chips, such as serial peripheral interface (SPI) chip 127. The SPI chip 127 can generate phase shifter control signals based on the data control signals, which are provided to the plurality of RFIC chips 126 to adjust the phase shifters therein, thereby causing the antenna 100 to operate as a phased array. The posts 122a can be RF interconnects that couple the RF connectors 144 to transmission lines to communicate RF signals.

[0014] The antenna 100 may include a beam-forming network (BFN) formed partially or entirely on at least one printed circuit board (PCB) section 128 (hereinafter exemplified as multiple PCB sections 128) coplanarly disposed between the RFIC chips 126 and attached to the second surface 139 of the antenna substrate 120. Each PCB section 128 may be comprised of a dielectric substrate, such as alumina, a signal conductor, and at least one ground conductor, collectively forming a transmission line section, e.g., in a coplanar waveguide (CPW) or microstrip configuration. Providing multiple PCB sections 128 rather than a single PCB section 128 may facilitate the manufacture of the antenna 100. The BFN is a combiner / divider network, sometimes referred to as a “combination network” or “distribution network,” that splits an input RF transmit signal into N separate “element signals” for transmission by the N antenna elements 125 forming the antenna array and / or combines the N receive path element signals provided by the N antenna elements 125 into a final composite receive signal. RF connector 144 may be electrically connected to the input of the BFN (for transmit) and / or the output of the BFN (for receive). In another embodiment, PCB section 128 is omitted and the BFN is instead formed within a layer of antenna substrate 120. Different methods of connecting the BFN to RF connector 144 are described below.

[0015] Each of the antenna elements 125 may be a microstrip patch antenna element printed on the antenna substrate 120 to form a planar array. Other types of antenna elements, such as dipoles or monopoles, may be substituted. The antenna elements 125 may be electrically or electromagnetically coupled to ("fed from") the RFIC chip 126 at their respective feed points. The RFIC chip 126 may be mechanically connected to the antenna substrate 25, such as by solder bump connections to connection pads located on the antenna substrate 25. The RFIC chip 126 may also be mechanically and electrically connected to an antenna ground plane proximate to and below the surface 139 in the case of a "single RF layer substrate" described below. In a typical embodiment, each RFIC chip 126 is coupled to multiple (e.g., several) antenna elements 125, with the RFIC chips 126 being distributed over substantially the entire effective aperture of the planar array formed by the antenna elements 125.

[0016] When embodied as a microstrip patch, the antenna elements 125 may have any suitable shape, such as circular, square, rectangular, elliptical, or variations thereof, and may be fed and configured in a manner sufficient to achieve a desired polarization, e.g., circular, linear, or elliptical. The number of antenna elements 125, their type, size, shape, inter-element spacing, and the manner in which they are fed may vary depending on the design to achieve target performance metrics. In a typical embodiment, the antenna 100 may include hundreds or thousands of antenna elements 125. In the embodiment described below, each antenna element 125 is a microstrip patch fed with a probe feed. The probe feed may be implemented as a via that electrically connects to an input / output (I / O) pad on the RFIC chip 126. The I / O pad is an interface that allows signals to enter or exit the RFIC chip 126. In another example, an electromagnetic feeding mechanism is used instead of vias, and each antenna element 125 is excited from its respective feed point with near-field energy.

[0017] The antenna 100 may be configured to operate over the millimeter (mm) wave frequency band, generally defined as the band within the range of 30 GHz to 300 GHz. In other examples, the antenna 100 operates in the microwave range of approximately 1 GHz to 30 GHz, or in the sub-microwave range below 1 GHz. Here, radio frequency (RF) signals refer to signals with frequencies below 1 GHz up to approximately 300 GHz. Note that RFIC chips configured to operate at microwave or millimeter wave frequencies are often referred to as monolithic microwave integrated circuits (MMICs). MMICs are typically made of III-V semiconductor materials or other materials such as silicon-germanium (SiGe).

[0018] Each RFIC chip 126 may include active beamforming circuitry, such as amplifiers and / or phase shifters used to condition one or more signals communicated with the connected antenna elements 125. In embodiments in which the RFIC chip 126 includes dynamically controlled phase shifters, the antenna 100 can operate as a phased array for transmit and / or receive operations. In phased array embodiments, the beams formed by the antenna 100 are steered to a desired beam direction angle set primarily according to the phase shifts of the phase shifters. Additional amplitude adjustment within the RFIC chip 126 may also be included to adjust the beam pattern. When RF front-end amplifiers and / or phase shifters are distributed throughout the effective aperture of the antenna array, the antenna 100 may be referred to as an active antenna array. In some embodiments, the antenna 100 operates as both a transmit antenna system and a receive antenna system, and each RFIC chip 126 includes receive circuitry including at least one low-noise amplifier (LNA) for amplifying receive signals and at least one power amplifier (PA) for amplifying transmit signals. In this case, each RFIC chip 126 may include suitable transmit / receive (T / R) switching / filtering circuitry to enable bidirectional signal flow over the shared resource. Antenna 100 may alternatively be configured to operate solely as a receive antenna system or solely as a transmit antenna system, in which case each RFIC chip 126 may include an LNA but no PA, or vice versa.

[0019] Figure 2 is a cross-sectional view of a portion of the antenna 100 of Figure 1 in an assembled state, according to one embodiment. The cross-sectional view represents a non-linear cross section of the antenna 100 shown in Figure 1, and some peripheral features of the view have been omitted for clarity. In this example, the antenna substrate 120 is configured in a "dual RF layer" configuration consisting of a first layer 121a and a second layer 121b. The top layer of the antenna substrate 120 at the second side 139, such as in region "A" (discussed below but not shown in Figure 2), may comprise one or more thin metal layers for DC signal routing and / or control signal routing.

[0020] Layer 121a may include a first dielectric layer 227a and a metal layer 250 that functions as an antenna ground plane to reflect signal energy transmitted / received by antenna elements 125. The antenna elements 125, forming a planar array, are disposed on a first surface 131 (below dielectric layer 227a) of antenna substrate 120. Each antenna element 125 may be coupled to a respective RFIC chip 126 through a first via 210 that functions as a signal conductor for the probe feed. The first via 210 traverses an opening 234 in the ground plane 250. A second via 211 on the opposite side of the first via 210 functions as a ground conductor for the probe feed and provides electrical connection between the respective ground contacts of the RFIC chip 126 and the ground plane 250. Second layer 121b includes a second dielectric layer 227b and another metal layer 240 patterned to form RF transmission line conductors between various connection points. Dielectric layers 227a, 227b may be made of any suitable dielectric, such as fused silica. Connections between metal layer 240 and RFIC chip 126, PCB section 128, IC chip 127, and connection points (e.g., I / O pads) on any pillars 122 that make RF connections may be made through respective short vias 243 and electrical connection joints 230, such as solder balls or copper pillars. For example, first portion 240a of second metal layer 240 is a transmission line conductor that couples I / O pads 215 of RFIC chip 126 to a connection point on PCB section 128. Second portion 240b is a transmission line conductor that couples another connection point on PCB section 128 to a connection point on "signal pillar" 122a2, described below.

[0021] Each pillar 122 may have a height greater than the thickness of any one of the components 126-128 attached to the antenna substrate 120. Thus, there may be an air gap between the top surface of the component 128 and the PCB 140. As described above, one method of forming each pillar 122 is by building up a liquid metal, such as solder, one layer at a time, pillar by pillar. Each pillar may be aligned with a respective connection pad on the second surface 139 of the antenna substrate 120. An alternative process may use preformed conductive pillars and conductively attach the bottom and top surfaces of the preformed pillars to the connection pads on surfaces 139 and 141, respectively, using a robotic tool or the like. Some examples of preformed pillars 122 include solid cylinders, solid cylinders with a copper-wrapped skin ("copper-wrapped pillars"), springs, and micro-coaxial cables. As previously mentioned, the structure and materials of the pillars 122 may be sufficient to allow stress relief by accommodating the CTE mismatch between the antenna substrate 120 and the PCB 140. As the PCB 140 and the antenna substrate 120 expand at different rates over temperature, the pillar 122 configuration may prevent fracture by bending, compressing, or stretching while maintaining mechanical and electrical connections. For example, a copper-wrapped pillar may be cracked and still maintain electrical connection.

[0022] Vias 220 formed in PCB 140 may couple conductive lines on top surface 149 to top ends 159 of respective pillars 122. For example, vias 220 electrically couple pillar 122c to connection points on FPGA 142 through conductive lines 261 on top surface 149. In other examples, vias 220 may connect directly to connection points on FPGA 142, if the layout permits. Bottom ends 151 of pillars 122c are coupled to I / O pads of RFIC chip 126 through conductive lines in dielectric layer 120b (e.g., part of layer 266 in FIG. 3A , described below) and conductive joints 230. If pillar 122c is designated for routing control signals, the ground connection path of the control signals on its underside to the ground connection point of RFIC chip 126 may similarly consist of another via 220 (either directly below it or through another conductive line on surface 149) coupled to the ground connection point of FPGA 142, another pillar 122, another conductor in dielectric layer 120b, and another conductive joint 230.

[0023] Similarly, DC connector 146 may provide a positive or negative voltage to RFIC chip 126 from an electrical contact on the underside of DC connector 146 through a path that includes signal conductor 263 on face 149, via 220, pillar 122b, a first metal layer within dielectric layer 227b, and a conductive joint 230 connected to an I / O pad of RFIC chip 126. A similar path through another pillar 122 and a second metal layer within dielectric layer 227b may provide a DC voltage ground connection between the ground contact of DC connector 146 and RFIC chip 126.

[0024] RF connector 144 may be a coaxial or other type of connector electrically coupled to an RF input port and / or output port of a BFN in PCB portion 128. For example, a ground-signal-ground (GSG) transition (“GSG interconnect”) 260 may be used in the coupling path and may include signal pillar 122a2, a first “ground pillar” 122a1 on one side of signal pillar 122a2, and a second ground pillar 122a3 on the other side of signal pillar 122a2. These pillars may connect at their top ends to first ground via 223a1, signal via 223a2, and second ground via 223a3, respectively, formed through PCB 140. RF connector 144 may include an inner conductor connected to signal via 223a2 and an outer conductor connected on one side to first ground via 223a1 and on the other side to signal via 223a3. It should be noted that in other embodiments, other connection structures may be substituted, such as a "GS" scheme utilizing only one ground post, or a scheme having three or more ground posts.

[0025] Signal pillar 122a3 may be coupled to the RF input and / or output points of the BFN in PCB section 128 via a redistribution layer (RDL) interconnect in antenna substrate 120. This interconnect may include a connection path that includes a via 243 (seen in FIG. 4) connected to the bottom end of signal pillar 122a3, one end of transmission line conductor 240b, another via 243 at the opposite end of conductor 240b, and a connection joint 230 connecting the latter to PCB section 128. Ground pillars 122a1 and 122a2 may connect to a microstrip ground layer in dielectric layer 120b or a CPW ground conductor formed in metal layer 240.

[0026] 3A shows an exemplary interconnect structure for region "A" in FIG. 2. In this example, the top structure of the antenna substrate 120 includes a first insulating layer 262 of a polymer, such as benzocyclobutene (BCB), the top surface of which forms the top surface 139 of the antenna substrate 120. A first metal layer 266 (the "first conductive trace layer") is directly below the first insulating layer 262 and may be designated to form ground conductors for DC and / or control signals, or to form signal conductors for DC / control signals. A second metal layer 270 (the "second conductive trace layer") is below the first ground layer 266 and is separated therefrom by a second insulating layer 268. If the first metal layer 266 is designated as a ground conductor for DC / control signals, the second metal layer may be designated to form signal conductors for these signals, or vice versa. The metal layer 240a used for the transmission line conductor is located between the top of the dielectric layer 227b (directly below the second metal layer 270) and the bottom of the dielectric layer 227b.

[0027] In the example of FIG. 3A , pillar 122b is electrically connected to first layer 266 through an opening in insulating layer 262 that is slightly larger than the diameter of pillar 122b. To facilitate the formation of an electrical connection joint, a surface finish metal layer 265, such as electroless palladium immersion gold (ENEPIG) or a nickel / gold alloy, may be formed within the opening in insulating layer 262. Layer 265 may be deposited to form a cavity, having a base portion on metal layer 266, a peripheral wall around the periphery of the opening, and an annular ring region on face 139. A well of solder or other liquefiable metal 264 may fill the cavity and adhere to both surface finish layer 265 and the bottom end of pillar 122b, forming a mechanical connection between pillar 122b and antenna substrate 120 and an electrical connection to metal layer 266 therein. In other embodiments, surface finish metal layer 265 is omitted.

[0028] Each of metal layers 266 and 270 and insulating layers 262 and 268 may be at least an order of magnitude thinner than the thickness of substrate 120. For example, each of these layers may have a thickness on the order of 2-10 μm, while substrate 120 may be on the order of 250 μm thick. Metal layers 266 and 268 may each form signal / ground lines in the x-y plane having widths on the order of 12 μm and spaced apart by intervals on the order of 12 μm. Each of layers 266 and 268 may be etched or otherwise patterned to form hundreds or thousands of signal and ground lines in a typical embodiment of antenna 100.

[0029] FIG. 3B shows another exemplary interconnect structure for region "A" in FIG. 2. In this example, pillar 122b is electrically connected to second metal layer 270 through openings in first insulating layer 262, first metal layer 266, and second insulating layer 268. The openings in these layers may be formed by aligning resist materials of different geometric shapes layer by layer during deposition of each layer. To prevent pillar 122b from shorting to first metal layer 266, first metal layer 266 may be formed by deposition patterning with an opening larger than those of first and second insulating layers 268 and 262. An annular insulating region 287 may be formed at the depth of metal layer 266 to insulate first metal layer 266 from a subsequent electrical connection between pillar 122b and second metal layer 270. A surface finish layer 285 similar to surface finish layer 265 may be formed using electroplating or the like. Surface finish layer 285 may have a base portion on second metal layer 270, annular wall portions against the edges of insulating layers 262, 266, and 268 in their respective openings, and a rim portion on top surface 139. This results in a metal-backed cavity that can be filled with solder or other liquefiable metal 284. When solder 284 cools while the lower end of pillar 122b is located within the cavity, solder 284 electrically connects pillar 122b to second layer 270 through surface finish layer 285. In other embodiments, surface finish layer 285 is omitted.

[0030] FIG. 4 illustrates an exemplary interconnect structure for region "B" of FIG. 2, in which signal post 122a2 is conductively attached to transmission line conductor 240b through via 243 in antenna substrate 120. Via 243 can connect its upper end to a disk-shaped catch pad 270a formed in metal layer 270. For example, metal layer 270 may be formed on dielectric layer 227b before forming via 243. When forming metal layer 270, catch pad 270a may be formed by concentrically aligning a ring-shaped resist material with the circular area of ​​via 243 (to be formed later). Metal layer 270 may then be deposited, resulting in a ring-shaped opening around catch pad 270a. Via 243 may then be formed through catch pad 270a. Insulating material may be deposited in a subsequent step to form an annular insulating region 289 in the opening around catch pad 270a, thereby insulating the remaining material of metal layer 270 from via 243. The interconnect structure between catch pad 270a and the lower end of pillar 122a2 may be the same as that described in connection with FIG. 3B for the connection to pillar 122b. That is, the interconnect structure may comprise a surface metal layer 285 having a base portion, an annular wall portion, and a rim portion on top of catch pad 270a, forming a cavity that is filled with liquefiable metal 284 as described above.

[0031] Transmission line conductor 240b may be, for example, a microstrip conductor, a coplanar waveguide (CPW) conductor, or a stripline conductor. If transmission line conductor 240b is configured as a CPW conductor, ground posts 122a1 and 122a3 may be conductively attached to other respective portions of transmission line layer 240 on opposite sides of layer portion 240b in the same manner as described for FIG. 4. In the case of a microstrip, the ground plane for the microstrip may be the region of second metal layer 268 overlying conductor 240b. In this case, ground posts 122a1 and 122a3 may each be conductively attached to second metal layer 270 in the same manner as described above for FIG. 3B. Alternatively, a region of the first metal layer 266 may be used as a ground plane (by removing a corresponding region of the second metal layer 270), in which case the ground pillars 122a1 and 122a3 may be conductively attached to the first metal layer 266 in the same manner as described for Figure 3A. In the case of a stripline, an additional metal layer would be provided below layer 240b and electrically connected to the ground plane provided by the first or second metal layer 266, 270.

[0032] 5A is an exemplary cross-sectional view of a portion of the antenna apparatus of FIG. 1 according to another embodiment. (The view of FIG. 5A represents a non-linear slice of the antenna 100, different from that of FIG. 2.) This embodiment employs a "single RF layer" antenna substrate 120a (another embodiment of the antenna substrate 120 of FIG. 1) in which the antenna ground plane 550 is located within the antenna substrate 120a adjacent its top surface 139. Note that the cross-sectional view of FIG. 5A shows the signal mast 122a2 electrically coupled between the RF connector 144 and the antenna substrate 120a through the via 223a2. In this view, the first and second ground masts 122a1 and 122a3 can be assumed to be invisible because they are behind and in front of the signal mast 122a2 (or vice versa), respectively.

[0033] Figure 5B is a cross-sectional view of an exemplary structure of region C of Figure 5A. Antenna substrate 120a may consist of a dielectric layer 527 and alternating metal / insulating layers on top of substrate 120a. These may include an antenna ground plane 550 directly above dielectric layer 527, followed by insulating layer 540, second metal layer 270, insulating layer 268, first metal layer 266, and top insulating layer 262, in that order, towards top surface 139.

[0034] The signal pillar 122a2 may be conductively attached to a first end of a conductive trace 266a formed in a metal layer 266 through a solder well 264 and a surface finish metal layer 265, similar to that described above in connection with FIG. 3A . The conductive trace 266a may be insulated from adjacent portions of the first metal layer 266 by a ring-shaped insulating region 595a surrounding the conductive trace 266a. An electrical interconnection may be formed between a second, opposite end of the conductive trace 266a and a CPW or microstrip signal conductor 604 on the top surface of the PCB portion 128. This interconnection may include a via 593 formed in the PCB portion 128, an electrical connection joint 230, and a surface finish metal layer 585 formed at the second end of the conductive trace 266a. The insulating portion 262a of the insulating layer 262 may be formed to support a wall of the surface finish metal layer 265. Alternatively, portion 265a is replaced with a conductive layer portion, for example, an additional surface finish metal layer material.

[0035] When PCB section 128 is configured as a CPW transmission line, first and second ground conductors on opposite sides of signal conductor 604 may be connected to the bottom ends of ground posts 122a1 and 122a3, respectively, using a configuration similar to that shown in FIG. 5B. In this case, the respective connections may be made via first and second additional conductive traces ("ground traces") formed in metal layer 266 on opposite sides of conductive trace 266a and insulated from conductive trace 266a. In other words, the first and second ground traces, in conjunction with conductive trace 266a, form the interconnection of the CPW transmission line. Alternatively, the ground connections may be made in a metal layer within substrate 120a different from the metal layer (e.g., 266) used for the signal conductor connections.

[0036] If PCB portion 128 is configured as a microstrip transmission line, the connection from signal line 604 to signal post 122b may be made via a similar conductive trace 266a, similar to FIG. 5B. In this case, a microstrip ground plane may be present on the bottom surface of PCB portion 128, and the bottom end of via 593 may pass through an opening in the microstrip ground plane. Additionally, first and second ground traces may extend on opposite sides of conductive trace 266a, each connected at one end to a respective connection point on the microstrip ground plane and connected at the opposite end to ground post 122a1 or 122a3, respectively.

[0037] Note that interconnections similar to those shown in FIG. 5B may be made between the I / O pads on the underside of the RFIC chip 126 and the first metal layer 266. (The interconnections may include conductive joints 230 in cavities lined with a surface-finishing metal layer 585.) To connect any I / O pads on the RFIC chip 126 to signal lines on the second metal layer 270, openings are formed within each of the first metal layer 266 and the second insulating layer 268. The periphery of these openings may be lined with a surface-finishing metal layer 585 that extends to the second metal layer 270 to form cavities. The cavities may be filled with a liquefiable metal to form conductive wells similar to the conductive wells 284 of FIG. 3B. The conductive wells may connect to the bottom ends of the I / O pads on the RFIC chip 126.

[0038] The antenna ground plane 550 may be electrically connected to a microstrip ground plane on the underside of the RFIC chip 126 and / or PCB portion 128. The interconnect for this connection may include at least one electrical connection joint 230, a solder well, or the like, in the antenna substrate 120a that extends to the antenna ground plane 550. Such a solder well may have an upper portion similar to the solder well 284 in FIG. 3B above, and a lower portion that extends through an insulated opening in the second metal layer 270 and connects to the ground plane 550.

[0039] FIG. 6 is an exemplary diagram taken along line 6-6 in FIG. 5A. This diagram shows an exemplary layout of IC chips and PCB sections looking down toward the top surface 139 of the antenna substrate 120a. The conductive posts 122 (including posts 122a, 122b, 122c, etc.) may be distributed in both peripheral and interior regions of the layout. An example is provided showing 16 RFIC chips 126_1 through 126_16 uniformly arranged in rows and columns, eight serial peripheral interface (SPI) chips 127_a through 127_8 linearly arranged between pairs of adjacent rows of RFIC chips 126, and five PCB sections 128_a through 128_5 on which at least a portion of the BFN is formed. The PCB section 128 includes a BFN signal conductor 620 on its top surface, which may be electrically connected to a respective signal conductor 613 in the RFIC chip 126 via an RDL interconnect 266b formed in the first metal layer 266 or to an interconnect formed in the second metal layer 270. (The RDL interconnect 266b can be assumed to be visible in the view of FIG. 6 through the first insulating layer 262.) If the PCB section 128 is implemented as a CPW, CPW ground conductors such as 630a, 630b, and 630c are present on opposite sides of the signal conductor 620. These ground conductors 630a-630c may each be electrically connected to a CPW ground conductor (not shown) of the RFIC chip 126 via an RDL interconnect on opposite sides of the signal conductor 613. In the case of a microstrip, a microstrip ground plane may be present on the underside of the PCB section 128 and RFIC chip 126, which are suitably connected together. It should be noted that a similar layout as shown in FIG. 6 may be implemented in the embodiment of FIG. 2, but in this case the electrical connection between signal conductors 613 and 620 may be made via a transmission line layer (metal layer 240) within antenna substrate 120.

[0040] The BFN in PCB section 128 may receive an input RF signal from RF connector 144 via a GSG transition 660 formed by signal strut 122a2, ground strut 122a1, and ground strut 122a3 in the transmit direction of antenna 100. The BFN may include a 2:1 I / O coupler 604 having an I / O port electrically connected to GSG transition 660 via an RDL connection in antenna substrate 120a or 120b (e.g., through conductive traces in first and / or second metal layers 266, 270, as described above). I / O coupler 604, in conjunction with other couplers in the BFN, such as 606 and 608, can split the input RF signal into 16 split transmit signals that are provided to RFIC chips 126_1 through 126_16, respectively. In the receive direction, RF receive signals output from RFIC chips 126_1-126_16 may be combined by a BFN, and the combined receive signal is output to RF connector 144 via GSG transition 660. Some examples of BFN couplers 604, 606, etc., include Wilkinson dividers (e.g., with resistors printed between the split output lines), hybrid ring ("rat race") couplers, and 90° branch line couplers. In other layout examples, a greater or lesser number of 2:1 and / or M:1 couplers (M>2) are provided to form a 1:K divider / combiner within transmission line section 128, where K is other than 16.

[0041] Each RFIC chip 126 may include active RF front-end components such as at least one amplifier 655 and at least one phase shifter 657. The antenna elements 125 coupled to an RFIC chip 126 may substantially overlie the RFIC chip 126. For example, RFIC chip 126_1 is shown overlaying four antenna elements 125, each of which may be connected to a respective signal path including one amplifier 655 and one phase shifter 657, which individually control the amplitude and phase of signals traversing that antenna element 125. (For clarity, one amplifier 655 and one phase shifter 657 are shown only on RFIC chips 126_9 and 126_16. For example, if four antenna elements 125 were coupled to each RFIC chip 126, each RFIC chip 126 may include four amplifiers 655 and four phase shifters 657.)

[0042] DC and control voltages originating from DC connector 146 and FGPA 142 may be routed via conductors formed in metal layers 266 and 270 through pillar 122 to RFIC chip 126 and SPI chip 127. The DC voltages may bias amplifier 655 and / or be used by other circuitry within RFIC chip 126 and SPI chip 127. For example, a DC bias voltage from DC connector 146 may be carried on pillar 122b2 and routed to amplifier 655 in RFIC chip 126_9 via conductive line 270_3 and an I / O contact pad on the underside of RFIC chip 126_9. A ground return for carrying the DC bias voltage back to DC connector 146 may include conductive line 266_3 and pillar 122b1.

[0043] In a similar manner, control signals may be routed from FGPA 142 to SPI chip 127 and / or RFIC chip 126 via pillar 122c. For example, phase / amplitude control signals for beam steering may be generated by FGPA 142 and routed to SPI chip 127. As an example, the control signal generated by FGPA 142 may be applied between pillars 122c1 and 122c2. The control signal may be routed to SPI chip 127_1 between conductive lines 270_1 and 266_1 connected to pillars 122c1 and 122c2, respectively. Based on the control signal, SPI chip 127_1 may generate a phase shifter control voltage and apply it to phase shifter 657 via conductive line 270_2 to dynamically set the phase shift of the signal across the antenna element 125 coupled to that phase shifter 657. In one example, pillar 122c2 may provide ground return paths for various control signals via electrical connections to each of the ground contacts of FGPA 142, the ground contact of SPI chip 127_1 (via conductive line 266_1), and the ground contact of RFIC chip 126_9 (via conductive line 266_2).

[0044] It should be noted that the BFN may be partially formed on the PCB portion 128 and partially formed on the RFIC chip 126. The BFN may be considered to be the signal path and divider / combiner circuitry between the GSG transitions 660 and the feed points of the amplifier elements 125. Thus, for example, if each RFIC chip 126 feeds N>1 antenna elements 125 as shown, then there may be an N:1 combiner / divider 692 (N=4 in the example of FIG. 6 ) within each RFIC chip 126. The N:1 combiner / divider 692 may be located between the input point 613 of the RFIC 126 and the N inputs of N respective amplifiers 655 and / or phase shifters 657, each coupled to a respective antenna element 125. The N:1 combiner / divider 692 may be considered the “early stage” of the BFN, while the BFN portion consisting of couplers 608, 606, etc. may be considered the “later stage” of the BFN.

[0045] 6, signal conductors 620 of adjacent PCB sections 128 may be connected to each other by wirebonds 503. In a CPW transmission line, a pair of ground conductors similar to 630a and 630c on opposite sides of signal conductor 620 may similarly be connected to corresponding ground conductors in adjacent PCB sections 128 via respective wirebonds 503. In an alternative embodiment, a common dielectric substrate is used for all of PCB sections 128_1 through 128_5, and wirebonds 503 are omitted.

[0046] In another embodiment, direct connections between adjacent PCB sections 128 are avoided by connecting BFN signal paths through RFIC chips 126 between different PCB sections 128 .

[0047] 7 is an exemplary cross-sectional view of a portion of the antenna 100 of FIG. 1 according to another embodiment. In this example, the beam-forming network (BFN) is formed in the antenna substrate 120b rather than in the PCB section 128, and the PCB section 128 is omitted. This embodiment employs a dual RF layer structure for the antenna substrate 120b, similar to that described above for the embodiment of FIG. 2. For example, the RF connector 144 may be coupled to the CPW transmission line formed by the metal layer 240 via a GSG transition 760 consisting of the posts 122a1, 122a2, and 122a3. Alternatively, if the metal layer 240 is used to form a microstrip signal conductor, the ground posts 122a1 and 122a3 may be conductively attached to another metal layer that functions as a microstrip ground within the antenna substrate 120b.

[0048] The GSG transition 760 may be located adjacent to an I / O RF coupler 604a, similar to the I / O coupler 604 of FIG. 6. The metal layer 240 may be patterned to form a BFN having a layout similar to that of FIG. 6 in one example. In this case, one signal path of the BFN may lead to a 2:1 directional coupler 608a (similar to coupler 608) that splits the RF transmit signal into two split signals that are applied to RFIC chips 126_13 and 126_14. A reciprocal signal flow from the RFIC chip 226 through the directional coupler to the GSG transition 760 may occur to the receive antenna system. Other aspects of this configuration may be the same as those described in connection with FIG. 2.

[0049] 8 is a flow chart illustrating an exemplary method of manufacturing the antenna device 100. Process step 820 may include forming a PCB assembly 140 having signal conductors 261 on the top surface 149 and / or bottom surface 141 (see, e.g., FIG. 2 ), with chips / connectors (e.g., 142, 144, 146) attached to vias 220 through the top surface 149 and the substrate of the PCB 140. The vias are formed to electrically couple the chips / connectors to contact pads on the bottom surface 141.

[0050] Another process step S840 may include forming an antenna substrate assembly comprising an antenna element 125 on the bottom surface 131 of the antenna substrate 120, a ground plane (e.g., 250, 550) within the antenna substrate 120, a first via 210 for coupling the antenna element 125 to the RFIC chip 126, a second via 243 at a location for connecting a GSG transition (formed by adjacent pillars 122a1, 122a2, 122a3) and / or for connecting the RFIC chip 126 to a transmission line conductor within the antenna substrate 120, the RFIC chip 126 and other chips 127 attached to the top surface 139 of the antenna substrate 120, and a PCB section 128 (if used) attached to the top surface 139.

[0051] With the PCB assembly and antenna substrate assembly formed separately, the pillars 122 may be formed and attached at one end to either the top surface of the antenna assembly or the bottom surface of the PCB assembly (S860). One example technique for this process involves incrementally building up the pillars from the top surface 139 of the antenna substrate 120 or from the bottom surface of the PCB assembly. One layer of pillars 122 may be formed at a time using a computer-controlled solder tool that moves sequentially from pillar to pillar, depositing small amounts of solder to incrementally build up each pillar. FIG. 9A shows an intermediate assembly structure, for example, where the bottoms of pillars 122b, 122c, etc., are formed on the top surface 139 of the antenna substrate 120. The process may be repeated layer by layer, incrementally building the height of the pillars until the desired height is reached on all pillars 122. Low-temperature solder may be applied to the open ends of the nearly completed pillars 122 (S880). 9B, each completed pillar 122 may have a majority portion 931 made of high-temperature solder and an end portion 935 made of low-temperature solder. Alternatively or additionally, low-temperature solder pads may be formed on the underside of PCB 140 at locations aligned with pillars 122.

[0052] An alternative implementation of process S860 includes conductively attaching preformed posts 122 to the antenna substrate 120 or PCB 140. For example, FIG. 9C shows an antenna substrate assembly having preformed posts 122 in the form of springs attached to the antenna substrate assembly. The bottom ends of the springs may be attached to surface 139 of the antenna substrate 120 with high-temperature solder. Low-temperature solder 935 may be applied to the top ends of the springs after the bottom ends are attached. As previously mentioned, the preformed posts 122 may have other configurations, such as a solid Pb / Sn alloy inner cylinder and a copper spiral-wrapped outer skin, for better thermal conduction and reliability. High-temperature and low-temperature solder may be applied to both ends of these other post configurations in the same or similar manner.

[0053] It should be noted that the process step S860 of forming / attaching the posts on the antenna substrate or PCB may be performed before attaching the IC chip / connector onto the antenna substrate or PCB on which the posts are first attached.

[0054] Thus, with the mast 122 conductively attached to one end of the antenna assembly or PCB assembly, and the PCB assembly or antenna assembly placed against the open end of the mast 122, the entire assembly may then be heated (S890) at a temperature low enough to melt only the low-temperature solder. Once the low-temperature solder has cooled, the previously open end of the mast 122 is conductively attached to the conductive contact of the PCB or antenna assembly.

[0055] The above embodiments have been described in the context of the antenna device 100. Other implementations of the techniques herein may be applied to non-antenna applications. For example, in other electronic devices, the antenna element 125 may be replaced with at least one other type of first circuit element, such as an IC chip. The RFIC chip 126 may be replaced with another type of second IC chip electrically coupled to the first IC chip through vias 210 extending through the substrate 120. The conductive pillars 122 of the electronic device may connect to at least one upper metal layer in the substrate 120 in a similar manner to provide DC interconnection, control signal interconnection, and / or RF signal interconnection. The pillar interconnect may connect a third IC chip / connector / component mounted on the top surface of the PCB 140 to a second IC chip mounted on the top surface 139 of the substrate 120. The resulting electronic device is formed in a compact three-dimensional laminate structure. Furthermore, if the substrate 120 and PCB 140 of an electronic device have different coefficients of thermal expansion (CTE), the same benefits of enabling stress relief between the substrate 120 and PCB 140 as described above may be applicable to the electronic device. That is, the structure and material of the pillars 122 may be sufficient to enable stress relief by accommodating the CTE mismatch between the substrate 120 and PCB 140. As the PCB 140 and substrate 120 expand at different rates over temperature, the pillar 122 configuration may prevent breakage by bending, compressing, or stretching while maintaining mechanical and electrical connections.

[0056] Furthermore, in the above embodiments, chip 142, DC connector 146, and / or RF connector 144 are shown and described as being attached to the top surface 149 of PCB substrate 140. In other embodiments, if space is available between antenna substrate 120 and PCB 140 and a flat, component-free surface is desired at top surface 149, the chip / connectors may alternatively be attached to the bottom surface of PCB 140. In this case, connectors such as 144, 146 may have side connection ports. In these or other embodiments, no circuit elements or antenna elements may be provided on bottom surface 131 of substrate 120.

[0057] While the technology described herein has been particularly shown and described with reference to exemplary embodiments thereof, those skilled in the art will recognize that various changes in form and details can be made therein without departing from the spirit and scope of the claimed subject matter as defined by the following claims and their equivalents.

Claims

1. An antenna device, an antenna substrate having first and second opposing surfaces; a plurality of antenna elements disposed on the first surface of the antenna substrate; a printed circuit board (PCB) having opposing first and second surfaces; a plurality of conductive posts, each having a first end attached to the second surface of the PCB and a second end attached to the second surface of the antenna substrate, for securing the PCB to the antenna substrate and providing an electrical interconnection between the PCB and the antenna substrate; a plurality of radio frequency integrated circuit (RFIC) chips respectively attached to the second surface of the antenna substrate and coupled to the plurality of antenna elements; at least one circuit element attached to the first surface of the PCB and electrically coupled to at least one of the RFIC chips via at least one of the conductive posts.

2. The antenna device of claim 1 , wherein the electrical interconnect is a radio frequency (RF) interconnect for communicating RF signals.

3. 3. The antenna arrangement according to claim 1 or 2, wherein the electrical interconnection is a direct current (DC) interconnection for communicating DC signals.

4. The antenna device according to any one of claims 1 to 3, wherein the electrical interconnection is a data control signal interconnection for communicating a data control signal.

5. 5. The antenna apparatus of claim 4, wherein the data control signals are provided to multiple ones of the RFIC chips to adjust phase shifters therein to create a phased array.

6. 6. The antenna device of claim 1, wherein the PCB and the antenna substrate have different coefficients of thermal expansion (CTE), and the posts deform by bending, compressing, or stretching to provide stress relief due to the different CTEs.

7. 7. The antenna device according to claim 1, wherein the at least one circuit element is an IC chip that provides control signals and / or bias voltages to the RFIC chip via at least one of the pillars and a conductive trace layer on the second surface of the antenna substrate.

8. The antenna device according to claim 7, wherein the IC chip is a field programmable gate array (FPGA).

9. 9. The antenna device according to claim 1, wherein the at least one circuit element is a DC connector that provides a DC voltage to the RFIC chip via the at least one of the pillars and a conductive trace layer on the second surface of the antenna substrate.

10. The antenna device according to any one of claims 1 to 9, wherein the at least one circuit element is an RF connector that routes RF signals to and from the RFIC chip via at least one of the posts.

11. the plurality of support columns include a first support column and second and third support columns on opposite sides of the first support column; 11. The antenna apparatus of claim 10, wherein the RF connector is coupled to the RFIC chip via a ground-signal-ground interconnection, the ground interconnection including the first solder pillar functioning as a signal interconnection and the second and third solder pillars functioning as respective ground interconnections.

12. the second surface of the antenna substrate comprises an antenna ground plane having an opening for an interconnection electrically coupling the RFIC and the antenna element; The antenna arrangement according to any one of claims 1 to 11, wherein the RFIC chip has a respective ground connection point electrically coupled to the antenna ground plane.

13. 13. The antenna device according to claim 1, wherein each of the RFIC chips has a lower surface attached to the second surface of the antenna substrate via a plurality of electrical connection joints, and an upper surface separated from the second surface of the PCB by an air gap.

14. The antenna device according to claim 13 , wherein the plurality of electrical connection joints are solder bumps or copper pillars.

15. 15. The antenna device of claim 1, wherein the plurality of conductive posts comprises at least one of a solder post, a solid cylinder with a copper spiral wrap, a spring, and a micro-coaxial cable.

16. The antenna device according to any one of claims 1 to 15, wherein the plurality of conductive posts are column grid array (CGA) copper wrapped solder posts.

17. The antenna device according to any one of claims 1 to 16, wherein each of the RFIC chips comprises at least one of a receiving amplifier, a transmitting amplifier, and a phase shifter.

18. 18. The antenna device according to claim 1, wherein each of the RFIC chips is coupled to one or more of the antenna elements via a respective via formed in the antenna substrate.

19. 19. The antenna device according to claim 1, further comprising a beam forming network (BFN) formed on at least one dielectric substrate located between the plurality of RFIC chips and attached to the second surface of the antenna substrate.

20. The antenna substrate is a first layer adjacent to the antenna element; a second layer adjacent to the RFIC; an antenna ground plane between the first layer and the second layer; 20. The antenna apparatus of claim 19, wherein the second layer comprises transmission lines coupling the plurality of RFIC chips to the BFN.

21. The antenna substrate is a first layer adjacent to the antenna element; a second layer adjacent to the RFIC chip; a patterned metal layer between the first layer and the second layer forming an antenna ground plane having an opening for a first via traversing therethrough, the first via connecting the RFIC chip to the antenna element; and a plurality of second vias in the second layer coupling the antenna ground plane to the RFIC chip.

22. 22. The antenna apparatus of claim 21, further comprising another patterned metal layer in the second layer forming a beam forming network for the antenna apparatus.

23. 23. The antenna device of claim 1, further comprising a plurality of serial peripheral interface (SPI) chips attached to the second surface of the antenna substrate, arranged coplanar with the RFIC chip, and coupled to the RFIC chip, the SPI chip being coupled to the at least one circuit element via at least one of the solder posts.

24. 1. An interconnect structure for an electronic device, comprising: a substrate having first and second opposing surfaces; a plurality of first circuit elements disposed on the first surface of the substrate; a printed circuit board (PCB) having opposing first and second surfaces; a plurality of conductive posts that secure the PCB to the substrate, each providing an electrical interconnection between the PCB and the substrate; a plurality of integrated circuit (IC) chips coupled to the first circuit element and attached to the second surface of the substrate; at least one second circuit element attached to the first surface of the PCB and electrically coupled to at least one of the IC chips via at least one of the conductive posts.

25. 25. The interconnect structure of claim 24, wherein the electrical interconnect is a radio frequency (RF) interconnect for communicating RF signals.

26. 26. The interconnect structure of claim 24 or 25, wherein the electrical interconnect is a direct current (DC) interconnect for communicating DC signals.

27. The interconnect structure of any one of claims 24 to 26, wherein the electrical interconnect is a data control signal interconnect for communicating data control signals.

28. 28. The interconnect structure of any one of claims 24 to 27, wherein the PCB and the substrate have different coefficients of thermal expansion (CTE), and the posts are deflected, bent, or compressed to provide stress relief due to the different CTEs.

29. 29. The interconnect structure of claim 24, wherein each of the IC chips has a lower surface attached to the second surface of the substrate via a plurality of electrical connection joints and an upper surface separated from the second surface of the PCB by an air gap.

30. 1. An interconnect structure for an electronic device, comprising: a substrate having a top surface; a printed circuit board (PCB) having a top surface and a bottom surface; a plurality of conductive posts mounted between the bottom surface of the PCB and the top surface of the substrate, securing the PCB to the substrate and providing electrical interconnections between the PCB and the substrate; a plurality of integrated circuit (IC) chips attached to the top surface of the substrate; at least one second circuit element attached to at least one of the top and bottom surfaces of the PCB and electrically coupled to at least one of the IC chips via at least one of the conductive posts.

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