Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device in which the warpage of a semiconductor wafer can be suppressed.SOLUTION: A semiconductor device in an embodiment includes a first electrode including a first metal layer, a second metal layer, and an insulator, a second electrode, a semiconductor layer provided between the first electrode and the second electrode, and an insulating layer provided between the first electrode and the semiconductor layer. The first electrode includes a first part that electrically connects the semiconductor layer and the first electrode. The first part is provided between a part of the insulating layer and another part of the insulating layer in a cross section parallel to a first direction connecting the first electrode and the second electrode. The first part includes the first metal layer in contact with the semiconductor layer, the second metal layer, and the insulator provided between the first metal layer and the second metal layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] One example of a power semiconductor device is a vertical power semiconductor device in which electrodes are provided above and below a semiconductor layer. When manufacturing a power semiconductor device using a semiconductor wafer, stress caused by a metal film can sometimes cause warping of the semiconductor wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-39219 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device that suppresses warpage of a semiconductor wafer. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a first electrode including a first metal layer, a second metal layer, and an insulator, a second electrode, a semiconductor layer provided between the first electrode and the second electrode, and an insulating layer provided between the first electrode and the semiconductor layer, wherein the first electrode has a first portion electrically connecting the semiconductor layer and the first electrode, and the first portion is provided between a portion of the insulating layer and another portion of the insulating layer in a cross section parallel to a first direction connecting the first electrode and the second electrode, and the first portion includes the first metal layer in contact with the semiconductor layer, the second metal layer, and the insulator provided between the first metal layer and the second metal layer. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic diagram of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 3] FIG. 1 is an enlarged schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 10 is a schematic cross-sectional view of a portion of a semiconductor device according to a first comparative embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of a portion of a semiconductor device according to a second comparative embodiment. [Figure 11] FIG. 4 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second modified example of the first embodiment. [Figure 13] FIG. 4 is a schematic diagram of a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second embodiment. [Figure 15] 5A to 5C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 16] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a modified example of the second embodiment. [Figure 17] FIG. 10 is a schematic diagram of a semiconductor device according to a third embodiment. [Figure 18] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a third embodiment. [Figure 19] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0008] In this specification, n + shape, n shape, n - When there is a notation with form, n + shape, n shape, n - This means that the n-type impurity concentration decreases in the order of the p + shape, p shape, p - If there is a form notation, p + shape, p shape, p - This means that the p-type impurity concentration decreases in the order of the type.

[0009] Qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor device herein can be performed by, for example, secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or Rutherford back-scattering spectroscopy (RBS). Furthermore, thicknesses of the components constituting the semiconductor device, distances between the components, and the like can be measured by, for example, a transmission electron microscope (TEM).

[0010] (First embodiment) A semiconductor device according to a first embodiment includes a first electrode including a first metal layer, a second metal layer, and an insulator, a second electrode, a semiconductor layer disposed between the first electrode and the second electrode, and an insulating layer disposed between the first electrode and the semiconductor layer. The first electrode has a first portion electrically connecting the semiconductor layer and the first electrode. The first portion is disposed between a portion of the insulating layer and another portion of the insulating layer in a cross section parallel to a first direction connecting the first electrode and the second electrode. The first portion includes the first metal layer in contact with the semiconductor layer, the second metal layer, and an insulator disposed between the first metal layer and the second metal layer.

[0011] The semiconductor device of the first embodiment is an insulated gate bipolar transistor (IGBT) 100. The IGBT 100 is a trench gate type IGBT that has a gate electrode in a trench formed in a semiconductor layer.

[0012] 1(a) and 1(b) are schematic diagrams of a semiconductor device according to a first embodiment, in which Fig. 1(a) is a front view of an IGBT 100, and Fig. 1(b) is a rear view of the IGBT 100.

[0013] 1(a), an emitter electrode 10, a gate electrode pad 31, and a gate electrode wiring 32 are provided on the front surface side of the IGBT 100. The gate electrode wiring 32 is connected to the gate electrode pad 31.

[0014] As shown in FIG. 1(b), a collector electrode 20 is provided on the back surface side of the IGBT 100.

[0015] A plurality of transistors are provided below the emitter electrode 10. A gate electrode pad 31 and a gate electrode wiring 32 are electrically connected to the gate electrodes of the transistors. A gate voltage is applied to the gate electrode pad 31 to control the switching operation of the transistors.

[0016] 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment, taken along the line AA' in FIG.

[0017] The IGBT 100 of the first embodiment includes an emitter electrode 10 (first electrode), a collector electrode 20 (second electrode), a gate electrode 30, a semiconductor layer 40, a gate insulating film 50, and an interlayer insulating layer 60 (insulating layer).

[0018] The emitter electrode 10 includes a first metal layer 11, a second metal layer 12, and an insulator 13. The emitter electrode 10 also includes a contact portion 10x (first portion).

[0019] A collector region 41, a drift region 42, a base region 43, an emitter region 44, and a contact region 46 are provided in the semiconductor layer 40. A gate trench 45 is provided in the semiconductor layer 40.

[0020] Hereinafter, the direction connecting the emitter electrode 10 and the collector electrode 20 will be referred to as the first direction. The first direction is the normal direction to the surface of the semiconductor layer 40. The direction perpendicular to the first direction will be referred to as the second direction.

[0021] The semiconductor layer 40 is provided between the emitter electrode 10 and the collector electrode 20. The semiconductor layer 40 is in contact with the emitter electrode 10 and the collector electrode 20.

[0022] The semiconductor layer 40 is made of, for example, single crystal silicon and has a thickness of, for example, 40 μm or more and 700 μm or less.

[0023] The collector region 41 is p + The collector region 41 is a semiconductor region having a shape similar to that of the collector electrode 20. The collector region 41 is electrically connected to the collector electrode 20. The collector region 41 is in contact with the collector electrode 20. The collector region 41 serves as a supply source of holes when the IGBT 100 is in the on state.

[0024] The drift region 42 has n - The drift region 42 is provided on the collector region 41.

[0025] The drift region 42 serves as a path for an on-current when the IGBT 100 is in an on-state. The drift region 42 is depleted when the IGBT 100 is in an off-state, and has the function of maintaining the breakdown voltage of the IGBT 100.

[0026] The base region 43 is a p-type semiconductor region and is provided on the drift region 42.

[0027] The depth of the base region 43 is, for example, 5 μm or less. An n-type inversion layer is formed in a region of the base region 43 facing the gate electrode 30 when the IGBT 100 is in the on state. The base region 43 functions as a channel region of the IGBT 100.

[0028] The emitter region 44 is n + The emitter region 44 is provided on the base region 43.

[0029] The emitter region 44 is in contact with the gate trench 45. The emitter region 44 is in contact with the gate insulating film 50.

[0030] The emitter region 44 is in contact with the contact portion 10x of the emitter electrode 10. The emitter region 44 is electrically connected to the emitter electrode 10. The emitter region 44 serves as a supply source of electrons when the IGBT 100 is in the on state.

[0031] The contact region 46 is p + The contact region 46 is provided on the base region 43.

[0032] The contact region 46 is in contact with the contact portion 10x of the emitter electrode 10. The contact region 46 is electrically connected to the emitter electrode 10. The contact region 46 electrically connects the emitter electrode 10 and the base region 43.

[0033] The contact region 46 does not necessarily have to be provided at a position sandwiched between the emitter regions 44 in the second direction. The contact region 46 may be provided, for example, in the depth direction of the emitter regions 44 in FIG.

[0034] The gate trench 45 is provided on the emitter electrode 10 side of the semiconductor layer 40. The gate trench 45 is a groove provided in the semiconductor layer 40. The gate trench 45 is a part of the semiconductor layer 40.

[0035] The gate trench 45 penetrates the emitter region 44 and the base region 43 and reaches the drift region 42. The gate trench 45 contacts the emitter region 44, the base region 43, and the drift region 42.

[0036] The gate electrode 30 is provided in the gate trench 45. The gate electrode 30 is electrically connected to a gate electrode wiring 32 and a gate electrode pad 31.

[0037] The gate electrode 30 is a conductor. The gate electrode 30 is, for example, a semiconductor or a metal. The gate electrode 30 is, for example, amorphous silicon containing conductive impurities or polycrystalline silicon containing conductive impurities.

[0038] The gate insulating film 50 is provided between the gate electrode 30 and the semiconductor layer 40. The gate insulating film 50 is provided between the gate electrode 30 and the drift region 42, between the gate electrode 30 and the base region 43, and between the gate electrode 30 and the emitter region 44. The gate insulating film 50 is provided between the emitter electrode 10 and the semiconductor layer 40.

[0039] The gate insulating film 50 is an insulator, and is made of, for example, silicon oxide.

[0040] The interlayer insulating layer 60 is provided between the semiconductor layer 40 and the emitter electrode 10. The interlayer insulating layer 60 is provided between the gate electrode 30 and the emitter electrode 10. The interlayer insulating layer 60 is an insulator. The interlayer insulating layer 60 is, for example, silicon oxide.

[0041] The emitter electrode 10 is provided above the semiconductor layer 40. The emitter electrode 10 is provided on the interlayer insulating layer 60.

[0042] The emitter electrode 10 includes a first metal layer 11, a second metal layer 12, and an insulator 13. The second metal layer 12 is provided on the first metal layer 11. The first metal layer 11 is provided, for example, between an interlayer insulating layer 60 and the second metal layer 12.

[0043] The emitter electrode 10 has a contact portion 10x, which electrically connects the emitter electrode 10 and the semiconductor layer 40.

[0044] The contact portion 10x is in contact with the semiconductor layer 40. The contact portion 10x is in contact with the emitter region 44, for example.

[0045] 2, the contact portion 10x is provided between a part of the interlayer insulating layer 60 and another part of the interlayer insulating layer 60. In FIG. 2, the interlayer insulating layer 60 on the left side of the contact portion 10x corresponds to the part of the interlayer insulating layer 60, and the interlayer insulating layer 60 on the right side of the contact portion 10x corresponds to the other part of the interlayer insulating layer 60.

[0046] The contact portion 10x is present in an opening provided in the interlayer insulating layer 60. The bottom surface of the contact portion 10x contacts the semiconductor layer 40. The side surface of the contact portion 10x contacts the interlayer insulating layer 60.

[0047] The contact portion 10x includes a first metal layer 11, a second metal layer 12, and an insulator 13.

[0048] At the contact portion 10x, the first metal layer 11 contacts the semiconductor layer 40. At the contact portion 10x, the first metal layer 11 contacts the emitter region 44, for example.

[0049] In the contact portion 10x, the insulator 13 is provided between the first metal layer 11 and the second metal layer 12. The insulator 13 is in contact with, for example, the first metal layer 11 and the second metal layer 12. The insulator 13 is surrounded by the first metal layer 11 and the second metal layer 12 in a cross section parallel to the first direction.

[0050] The first metal layer 11 is an electrical conductor. The first metal layer contains, for example, a metal or a metal compound. The first metal layer contains at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), and molybdenum (Mo).

[0051] The second metal layer 12 is an electrical conductor. The chemical composition of the second metal layer 12 is different from the chemical composition of the first metal layer 11, for example.

[0052] The second metal layer 12 includes, for example, a metal or a metal compound, and the first metal layer includes, for example, aluminum (Al) or copper (Cu).

[0053] The insulator 13 is an insulator. The insulator 13 includes, for example, an oxide, a nitride, or an oxynitride. The insulator 13 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0054] The collector electrode 20 is provided under the semiconductor layer 40. The collector electrode 20 contacts the collector region 41.

[0055] The collector electrode 20 is a conductor and includes, for example, a metal or a metal compound.

[0056] Fig. 3 is an enlarged schematic cross-sectional view of the semiconductor device of the first embodiment. Fig. 3 is an enlarged view of a part of Fig. 2. Fig. 3 is a view including the contact portion 10x of the emitter electrode 10.

[0057] 3, the first metal layer 11 has, for example, a stacked structure of a first film 11a and a second film 11b. The first film 11a contains, for example, a metal nitride. The first film 11a is, for example, a stacked film of an elemental metal film and a metal nitride film. The second film 11b contains, for example, an elemental metal.

[0058] The first film 11a is, for example, a laminated film of a titanium film and a titanium nitride film, and the second film 11b is, for example, a tungsten film.

[0059] In a cross section parallel to the first direction, for example, a first thickness (t1 in FIG. 3) in the first direction of the insulator 13 of the contact portion 10x is thicker than a second thickness (t2 in FIG. 3) in the first direction of the first metal layer 11 on the bottom surface of the contact portion 10x. The first thickness t1 is, for example, from 2 to 20 times the second thickness t2.

[0060] In a cross section parallel to the first direction, for example, a first thickness t1 in the first direction of the insulator 13 of the contact portion 10x is greater than a first width (W1 in FIG. 3) in the second direction of the insulator 13 of the contact portion 10x. The first thickness t1 is, for example, 1.5 to 10 times the first width W1. Note that the first width W1 does not necessarily have to match the width of the contact region 46 in the second direction as shown in FIG. 3.

[0061] In a cross section parallel to the first direction, for example, the first width W1 in the second direction of the insulator 13 of the contact portion 10x is at least half and at most nine-tenths of the second width (W2 in Figure 3) in the second direction of the contact portion 10x.

[0062] In a cross section parallel to the first direction, for example, the third thickness (t3 in FIG. 3) in the first direction of the second metal layer 12 of the contact portion 10x is thicker than the second thickness t2 in the first direction of the first metal layer 11 on the bottom surface of the contact portion 10x. The third thickness t3 is, for example, 1.5 to 20 times the second thickness t2.

[0063] In a cross section parallel to the first direction, for example, the second thickness t2 in the first direction of the first metal layer 11 on the bottom surface of the contact portion 10x is substantially equal to the fourth thickness (t4 in Figure 3) in the second direction of the first metal layer 11 on the side surface of the contact portion 10x.

[0064] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0065] The method for manufacturing a semiconductor device of the first embodiment includes forming a first insulating film on a first layer that is a semiconductor layer, forming an opening in the first insulating film, forming a first metal film in contact with the first layer within the opening, forming a second insulating film on the first metal film that fills the opening, removing the second insulating film around the opening, and forming a second metal film on the first metal film in contact with the first metal film and the second insulating film.

[0066] 4, 5, 6, 7, and 8 are diagrams illustrating a method for manufacturing the semiconductor device of the first embodiment, and are cross-sectional views corresponding to FIG. 2 of the first embodiment.

[0067] First, using a known process technology, a drift region 42, a base region 43, an emitter region 44, a contact region 46, and a gate trench 45 are formed in a semiconductor layer 40. Next, using a known process technology, a gate insulating film 50 and a gate electrode 30 are formed. The semiconductor layer 40 is an example of a first layer.

[0068] Next, a first silicon oxide film 70 is formed on the surface of the semiconductor layer 40. The first silicon oxide film 70 is formed by, for example, chemical vapor deposition (CVD). The first silicon oxide film 70 is an example of a first insulating film. The first silicon oxide film 70 will eventually become the interlayer insulating layer 60.

[0069] Next, an opening 71 is formed in the first silicon oxide film 70 (FIG. 4). The opening 71 reaches the semiconductor layer 40. The semiconductor layer 40 is exposed at the bottom of the opening 71. The opening 71 is formed by using, for example, lithography and reactive ion etching (RIE).

[0070] Next, a laminated film 72 of titanium and titanium nitride is formed (FIG. 5). The laminated film 72 contacts the semiconductor layer 40 in the opening 71.

[0071] The laminated film 72 is formed by, for example, a CVD method. The laminated film 72 is an example of a first metal film. The laminated film 72 will eventually become the first metal layer 11.

[0072] Next, a second silicon oxide film 73 is formed on the laminated film 72 (FIG. 6). The second silicon oxide film 73 fills the opening 71.

[0073] The second silicon oxide film 73 is formed by, for example, a CVD method. The second silicon oxide film 73 is an example of a second insulating film. A part of the second silicon oxide film 73 will eventually become the insulator 13.

[0074] Next, the second silicon oxide film 73 around the opening 71 is removed (FIG. 7). The second silicon oxide film 73 on the stacked film 72 around the opening 71 is removed. A part of the second silicon oxide film 73 remains in the opening 71.

[0075] The second silicon oxide film 73 is removed by, for example, the RIE method.

[0076] Next, an aluminum film 74 is formed on the laminated film 72 (FIG. 8). The aluminum film 74 contacts the laminated film 72 and the second silicon oxide film 73 in the opening 71.

[0077] The aluminum film 74 is formed by, for example, sputtering. The aluminum film 74 is an example of a second metal film. The aluminum film 74 will eventually become the second metal layer 12.

[0078] Thereafter, the collector region 41 and the collector electrode 20 are formed on the back surface side of the semiconductor layer 40 using a known process technology.

[0079] By the above-described method for manufacturing a semiconductor device, the IGBT 100 of the first embodiment shown in FIG. 2 is manufactured.

[0080] Next, the functions and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0081] 9 is a schematic cross-sectional view of a part of a semiconductor device of a first comparative embodiment, which corresponds to FIG. 2 of the first embodiment.

[0082] The IGBT 901 of the first comparative example differs from the IGBT 100 of the first embodiment in that the contact portion 10x does not include the insulator 13.

[0083] In the IGBT 901, the contact portion 10x is buried with a first metal layer 11 and a second metal layer 12. Stress from the metal material in which the contact portion 10x is buried may cause warping of the semiconductor wafer. If warping occurs in the semiconductor wafer, it becomes difficult to manufacture the IGBT 901.

[0084] In the IGBT 100 of the first embodiment, the contact portions 10x are embedded with an insulator 13 instead of a metal material. Embedding the contact portions 10x with the insulator 13 reduces stress caused by the metal material, thereby suppressing warpage of the semiconductor wafer.

[0085] 10 is a schematic cross-sectional view of a portion of a semiconductor device of a second comparative embodiment, which corresponds to FIG. 2 of the first embodiment.

[0086] The IGBT 902 of the second comparative embodiment differs from the IGBT 100 of the first embodiment in that the contact portion 10x does not include the insulator 13 and has a void 14.

[0087] In the IGBT 902, for example, cracks may occur from the cavity 14 of the contact portion 10x during operation of the IGBT 902. Also, in the IGBT 902, cracks may occur, for example, when the aluminum film sinks into the cavity 14. Cracks occurring in the IGBT 902 reduce the reliability of the IGBT 902.

[0088] In the IGBT 100 of the first embodiment, the contact portion 10x does not have a cavity 14 and is filled with the insulator 13. Therefore, the mechanical strength of the contact portion 10x is improved, the occurrence of cracks is suppressed, and the reliability of the IGBT 100 is improved.

[0089] In a cross section parallel to the first direction, the first thickness (t1 in FIG. 3) of the insulator 13 of the contact portion 10x in the first direction is preferably greater than the second thickness (t2 in FIG. 3) of the first metal layer 11 on the bottom surface of the contact portion 10x in the first direction. When the first thickness t1 is greater than the second thickness t2, stress caused by the metal material is alleviated.

[0090] (First Modification) The semiconductor device of the first modification of the first embodiment differs from the semiconductor device of the first embodiment in that, in a cross section parallel to the first direction, part of the side surface of the first portion is in contact with the semiconductor layer.

[0091] Fig. 11 is a schematic cross-sectional view of a part of a semiconductor device according to a first modification of the first embodiment, and corresponds to Fig. 2 of the first embodiment.

[0092] In the IGBT 101 of the first modification, in a cross section parallel to the first direction, a part of the side surface of the contact portion 10x is in contact with the semiconductor layer 40. The side surface of the contact portion 10x is in contact with, for example, the interlayer insulating layer 60, the emitter region 44, and the base region 43. The bottom surface of the contact portion 10x is in contact with, for example, the contact region 46.

[0093] The first variant IGBT 101 can be manufactured, for example, by etching the semiconductor layer 40 when forming the opening 71 in the first silicon oxide film 70 in the method for manufacturing the semiconductor device of the first embodiment described above, and then forming the contact region 46 using an ion implantation method.

[0094] (Second Modification) The semiconductor device of the second variant of the first embodiment differs from the semiconductor device of the first embodiment in that, in a cross section parallel to the first direction, the second thickness in the first direction of the first metal layer on the bottom surface of the first portion is thicker than the fourth thickness in the second direction of the side surface of the first portion.

[0095] Fig. 12 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the first embodiment, and corresponds to Fig. 2 of the first embodiment.

[0096] In the IGBT 102 of the second variant, in a cross section parallel to the first direction, for example, the second thickness t2 (t2 in Figure 3) in the first direction of the first metal layer 11 on the bottom surface of the contact portion 10x is thicker than the fourth thickness (t4 in Figure 3) in the second direction of the first metal layer 11 on the side surface of the contact portion 10x.

[0097] The second variant IGBT 102 can be manufactured, for example, by forming the stacked film 72 in the method for manufacturing the semiconductor device of the first embodiment described above under conditions such that the thickness deposited on the bottom of the opening 71 is greater than the thickness deposited on the sidewall.

[0098] According to the IGBT 102 of the second modified example, for example, the electrical resistance of the contact portion 10x can be reduced.

[0099] As described above, according to the semiconductor device of the first embodiment and the modified example, and the method for manufacturing the semiconductor device, it is possible to realize a semiconductor device that suppresses warpage of the semiconductor wafer.

[0100] (Second embodiment) A semiconductor device according to a second embodiment includes a first electrode including a first metal layer, a second metal layer, and an insulator; a second electrode; a semiconductor layer disposed between the first electrode and the second electrode; a first insulating layer disposed between the first electrode and the semiconductor layer; a second insulating layer disposed between the first insulating layer and the first electrode; and a conductive layer disposed between the first insulating layer and the second insulating layer. The first electrode has a first portion connecting the conductive layer to the first electrode. The first portion is disposed between a portion of the second insulating layer and another portion of the second insulating layer in a cross section parallel to a first direction connecting the first electrode and the second electrode. The first portion includes the first metal layer in contact with the conductive layer, the second metal layer, and an insulator disposed between the first metal layer and the second metal layer. The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the first portion connects the conductive layer and the first electrode. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0101] The semiconductor device of the second embodiment is an IGBT 200. The IGBT 200 is a trench gate type IGBT that includes a gate electrode in a trench formed in a semiconductor layer.

[0102] 13(a) and 13(b) are schematic diagrams of the semiconductor device of the second embodiment, in which Fig. 13(a) is a front view of the IGBT 200, and Fig. 13(b) is a rear view of the IGBT 200.

[0103] 13(a), an emitter electrode 10, a gate electrode pad 31, and a gate electrode wiring 32 are provided on the front surface side of the IGBT 200. The gate electrode wiring 32 is connected to the gate electrode pad 31.

[0104] As shown in FIG. 13(b), a collector electrode 20 is provided on the back surface side of the IGBT 200.

[0105] A plurality of transistors are provided below the emitter electrode 10. A gate electrode pad 31 and a gate electrode wiring 32 are electrically connected to the gate electrodes of the transistors. A gate voltage is applied to the gate electrode pad 31 to control the switching operation of the transistors.

[0106] In the cross section AA' of FIG. 13(a), the IGBT 200 has a structure similar to that of the IGBT 100 of the first embodiment shown in FIG. 2, for example.

[0107] 14 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment, taken along the line BB' in FIG.

[0108] The IGBT 200 of the second embodiment includes a collector electrode 20 (second electrode), a gate electrode 30 (conductive layer), a gate electrode wiring 32 (first electrode), a semiconductor layer 40, a gate insulating film 50 (first insulating layer), and an interlayer insulating layer 60 (second insulating layer).

[0109] The gate electrode wiring 32 includes a first metal layer 11, a second metal layer 12, and an insulator 13. The gate electrode wiring 32 also includes a contact portion 32x (first portion).

[0110] A collector region 41, a drift region 42, and a base region 43 are provided in the semiconductor layer 40. A gate trench 45 (trench) is provided in the semiconductor layer 40.

[0111] Hereinafter, the direction connecting the gate electrode wiring 32 and the collector electrode 20 will be referred to as a first direction, and the direction perpendicular to the first direction will be referred to as a second direction.

[0112] The semiconductor layer 40 is provided between the gate electrode wiring 32 and the collector electrode 20. The semiconductor layer 40 is in contact with the collector electrode 20.

[0113] The gate trench 45 is provided on the side of the semiconductor layer 40 where the gate electrode wiring 32 is provided. The gate trench 45 is a groove provided in the semiconductor layer 40. The gate trench 45 is a part of the semiconductor layer 40.

[0114] The gate trench 45 penetrates the base region 43 and reaches the drift region 42. The gate trench 45 contacts the base region 43 and the drift region 42.

[0115] The gate electrode 30 is provided in the gate trench 45. The gate electrode 30 is provided between the gate insulating film 50 and the interlayer insulating layer 60. The gate electrode 30 is electrically connected to a gate electrode wiring 32 and a gate electrode pad 31. The gate electrode 30 is an example of a conductive layer.

[0116] The gate electrode 30 is a conductor. The gate electrode 30 is, for example, a semiconductor or a metal. The gate electrode 30 is, for example, amorphous silicon containing conductive impurities or crystalline silicon containing multiple conductive impurities.

[0117] The gate insulating film 50 is provided between the gate electrode 30 and the semiconductor layer 40. The gate insulating film 50 is provided between the gate electrode 30 and the drift region 42 and between the gate electrode 30 and the base region 43. The gate insulating film 50 is provided between the gate electrode wiring 32 and the semiconductor layer 40. The gate insulating film 50 is an example of a first insulating layer.

[0118] The gate insulating film 50 is an insulator, and is made of, for example, silicon oxide.

[0119] The interlayer insulating layer 60 is provided between the semiconductor layer 40 and the gate electrode wiring 32. The interlayer insulating layer 60 is provided between the gate insulating film 50 and the gate electrode wiring 32. The interlayer insulating layer 60 is provided between the gate electrode 30 and the gate electrode wiring 32. The interlayer insulating layer 60 is an example of a second insulating layer.

[0120] The interlayer insulating layer 60 is an insulator, such as silicon oxide.

[0121] The gate electrode wiring 32 is provided above the semiconductor layer 40. The gate electrode wiring 32 is provided on the interlayer insulating layer 60.

[0122] The gate electrode wiring 32 includes a first metal layer 11, a second metal layer 12, and an insulator 13. The second metal layer 12 is provided on the first metal layer 11. The first metal layer 11 is provided, for example, between the interlayer insulating layer 60 and the second metal layer 12.

[0123] The gate electrode wiring 32 has a contact portion 32x. The contact portion 32x electrically connects the gate electrode wiring 32 and the gate electrode 30. The contact portion 32x is in contact with the gate electrode 30.

[0124] 14, the contact portion 32x is provided between a part of the interlayer insulating layer 60 and another part of the interlayer insulating layer 60. In FIG. 14, the interlayer insulating layer 60 on the left side of the contact portion 32x corresponds to the part of the interlayer insulating layer 60, and the interlayer insulating layer 60 on the right side of the contact portion 32x corresponds to the other part of the interlayer insulating layer 60.

[0125] The contact portion 32x is present in an opening provided in the interlayer insulating layer 60. The bottom surface of the contact portion 32x contacts the gate electrode 30. The side surface of the contact portion 32x contacts the interlayer insulating layer 60.

[0126] The contact portion 32x includes a first metal layer 11, a second metal layer 12, and an insulator 13.

[0127] The first metal layer 11 contacts the gate electrode 30 at the contact portion 32x.

[0128] In the contact portion 32x, the insulator 13 is provided between the first metal layer 11 and the second metal layer 12. The insulator 13 is in contact with, for example, the first metal layer 11 and the second metal layer 12. The insulator 13 is surrounded by the first metal layer 11 and the second metal layer 12 in a cross section parallel to the first direction.

[0129] The first metal layer 11 is an electrical conductor. The first metal layer contains, for example, a metal or a metal compound. The first metal layer contains at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), and molybdenum (Mo).

[0130] The second metal layer 12 is an electrical conductor. The chemical composition of the second metal layer 12 is different from the chemical composition of the first metal layer 11, for example.

[0131] The second metal layer 12 includes, for example, a metal or a metal compound, and the first metal layer includes, for example, aluminum (Al) or copper (Cu).

[0132] The insulator 13 is an insulator. The insulator 13 includes, for example, an oxide, a nitride, or an oxynitride. The insulator 13 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0133] The contact portion 32x has the same structure as the contact portion 10x of the first embodiment shown in FIG. 3, except that the bottom surface thereof is in contact with the gate electrode 30 instead of the semiconductor layer 40.

[0134] Next, an example of a method for manufacturing the semiconductor device according to the second embodiment will be described.

[0135] The method for manufacturing a semiconductor device according to the second embodiment includes forming a first insulating film on a first layer, which is a conductive layer, forming an opening in the first insulating film, forming a first metal film in the opening so that the first layer is in contact with the first layer, forming a second insulating film on the first metal film so that the opening is filled, removing the second insulating film around the opening, and forming a second metal film on the first metal film so that the second metal film is in contact with the first metal film and the second insulating film. The method for manufacturing a semiconductor device according to the second embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that the first layer is a conductive layer rather than a semiconductor layer. Below, descriptions of the same content as in the first embodiment will be omitted.

[0136] 15A to 15C are diagrams illustrating a method for manufacturing a semiconductor device according to the second embodiment, and are cross-sectional views corresponding to FIG.

[0137] First, using a known process technique, the drift region 42, the base region 43, and the gate trench 45 are formed in the semiconductor layer 40. Next, using a known process technique, the gate insulating film 50 and the gate electrode 30 are formed.

[0138] The gate electrode 30 is a conductive layer and is an example of a first layer.

[0139] Next, a first silicon oxide film 70 is formed on the surfaces of the semiconductor layer 40 and the gate electrode 30. The first silicon oxide film 70 is formed by, for example, a chemical vapor deposition method (CVD method). The first silicon oxide film 70 is an example of a first insulating film. The first silicon oxide film 70 will eventually become the interlayer insulating layer 60.

[0140] Next, an opening 71 is formed in the first silicon oxide film 70 (FIG. 15). The opening 71 reaches the gate electrode 30. The gate electrode 30 is exposed at the bottom of the opening 71. The opening 71 is formed by using, for example, lithography and reactive ion etching (RIE).

[0141] After the opening 71 is formed, the IGBT 200 of the second embodiment shown in FIG. 14 is manufactured using a manufacturing method similar to that of the semiconductor device of the first embodiment.

[0142] (Variation) The semiconductor device of the modified example of the second embodiment differs from the semiconductor device of the second embodiment in that, in a cross section parallel to the first direction, part of the side surface of the first portion is in contact with the conductive layer.

[0143] Fig. 16 is a schematic cross-sectional view of a part of a semiconductor device according to a modification of the second embodiment, and corresponds to Fig. 14 of the second embodiment.

[0144] In the IGBT 201 of the modified example, in a cross section parallel to the first direction, a part of the side surface of the contact portion 32x contacts the gate electrode 30. The side surface of the contact portion 32x contacts the interlayer insulating layer 60 and the gate electrode 30.

[0145] The IGBT 201 of the modified example can be manufactured by, for example, etching the gate electrode 30 when forming the opening 71 in the first silicon oxide film 70 in the manufacturing method of the semiconductor device of the second embodiment described above.

[0146] According to the IGBT 201 of the modified example, for example, the contact area between the contact portion 32x and the gate electrode 30 increases, and the contact resistance can be reduced.

[0147] As described above, according to the semiconductor device of the second embodiment and the modified example, and the method for manufacturing the semiconductor device, it is possible to realize a semiconductor device that suppresses warpage of the semiconductor wafer, similar to the first embodiment.

[0148] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that the conductive layer to which the first portion is connected is not inside the trench. Hereinafter, some of the description overlapping with the first or second embodiment may be omitted.

[0149] The semiconductor device of the third embodiment is an IGBT 300. The IGBT 300 is a trench gate type IGBT that includes a gate electrode in a trench formed in a semiconductor layer.

[0150] 17(a) and 17(b) are schematic diagrams of the semiconductor device of the third embodiment. Fig. 17(a) is a front view of the IGBT 300. Fig. 17(b) is a rear view of the IGBT 300.

[0151] 17(a), an emitter electrode 10, a gate electrode pad 31, and a gate electrode wiring 32 are provided on the front surface side of the IGBT 300. The gate electrode wiring 32 is connected to the gate electrode pad 31.

[0152] As shown in FIG. 17(b), a collector electrode 20 is provided on the back surface side of the IGBT 300.

[0153] A plurality of transistors are provided below the emitter electrode 10. A gate electrode pad 31 and a gate electrode wiring 32 are electrically connected to the gate electrodes of the transistors. A gate voltage is applied to the gate electrode pad 31 to control the switching operation of the transistors.

[0154] In the cross section AA' of FIG. 17(a), the IGBT 300 has a structure similar to that of the IGBT 100 of the first embodiment shown in FIG. 2, for example.

[0155] 18 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment, taken along the line CC' in FIG.

[0156] The IGBT 300 of the third embodiment includes a collector electrode 20 (second electrode), a gate electrode 30 (conductive layer), a gate electrode wiring 32 (first electrode), a semiconductor layer 40, a surface insulating layer 55 (first insulating layer), and an interlayer insulating layer 60 (second insulating layer).

[0157] The gate electrode wiring 32 includes a first metal layer 11, a second metal layer 12, and an insulator 13. The gate electrode wiring 32 also includes a contact portion 32x (first portion).

[0158] In the semiconductor layer 40, a collector region 41, a drift region 42, and a base region 43 are provided.

[0159] Hereinafter, the direction connecting the gate electrode wiring 32 and the collector electrode 20 will be referred to as a first direction, and the direction perpendicular to the first direction will be referred to as a second direction.

[0160] The semiconductor layer 40 is provided between the gate electrode wiring 32 and the collector electrode 20. The semiconductor layer 40 is in contact with the collector electrode 20.

[0161] The surface insulating layer 55 is provided on the surface of the semiconductor layer 40. The surface insulating layer 55 is provided between the gate electrode wiring 32 and the semiconductor layer 40. The surface insulating layer 55 is provided between the semiconductor layer 40 and the gate electrode 30. The surface insulating layer 55 is an example of a first insulating layer.

[0162] The surface insulating layer 55 is an insulator, such as silicon oxide.

[0163] The gate electrode 30 is provided on the surface insulating layer 55. The gate electrode 30 is provided between the surface insulating layer 55 and the interlayer insulating layer 60. The gate electrode 30 is electrically connected to a gate electrode wiring 32 and a gate electrode pad 31. The gate electrode 30 is an example of a conductive layer.

[0164] The gate electrode 30 is a conductor. The gate electrode 30 is, for example, a semiconductor or a metal. The gate electrode 30 is, for example, amorphous silicon containing conductive impurities or polycrystalline silicon containing conductive impurities.

[0165] The interlayer insulating layer 60 is provided between the semiconductor layer 40 and the gate electrode wiring 32. The interlayer insulating layer 60 is provided between the surface insulating layer 55 and the gate electrode wiring 32. The interlayer insulating layer 60 is provided between the gate electrode 30 and the gate electrode wiring 32. The interlayer insulating layer 60 is an example of a second insulating layer.

[0166] The interlayer insulating layer 60 is an insulator, such as silicon oxide.

[0167] The gate electrode wiring 32 is provided above the semiconductor layer 40. The gate electrode wiring 32 is provided on the interlayer insulating layer 60.

[0168] The gate electrode wiring 32 includes a first metal layer 11, a second metal layer 12, and an insulator 13. The second metal layer 12 is provided on the first metal layer 11. The first metal layer 11 is provided, for example, between the interlayer insulating layer 60 and the second metal layer 12.

[0169] The gate electrode wiring 32 has a contact portion 32x. The contact portion 32x electrically connects the gate electrode wiring 32 and the gate electrode 30. The contact portion 32x is in contact with the gate electrode 30.

[0170] 18, the contact portion 32x is provided between a part of the interlayer insulating layer 60 and another part of the interlayer insulating layer 60. In FIG. 18, the interlayer insulating layer 60 on the left side of the contact portion 32x corresponds to the part of the interlayer insulating layer 60, and the interlayer insulating layer 60 on the right side of the contact portion 32x corresponds to the other part of the interlayer insulating layer 60.

[0171] The contact portion 32x is present in an opening provided in the interlayer insulating layer 60. The bottom surface of the contact portion 32x contacts the gate electrode 30. The side surface of the contact portion 32x contacts the interlayer insulating layer 60.

[0172] The contact portion 32x includes a first metal layer 11, a second metal layer 12, and an insulator 13.

[0173] The first metal layer 11 contacts the gate electrode 30 at the contact portion 32x.

[0174] In the contact portion 32x, the insulator 13 is provided between the first metal layer 11 and the second metal layer 12. The insulator 13 is in contact with, for example, the first metal layer 11 and the second metal layer 12. The insulator 13 is surrounded by the first metal layer 11 and the second metal layer 12 in a cross section parallel to the first direction.

[0175] The first metal layer 11 is an electrical conductor. The first metal layer contains, for example, a metal or a metal compound. The first metal layer contains at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), and molybdenum (Mo).

[0176] The second metal layer 12 is an electrical conductor. The chemical composition of the second metal layer 12 is different from the chemical composition of the first metal layer 11, for example.

[0177] The second metal layer 12 includes, for example, a metal or a metal compound, and the first metal layer includes, for example, aluminum (Al) or copper (Cu).

[0178] The insulator 13 is an insulator. The insulator 13 includes, for example, an oxide, a nitride, or an oxynitride. The insulator 13 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0179] The contact portion 32x has the same structure as the contact portion 10x of the first embodiment shown in FIG. 3, except that the bottom surface thereof is in contact with the gate electrode 30 instead of the semiconductor layer 40.

[0180] Next, an example of a method for manufacturing the semiconductor device according to the third embodiment will be described.

[0181] The method for manufacturing a semiconductor device according to the third embodiment differs from the method for manufacturing a semiconductor device according to the second embodiment in that the conductive layer is not located in the trench. Hereinafter, a description of the same content as in the first or second embodiment will be omitted.

[0182] 19A to 19C are diagrams illustrating a method for manufacturing a semiconductor device according to the third embodiment, and are cross-sectional views corresponding to FIG.

[0183] First, using a known process technique, the drift region 42 and the base region 43 are formed in the semiconductor layer 40. Next, using a known process technique, a silicon oxide film 61 is formed on the semiconductor layer 40.

[0184] Next, the gate electrode 30 is formed on the silicon oxide film 61. The gate electrode 30 is a conductive layer. The gate electrode 30 is an example of a first layer.

[0185] Next, a first silicon oxide film 70 is formed on the gate electrode 30. The first silicon oxide film 70 is formed by, for example, chemical vapor deposition (CVD). The first silicon oxide film 70 is an example of a first insulating film. The first silicon oxide film 70 will eventually become the interlayer insulating layer 60.

[0186] Next, an opening 71 is formed in the first silicon oxide film 70 (FIG. 19). The opening 71 reaches the gate electrode 30. The gate electrode 30 is exposed at the bottom of the opening 71. The opening 71 is formed by using, for example, lithography and reactive ion etching (RIE).

[0187] After the opening 71 is formed, the IGBT 300 of the third embodiment shown in FIG. 18 is manufactured using a manufacturing method similar to that of the semiconductor device of the first embodiment.

[0188] As described above, according to the semiconductor device and the method for manufacturing the semiconductor device of the third embodiment, a semiconductor device that suppresses warpage of the semiconductor wafer can be realized, similarly to the first embodiment.

[0189] In the first to third embodiments, the semiconductor layer is made of single crystal silicon, but the semiconductor layer is not limited to single crystal silicon. For example, the semiconductor layer may be made of other single crystal semiconductors such as single crystal silicon carbide.

[0190] In the first to third embodiments, a trench gate type IGBT has been described as an example of the semiconductor device, but the semiconductor device may be, for example, a planar gate type IGBT.

[0191] In the first to third embodiments, an IGBT has been described as an example of a semiconductor device, but the semiconductor device may be, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, or an RC-IGBT in which an IGBT and a diode are formed on the same semiconductor chip.

[0192] In the second embodiment, the conductive layer provided in the trench is a gate electrode, but the conductive layer provided in the trench may be, for example, a dummy gate electrode or a field plate electrode. When the conductive layer is a dummy gate electrode or a field plate electrode, the first electrode connected to the dummy gate electrode or the field plate electrode is, for example, an emitter electrode.

[0193] In the third embodiment, the conductive layer is a gate electrode, but the conductive layer may be, for example, a dummy gate electrode or a field plate electrode. When the conductive layer is a dummy gate electrode or a field plate electrode, the first electrode connected to the dummy gate electrode or the field plate electrode is, for example, an emitter electrode.

[0194] In the third embodiment, the conductive layer is a gate electrode, but the conductive layer is not limited to a gate electrode and may be any other wiring layer.

[0195] In the first to third embodiments, the first electrode is an emitter electrode or a gate electrode wiring, but the first electrode is not limited to an emitter electrode or a gate electrode wiring, and may be any other electrode or electrode wiring.

[0196] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0197] 10 Emitter electrode (first electrode) 10x contact part (first part) 11 First metal layer 12 Second Metal Layer 13 Insulators 20 Collector electrode (second electrode) 30 Gate electrode (conductive layer, first layer) 32 gate electrode wiring (first electrode) 32x contact part (first part) 40 Semiconductor layer (first layer) 45 Gate trench (trench) 50 Gate insulating film (first insulating layer) 55 Surface insulating layer (first insulating layer) 60 Interlayer insulating layer (insulating layer, second insulating layer) 70 First silicon oxide film (first insulating film) 71 Opening 72 Laminated film (first metal film) 73 Second silicon oxide film (second insulating film) 74 Aluminum film (second metal film) 100 IGBT (semiconductor device) 101 IGBT (semiconductor device) 102 IGBT (semiconductor device) 200 IGBT (semiconductor device) 201 IGBT (semiconductor device) 300 IGBT (semiconductor device)

Claims

1. a first electrode including a first metal layer, a second metal layer, and an insulator; a second electrode; and a semiconductor layer provided between the first electrode and the second electrode; an insulating layer provided between the first electrode and the semiconductor layer, the first electrode has a first portion that electrically connects the semiconductor layer and the first electrode; the first portion is provided between a part of the insulating layer and another part of the insulating layer in a cross section parallel to a first direction connecting the first electrode and the second electrode, The first portion includes the first metal layer in contact with the semiconductor layer, the second metal layer, and the insulator provided between the first metal layer and the second metal layer.

2. 2. The semiconductor device according to claim 1, wherein said insulator is surrounded by said first metal layer and said second metal layer in said cross section.

3. The semiconductor device according to claim 1 , wherein the insulator includes an oxide, a nitride, or an oxynitride.

4. 2. The semiconductor device according to claim 1, wherein the chemical composition of said second metal layer is different from the chemical composition of said first metal layer.

5. 2. The semiconductor device according to claim 1, wherein said first metal layer includes tungsten (W) and said second metal layer includes aluminum (Al).

6. The semiconductor device according to claim 1 , wherein in the cross section, a part of a side surface of the first portion is in contact with the semiconductor layer.

7. 2. The semiconductor device according to claim 1, wherein, in the cross section, a first thickness in the first direction of the insulator in the first portion is greater than a second thickness in the first direction of the first metal layer at the bottom surface of the first portion.

8. 2. The semiconductor device according to claim 1, wherein, in the cross section, a first thickness of said insulator in said first direction in said first portion is greater than a first width of said insulator in said first portion in a second direction.

9. 2. The semiconductor device according to claim 1, wherein in the cross section, a first width in the second direction of said first portion of said insulator is equal to or greater than half of a second width in the second direction of said first portion.

10. 2. The semiconductor device of claim 1, wherein in the cross section, a third thickness in the first direction of the second metal layer in the first portion is thicker than a second thickness in the first direction of the first metal layer at the bottom surface of the first portion.

11. 2. The semiconductor device of claim 1, wherein in the cross section, a second thickness in the first direction of the first metal layer at the bottom surface of the first portion is thicker than a fourth thickness in a second direction perpendicular to the first direction of the first metal layer at the side surface of the first portion.

12. a first electrode including a first metal layer, a second metal layer, and an insulator; a second electrode; and a semiconductor layer provided between the first electrode and the second electrode; a first insulating layer provided between the first electrode and the semiconductor layer; a second insulating layer provided between the first insulating layer and the first electrode; a conductive layer provided between the first insulating layer and the second insulating layer; Equipped with the first electrode has a first portion connecting the conductive layer and the first electrode; the first portion is provided between a part of the second insulating layer and another part of the second insulating layer in a cross section parallel to a first direction connecting the first electrode and the second electrode, The first portion of the semiconductor device includes the first metal layer in contact with the conductive layer, the second metal layer, and the insulator provided between the first metal layer and the second metal layer.

13. 13. The semiconductor device of claim 12, wherein the semiconductor layer includes a trench, the first insulating layer and the conductive layer are disposed in the trench, and the first metal layer contacts the conductive layer in the trench.

14. 13. The semiconductor device according to claim 12, wherein said conductive layer is polycrystalline silicon.

15. The semiconductor device according to claim 12 , wherein in the cross section, a part of a side surface of the first portion is in contact with the conductive layer.

16. forming a first insulating film on a first layer which is either a semiconductor layer or a conductive layer; forming an opening in the first insulating film; forming a first metal film in contact with the first layer in the opening; forming a second insulating film on the first metal film to fill the opening; removing the second insulating film around the opening; forming a second metal film on the first metal film, the second metal film being in contact with the first metal film and the second insulating film;

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein a part of said second insulating film is left in said opening when said second insulating film is removed.

18. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the second metal film has a thickness greater than that of the first metal film.

19. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the second insulating film includes an oxide, a nitride, or an oxynitride.

20. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the chemical composition of the second metal film is different from the chemical composition of the first metal film.

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