Semiconductor switch

Abstract

To accurately drive a load using weak current.SOLUTION: A semiconductor switch includes an electromotive power generation circuit that generates electromotive power by light reception, a first switching transistor that is connected between a first output terminal and a reference voltage node and drives a load when the electromotive power is generated, a second switching transistor that is connected between a second output terminal and the reference voltage node and drives the load when the electromotive power is generated, and a protection circuit that protects the first switching transistor and the second switching transistor from overcurrent and overheat using the electromotive power as a power source voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION An embodiment of the present invention relates to a semiconductor switch. [Background technology]

[0002] Photorelays have several operating modes, one of which is solar cell mode, in which a small electromotive force generated by the light emission of the LED inside the photorelay is used to turn on the switching transistor and drive the load.

[0003] To control the on / off of the switching transistor, a timer is required to determine the on / off timing. The timer can be configured with a digital or analog circuit, but in the solar cell mode mentioned above, the current that can be passed to the light-receiving side of the photorelay is very small, and it is not easy to operate a timer using this weak current. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-102911 [Patent Document 2] Japanese Patent Application Publication No. 10-214939 [Patent Document 3] Japanese Patent Application Publication No. 09-186573 Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, an embodiment of the present invention provides a semiconductor switch that can drive a load with high precision by utilizing a weak current. [Means for solving the problem]

[0006] In order to solve the above problems, according to one embodiment of the present invention, there is provided an electromotive force generating circuit that generates an electromotive force by receiving light, a first switching transistor connected between the first output terminal and a reference voltage node, for driving a load when the electromotive force is generated; a second switching transistor connected between a second output terminal and the reference voltage node, for driving a load when the electromotive force is generated; a protection circuit that uses the electromotive force as a power supply voltage to protect the first switching transistor and the second switching transistor from overcurrent and overheat. A semiconductor switch is provided. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing the overall configuration of a semiconductor switch according to an embodiment. [Figure 2] Detailed circuit diagram of an electromotive force generating circuit. [Figure 3] Equivalent circuit diagram of the current generation circuit in Figure 2. [Figure 4] FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of the protection circuit of FIG. 1. [Figure 5A] FIG. 5 is a circuit diagram showing an example of a specific circuit configuration of the minute current source in FIG. 4. [Figure 5B] Schematic diagram continuing from Figure 5A. [Figure 6] FIG. 5 is a circuit diagram showing an example of a specific circuit configuration of the overcurrent and overheat detection circuit of FIG. 4. [Figure 7] FIG. 5 is a circuit diagram showing an example of a specific circuit configuration of an RS-F / F in the protection control circuit of FIG. 4. [Figure 8] A diagram showing the truth table of an RS-F / F. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of a semiconductor switch will be described with reference to the drawings. The following description will focus on the main components of the semiconductor switch, but the semiconductor switch may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0009] 1 is a block diagram showing the overall configuration of a semiconductor switch 1 according to one embodiment. As shown in FIG. 1, the semiconductor switch 1 according to one embodiment includes an electromotive force generating circuit 2, a first switching transistor Q1, a second switching transistor Q2, and a protection circuit 3.

[0010] The electromotive force generating circuit 2 has a light emitting element and a light receiving element, and receives light emitted by the light emitting element with the light receiving element to generate an electromotive force due to the received light. The light emitting element is, for example, an LED (Light Emitting Diode). The light receiving element is, for example, a photodiode. Below, an example will be described in which a photodiode is used as the light receiving element. A photodiode has multiple operation modes, one of which is called a solar cell mode. In the solar cell mode, the photodiode generates an electromotive force when it receives light. The electromotive force generating circuit 2 according to this embodiment operates, for example, a photodiode in the solar cell mode.

[0011] A current source CS1 that supplies a current to the light-emitting element is connected to the electromotive force generating circuit 2. The electromotive force generating circuit 2 outputs an electromotive force VCC and a GATE1 signal that sets the voltage of the GATE wiring connected to the gate of the first switching transistor Q1 and the gate of the second switching transistor Q2.

[0012] The first switching transistor Q1 is connected between the VSEN1 terminal and a reference voltage node (for example, a ground node), and drives a load (not shown) based on the electromotive force generated by the electromotive force generating circuit 2.

[0013] The second switching transistor Q2 is connected between the VSEN2 terminal and a reference voltage node (for example, a ground node), and drives a load (not shown) based on the electromotive force generated by the electromotive force generating circuit 2.

[0014] The first switching transistor Q1 and the second switching transistor Q2 are, for example, NMOS transistors. A first resistor R1 is connected between the body of the first switching transistor Q1 and a reference voltage node (for example, a ground node GND_S). A Zener diode D1 is connected between the gate and drain of the first switching transistor Q1. The anode of the Zener diode D1 is connected to the gate of the first switching transistor Q1, and the cathode of the Zener diode D1 is connected to the drain of the first switching transistor Q1. A first overcurrent detection signal VSEN1 is output from a VSEN1 terminal connected to the body of the first switching transistor Q1.

[0015] A second resistor R2 is connected between the body of the second switching transistor Q2 and a reference voltage node (for example, the ground node GND_S). A Zener diode D2 is connected between the gate and drain of the second switching transistor Q2. The anode of the Zener diode D2 is connected to the gate of the second switching transistor Q2, and the cathode of the Zener diode D2 is connected to the drain of the second switching transistor Q2. A second overcurrent detection signal VSEN2 is output from a VSEN2 terminal connected to the body of the second switching transistor Q2.

[0016] The above-mentioned first overcurrent detection signal VSEN1 and second overcurrent detection signal VSEN2 are signals that go to a high level when an overcurrent is detected.

[0017] The protection circuit 3 protects the first switching transistor Q1 and the second switching transistor Q2 from overcurrent and overheating by using the electromotive force VCC generated by the electromotive force generating circuit 2 as a power supply voltage. The protection circuit 3 generates a first reference voltage SC_REF, a second reference voltage TSD_REF, a third reference voltage REF_285, and a fourth reference voltage VCT using the electromotive force VCC generated by the electromotive force generating circuit 2. The first reference voltage SC_REF is used to detect overcurrent. The second reference voltage TSD_REF is used to detect overheating. The fourth reference voltage VCT is a low-voltage signal generated from the third reference voltage REF_285.

[0018] The protection circuit 3 outputs an overcurrent monitor signal indicating whether an overcurrent has been detected and an overheat monitor signal indicating whether an overheat has been detected. The overcurrent monitor signal is a signal that goes low when an overcurrent has been detected, for example. The overheat monitor signal is a signal that goes low when an overheat has been detected, for example.

[0019] Fig. 2 is a detailed circuit diagram of the electromotive force generating circuit 2. As shown in Fig. 2, the electromotive force generating circuit 2 includes a current generating circuit 4, a first photodiode row 5, a second photodiode row 6, a third photodiode row 7, an OFF control circuit 8, and resistors R3 and R4.

[0020] A GATE line is connected to the gate of the first switching transistor Q1 and the gate of the second switching transistor Q2. A GATE1 line is connected to this GATE line via an analog switch (described later), and is branched into a GATE2 line and a GATE3 line via resistors R3 and R4.

[0021] The anode of the diode D3 is connected to the fGND node. In this specification, the cathode of the diode D3 is referred to as the fGND1 node.

[0022] As will be described later, the current generating circuit 4 generates a current when it receives light emitted from the light emitting element 2 a. The generated current flows through the first photodiode row 5, the second photodiode row 6, and the third photodiode row 7.

[0023] Each of the first photodiode row 5, the second photodiode row 6, and the third photodiode row 7 has a configuration in which a plurality of photodiodes PD are connected in series. In the first photodiode row and the second photodiode row, the plurality of photodiodes PD connected in series have the same orientation, whereas in the third photodiode row, the plurality of photodiodes PD are connected in series in the opposite orientation to the first photodiode row and the second photodiode row.

[0024] More specifically, the first photodiode column has a plurality of photodiodes PD connected in series between the VCC node and the fGND1 node, and the anode of each photodiode PD is arranged on the VCC node side, and the cathode is arranged on the fGND1 node side.

[0025] The second photodiode row has a plurality of photodiodes PD connected in series between the GATE2 wiring and the fGND1 node, with the anode of each photodiode PD being arranged on the GATE2 wiring side and the cathode being arranged on the fGND1 node side.

[0026] The third photodiode row has a plurality of photodiodes PD connected in series between the input node of the off control circuit 8 and the fGND1 node, and the anode of each photodiode PD is arranged on the fGND1 node side, and the cathode is arranged on the input node side of the off control circuit 8.

[0027] The OFF control circuit 8 has an NMOS transistor Q3, an NPN transistor Q4, a diode D3, Zener diodes D4 and D5, and resistors R3 and R4.

[0028] The NMOS transistor Q3 is a depletion type, and even if the gate voltage is 0V or less, current flows between the drain and source of the NMOS transistor Q3, causing the voltage level of the GATE1 wiring to be the ground voltage. The gate of the NMOS transistor Q3 is connected in parallel to the third photodiode row and resistor R6 via resistor R5. The drain of the NMOS transistor Q3 is connected to the GATE3 wiring. The source of the NMOS transistor Q3 is connected to the base of the NPN transistor Q4 and the fGND1 node. The emitter of the NPN transistor Q4 is connected to the ground node, and the collector is connected to the GATE3 wiring.

[0029] Between the GATE2 wiring and the ground node f_GND, two Zener diodes D4 and D5 are connected in series in the opposite directions.

[0030] Next, we will explain the operation of the electromotive force generating circuit 2. When the light-emitting element 2a is not emitting light, the NMOS transistor Q3 in the off control circuit 8 is of the depletion type, so current flows between the drain and source of the NMOS transistor Q3, and the GATE1 wiring and the GATE wiring become at a voltage level close to the ground voltage. As a result, both the first switching transistor Q1 and the second switching transistor Q2 in FIG. 1 are turned off.

[0031] When the light-emitting element 2a emits light, an electromotive force is generated across the first photodiode row 5, and this electromotive force is output from the VCC line. When the light-emitting element 2a emits light, an electromotive force is generated across the second photodiode row 6, causing the voltage level of the GATE1 line to rise. When the light-emitting element 2a emits light, an electromotive force is generated across the third photodiode row 7, causing the gate voltage of the NMOS transistor Q3 in the off control circuit 8 to become negative. The NMOS transistor Q3 turns off, and no current flows between its drain and source. This causes the voltage level of the GATE1 line to rise, turning on the first switching transistor Q1 and the second switching transistor Q2. This enables the first switching transistor Q1 and the second switching transistor Q2 to drive the load.

[0032] Figure 3 is an equivalent circuit diagram of the current generating circuit 4 in Figure 2. The current generating circuit 4 has a light-emitting circuit 4a and a light-receiving circuit 4b. The light-emitting circuit 4a has a light-emitting element 2a and a current source CS1. As shown in Figure 3, the current source CS1 can be equivalently represented by two resistors R7 and R8 and a voltage source VS.

[0033] The light receiving circuit 4b has a first current generating unit 4c connected to one end of the first photodiode row 5, a second current generating unit 4d connected to one end of the second photodiode row 6, and a third current generating unit 4e connected to one end of the third photodiode row 7.

[0034] The first current generating unit 4c has a first current source CS2, a second current source CS3, resistors R9, R10, R11, and a capacitor C1. The first current source CS2 and the resistor R9 are connected in series, the second current source CS3, the resistor R10, and the capacitor C1 are connected in parallel, and the resistor R11 is connected in series to this parallel circuit.

[0035] The second current generator 4d has a third current source CS4 and a fourth current source CS5, resistors R12, R13, and R14, and a capacitor C2. The third current generator 4e has a fifth current source CS6 and a sixth current source CS7, resistors R15, R16, and R17, and a capacitor C3. The circuit configurations of the second current generator 4d and the third current generator 4e are the same as that of the first current generator 4c.

[0036] A current generated by the electromotive force generated in the first photodiode row 5 flows to the first current generating unit 4c. A current generated by the electromotive force generated in the second photodiode row 6 flows to the second current generating unit 4d. A current generated by the electromotive force generated in the third photodiode row 7 flows to the third current generating unit 4e. The first current source CS2 and the second current source CS3 in the first current generating unit 4c are equivalent representations of the current generated by the electromotive force generated in the first photodiode row 5. The third current source CS4 and the fourth current source CS5 in the second current generating unit 4d are equivalent representations of the current generated by the electromotive force generated in the second photodiode row 6. The fifth current source CS6 and the sixth current source CS7 in the third current generating unit 4e are equivalent representations of the current generated by the electromotive force generated in the third photodiode row 7.

[0037] Fig. 4 is a circuit diagram showing an example of a specific circuit configuration of the protection circuit 3 of Fig. 1. As shown in Fig. 4, the protection circuit 3 includes an overcurrent / overheat detection circuit 11, a minute current source 12, a protection control circuit 13, an analog switch 14, a low-voltage holding circuit 15, and an internal power supply voltage holding circuit 16.

[0038] The overcurrent and overheat detection circuit 11 includes a comparator 31 that detects overcurrent, a comparator 32 that detects overheat, and a diode D6 that generates a reference voltage for overheat detection. The comparator 31 outputs an overcurrent detection signal O_SC that goes low when an overcurrent is detected. The comparator 32 outputs an overheat detection signal O_TSD that goes low when overheat is detected. The detailed configuration of the overcurrent and overheat detection circuit 11 will be described later.

[0039] The minute current source 12 uses the electromotive force VCC generated by the first photodiode array 5 in the electromotive force generating circuit 2 as a power supply voltage to generate a minute current and supply it to the overcurrent / overheating detection circuit 11. The minute current generated by the minute current source 12 is, for example, about several tens of nA. The detailed configuration of the minute current source 12 will be described later.

[0040] The protection control circuit 13 forcibly turns off the first switching transistor Q1 and the second switching transistor Q2 when at least one of an overcurrent or overheating is detected in the protection circuit 3. The protection control circuit 13 includes an AND gate G1, a resistor R21, a capacitor C4, an OR gate G2, an RS flip-flop (hereinafter referred to as RS-F / F) 17, a resistor R22, an NMOS transistor Q5, a PMOS transistor Q6, an NMOS transistor Q7, a resistor R23, a capacitor C5, inverters IV1 to IV5, and an NMOS transistor Q8.

[0041] The AND gate G1 outputs a logical AND signal of the overcurrent detection signal O_SC and the overheat detection signal O_TSD. The output of the AND gate G1 goes low when at least one of an overcurrent and an overheat is detected.

[0042] The output signal of the AND gate G1 is input to one input terminal of the OR gate G2. One end of the resistor R21 and one end of the capacitor C4 are connected to the other input terminal of the OR gate G2. The other end of the resistor R21 is connected to the output node of the AND gate G1, and the other end of the capacitor C4 is connected to the ground node GND_S. As a result, the output of the OR gate G2 transitions to a low level after waiting for a time period corresponding to the time constant determined by the resistance value of the resistor R21 and the capacitance of the capacitor C4 after the output signal of the AND gate G1 transitions from high to low. In this way, the OR gate G2, the resistor R21, and the capacitor C4 function as a timer that waits for a time period corresponding to the time constant determined by the resistance value of the resistor R21 and the capacitance of the capacitor C4.

[0043] The output signal of the OR gate G2 is input to the set (S) terminal of the RS-F / F 17. A reset signal RST, which will be described later, is input to the reset (RST) terminal of the RS-F / F 17.

[0044] When the S terminal of the RS-F / F 17 goes low, it enters the set state and the Q terminal goes high. This turns on the NMOS transistor Q5, and the drain of the NMOS transistor Q5 goes to ground. This turns on the PMOS transistor Q6, and the drain of the PMOS transistor Q6 goes to high voltage.

[0045] One end of resistor R23 is connected to the drain of PMOS transistor Q6, and capacitor C5 is connected between the other end of resistor R23 and the ground node. When the voltage level of the drain of transistor Q6 changes, the signal logic of each output node of inverters IV1, IV2, and IV4 changes with a delay corresponding to a time constant determined by the resistance value of resistor R23 and the capacitance of capacitor C5.

[0046] For example, when the drain of transistor Q6 goes high, after a short delay, the signal logic of the output nodes of inverters IV4 and IV5 changes, and the gate signal Gshunt of NMOS transistor Q8 goes high. This turns on NMOS transistor Q8, pulling down the voltage level of the GATE wiring. This forces first switching transistor Q1 and second switching transistor Q2 to turn off.

[0047] At this time, the output of inverter IV3 becomes high level and the output of inverter IV1 becomes low level, turning off both the NMOS transistor Q9 and PMOS transistor Q10 that make up analog switch 14. When analog switch 14 is turned off, even if the GATE1 signal output from electromotive force generating circuit 2 is high level, the GATE wiring connected to the gate of first switching transistor Q1 and the gate of second switching transistor Q2 no longer becomes high level, and it is possible to reliably turn off first switching transistor Q1 and second switching transistor Q2.

[0048] A diode D7 may be connected instead of the analog switch 14. The anode of the diode D7 is connected to the GATE line, and the cathode of the diode D7 is connected to the GATE1 line. The diode D7 functions as a blocking diode and prevents the voltage of the GATE1 line from being supplied to the gate of the first switching transistor Q1 and the gate of the second switching transistor Q2. In this way, the analog switch 14 or the diode D7 functions as a voltage blocking circuit that blocks the GATE line (first line) connecting the output node of the protection circuit 3 with the gate of the first switching transistor Q1 and the gate of the second switching transistor Q2 from the GATE1 line (second line) that supplies electromotive force when the protection circuit 3 forcibly turns off the first switching transistor Q1 and the second switching transistor Q2.

[0049] The low-voltage holding circuit 15 includes a PNP transistor Q11 and three capacitors C6, C7, and C8 connected in parallel between the emitter and collector of the PNP transistor Q11. The emitter of the PNP transistor Q11 is supplied with a fourth reference voltage VCT generated by a minute current source 12, which will be described later.

[0050] A third reference voltage REF_285 having a predetermined voltage level is input to the base of the PNP transistor Q11. Based on the third reference voltage REF_285 input to the base, the PNP transistor Q11 maintains a fourth reference voltage VCT between the emitter and collector, the fourth reference voltage VCT having a voltage level lower than the voltage level of the third reference voltage REF_285.

[0051] The internal power supply voltage holding circuit 16 has a capacitor C21 that holds the internal power supply voltage VCC_int generated by the minute current source 12.

[0052] 5A and 5B are circuit diagrams showing an example of a specific circuit configuration of the minute current source 12 of Fig. 4. All of the circuits in Fig. 5A and 5B constitute the minute current source 12. As shown in Fig. 5A and 5B, the minute current source 12 has an internal power supply voltage generation circuit 21, a first reference voltage generation circuit 22, a second reference voltage generation circuit 23, a third reference voltage generation circuit 24, and a minute current generation circuit 25.

[0053] The internal power supply voltage generating circuit 21 has a resistor R31, Zener diodes D8, D9, and D10, a diode-connected depletion-type PMOS transistor Q21, an NPN transistor Q22, a resistor R32, an NPN transistor Q23, resistors R33 and R34, and Zener diodes D11 and D12.

[0054] One end of resistor R31 is connected to the VCC line. Three Zener diodes D8, D9, and D10 are connected in series between the other end of resistor R31 and the ground node. The cathodes of these Zener diodes D8, D9, and D10 are connected to the other end of resistor R31, and the anodes are connected to the ground node GND.

[0055] The diode-connected PMOS transistor Q21 functions as a blocking diode D13. This blocking diode D13 is provided to separate the electromotive force VCC from the internal power supply voltage VCC_int, with the anode of the blocking diode D13 located on the wiring side of the electromotive force VCC and the cathode located on the wiring side of the internal power supply voltage VCC_int.

[0056] The collector of NPN transistor Q22 is connected to the cathode of blocking diode D13. Resistor R32 is connected between the base and collector of NMOS transistor Q22. The base of NPN transistor Q22 is connected to the collector of NPN transistor Q23. Resistor R33 is connected between the collector and base of NPN transistor Q23, and resistor R34 is connected between the base and emitter of NPN transistor Q23. Two Zener diodes D11 and D12 are connected in series, facing in opposite directions, between the emitter of NPN transistor Q23 and ground node GND.

[0057] The first reference voltage generating circuit 22 includes capacitors C11 and C12, PNP transistors Q24 to Q27, resistors R35 to R39, and an NMOS transistor Q28. The emitter of the PNP transistor Q24 is connected to the VCC_int node. The collector of the PNP transistor Q24 is connected to the emitter of the PNP transistor Q25. The collector and base of the PNP transistor Q25 are short-circuited, and a capacitor C12 is connected between this short-circuit node and the VCC_int node. Four resistors R35 to R38 are connected in series between the collector of the PNP transistor Q25 and the ground node.

[0058] A resistor R39 is connected between the emitter of PNP transistor Q26 and the VCC_int node. The collector of PNP transistor Q26 and the emitter of PNP transistor Q27 are connected, and this connection node is connected to the base of PNP transistor Q24. The base of PNP transistor Q26, the collector of PNP transistor Q24, and the emitter of PNP transistor Q25 are commonly connected. The collector of PNP transistor Q27 is connected to the drain of NMOS transistor Q28. The source of NMOS transistor Q28 is connected to the ground node GND.

[0059] A third reference voltage REF_285 is output between resistors R35 and R36. A capacitor C11 is connected between the node that outputs the third reference voltage REF_285 and the ground node GND. A first reference voltage SC_REF is output between resistors R36 and R37.

[0060] The second reference voltage generating circuit 23 includes an NMOS transistor Q31, two PMOS transistors Q32 and Q33, a resistor R41, an NMOS transistor Q34, two PMOS transistors Q35 and Q36, two NMOS transistors Q37 and Q38, two PMOS transistors Q39 and Q40, an NMOS transistor Q41, resistors R41 to R47, and capacitors C13 to C15.

[0061] The gate and drain of the NMOS transistor Q28 are shorted, and the gate of the NMOS transistor Q28 is connected to the gate of the NMOS transistor Q31. In this way, the NMOS transistor Q31 and the NMOS transistor Q28 form a current mirror circuit.

[0062] The drain of the NMOS transistor Q31 is connected to the drain and gate of the PMOS transistor Q32. The source of the PMOS transistor Q32 is connected to the VCC_int node. The gate of the PMOS transistor Q32 is connected to the gate of the PMOS transistor Q33, and the PMOS transistors Q32 and Q33 form a current mirror circuit. The source of the PMOS transistor Q33 is connected to the VCC_int node. A resistor R41 is connected between the drain of the PMOS transistor Q33 and the ground node.

[0063] The drain of the NMOS transistor Q34 is connected to the VCC_int node, and the source and gate of the NMOS transistor Q34 are shorted.

[0064] The source of the PMOS transistor Q35 is connected to the VCC_int node, and the gate is connected to the gate and drain of the PMOS transistor Q36. In this way, the PMOS transistor Q35 and the PMOS transistor Q36 form a current mirror circuit.

[0065] The drain of PMOS transistor Q35 is connected to the drain of NMOS transistor Q37. The drain of PMOS transistor Q36 is connected to the drain of NMOS transistor Q38. The sources of these NMOS transistors Q37 and Q38 are connected together. In addition, a resistor R42 and a capacitor C13 are connected in series between the drains of these NMOS transistors Q37 and Q38.

[0066] The source of the PMOS transistor Q39 is connected to the VCC_int node. The gate of the PMOS transistor Q39 is connected to the drains of the transistors Q35 and Q37. The drain of the PMOS transistor Q39 is connected to the drain of the NMOS transistor Q41. The gate and source of the NMOS transistor Q41 are shorted.

[0067] The source of NMOS transistor Q37, the source of NMOS transistor Q38, and the gate and source of NMOS transistor Q41 are commonly connected, and two resistors R43 and R44 are connected in series between this connection node and the ground node. Resistor R45 is connected between the drain of NMOS transistor Q41 and the ground node GND.

[0068] The source of the PMOS transistor Q40 is connected to the VCC_int node, and the gate of the PMOS transistor Q40 is connected to the gate of the PMOS transistor Q39 and the drains of the transistors Q35 and Q37.

[0069] Two resistors R46 and R47 are connected in series between the drain of the PMOS transistor Q40 and the ground node GND. A capacitor C15 is connected in parallel to the resistor R47. A capacitor C14 is connected between the connection node of the drain of the PMOS transistor Q40 and the resistor R46 and the ground node GND.

[0070] A first reference voltage SC_REF is output from the connection node between the drain of the PMOS transistor Q40 and the resistor R46, and a second reference voltage TSD_REF is output from the connection node between the resistors R46 and R47.

[0071] The third reference voltage generating circuit 24 shown in FIG. 5B includes six PMOS transistors Q51 to Q56, an NMOS transistor Q57, and a PNP transistor Q58.

[0072] The gate and drain of the PMOS transistor Q53 are shorted, and the gates of the six PMOS transistors Q51 to Q56 are connected to this shorted node, so that the six PMOS transistors Q51 to Q56 form a current mirror circuit.

[0073] The source of the PMOS transistor Q51 is connected to the VCC_int node, and the drain of the PMOS transistor Q51 is connected to the source of the PMOS transistor Q52, whose drain is connected to the source of the PMOS transistor Q53.

[0074] The source of the PMOS transistor Q54 is connected to the VCC_int node, and the drain of the PMOS transistor Q54 is connected to the source of the PMOS transistor Q55, whose drain is connected to the source of the PMOS transistor Q56.

[0075] The gate and drain of the PMOS transistor Q53 are connected to the drain of the NMOS transistor Q57, whose source is connected to the ground node.

[0076] The drain of the PMOS transistor Q56 is connected to the emitter and base of a PNP transistor Q58, the collector of which is connected to the ground node, and the fourth reference voltage VCT is output from the drain of the PMOS transistor Q56.

[0077] The minute current generating circuit 25 has a total of 14 PMOS transistors Q61 to Q74 that form a current mirror circuit, and an NMOS transistor Q75.

[0078] The source of PMOS transistor Q61 is connected to the VCC_int node, its gate and drain are shorted, and the drain of NMOS transistor Q75 is connected to this shorted node. The source of NMOS transistor Q75 is connected to the ground node GND. The gate of NMOS transistor Q75 is connected to the gate of NMOS transistor Q57.

[0079] The sources of the thirteen PMOS transistors Q62 to Q74 are connected to the VCC_int node, and the gates are connected together, with the gate of the PMOS transistor Q61 also connected to this connection node.

[0080] A minute current is output from each drain of the thirteen PMOS transistors Q62 to Q74. Twelve of the thirteen minute currents are supplied to the overcurrent and overheat detection circuit 11, and the remaining one is supplied to the protection circuit 3.

[0081] 6 is a circuit diagram showing an example of a specific circuit configuration of the overcurrent and overheat detection circuit 11 of FIG. 4. As shown in FIG. 6, the overcurrent and overheat detection circuit 11 has a first comparator 31a and a second comparator 31b that constitute a comparator 31 for overcurrent detection, and a third comparator 32 for overheat detection. The first comparator 31a compares the voltage level of the first overcurrent detection signal VSEN1 with the voltage level of the first reference voltage SC_REF, and outputs an error signal indicative of the comparison result. The first comparator 31a outputs a low-level error signal when the voltage level of the first overcurrent detection signal VSEN1 is higher than the voltage level of the first reference voltage.

[0082] The second comparator 31b compares the voltage level of the second overcurrent detection signal VSEN2 with the voltage level of the first reference voltage, and outputs an error signal indicating the comparison result. When the voltage level of the second overcurrent detection signal VSEN2 is higher than the voltage level of the first reference voltage, the second comparator 31b outputs a low-level error signal.

[0083] A first wiring that transmits the error signal output from the first comparator 31a and a second wiring that transmits the error signal output from the second comparator 31b are wired-ORed to generate an overcurrent monitor signal O-SC.

[0084] Since the forward voltage of a typical diode decreases as the temperature increases, overheating can be determined by comparing the forward voltage of the diode with a predetermined reference voltage. Therefore, the third comparator 32 compares the forward voltage of diode D6 with a fifth reference voltage and outputs an error signal indicating the comparison result. When the forward voltage of the diode falls below the fifth reference voltage due to overheating, the third comparator 32 outputs a low-level overheat detection signal O-TSD.

[0085] The first comparator 31a has resistors R51 and R52, a Zener diode D21, four PNP transistors Q81 to Q84, two NPN transistors Q85 and Q86, a capacitor C21, an NPN transistor Q87, a capacitor C21, and a resistor R53.

[0086] The first overcurrent detection signal VSEN1 is input to the base of a PNP transistor Q81 via a resistor R51. A resistor R52 and a Zener diode D21 are connected in parallel between the base of the PNP transistor Q81 and the ground node.

[0087] The emitter of PNP transistor Q81 is supplied with a minute current from minute current source 12. The emitter of PNP transistor Q81 is connected to the base of PNP transistor Q82. The minute current from minute current source 12 is supplied to the emitters of PNP transistor Q82 and PNP transistor Q83.

[0088] The collector of PNP transistor Q82 is connected to the collector and base of NPN transistor Q85. The collector of PNP transistor Q83 is connected to the collector of NPN transistor Q86. The bases of NPN transistor Q85 and NPN transistor Q86 are connected to each other, forming a current mirror circuit.

[0089] The base of PNP transistor Q83 and the emitter of PNP transistor Q84 are supplied with a minute current from minute current source 12. The collector of PNP transistor Q84 is connected to the ground node. The first reference voltage SC_REF is supplied to the base of PNP transistor Q84 via resistor R53.

[0090] The base of NPN transistor Q87 is connected to the collector of PNP transistor Q83 and the collector of NPN transistor Q86, the collector of which outputs an overcurrent monitor signal.

[0091] The second comparator 31b has resistors R54 and R55, a Zener diode D22, four PNP transistors Q88 to Q91, two NPN transistors Q92 and Q93, a capacitor C22, an NPN transistor Q94, and a resistor R56.

[0092] The second overcurrent detection signal VSEN2 is input to the base of a PNP transistor Q88 via a resistor R54. A resistor R55 and a Zener diode D22 are connected in parallel between the base of the PNP transistor Q88 and the ground node.

[0093] The emitter of PNP transistor Q88 is supplied with a minute current from minute current source 12. The emitter of PNP transistor Q88 is connected to the base of PNP transistor Q89. The minute current from minute current source 12 is supplied to the emitters of PNP transistor Q89 and PNP transistor Q90.

[0094] The collector of PNP transistor Q89 is connected to the collector and base of NPN transistor Q92. The collector of PNP transistor Q90 is connected to the collector of NPN transistor Q93. The bases of NPN transistor Q92 and NPN transistor Q93 are connected to each other, forming a current mirror circuit.

[0095] The base of PNP transistor Q90 and the emitter of PNP transistor Q91 are supplied with a minute current from minute current source 12. The collector of PNP transistor Q91 is connected to the ground node. The first reference voltage SC_REF is supplied to the base of PNP transistor Q91 via resistor R56.

[0096] The collector of the PNP transistor Q90 and the collector of the NPN transistor Q93 are connected to the base of the NPN transistor Q94, and the overcurrent monitor signal O_SC is output from the collector of the NPN transistor Q94.

[0097] The third comparator 32 has a diode-connected NPN transistor Q95, four PNP transistors Q96 to Q99, two NPN transistors Q100 and Q101, a capacitor C23, a resistor R58, and an NPN transistor Q102.

[0098] A minute current is supplied from minute current source 12 to the base and collector (anode of diode D6) of diode-connected NPN transistor Q95. The emitter of NPN transistor Q95 is connected to the ground node. The forward voltage of diode D6, which is formed by NPN transistor Q95, is input to the base of PNP transistor Q96 via resistor R57. A second reference voltage TSD_REF is input to the base of PNP transistor Q99 via resistor R58. The emitter of PNP transistor Q96 is connected to the base of PNP transistor Q97, and the emitter of PNP transistor Q99 is connected to the base of PNP transistor Q98. The emitters of PNP transistors Q97 and Q98 are connected together, and a minute current is supplied from minute current source 12.

[0099] The collector of PNP transistor Q97 is connected to the collector of NPN transistor Q100, and the collector of PNP transistor Q98 is connected to the collector and base of NPN transistor Q101. These NPN transistors Q100 and Q101 form a current mirror circuit.

[0100] A capacitor C23 is connected between the base of the PNP transistor Q99 and the ground node. The collector of the PNP transistor Q97 and the collector of the NPN transistor Q100 are connected to the base of the NPN transistor Q102. A minute current is supplied to the collector of the NPN transistor Q102 from the minute current source 12. The emitter of the NPN transistor Q102 is connected to the ground node. The overheat monitor signal O_TSD is output from the collector of the NPN transistor Q102.

[0101] 7 is a circuit diagram showing an example of a specific circuit configuration of the RS-F / F 17 in the protection control circuit 13 of FIG. 4. As shown in FIG. 7, the RS-F / F 17 has a three-input NAND gate G3, a two-input NAND gate G4, and an inverter IV10. VDD, a set signal S, and the output signal of the two-input NAND gate G4 are input to the three-input NAND gate G3, and the three-input NAND gate G3 outputs a NAND signal of these signals. The output signal of the three-input NAND gate G3 is output from the Q terminal, and a signal obtained by inverting this output signal by the inverter IV10 is output from the / Q terminal.

[0102] The two-input NAND gate G4 receives the output signal of the three-input NAND gate G3 and the reset signal R, and outputs a NAND signal of these signals. The output signal of the two-input NAND gate G4 is input to the three-input NAND gate G3.

[0103] 8 is a diagram showing the truth table of the RS-F / F 17. When the set signal S goes low, the Q terminal goes high, and when the reset signal R goes low, the / Q terminal goes high.

[0104] As described above, in this embodiment, the first switching transistor Q1 and the second switching transistor Q2 can be protected from overcurrent and overheat by operating the protection circuit 3 using the electromotive force generated by receiving light. According to this embodiment, a power supply circuit is not required to operate the protection circuit 3, which allows the semiconductor switch 1 to be miniaturized and the range of application of the semiconductor switch 1 according to this embodiment to be expanded.

[0105] Furthermore, in this embodiment, overcurrent is detected based on the minute current flowing in the body in response to the current flowing between the drain and source of the first switching transistor Q1 and the second switching transistor Q2, and overheating is detected based on changes in the forward voltage of the diode, so that overcurrent and overheating can be detected accurately with low power consumption.

[0106] Furthermore, after at least one of an overcurrent and overheating is detected, the first switching transistor Q1 and the second switching transistor Q2 wait for a period of time corresponding to a time constant determined by the resistance value of resistor R21 and the capacitance of capacitor C4, and then turn off. This makes it possible to drive the timer made up of an analog circuit using a small amount of power, and to protect the first switching transistor Q1 and the second switching transistor Q2 with a small-scale circuit configuration and low power consumption.

[0107] [Note] [Item 1] an electromotive force generating circuit that generates an electromotive force by receiving light; a first switching transistor connected between the first output terminal and a reference voltage node, for driving a load when the electromotive force is generated; a second switching transistor connected between a second output terminal and the reference voltage node, for driving a load when the electromotive force is generated; a protection circuit that uses the electromotive force as a power supply voltage to protect the first switching transistor and the second switching transistor from overcurrent and overheat. Solid state switch. [Item 2] a first overcurrent detection circuit that outputs a first overcurrent detection signal according to a current flowing between the drain and source of the first switching transistor; a second overcurrent detection circuit that outputs a second overcurrent detection signal according to a current flowing between the drain and source of the second switching transistor, the protection circuit determines whether to turn off the first switching transistor and the second switching transistor based on signal levels of the first overcurrent detection signal and the second overcurrent detection signal. Item 1. The semiconductor switch according to item 1. [Item 3] the first overcurrent detection circuit has a first resistor connected between a body and a source of the first switching transistor, and outputs the first overcurrent detection signal having a signal level corresponding to a voltage across the first resistor; the second overcurrent detection circuit has a second resistor connected between the body and the source of the second switching transistor, and outputs the second overcurrent detection signal at a signal level corresponding to a voltage across the second resistor. Item 2. The semiconductor switch according to item 2. [Item 4] the protection circuit has an overcurrent determination circuit, The overcurrent determination circuit a first comparator that compares the signal level of the first overcurrent detection signal with a predetermined first reference voltage; a second comparator that compares the signal level of the second overcurrent detection signal with the first reference voltage; Item 2 or 3. The semiconductor switch according to item 2 or 3. [Item 5] a first wiring connected to an output node of the first comparator; a second wiring connected to the output node of the second comparator; a connection node between the first wiring and the second wiring that generates an overcurrent detection signal by wired-ORing the output signal of the first comparator and the output signal of the second comparator; Item 4. The semiconductor switch according to item 4. [Item 6] the protection circuit includes an overheat detection circuit; The overheat detection circuit A diode for detecting overheating; a third comparator that compares the forward voltage of the diode with a second reference voltage; Item 4. The semiconductor switch according to item 4. [Item 7] the protection circuit has a minute current source that generates a minute current using the electromotive force as a power supply voltage, the first comparator, the second comparator, and the third comparator are each supplied with a minute current from the minute current source; Item 7. The semiconductor switch according to item 6. [Item 8] the protection circuit includes a protection control circuit that forcibly turns off the first switching transistor and the second switching transistor when at least one of an overcurrent and an overheat is detected by the first comparator, the second comparator, and the third comparator. Item 8. The semiconductor switch according to item 6 or 7. [Item 9] the protection circuit includes a timer that waits for a predetermined period of time after at least one of an overcurrent and an overheat is detected by the first comparator, the second comparator, and the third comparator; the protection control circuit forcibly turns off the first switching transistor and the second switching transistor after waiting for the predetermined period of time by the timer. Item 9. The semiconductor switch according to item 8. [Item 10] the timer includes a resistor, a capacitor, and a logic gate circuit; the logic gate circuit performs a logic operation between a detection signal that becomes a predetermined signal logic when at least one of an overcurrent and overheat is detected and a delay signal that delays the timing at which the detection signal becomes the predetermined signal logic, the protection circuit forcibly turns off the first switching transistor and the second switching transistor when the signal logic of the output signal of the logic gate circuit changes. Item 9. The semiconductor switch according to item 9. [Item 11] The predetermined period is adjusted by a time constant determined by the resistance value of the resistor and the capacitance of the capacitor. Item 11. The semiconductor switch according to item 10. [Item 12] a voltage cutoff circuit that cuts off a first wiring connecting an output node of the protection circuit with a gate of the first switching transistor and a gate of the second switching transistor from a second wiring that supplies the electromotive force when the protection circuit forcibly turns off the first switching transistor and the second switching transistor; Item 12. The semiconductor switch according to any one of items 1 to 11. [Item 13] the voltage blocking circuit includes a diode having an anode connected to the gate of the first switching transistor and the gate of the second switching transistor, and a cathode connected to the output node of the electromotive force generating circuit. Item 13. The semiconductor switch according to item 12. [Item 14] the voltage cutoff circuit has an analog switch that switches between connecting and disconnecting the gate of the first switching transistor and the gate of the second switching transistor to and from the output node of the electromotive force generating circuit. Item 13. The semiconductor switch according to item 12. [Item 15] The electromotive force generating circuit comprises: A light-emitting element; a first photodiode row having two or more photodiodes connected in series, which receives light emitted by the light emitting element and generates an electromotive force; a second photodiode array having two or more photodiodes connected in series, which receives light emitted by the light emitting element and generates an electromotive force; a third photodiode row having two or more photodiodes connected in series, which receives light emitted by the light emitting element and generates an electromotive force; a voltage control circuit that controls voltages of wirings connected to the gates of the first switching transistor and the second switching transistor based on an electromotive force generated by light received by the second photodiode row and an electromotive force generated by light received by the third photodiode row, The electromotive force of the first photodiode row is used as a power supply voltage for the protection circuit. 15. A semiconductor switch according to any one of claims 1 to 14. [Item 16] a connection direction of the two or more photodiodes in the first photodiode row and the second photodiode row is opposite to a connection direction of the two or more photodiodes in the third photodiode row; Item 16. The semiconductor switch according to item 15. [Item 17] the voltage control circuit turns on both the first switching transistor and the second switching transistor when an electromotive force caused by light received by the second photodiode row exceeds a first threshold voltage, and turns off both the first switching transistor and the second switching transistor when an electromotive force caused by light received by the third photodiode row becomes equal to or less than a second threshold voltage. Item 17. The semiconductor switch according to item 16. [Item 18] a semiconductor chip incorporating the electromotive force generating circuit and the protection circuit; Item 18. The semiconductor switch according to any one of items 1 to 17.

[0108] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0109] 1 semiconductor switch, 2 electromotive force generation circuit, 2a light-emitting element, 3 protection circuit, 4 current generation circuit, 4a light-emitting circuit, 4b light-receiving circuit, 4c first current generation section, 4d second current generation section, 4e third current generation section, 5 first photodiode row, 6 second photodiode row, 7 third photodiode row, 8 off control circuit, 11 overcurrent / overheat detection circuit, 12 minute current source, 13 protection control circuit, 14 analog switch, 15 low-voltage holding circuit, 16 internal power supply voltage holding circuit, 17 RS-F / F, 21 internal power supply voltage generation circuit, 22 first reference voltage generation circuit, 23 second reference voltage generation circuit, 24 third reference voltage generation circuit, 25 minute current generation circuit, 31 comparator, 31a first comparator, 31b second comparator, 32 third comparator

Claims

1. an electromotive force generating circuit that generates an electromotive force by receiving light; a first switching transistor connected between the first output terminal and a reference voltage node, for driving a load when the electromotive force is generated; a second switching transistor connected between a second output terminal and the reference voltage node, for driving a load when the electromotive force is generated; a protection circuit that uses the electromotive force as a power supply voltage to protect the first switching transistor and the second switching transistor from overcurrent and overheat. Solid state switch.

2. a first overcurrent detection circuit that outputs a first overcurrent detection signal corresponding to a current flowing between the drain and source of the first switching transistor; a second overcurrent detection circuit that outputs a second overcurrent detection signal according to a current flowing between the drain and source of the second switching transistor, the protection circuit determines whether to turn off the first switching transistor and the second switching transistor based on signal levels of the first overcurrent detection signal and the second overcurrent detection signal. The semiconductor switch according to claim 1 .

3. the first overcurrent detection circuit has a first resistor connected between a body and a source of the first switching transistor, and outputs the first overcurrent detection signal having a signal level corresponding to a voltage across the first resistor; the second overcurrent detection circuit has a second resistor connected between the body and the source of the second switching transistor, and outputs the second overcurrent detection signal having a signal level corresponding to a voltage across the second resistor. The semiconductor switch according to claim 2 .

4. the protection circuit has an overcurrent determination circuit, The overcurrent determination circuit a first comparator that compares a signal level of the first overcurrent detection signal with a predetermined first reference voltage; a second comparator that compares the signal level of the second overcurrent detection signal with the first reference voltage; The semiconductor switch according to claim 2 .

5. a first wiring connected to an output node of the first comparator; a second wiring connected to the output node of the second comparator; a connection node between the first wiring and the second wiring generates an overcurrent detection signal by wired-ORing the output signal of the first comparator and the output signal of the second comparator; 5. The semiconductor switch according to claim 4.

6. the protection circuit includes an overheat detection circuit; The overheat detection circuit A diode for detecting overheating; a third comparator that compares the forward voltage of the diode with a second reference voltage; 5. The semiconductor switch according to claim 4.

7. the protection circuit has a minute current source that generates a minute current using the electromotive force as a power supply voltage, the first comparator, the second comparator, and the third comparator are each supplied with a minute current from the minute current source; 7. The semiconductor switch according to claim 6.

8. the protection circuit includes a protection control circuit that forcibly turns off the first switching transistor and the second switching transistor when at least one of an overcurrent and an overheat is detected by the first comparator, the second comparator, and the third comparator.

7. The semiconductor switch according to claim 6.

9. the protection circuit includes a timer that waits for a predetermined period of time after at least one of an overcurrent and an overheat is detected by the first comparator, the second comparator, and the third comparator; the protection control circuit forcibly turns off the first switching transistor and the second switching transistor after waiting for the predetermined period of time using the timer; 9. The semiconductor switch according to claim 8.

10. The electromotive force generating circuit comprises: A light-emitting element; a first photodiode array having two or more photodiodes connected in series, which receives light emitted by the light emitting element and generates an electromotive force; a second photodiode array having two or more photodiodes connected in series, which receives light emitted by the light emitting element and generates an electromotive force; a third photodiode row having two or more photodiodes connected in series, which receives light emitted by the light emitting element and generates an electromotive force; a voltage control circuit that controls voltages of wirings connected to the gates of the first switching transistor and the second switching transistor based on an electromotive force generated by light received by the second photodiode row and an electromotive force generated by light received by the third photodiode row, the electromotive force of the first photodiode row is used as a power supply voltage for the protection circuit; 10. A semiconductor switch according to any one of claims 1 to 9.

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