Semiconductor device

Abstract

To solve a problem in which there is room for further study regarding the suppression of a leakage current in a semiconductor device.SOLUTION: A semiconductor device 10 includes a drain region 13, a body region 15, an N+ type source region 16, an N+ type drain contact region 18, a P+ type region 19, a drain electrode 22, a source electrode 23, a gate electrode 21, a charging film f1, and a resistive layer 14, Rnw. The resistive layer 14, Rnw is formed in the drain region 13, at least between each P+ type region 19 and the body region 15, and has a lower impurity concentration than the N+ type drain contact region 18.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The invention disclosed herein relates to a semiconductor device. [Background technology]

[0002] Conventionally, there is an LDMOSFET (semiconductor device) configured to operate as a thyristor.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-10127

[0005] [overview] The semiconductor device disclosed in Patent Document 1 leaves room for further consideration in terms of suppressing leakage current.

[0006] The semiconductor device disclosed in this specification includes a drain region, a body region, an N+ type source region, an N+ type drain contact region, a P+ type region, a drain electrode, a source electrode, a gate electrode, a charging film, and a resistive layer. The drain region is an N-type semiconductor layer formed on a semiconductor substrate. The body region is a P-type semiconductor region formed in the drain region. The N+ type source region is formed in the body region. The N+ type drain contact region is formed on the surface of the drain region. A plurality of P+ type regions are formed in the drain region, alternating with the N+ type drain contact regions along the N+ type source region, and are electrically connected to have the same potential as the N+ type drain contact region. The drain electrode is configured to contact the N+ type drain contact region. The source electrode is configured to contact the N+ type source region. The gate electrode is configured to contact the surface of the body region via a gate insulating film. The charging film covers the surface of at least the region between each P+ type region and the body region, among regions other than the drain electrode, source electrode, and gate electrode. A resistive layer is formed in the drain region between at least each P+ type region and the body region, and has a lower impurity concentration than the N+ type drain contact region. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing the structure of a semiconductor device 10 of the comparative example. [Figure 2] FIG. 2 is a cross-sectional view showing a cross section of the semiconductor device 10 taken along the AA cross-sectional line shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view showing a modification of the semiconductor device 10 of the comparative example. [Figure 4] FIG. 4 is a diagram showing a configuration of a semiconductor device 1 according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a cross-sectional view showing a cross section of the semiconductor device 1 taken along the line BB shown in FIG. [Figure 6]FIG. 6 is a cross-sectional view showing a modified example of the semiconductor device 1 according to the embodiment of the present disclosure.

[0008] [Detailed explanation] <Regarding the semiconductor device 10 of the comparative example> First, the semiconductor device 10 will be described as a comparative example to the semiconductor device 1 of the present disclosure. Next, the problems of the comparative example will be described, followed by a description of the semiconductor device 10 of the present disclosure. Note that the semiconductor device 10 of the comparative example and the semiconductor device 1 of the present disclosure have common configurations. Therefore, in the following description of the semiconductor device 1 of the present disclosure, parts common to the semiconductor device 10 of the comparative example will be assigned the same reference numerals as those of the semiconductor device 10 and description thereof will be omitted, and only parts different from the semiconductor device 10 will be described.

[0009] Fig. 1 is a plan view showing the structure of a semiconductor device 10 of a comparative example. Fig. 2 is a cross-sectional view showing a cut surface of the semiconductor device 10 taken along the AA cross-sectional line shown in Fig. 1.

[0010] The semiconductor device 10 is an N-channel LDMOSFET (Laterally Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor). As shown in Figures 1 and 2, the semiconductor device 10 includes a semiconductor substrate 11, a drain region 13, an N-well 14, a body region 15, an N+ type source region 16, a P+ type region 17, an N+ type drain contact region 18, a P+ type region 19, and a channel region 20. The semiconductor device 10 also includes a drain electrode 22, a source electrode 23, a gate electrode 21, and a charging film f1.

[0011] The drain region 13 is formed on the semiconductor substrate 11 via an N+ type underlayer film 12. The drain region 13 is formed by epitaxially growing an N type semiconductor layer. The N-well 14 is formed by diffusing N type impurities into the drain region 13. The body region 15 is formed by diffusing P type impurities.

[0012] The N-well 14 and the body region 15 are located on the surface of the drain region 13. A pair of N-wells 14 are arranged, one on each side of the body region 15 in the direction along the semiconductor substrate 11 (the direction of the arrows xx' shown in FIGS. 1 and 2).

[0013] The direction along the semiconductor substrate 11 in which the N-well 14 and the body region 15 are aligned (the direction parallel to the arrow xx' shown in FIGS. 1 and 2) will be simply referred to as the "first direction" hereinafter. The direction along the semiconductor substrate 11 and perpendicular to the first direction (the direction parallel to the arrow yy' shown in FIG. 1) will be simply referred to as the "second direction." The direction perpendicular to the first and second directions (the direction parallel to the arrow zz' shown in FIG. 2) will be simply referred to as the "third direction."

[0014] The N+ type source regions 16 and the P+ type regions 17 are located on the surface of the body region 15 (more specifically, on the end surface of the body region 15 opposite to the semiconductor substrate 11 in the third direction). The N+ type source regions 16 and the P+ type regions 17 are alternately arranged along the second direction. The N+ type source regions 16 and the P+ type regions 17 are in contact with each other.

[0015] The N+ type drain contact region 18 has a higher N-type impurity concentration than the N-well 14. The N+ type drain contact region 18 and the P+ type region 19 are located on the surface of the N-well 14 (more specifically, on the end face of the N-well 14 on the side opposite to the semiconductor substrate 11 in the third direction).

[0016] A plurality of notches 30 are formed in the N-well 14 and the N+ type drain contact region 18. The notches 30 are recessed along the third direction from the surfaces of the N-well 14 and the N+ type drain contact region 18 (more specifically, from the end faces of the N-well 14 and the N+ type drain contact region 18 on the side opposite the semiconductor substrate 11 with respect to the third direction) toward the semiconductor substrate 11. The notches 30 are arranged at equal intervals along the second direction.

[0017] The P+ type regions 19 are embedded in each of the notches 30. The N+ type drain contact regions 18 and the P+ type regions 19 are arranged alternately in the second direction. The N+ type drain contact regions 18 and the P+ type regions 19 are in contact with each other.

[0018] The end of the P+ type region 19 on the body region 15 side is located farther from the body region 15 in the first direction than the end of the N+ type drain contact region 18 on the body region 15 side.

[0019] The channel region 20 is formed between the N+ type source region 16 and the N- well 14 in the first direction.

[0020] The gate electrode 21 is in contact with the surfaces (end faces opposite to the semiconductor substrate 11 in the third direction) of the N+ type source region 16, the P+ type region 17, and the channel region 20 via a gate insulating film (=oxide film). The gate electrode 21 extends from a position inside the N+ type source region 16 relative to the edge of the N+ type source region 16 to a position inside the channel region 20 relative to the edge of the channel region 20 in the first direction.

[0021] When a voltage is applied to the gate electrode 21, the channel region 20 expands in the first direction, and the drain and source of the semiconductor device 10 become conductive.

[0022] The drain electrode 22 is in contact with the N+ type drain contact region 18. The drain electrode 22, the N+ type drain contact region 18, and the P+ type region 19 are all at the same potential.

[0023] The source electrode 23 is in contact with the surfaces of both the N+ type source region 16 and the P+ type region 17 (end faces on the opposite side from the semiconductor substrate 11 in the third direction). The source electrode 23 is also in contact with the gate electrode 21. The source electrode 23, the N+ type source region 16, the P+ type region 17, and the gate electrode 21 are at the same potential. The source electrode 23 is connected to the ground terminal GND.

[0024] A parasitic NPN transistor N1 and a parasitic transistor PNP1 are configured inside the semiconductor device 10. The parasitic NPN transistor N1 is configured with an N+ type source region 16 which is an N-type semiconductor region, a drain region 13 which is a P-type semiconductor region, and a body region 15 which is an N-type semiconductor region. The parasitic transistor PNP1 is configured with a P+ type region 19 which is a P-type semiconductor region, an N+ type drain contact region 18 which is an N-type semiconductor region, and the drain region 13 which is a P-type semiconductor region.

[0025] A parasitic PNP transistor P1 and a parasitic NPN transistor N1 form a parasitic thyristor inside the semiconductor device 10. The drain of the semiconductor device 10 serves as the cathode of this parasitic thyristor, and the source of the semiconductor device 10 serves as the anode of this parasitic thyristor.

[0026] The parasitic PNP transistor P1 is configured so that the emitter and base are shorted. Therefore, the parasitic PNP transistor P1 is basically off. That is, the semiconductor device 10 normally operates in the same manner as a conventional LDMOSFET.

[0027] On the other hand, when a high voltage such as static electricity is applied to the drain from the outside, the parasitic thyristor operates. Specifically, in this case, the emitter voltage of the parasitic PNP transistor P1 rises. This causes a potential difference between the gate and emitter, turning on the parasitic PNP transistor P1. Then, a large current flowing from the drain passes through the parasitic PNP transistor P1 and flows to the source (ground terminal GND). In this way, a large current is prevented from flowing through the parasitic NPN transistor N1.

[0028] In addition to the above-described configuration, the semiconductor device 10 includes a high-voltage N-well region 50, an N+ type region 51, a high-voltage P-well 52, a P-well 53, a P+ type region 54, and a metal line 55.

[0029] The high-voltage N-well region 50 is in contact with the N-type underlying film 12. The N+-type region 51 is formed in the surface portion of the high-voltage N-well region 50.

[0030] The high-voltage P-well 52 is electrically connected to the semiconductor substrate 11 via a metal line 55. The P-well 53 is formed in the surface portion of the high-voltage P-well 52. The P+ type region 54 is formed in the surface of the P-well 53. The P+ type region 54 is electrically connected to the drain of the semiconductor device 10.

[0031] In addition to the above-described configuration, the semiconductor device 10 also has a charged film f1. The charged film f1 is laminated over the entire surface of the semiconductor device 10 except for contact holes (not shown) in contact with the gate electrode 21, the drain electrode 22, and the source electrode 23. The charged film f1 is a so-called etching stop layer that prevents the gate electrode 21 from being etched. An insulating nitride film or the like can be used as the charged film f1.

[0032] <Considerations on charged films> However, if a high temperature state is maintained while a voltage is applied to the drain, a surface potential (=mobile ions) may remain on the charged film f1. If a surface potential remains on the charged film f1, ions will be attracted to the area directly below the charged film f1.

[0033] Here, the charged film f1 is also laminated on the surface of the N-well 14. As described above, the N-well 14 has a lower N-type impurity concentration than the N+-type drain contact region 18. Therefore, if the charged film f1 becomes charged and ions concentrate in the N-well 14, there is a risk of field inversion and the formation of a channel. If a channel is formed in this way, there is a risk of adversely affecting the breakdown voltage of the element, such as the generation of a leak current through this channel as a leak path.

[0034] 3, in order to suppress field inversion, an N+ type drain contact region 18 is formed in a location of the N-well 14 where field inversion may occur. The N+ type drain contact region 18 has a higher N-type impurity concentration than the N-well 14. This makes it possible to suppress channel formation due to field inversion as described above.

[0035] However, in this case, the base resistance of the parasitic PNP transistor P1 decreases. As a result, when a voltage is applied to the drain, the potential difference between the base and emitter of the parasitic PNP transistor P1 decreases. As a result, even if a relatively large voltage is applied to the drain, the parasitic PNP transistor P1 becomes less likely to turn on. In other words, as mentioned above, thyristor operation becomes more difficult, and electrostatic breakdown due to static electricity and the like may become more likely to occur.

[0036] To address these problems, the semiconductor device 1 of the present disclosure is capable of suppressing the occurrence of the above-described leak path while facilitating thyristor operation. The semiconductor device 1 according to the embodiment of the present disclosure will be described in detail below. As described above, the semiconductor device 1 according to the embodiment of the present disclosure includes components in common with the semiconductor device 10 described above. For this reason, the same reference numerals are used to designate the common components, and descriptions thereof will be omitted.

[0037] <Regarding the semiconductor device 1 according to the embodiment of the present disclosure> FIG. 4 is a diagram illustrating a configuration of a semiconductor device 1 according to an embodiment of the present disclosure. FIG. 5 is a cross-sectional view illustrating a cross section of the semiconductor device 1 taken along the line BB in FIG. 4. The semiconductor device 1 is an N-channel LDMOSFET. As shown in FIGS. 4 and 5, the semiconductor device 1 includes a semiconductor substrate 11, a drain region 13, an N-well 14, a body region 15, an N+ type source region 16, a P+ type region 17, a P+ type region 19, a channel region 20, a drain electrode 22, a source electrode 23, a gate electrode 21, a high-voltage N-well region 50, an N+ type region 51, a high-voltage P-well 52, a P-well 53, a P+ type region 54, a metal line 55, and a charging film f1, which are similar to those described above.

[0038] In addition to these, the semiconductor device 1 also includes N+ type drain contact regions 18a and 18b. The N+ type drain contact regions 18a and 18b correspond to the N+ type drain contact region 18 described above.

[0039] The N+ type drain contact regions 18a are arranged alternately with the P+ type regions 19 in the second direction. The N+ type drain contact regions 18b are disposed between pairs of adjacent N+ type drain contact regions 18a. The N+ type drain contact regions 18b are in contact with each of the pair of N+ type drain contact regions 18a and are electrically connected to each other so as to have the same potential.

[0040] Each P+ type region 19 is located between a pair of N+ type drain contact regions 18b in the first direction. Also, each P+ type region 19 is located between a pair of adjacent N+ type drain contact regions 18a in the second direction. In other words, each P+ type region 19 is surrounded on all four sides by a pair of N+ type drain contact regions 18a and a pair of N+ type drain contact regions 18b.

[0041] The N-well 14 extends along the third direction from below the N+ type drain contact region 18b and the P+ type region 19 (toward the semiconductor substrate 11 side in the third direction) so as to get between the N+ type drain contact region 18b and the P+ type region 19. That is, the N-well 14 is located between each N+ type drain contact region 18b and each P+ type region 19 in the second direction.

[0042] The N-well 14 is in contact with the N+ type drain contact region 18b and the P+ type region 19. That is, the N+ type drain contact region 18b and the P+ type region 19 are electrically connected to each other via the N-well 14.

[0043] As described above, the N-well 14 has a relatively low concentration of N-type impurities. In other words, the N-well 14 functions as an electrical resistance (=resistive layer) between the N+ type drain contact region 18b and the P+ type region 19. As a result, when a voltage is applied to the drain, the base resistance of the parasitic PNP transistor P1 increases, making it easier for the parasitic PNP transistor P1 to turn on. In other words, when static electricity is applied to the drain, the semiconductor device 1 is more likely to operate as a thyristor, making it easier for a large current caused by static electricity to flow to the ground terminal GND.

[0044] Furthermore, the N+ type drain contact regions 18b are disposed on both sides of the P+ type region 19 in the first direction. The N+ type drain contact regions 18b have a higher impurity concentration than the N-well 14. Therefore, even if a surface potential accumulates in the charged film f1, the portions on both sides of the P+ type region 19, i.e., the N+ type drain contact regions 18b, are less likely to undergo field inversion as described above. This makes it possible to prevent a channel from being formed between the P+ type region 19 and the body region 15, thereby preventing a leak path from occurring.

[0045] Furthermore, there is no need to provide a new protection circuit or the like to suppress large currents due to leakage current or static electricity, which makes it possible to suppress increases in the manufacturing costs of the semiconductor device 1.

[0046] <Modification> The present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure. For example, although the N-well 14 is located between the P+ type region 19 and the N+ type drain contact region 18b, this is not limiting. For example, as shown in FIG. 6, a resistive layer Rnw separate from the N-well 14 can be located between the P+ type region 19 and the N+ type drain contact region 18b.

[0047] In this case, the impurity concentration of the resistive layer Rnw is lower than the impurity concentration of the N+ type drain contact region 18. The electrical resistance of the resistive layer Rnw is higher than the electrical resistance of the N+ type drain contact region 18. The resistive layer Rnw is embedded in the cutout portion 30 together with the P+ type region 19. The resistive layer Rnw is located between the P+ type region 19 and the N+ type drain contact region 18b in the width direction. The resistive layer Rnw is in contact with the adjacent N+ type drain contact regions 18a, 18b and the P+ type region 19, and is at the same potential as each other.

[0048] <Additional Notes> The semiconductor device (10) disclosed in the specification includes a drain region (13) of an N-type semiconductor layer formed on a semiconductor substrate (11), a body region (15) of a P-type semiconductor region formed in the drain region (13), an N+ type source region (16) formed in the body region (15), an N+ type drain contact region (18) formed on the surface of the drain region (13), and a plurality of P+ type regions (19) formed in the drain region (13) alternately with the N+ type drain contact region (18) along the N+ type source region (16) and electrically connected to the N+ type drain contact region (18) so as to have the same potential as the N+ type drain contact region (18), and configured to contact the N+ type drain contact region (18). a drain electrode (22) formed in contact with the N+ type source region (16); a source electrode (23) configured to be in contact with the N+ type source region (16); a gate electrode (21) configured to be in contact with the surface of the body region (15) via a gate insulating film; a charged film (f1) covering the surface of at least a region between each P+ type region (19) and the body region (15) among regions other than the drain electrode (22), the source electrode (23), and the gate electrode (21); and a resistive layer (14, Rnw) formed in the drain region (13) at least between each P+ type region (19) and the body region (15) and having an impurity concentration lower than that of the N+ type drain contact region (18) (first configuration).

[0049] The semiconductor device (10) according to the first configuration preferably includes an N-well (14) formed on the surface of the drain region (13), and the N+ type drain contact region (18) and the P+ type region (19) are preferably formed within the N-well (14) (second configuration).

[0050] In the semiconductor device (10) according to the second configuration, the resistive layer (14) may be formed integrally with the N-well (14) (third configuration).

[0051] In the semiconductor device (10) according to the second configuration, the resistive layer (Rnw) may be configured to be separate from the N-well (14) (fourth configuration).

[0052] In the semiconductor device (10) according to any one of the first to fourth configurations, the resistive layer (14, Rnw) may be further formed in the drain region (13) at a position opposite the body region (15) of each P+ type region (19) (fifth configuration).

[0053] In the semiconductor device (10) according to any one of the first to fifth configurations, the charging film (f1) may be a nitride film (sixth configuration).

[0054] The semiconductor device (10) according to any one of the first to sixth configurations may be configured to include a semiconductor substrate (11) (seventh configuration). [Explanation of symbols]

[0055] 1. Semiconductor device 10 Semiconductor device 11 Semiconductor substrate 12 N+ type lower layer membrane 13 Drain region 14 N-well (resistive layer) 15 Body Region 16 N+ type source region 17 P+ type region 18a, 18b N+ type drain contact region 19 P+ type region 20 channel region 21 gate electrode 22 drain electrode 23 Source electrode 30 Notch GND grounding end N1 Parasitic NPN transistor P1 Parasitic PNP transistor Rnw resistive layer f1 Charged film

Claims

1. a drain region of an N-type semiconductor layer formed on a semiconductor substrate; a body region of a P-type semiconductor region formed in the drain region; an N+ type source region formed in the body region; an N+ type drain contact region formed on the surface of the drain region; a plurality of P+ type regions formed in the drain region along the N+ type source region so as to be alternately arranged with the N+ type drain contact regions, the P+ type regions being electrically connected to the N+ type drain contact regions so as to have the same potential as the N+ type drain contact regions; a drain electrode configured to contact the N+ type drain contact region; a source electrode configured to contact the N+ type source region; a gate electrode configured to contact a surface of the body region via a gate insulating film; a charged film covering the surface of at least a region between each of the P+ type regions and the body region, among regions other than the drain electrode, the source electrode, and the gate electrode; a resistive layer formed in the drain region at least between each of the P+ type regions and the body region, the resistive layer having a lower impurity concentration than the N+ type drain contact region; A semiconductor device comprising:

2. an N-well formed on a surface of the drain region; 2. The semiconductor device according to claim 1, wherein the N+ type drain contact region and the P+ type region are formed in the N- well.

3. 3. The semiconductor device according to claim 2, wherein the resistive layer is formed integrally with the N-well.

4. 3. The semiconductor device according to claim 2, wherein the resistive layer is separate from the N-well.

5. The semiconductor device according to claim 1 , wherein the resistive layer is further formed in the drain region at a position opposite to the body region of each of the P+ type regions.

6. 2. The semiconductor device according to claim 1, wherein the charged film is a nitride film.

7. The semiconductor device according to claim 1 , comprising the semiconductor substrate.

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