Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device capable of controlling warpage of a semiconductor chip and thus a semiconductor wafer.SOLUTION: There is provided a semiconductor device including, in a first main surface of a semiconductor chip, a trench having a portion extending in a first direction and a portion extending in a second direction different from the first direction in a plan view. The trench has a portion extending in a third direction different from the first direction and the second direction between the portion extending in the first direction and the portion extending in the second direction in the plan view. The portion extending in the first direction may intersect the portion extending in the third direction at an obtuse angle, and the portion extending in the second direction may intersect the portion extending in the third direction at the obtuse angle.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 describes a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which a field plate electrode and a gate electrode are formed in a trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-1723 Summary of the Invention [Problem to be solved by the invention]

[0004] However, because the trenches are arranged parallel to one another in one direction on the semiconductor chip, there is a problem that the semiconductor wafer on which multiple semiconductor chips are formed warps. Therefore, an object of the present disclosure is to provide a semiconductor device in which trenches extending continuously in the first and second directions are formed in the semiconductor chip, thereby controlling warpage.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a trench having a portion extending in a first direction and a portion extending in a second direction, which are continuous in a plan view. [Effects of the Invention]

[0007] According to the embodiment, it is possible to provide a semiconductor device that can control the warpage of the semiconductor chip, and therefore the semiconductor wafer. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a related semiconductor device. [Figure 2] FIG. 1 is an enlarged plan view showing a main part of a related semiconductor device. [Figure 3] FIG. 1 is an enlarged plan view showing a main part of a related semiconductor device. [Figure 4] FIG. 1 is a cross-sectional view showing a related semiconductor device. [Figure 5] FIG. 1 is a cross-sectional view showing a related semiconductor device. [Figure 6] 1 is a layout of a trench in a related semiconductor device. [Figure 7] 1A and 1B are diagrams showing wafer warpage in a related semiconductor device. [Figure 8] 1 is a layout of trenches in a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiment Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the invention according to the claims is not limited to the following embodiments. Furthermore, not all of the configurations described in the embodiments are necessarily essential means for solving the problems. For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0011] (Explanation of related semiconductor device configuration and issues) A related semiconductor device 100 will be described below with reference to Figures 1 to 5. Problems with the related semiconductor device will also be described with reference to Figures 6 and 7. The semiconductor device 100 includes a MOSFET with a trench gate structure as a semiconductor element. In particular, the related MOSFET has a split gate structure including a gate electrode GE and a field plate electrode FP.

[0012] Fig. 1 is a plan view of a semiconductor chip that is a semiconductor device 100. Fig. 1 mainly shows a wiring pattern formed above a semiconductor substrate SUB. Fig. 2 is a plan view of a main part, enlarging a part of Fig. 1. Fig. 3 shows the structure below Fig. 2, and illustrates the structure of a trench gate formed in the semiconductor substrate SUB.

[0013] As shown in FIG. 1, most of the semiconductor device 100 is covered with a source electrode (fixed potential supply wiring) SE. A gate wiring GW is provided along the periphery of the semiconductor device 100 and surrounds the source electrode SE in a plan view. Although not shown here, the source electrode SE and gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the source electrode SE and gate wiring GW exposed in the opening become a source pad SP and a gate pad GP. External connection members such as wire bonding or clips (copper plates) are connected to the source pad SP and the gate pad GP, thereby electrically connecting the semiconductor device 100 to another semiconductor chip or a wiring board.

[0014] The semiconductor device 100 also includes a region 1A and regions 2A and 2A' surrounding the region 1A in a plan view. The region 1A is a cell region where main semiconductor elements such as multiple MOSFETs are formed. The regions 2A and 2A' are peripheral regions used for connecting the gate electrode GE to the gate wiring GW, etc.

[0015] The positional relationship of the holes CH1 to CH3 shown in Fig. 3 is the same as the positional relationship of the holes CH1 to CH3 shown in Fig. 2. The structure of region 2A' is obtained by inverting the structure of region 2A on the drawing. Therefore, like the CC cross section in Fig. 5, the cross-sectional structure of region 2A' is similar to the cross-sectional structure of region 2A.

[0016] 3, a plurality of trenches TR extend in the Y direction and are adjacent to each other in the X direction. The width of each trench TR in the X direction is, for example, not less than 1.5 μm and not more than 1.8 μm.

[0017] Inside the trench TR, a field plate (fixed potential electrode) electrode FP is formed at the bottom of the trench TR, and a gate electrode GE is formed at the top of the trench TR. Therefore, the gate electrode GE is exposed in Fig. 3. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR.

[0018] A part of the field plate electrode FP forms a contact portion FPa. The field plate electrode FP constituting the contact portion FPa is formed inside the trench TR in region 1A not only in the lower portion of the trench TR but also in the upper portion of the trench TR. Therefore, in FIG. 3, the contact portion FPa is exposed.

[0019] The gate electrode GE is divided into the region 2A side and the region 2A' side by the contact portion FPa.

[0020] The cross-sectional structure of the semiconductor device 100 will be described below with reference to Figures 4 and 5. Figure 4 is a cross-sectional view taken along lines AA and BB shown in Figure 3. Figure 5 is a cross-sectional view taken along lines CC and DD shown in Figure 3.

[0021] First, the basic structure of a MOSFET will be described using the AA cross section in FIG. 4. The semiconductor device 100 includes a semiconductor substrate SUB having an upper surface and a lower surface. The semiconductor substrate SUB has a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked body consisting of an n-type silicon substrate and an n-type semiconductor layer will also be described as the semiconductor substrate SUB.

[0022] A plurality of trenches TR1 are formed in the semiconductor substrate SUB, each extending from the upper surface of the semiconductor substrate SUB to a predetermined depth. The depth of each trench is, for example, 5 μm or more and 7 μm or less. Inside the trenches TR, a field plate electrode FP is formed at the bottom of the trenches TR via an insulating film IF1. The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. An insulating film IF2 is formed on the upper surface and side surfaces of the field plate electrode FP exposed from the insulating film IF1. Furthermore, a gate insulating film GI is formed on the semiconductor substrate SUB inside the trenches TR.

[0023] A gate electrode GE is formed inside the trench TR above the trench TR. The gate electrode GE is electrically insulated from the field plate electrode FP by an insulating film IF2 and from the semiconductor substrate SUB by a gate insulating film GI. The gate electrode GE is also formed between the field plate electrode FP exposed from the insulating film IF1 and the semiconductor substrate SUB, with the gate insulating film GI and insulating film IF2 interposed therebetween.

[0024] The upper surface of the gate electrode GE is slightly recessed from the upper surface of the semiconductor substrate SUB. An insulating film IF3 is formed on part of the upper surface of the gate electrode GE so as to be in contact with the gate insulating film GI.

[0025] The gate electrode GE and the field plate electrode FP are made of, for example, a polycrystalline silicon film doped with n-type impurities. The insulating films IF1, IF2, IF3 and gate insulating film GI are made of, for example, a silicon oxide film.

[0026] The thickness of the insulating film IF1 is greater than the thicknesses of the insulating films IF2, IF3, and gate insulating film GI. The thickness of the insulating film IF1 is, for example, 400 nm or more and 600 nm or less. The thickness of each of the insulating film IF2 and the gate insulating film is, for example, 50 nm or more and 80 nm or less. The thickness of the insulating film IF3 is, for example, 30 nm or more and 80 nm or less.

[0027] A p-type body region PB is formed in the semiconductor substrate SUB on the upper surface side thereof so as to be shallower than the trench TR. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0028] An n-type drain region ND is formed in the semiconductor substrate SUB on the lower surface side thereof. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed below the lower surface of the semiconductor substrate SUB. The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film made by appropriately stacking these metal films.

[0029] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 700 nm or more and 900 nm or less. The interlayer insulating film IL may be a stacked film of a thin silicon oxide film and a thick silicon oxide film containing phosphorus (PSG: Phospho Silicate Glass film).

[0030] A hole CH1 is formed in the interlayer insulating film IL, the source region NS, and the body region PB. A high-concentration region PR is formed in the body region PB at the bottom of the hole CH1. The high-concentration region PR has a higher impurity concentration than the body region PB.

[0031] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is embedded in the hole CH1. The source electrode SE is electrically connected to the source region NS, the body region PB, and the heavily doped region PR, and supplies a source potential (fixed potential) to these regions.

[0032] 3 and 5, the gate electrode GE includes a first end portion on the region 2A side and a second end portion on the region 2A' side in the Y direction. A hole CH2 is formed in the interlayer insulating film IL. The hole CH2 on the region 2A side is formed so as to overlap the first end portion of the gate electrode GE in a planar view, and the hole CH2 on the region 2A' side is formed so as to overlap the second end portion of the gate electrode GE in a planar view.

[0033] Note that the "first end of the gate electrode GE" described in this specification refers to a portion of the gate electrode GE where the hole CH2 in the region 2A is provided, and is a portion adjacent to the body region PB where the source region NS is not formed, as in the CC cross section of Fig. 5. Similarly, the "second end of the gate electrode GE" described in this specification refers to a portion of the gate electrode GE where the hole CH2 in the region 2A' is provided, and is a portion adjacent to the body region PB where the source region NS is not formed, as in the CC cross section of Fig. 5.

[0034] A gate wiring GW is formed on the interlayer insulating film IL. The gate wiring GW is buried inside the hole CH2. The gate wiring GW is electrically connected to the gate electrode GE and supplies a gate potential to the gate electrode GE.

[0035] 3 and the BB cross section in Fig. 4 and the DD cross section in Fig. 5, a part of the field plate electrode FP forms a contact portion FPa of the field plate electrode FP. The contact portion FPa is formed not only in the lower portion of the trench TR but also in the upper portion of the trench TR, inside the trench TR located between the gate electrode GE on the region 2A side (first end side) and the gate electrode GE on the region 2A' side (second end side).

[0036] The position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the contact portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the contact portion FPa. That is, the position of the upper surface of the insulating film IF1 in the AA cross section is located at a depth of, for example, 700 nm or more and 900 nm or less from the upper surface of the semiconductor substrate SUB. The position of the upper surface of the insulating film IF1 in the BB cross section is located at a depth of, for example, 600 nm or more and 800 nm or less from the upper surface of the semiconductor substrate SUB.

[0037] The position of the upper surface of the contact portion FPa is higher than the position of the upper surface of the semiconductor substrate SUB, and is located at a height of, for example, 200 nm or more and 400 nm or less from the upper surface of the semiconductor substrate SUB.

[0038] The coupling portion GEa is formed on both side surfaces of the contact portion FPa in the X direction via an insulating film IF2. The coupling portion GEa also extends in the Y direction and connects the gate electrode GE on the region 2A side (first end side) to the gate electrode GE on the region 2A' side (second end side). The gate electrode GE and the coupling portion GEa are made of an integrated n-type polycrystalline silicon film. Therefore, the gate potential is also supplied to the coupling portion GEa from the gate wiring GW. The coupling portion GEa is also covered with an insulating film IF3.

[0039] A hole CH3 is formed in the interlayer insulating film IL. The hole CH3 is formed so as to overlap the contact portion FPa in a plan view. A source electrode SE is buried inside the hole CH3. The source electrode SE is electrically connected to the field plate electrode FP and supplies a source potential to the field plate electrode FP.

[0040] The source electrode SE and the gate wiring GW are each made of, for example, a barrier metal film and a conductive film formed on the barrier metal film, where the barrier metal film is, for example, a titanium nitride film, and the conductive film is, for example, an aluminum film.

[0041] The source electrode SE and the gate wiring GW may be composed of a plug layer filling the holes CH1 to CH3 and a wiring layer formed on the interlayer insulating film IL. In this case, the wiring layer is composed of the barrier metal film and the conductive film. The plug layer is composed of a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0042] Such a semiconductor device is called a split-gate MOSFET.

[0043] Fig. 6 shows a layout of trenches in a related semiconductor device. As shown in the upper diagram of Fig. 6, in the layout of the related semiconductor device, a plurality of trenches are arranged in parallel in one direction within a semiconductor chip.

[0044] FIG. 7 is a diagram showing wafer warpage of a related semiconductor device. The wafer in FIG. 7 has a trench arranged perpendicular to the notch or orientation flat. As shown in FIG. 7, the amount of wafer warpage is smallest at 0°, which is perpendicular to the notch. Next, the amount of warpage is large at 45° or 135° relative to the notch. The amount of warpage is largest at 90° relative to the notch.

[0045] When the trench is arranged parallel to the notch in this way, the warp in the left-right direction relative to the notch becomes large, which may affect wafer transport and have a negative impact on productivity.

[0046] One possible solution to this problem is to form trenches in two directions, vertically and horizontally, within the semiconductor chip, as shown in the lower diagram of Figure 6. However, if an attempt is made to form a transistor with the same area as the upper diagram of Figure 6, the chip size will increase, reducing productivity.

[0047] (Description of Semiconductor Device According to an Embodiment) Therefore, the semiconductor device according to the embodiment provides a trench layout that controls wafer warpage without reducing productivity. Fig. 8 shows the trench layout of the semiconductor device according to the embodiment.

[0048] As shown in the upper diagram of Figure 8, the semiconductor device according to the embodiment includes a trench on a first main surface of a semiconductor chip, the trench having a portion extending continuously in a first direction in a plan view and a portion extending in a second direction different from the first direction. For example, the trench is formed in a diagonal direction relative to the semiconductor chip. The first direction may be at a 45° angle relative to the notch, and the second direction may be at a 135° angle relative to the notch.

[0049] Furthermore, as shown in the lower diagram of FIG. 8, the trench may have a portion extending in a third direction different from the first and second directions between a portion extending in a first direction and a portion extending in a second direction in a plan view. For example, the third direction may be at an angle of 0° relative to the notch. In this case, the portion extending in the first direction intersects with the portion extending in the third direction at an obtuse angle. Furthermore, the portion extending in the second direction intersects with the portion extending in the third direction at an obtuse angle.

[0050] The semiconductor device according to the embodiment may have a plurality of trenches, and the plurality of trenches may have portions extending parallel to each other in a first direction and portions extending in a second direction. The plurality of trenches may not have portions extending in the first direction and portions extending in the second direction as a continuous line. The lengths of the trenches may also be different. It is important that portions extending in the first direction and portions extending in the second direction are arranged within a single semiconductor chip. This allows for the arrangement of multiple transistors. Furthermore, wafer warpage can be controlled without increasing the chip size.

[0051] Here, let us consider the electrical properties of the semiconductor device. In the related semiconductor device, the reason why the trench is formed parallel to the notch is that the surface is a {100} plane and the notch is a {100} plane. <100> The purpose was to use a silicon wafer with a {100} orientation to make the channel of the trench MOSFET a {100} plane, thereby improving its electrical characteristics.

[0052] When a trench is formed at an angle of 45° to the notch as in the semiconductor device according to the embodiment, the crystal plane of the first main surface is {100}, and the notch is <110> Preferably, the crystal plane of the first main surface of the semiconductor device according to the embodiment is {100}, the first direction is at a 45° angle when viewed from the front of the notch or orientation flat, and the second direction is at a 135° angle when viewed from the front of the notch or orientation flat.

[0053] The present disclosure provides a semiconductor device capable of controlling warpage of a semiconductor chip, and therefore a semiconductor wafer. It also provides a method for manufacturing a semiconductor device, which includes forming a trench in a first main surface of a semiconductor chip, the trench having a portion extending continuously in a first direction in a plan view and a portion extending in a second direction different from the first direction.

[0054] For example, the semiconductor device according to the above embodiments may be configured such that the conductivity types (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. are reversed. Therefore, when one of the n-type and p-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0055] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0056] 100 semiconductor device, SUB semiconductor substrate, SE source electrode, GW gate wiring, GP gate pad, SP source pad, 1A region, 2A region, 2A' region, TR trench, GE gate electrode, FP field plate electrode, FPa contact portion, GEa connection portion, NV drift region, GI gate insulating film, IF1 insulating film, IF2 insulating film, IF3 insulating film, PB body region, ND drain region, DE drain electrode, NS source region, CH1 hole, PR high concentration region, IL interlayer insulating film, CH2 hole, CH3 hole

Claims

1. A semiconductor device comprising: a semiconductor chip having, in a first main surface thereof, a trench having, in a plan view, a portion extending continuously in a first direction and a portion extending in a second direction different from the first direction.

2. the trench has a portion extending in the first direction and a portion extending in the second direction in a plan view, the portion extending in a third direction different from the first direction and the second direction; the portion extending in the first direction intersects with the portion extending in the third direction at an obtuse angle; The semiconductor device according to claim 1 , wherein said portion extending in the second direction intersects with said portion extending in the third direction at an obtuse angle.

3. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a split-gate metal oxide semiconductor field effect transistor (MOSFET).

4. The semiconductor device according to claim 3 , wherein a field plate and a gate electrode are formed in said trench.

5. The trenches are plural, 2. The semiconductor device according to claim 1, wherein the plurality of trenches have portions extending in the first direction and portions extending in the second direction that are arranged parallel to each other.

6. the crystal plane of the first principal surface is {100}; The notch or orientation flat is in the <110> direction; the first direction is an angle of 45° when the notch or the orientation flat is viewed from the front, 2. The semiconductor device according to claim 1, wherein said second direction is an angle of 135 degrees when said notch or said orientation flat is viewed from the front.

7. A method for manufacturing a semiconductor device, comprising forming a trench in a first main surface of a semiconductor chip, the trench having a portion extending continuously in a first direction in a plan view and a portion extending in a second direction different from the first direction.

8. the trench has a portion extending in the first direction and a portion extending in the second direction in a plan view, the portion extending in a third direction different from the first direction and the second direction; the portion extending in the first direction intersects with the portion extending in the third direction at an obtuse angle; 8. The method for manufacturing a semiconductor device according to claim 7, wherein the portion extending in the second direction intersects with the portion extending in the third direction at an obtuse angle.

9. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is a split-gate metal oxide semiconductor field effect transistor (MOSFET).

10. 10. The method for manufacturing a semiconductor device according to claim 9, wherein a field plate and a gate electrode are formed in the trench.

11. The trenches are plural, 8. The method for manufacturing a semiconductor device according to claim 7, wherein the plurality of trenches have portions extending in the first direction and portions extending in the second direction that are arranged parallel to each other.

12. the crystal plane of the first principal surface is {100}; The notch or orientation flat is in the <110> direction; the first direction is an angle of 45° when the notch or the orientation flat is viewed from the front, 8. The method for manufacturing a semiconductor device according to claim 7, wherein the second direction is an angle of 135 degrees when the notch or the orientation flat is viewed from the front.

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