Photoelectric conversion device

Abstract

To propose a wiring structure for a photoelectric conversion device in which a plurality of substrates are laminated.SOLUTION: There is provided a photoelectric conversion device in which a first chip including a first semiconductor layer having a photoelectric conversion unit and a first readout circuit, and a first wiring structure, a second chip including a second semiconductor layer having a memory and an output circuit, and a second wiring structure, and a third chip including a third semiconductor layer having a second readout circuit, and a third wiring structure are laminated. The first wiring structure includes first wiring for supplying a power supply to the photoelectric conversion unit and second wiring for supplying a power supply to the first readout circuit. The second wiring structure includes third wiring for supplying a power supply to the memory and fourth wiring for supplying a power supply to the output circuit. The third wiring structure includes fifth wiring for supplying a first power supply to the second readout circuit and sixth wiring for supplying a second power supply different from the first power supply. Among the first to sixth wiring, at least two pieces of wiring are connected between at least two chips of the first to third chips.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Photoelectric conversion devices that have an analog-to-digital (AD) converter for each pixel column are known. As an example of this type of photoelectric conversion device, Patent Document 1 describes an imaging device that has a global shutter function that simultaneously starts exposure for all pixels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 215105 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 discloses an imaging device in which multiple substrates are stacked, but does not consider the arrangement of power supplies and wiring on each substrate. [Means for solving the problem]

[0005] One aspect of the present invention is a photoelectric conversion device in which a first chip including a first semiconductor layer having a photoelectric conversion unit and a first readout circuit that reads out a signal based on the photoelectric conversion of the photoelectric conversion unit, and a first wiring structure electrically connected to each of the photoelectric conversion unit and the first readout circuit, a second chip including a second semiconductor layer having a memory that holds a voltage according to the signal and an output circuit that outputs the voltage held in the memory, and a second wiring structure electrically connected to each of the memory and the output circuit, and a third chip including a third semiconductor layer having a second readout circuit that reads out a signal according to the held voltage, and a third wiring structure electrically connected to the second readout circuit, a first wiring structure including a first wiring that supplies power to the photoelectric conversion unit and a second wiring that supplies power to the first readout circuit; the second wiring structure including a third wiring that supplies power to the memory and a fourth wiring that supplies power to the output circuit; the third wiring structure including a fifth wiring that supplies a first power supply to the second readout circuit and a sixth wiring that supplies a second power supply different from the first power supply to the second readout circuit; and at least two of the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring are connected between at least two of the first chip, the second chip, and the third chip. [Effects of the Invention]

[0006] According to the present invention, it is possible to reduce the wiring resistance of the power supply wiring in a photoelectric conversion device in which a plurality of substrates are stacked. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is an overall circuit diagram according to a first embodiment. [Figure 2] 2 is a stacking surface according to the first embodiment. [Figure 3] FIG. 2 is a read circuit diagram according to the first embodiment. [Figure 4] FIG. 2 is a circuit diagram of a current source according to the first embodiment. [Figure 5] 1 is an ADC circuit diagram according to a first embodiment. [Figure 6] FIG. 2 is a pad layout diagram according to the first embodiment. [Figure 7] 1 is a cross-sectional view of a laminated chip according to a first embodiment. [Figure 8] 1 is a cross-sectional view of a laminated chip according to a first embodiment. [Figure 9] FIG. 2 is a plan view of a pixel array according to the first embodiment. [Figure 10] FIG. 2 is a plan view of the chip according to the first embodiment. [Figure 11] FIG. 2 is a plan view of the chip according to the first embodiment. [Figure 12] 1 is a cross-sectional view of a laminated chip according to a first embodiment. [Figure 13] FIG. 2 is a plan view of a pixel array according to the first embodiment. [Figure 14] FIG. 2 is a plan view of the chip according to the first embodiment. [Figure 15] FIG. 2 is a read circuit diagram according to the first embodiment. [Figure 16] FIG. 10 is a read circuit diagram according to a second embodiment. [Figure 17] FIG. 10 is a cross-sectional view of a laminated chip according to a second embodiment. [Figure 18] FIG. 10 is a cross-sectional view of a laminated chip according to a second embodiment. [Figure 19] FIG. 10 is a plan view of a pixel array according to a second embodiment. [Figure 20] FIG. 10 is a plan view of a pixel array according to a second embodiment. [Figure 21] FIG. 10 is a diagram illustrating a read circuit according to a third embodiment. [Figure 22] FIG. 10 is a circuit diagram of a current source according to a third embodiment. [Figure 23] FIG. 10 is a pad layout diagram according to a third embodiment. [Figure 24] FIG. 10 is a cross-sectional view of a laminated chip according to a third embodiment. [Figure 25] FIG. 10 is a cross-sectional view of a laminated chip according to a third embodiment. [Figure 26] FIG. 10 is a cross-sectional view of a laminated chip according to a third embodiment. [Figure 27] FIG. 10 is a read circuit diagram according to a fourth embodiment. [Figure 28] FIG. 10 is a circuit diagram of a current source according to a fourth embodiment. [Figure 29] FIG. 10 is a pad layout diagram according to a fourth embodiment. [Figure 30] FIG. 10 is a cross-sectional view of a laminated chip according to a fourth embodiment. [Figure 31] FIG. 10 is a cross-sectional view of a laminated chip according to a fourth embodiment. [Figure 32] FIG. 10 is a plan view of a pixel array according to a fourth embodiment. [Figure 33] FIG. 11 is a read circuit diagram according to a fifth embodiment. [Figure 34] FIG. 10 is a buffer circuit diagram according to a fifth embodiment. [Figure 35] FIG. 10 is a pad layout diagram according to a fifth embodiment. [Figure 36] FIG. 10 is a cross-sectional view of a laminated chip according to a fifth embodiment. [Figure 37] FIG. 10 is a cross-sectional view of a laminated chip according to a fifth embodiment. [Figure 38] FIG. 10 is a pad layout diagram according to a sixth embodiment. [Figure 39] FIG. 10 is a cross-sectional view of a laminated chip according to a sixth embodiment. [Figure 40] FIG. 10 is a cross-sectional view of a laminated chip according to a sixth embodiment. [Figure 41] FIG. 10 is a cross-sectional view of a laminated chip according to a sixth embodiment. [Figure 42] FIG. 10 is a cross-sectional view of a laminated chip according to a sixth embodiment. [Figure 43] FIG. 13 is a functional block diagram of a photoelectric conversion system according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0010] In this specification, a planar view refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a view of a cross section perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0011] In this specification, when the term "impurity concentration" is used simply, it means the net impurity concentration minus the amount compensated for by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the NET doping concentration. A region where the P-type doped impurity concentration is higher than the N-type doped impurity concentration is a P-type semiconductor region. Conversely, a region where the N-type doped impurity concentration is higher than the P-type doped impurity concentration is an N-type semiconductor region.

[0012] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0013] (First embodiment) The first embodiment will be described with reference to Figs. 1 to 15. Fig. 1 is a schematic diagram showing one embodiment of a photoelectric conversion device according to the present invention. The photoelectric conversion device 10 has a configuration in which a pixel chip 100 (first chip), a memory chip 200 (second chip), and a signal processing chip 300 (third chip) are stacked as shown in Fig. 2. Signals can be exchanged between the chips by joining the wiring provided on each chip.

[0014] The pixel chip 100 shown in FIG. 1 includes a pixel region 110, a vertical scanning circuit 120, and a pixel control circuit 20. The pixel region 110 is an area in which pixels 30, which are unit pixels, are arranged in an array in a row and column direction. The pixels 30 include photoelectric conversion elements such as photodiodes and output signal voltages corresponding to the amount of incident light. In addition to effective pixels that output signal voltages (pixel signals) corresponding to the amount of incident light, the pixel region 110 may also include optical black pixels whose photoelectric conversion units are shielded from light and dummy pixels that do not output signals. The number of rows and columns of the pixel array arranged in the pixel region 110 is not particularly limited. The pixel control circuit 20 is a logic circuit that generates timing for operating the pixels 30 and outputs drive pulses for the pixels 30 to the vertical scanning circuit 120. The vertical scanning circuit 120 has drivers that drive the pixels 30 row by row.

[0015] The memory chip 200 includes a memory region 210, a memory vertical scanning circuit 220, a current source 230, and a memory control circuit 21. The memory region 210 is an area in which pixel memories 40 are arranged in a matrix. The pixel memories 40 function to store signal voltages output from the pixels 30. The number of pixels 30 and pixel memories 40 does not need to be the same. For example, pixel memories 40 do not need to be arranged for dummy pixels that do not output signals. Furthermore, dummy pixel memories that do not output signals may be arranged corresponding to the dummy pixels. The current source 230 supplies a reference current to the pixel memories 40. The memory control circuit 21 includes a logic circuit that generates timing for operating the pixel memories 40 and controls circuits arranged around the pixels, such as the current source 230. The drive pulses output from the memory control circuit 21 are input to the memory vertical scanning circuit 220. The memory vertical scanning circuit 220 includes a driver that drives the pixel memories 40 row by row.

[0016] The signal processing chip 300 includes a signal processing unit 310, a column control circuit 320, a ramp generator 340, a current source 330, and a signal processing control circuit 22. The signal processing unit 310 includes column signal processing circuits 50 arranged in an array in the column direction. The column signal processing circuit 50 performs AD conversion on the signal voltage output from the pixel memory 40 based on a reference voltage generated by the ramp generator 340, and outputs the converted signal as image data to the outside of the signal processing chip 300. While ramp-type AD conversion is described as an example in this embodiment, the AD conversion method is not limited to ramp-type conversion. The column signal processing circuit 50 may also perform digital processing such as noise reduction on image data. The current source 330 supplies a reference current to the column signal processing circuit 50. The signal processing control circuit 22 includes a logic circuit that generates timing for operating the column signal processing circuit 50 and sets the functions of the ramp generator 340 and the current source 330. The drive pulse output from the signal processing control circuit 22 is input to the column control circuit 320. The column control circuit 320 includes a driver that outputs a drive pulse to the column signal processing circuit 50 .

[0017] The pixel chip 100, memory chip 200, and signal processing chip 300 are stacked as shown in FIG.

[0018] The photoelectric conversion device according to this embodiment is a photoelectric conversion device that performs a so-called voltage domain global shutter operation. An example of the configuration of a signal readout circuit of a pixel 30 in the photoelectric conversion device according to this embodiment will be described with reference to FIG.

[0019] First, the pixel 30 has a photoelectric conversion element (PD) 115, a PD 116, a pixel transfer transistor 113, a pixel transfer transistor 114, and a pixel reset transistor 112. Furthermore, the pixel 30 has a pixel amplification transistor 111, a pixel selection transistor 117, and a floating diffusion capacitance (FD capacitance).

[0020] The photoelectric conversion device according to this embodiment is a photoelectric conversion device compatible with so-called PDAF, in which PD115 and PD116 form one pixel and the signals of each PD are used for phase difference detection. The imaging device (here, a CMOS sensor) uses the signal of at least one of the PDs, PD115 and PD116, for image generation. The anode terminal of PD115 is connected to a reference power supply SGND, and the cathode terminal is connected to the source of the pixel transfer transistor 113. The anode terminal of PD116 is connected to a reference power supply SGND, and the cathode terminal is connected to the source of the pixel transfer transistor 114. The drains of the pixel transfer transistor 113 and 114 are connected to the gate of the pixel amplifier transistor 111 and the source of the pixel reset transistor 112, respectively. An FD capacitor is connected to the gate of the pixel amplifier transistor 111, with the reference power supply SGND as a reference, and can hold signal charges generated by PD115 and PD116. The drains of the pixel reset transistor 112 and pixel amplifier transistor 111 are connected to a reference power supply SVDD. The source of the pixel amplification transistor 111 is connected to the drain of the pixel selection transistor 117 .

[0021] When light is incident on each of PD115 and PD116, photoelectric conversion occurs, generating an electric charge corresponding to the incident light. A control signal TX_A output from the vertical scanning circuit 120 is input to the gate of the pixel transfer transistor 113, turning on the pixel transfer transistor 113 and transferring the electric charge generated in PD115 to the FD capacitor. Similarly, a control signal TX_B output from the vertical scanning circuit 120 is input to the gate of the pixel transfer transistor 114, turning on the pixel transfer transistor 114 and transferring the electric charge generated in PD116 to the FD capacitor. When a control signal PRST is input to the gate of the pixel reset transistor 112, the FD capacitor is connected to the reference power supply SVDD, and a reset operation is performed to extract the electric charge held in the FD capacitor.

[0022] The charge held in the FD capacitance is converted into a voltage by the pixel amplification transistor 111 and output as a signal voltage from the pixel 30 in accordance with PSEL input to the gate of the pixel selection transistor 117. The output of the pixel 30 is input to the pixel memory 40 via the junction 1-2 that joins the pixel chip 100 and the memory chip 200.

[0023] Next, an example configuration of the pixel memory 40 will be described. The pixel memory 40 has a signal retention memory Nmem, a signal retention memory Smem-A, and a signal retention memory Smem-AB. The signal retention memory Nmem has a memory write transistor 213, the signal retention memory Smem-A has a memory write transistor 214, and the signal retention memory Smem-AB has a memory write transistor 215. The pixel memory 40 further includes a memory reset transistor 212, a memory amplification transistor 211, a current source transistor 216, a switch transistor 217, and a memory selection transistor 218.

[0024] The source of the pixel selection transistor 117 of the pixel 30 is connected to the drain of the current source transistor 216 of the pixel memory 40 via junction 1-2. The source of the current source transistor 216 is connected to the drain of the switch transistor 217. The source of the switch transistor 217 is connected to the power supply wiring that supplies the reference power supply AGND-1 via junction 2-3-1. At this time, VBIAS1 is supplied to the gate of the current source transistor 216 from a current source 230, and the current source transistor 216 is controlled so that a current based on VBIAS1 flows. The configuration of the current source 230 will be described later.

[0025] The signal retention memory Nmem has one terminal connected to a power supply wiring that supplies the reference power supply MGND, and the other terminal connected to the source of the memory write transistor 213. The drain of the memory write transistor 213 is connected to the gate of the memory amplification transistor 211. Similarly, the signal retention memory Smem-A has one terminal connected to a power supply wiring that supplies the reference power supply MGND, and the other terminal connected to the source of the memory write transistor 214. The drain of the memory write transistor 214 is connected to the gate of the memory amplification transistor 211. The signal retention memory Smem-AB has one terminal connected to a power supply wiring that supplies the reference power supply MGND, and the other terminal connected to the source of the memory write transistor 215. The drain of the memory write transistor 215 is connected to the gate of the memory amplification transistor 211.

[0026] In this case, the signal retention memory may be any element that has the function of retaining a signal, such as a DRAM or MIM capacitor.

[0027] The memory vertical scanning circuit 220 outputs control signals WR_N, WR_SA, and WR_SAB. The control signal WR_N is input to the gate of the memory write transistor 213, and the control signal WR_SA is input to the gate of the memory write transistor 214. The control signal WR_SAB is input to the gate of the memory write transistor 215. When the memory write transistor 213 is turned on by the control signal WR_N output from the memory vertical scanning circuit 220, the signal voltage output from the pixel amplification transistor 111 is written to the signal retention memory Nmem. Similarly, a signal voltage can be written to Smem-A in accordance with WR_SA, and a signal voltage can be written to Smem-AB in accordance with WR_SAB. The pixel reset transistor 112 retains the signal voltage after resetting the FD capacitance in Nmem, and retains the signal voltage based on the signal charge generated by the PD 115 in Smem-A. Furthermore, a signal voltage based on the sum of the signal charges generated by the PD 115 and PD 116 can be retained in Smem-AB.

[0028] The memory reset transistor 212 writes the reference voltage MVDD to the signal retention memories Nmem, Smem-A, and Smem-AB when a control signal MRST output from the memory vertical scanning circuit 220 is input to its gate, which resets the signal voltages held in the signal retention memories.

[0029] The source of the memory reset transistor 212 is connected to the gate of the memory amplification transistor 211, and the drain of the memory reset transistor 212 is connected to a power supply line that supplies a reference power supply MVDD. The source of the memory amplification transistor 211 is connected to the drain of the memory selection transistor 218.

[0030] The selection transistor 117 is turned on by receiving a control signal PSEL output from the vertical scanning circuit 120 at its gate. At the same time, the switch transistor 217 is turned on by receiving a control signal PCSW output from the memory vertical scanning circuit 220 at its gate. Accordingly, a current based on the gate voltage VBIAS1 of the current source transistor 216 flows to the pixel amplification transistor 111, causing it to operate as a source follower. As a result, a signal voltage based on the charge held in the FD capacitance is output to the gate of the memory amplification transistor 211 connected to junction 1-2.

[0031] The signal amplified by the memory amplification transistor 211 is output from the pixel memory 40 in accordance with MSEL input to the gate of the memory selection transistor 218. The output terminal of the pixel memory 40 is input to the column signal processing circuit 50 via the junction 2-3-1 that joins the memory chip 200 and the signal processing chip 300.

[0032] A description will be given of an example of the configuration of the column signal processing circuit 50. The column signal processing circuit 50 includes an ADC 311, a current source transistor 313, and a switch transistor 314.

[0033] The source of the current source transistor 313 is connected to the drain of the switch transistor 314, and the source of the switch transistor 314 is connected to the power supply wiring that supplies the reference power supply AGND_1. At this time, VBIAS2 is supplied to the gate of the current source transistor 313 from the current source 330, and a current based on VBIAS2 flows through the current source transistor 313.

[0034] The memory selection transistor 218 is turned on by inputting the control signal MSEL output from the memory vertical scanning circuit 220 to the gate, and the switch transistor 314 is turned on by MCSW output from the column control circuit 320. A current flows through the memory amplification transistor 211, and a signal voltage based on the gate voltage of the memory amplification transistor is output to the signal line VLOUT via the junction 2-3-1.

[0035] At this time, the signal retention memory Nmem can be selected by the control signal WR_N, and the signal voltages written to the signal retention memory Nmem can be read out sequentially. Similarly, the signal retention memory Smem-A can be selected by the control signal WR_SA, and the signal voltages written to each of the signal retention memories Smem-A can be read out sequentially. The signal retention memory Smem-AB can be selected by the control signal WR_SAB, and the signal voltages written to each of the signal retention memories Smem-AB can be read out sequentially.

[0036] In this configuration, bonding portion 1-2 indicates the bonding portion when the pixel chip 100 and memory chip 200 are bonded together. Bonding portion 2-3-1 and bonding portion 2-3-2 indicate the bonding portions when the memory chip 200 and signal processing chip 300 are bonded together. Each chip is electrically connected by a bonding portion. The bonding portion is configured using, for example, CCB (Cu to Cu Bonding) or TSV (Through Silicon Via).

[0037] In this embodiment, the pixel chip 100, memory chip 200, and signal processing chip 300 are joined together according to the path for reading out signals photoelectrically converted by PD 115 and PD 116 from the pixel 30. Furthermore, a reference power supply is supplied from the signal processing chip 300 to the memory chip 200 via joint 2-3-2.

[0038] Here, an example of the configuration of the current source 230 and the current source 330 in FIG. 1 is shown in FIG.

[0039] The current source 230 configures a current mirror with a reference current source 232 and a bias generation transistor 231. The reference current source 232 that generates a reference current is connected between a power supply wiring that supplies a reference power supply MVDD and the drain of the bias generation transistor 231. The source of the bias generation transistor 231 is connected to a power supply wiring that supplies a reference power supply AGND_1. VBIAS1, which is generated by connecting the gate of the bias generation transistor 231 to the drain of the bias generation transistor 231, is supplied to each pixel memory 40.

[0040] The current source 330 configures a current mirror with a reference current source 332 and a bias generation transistor 331. The reference current source 332, which generates a reference current, is connected between a power supply wiring that supplies a reference power supply MVDD and the drain of the bias generation transistor 331. The source of the bias generation transistor 331 is connected to a power supply wiring that supplies a reference power supply AGND_1. VBIAS2, which is generated by connecting the gate of the bias generation transistor 331 to the drain of the bias generation transistor 331, is supplied to each column signal processing circuit 50.

[0041] The drain of the current source transistor is connected to the input of the ADC 311 via a signal line VLOUT, and the ADC 311 is connected to a power supply wiring to which a reference power supply AVDD_1 is supplied and a power supply wiring to which a reference power supply AGND_1 is supplied.

[0042] 5 shows an example of the configuration of the ADC 311 in Fig. 3. The ADC 311 includes a comparator 312, a clamp capacitor 315, a clamp capacitor 316, a counter circuit 317, and a digital processing unit 318.

[0043] The comparator 312 has a non-inverting input terminal (+), an inverting input terminal (-), an inverting output terminal (-), and a non-inverting output terminal (+). The non-inverting input terminal (+) is connected to a signal line VLOUT, through which a signal is output from the pixel memory 40, via a clamp capacitor 315.

[0044] The inverting input terminal (-) is connected to the output terminal of the ramp generator 340 via a clamp capacitor 316. The ramp generator 340 is connected to a power supply wiring supplied with a reference power supply AVDD_1 and a power supply wiring supplied with a reference power supply AGND_1. The non-inverting input terminal (+) and the inverting output terminal (-) are connected via a switch 321, and the inverting input terminal (-) and the non-inverting output terminal (+) are connected via a switch 322. The switches 321 and 322 are reset switches that are turned on by a control signal AZ output from the column control circuit 320 and are used to initialize the comparator 312.

[0045] The comparator 312 compares the signal voltage VOUT output from the pixel memory 40 to the signal line VLOUT with the reference signal RAMP generated by the ramp generator 340, and outputs the result to the counter circuit 317. For example, if the signal voltage VOUT is greater than the reference signal RAMP, the comparator 312 outputs a high level, and if the signal voltage VOUT is smaller than the reference signal RAMP, the comparator 312 outputs a low level. Here, the magnitude relationship between the high and low levels of the output and the input signal may be reversed. The counter circuit 317 counts the time until the output of the comparator 312 inverts from a high level to a low level, and outputs the value as a digital signal to the digital processing unit 318. The digital processing unit 318 has the function of performing digital processing, such as amplification and correction using correlated double sampling. The counter circuit 317 and the digital processing unit 318 are supplied with reference power supplies DVDD and DGND.

[0046] The power supply method for each chip of the photoelectric conversion device according to this embodiment and the wiring structure of each semiconductor substrate will be described in detail below. An example of the layout of pads that supply each power source is shown in the pad layout diagram of FIG.

[0047] The pixel chip 100 is provided with a PAD that supplies a reference power supply SVDD and a PAD that supplies a reference power supply SGND, and the reference power supplies SVDD and SGND are supplied to each pixel 30 in the pixel region 110 via wiring within the pixel chip 100.

[0048] The memory chip 200 also has a PAD for supplying a reference power supply MVDD and a PAD for supplying a reference power supply MGND, which are supplied to the pixel memory 40 in the memory area 210 via wiring within the pixel memory. The reference power supply MVDD is supplied to a current source 230.

[0049] Furthermore, the signal processing chip 300 is provided with pads that supply the reference power supplies AVDD-1, AVDD-2, AGND-1, AGND-2, DVDD, and DGND. The reference power supplies AVDD-1, AGND-1, DVDD, and DGND are supplied to the signal processing unit 310 and the column signal processing circuit. The reference power supplies AVDD-2 and AGND-2 are supplied to the ramp generator. The reference power supplies AVDD-1 and AGND-1 are supplied to the current source 330. The connections between each reference power supply and the circuit are as shown in Figures 3, 4, and 5, and pads are also provided to supply reference power supplies via power supply wiring to the other circuits in the pixel chip 100, memory chip 200, and signal processing chip 300.

[0050] In this case, the magnitude relationships of the voltages of each reference power supply are SVDD>SGND, MVDD>AGND-1, (AVDD-1, AVDD-2)>(AGND-1, AGND-2), and DVDD>DGND. If DVDD is the first power supply, then the reference power supply DGND can also be said to be a second power supply that is different from the first power supply. Generally, the logic circuit section operates at a lower voltage than the circuits that output signals. For this reason, the reference power supply DVDD has a lower voltage than the reference power supplies SVDD, MVDD, AVDD-1, and AVDD-2. In this case, the magnitude relationships of the voltages of the reference power supplies SVDD, MVDD, AVDD-1, and AVDD-2 are not limited.

[0051] For example, due to the source follower operation of the pixel amplifier transistor 111 in Figure 3, the signal output relative to the signal voltage of the FD is lower by the threshold voltage of the pixel amplifier transistor 111. Therefore, the upper limit of the input range of the memory amplifier transistor 211 may be lower than that of the pixel amplifier transistor 111. In other words, the relationship SVDD > MVDD may be satisfied. On the other hand, if SVDD > MVDD, the lower limit voltage of the input range of the memory amplifier transistor 211 may be compressed. In that case, it may also be satisfied that SGND > AGND-1.

[0052] At this time, the reference power supply AGND-1 is supplied to both the memory chip 200 and the signal processing chip 300 via the joint 2-3-2 in Fig. 3 and the joint 2-3 in Fig. 4. The cross-sectional structure of the pixel chip 100, memory chip 200, and signal processing chip 300 when they are joined together will be described with reference to Fig. 7.

[0053] The pixel chip 100 includes a pixel Si substrate 1100 and a pixel chip wiring structure 1110. The pixel Si substrate 1100 is a silicon semiconductor substrate and is a first semiconductor layer in which a photoelectric conversion unit and a first readout circuit that reads out a signal based on the photoelectric conversion of the photoelectric conversion unit are formed.

[0054] 7 shows PD 115, PD 116, and selection transistor 117 as examples of elements provided on the pixel Si substrate 1100. A microlens 103 and a color filter 102 are formed on the light incident surface side of the pixel Si substrate 1100. The color filter 102 has the function of limiting the wavelength band of incident light. For example, it can transmit light of wavelength bands corresponding to the red, green, and blue colors of visible light. The microlens 103 has the function of focusing incident light onto PD 115 and PD 116.

[0055] Metal wiring 105 connecting each circuit is arranged in multiple layers in pixel chip wiring structure 1110. Pixel chip wiring structure 1110 has contact vias 104 that connect the metal wiring 105 in each layer and that connect the metal wiring 105 with pixel Si substrate 1100 and transistors formed in pixel Si substrate 1100. Pixel chip wiring structure 1110 is a first wiring structure that electrically connects a photoelectric conversion unit and a first readout circuit. The first wiring structure includes a first wiring that supplies power to the photoelectric conversion unit and a second wiring that supplies power to the first readout circuit.

[0056] The memory chip 200 includes a memory Si substrate 1200 and a memory chip wiring structure 1210. The memory Si substrate 1200 is a silicon semiconductor substrate and is a second semiconductor layer having a memory and an output circuit that outputs a voltage held by the memory. As examples of elements provided on the memory Si substrate 1200, a current source transistor 216 and a switch transistor 217 are shown in FIG. 7.

[0057] The memory chip wiring structure 1210 is a wiring structure formed of metal wiring 105 and contact vias 104, similar to the pixel chip wiring structure 1110. The signal retention memories Nmem, Smem-A, and Smem-AB in FIG. 3 are formed within the memory chip wiring structure 1210. The memory chip wiring structure 1210 is a second wiring structure that electrically connects each signal retention memory to an output circuit. The second wiring structure includes a third wiring that supplies power to the signal retention memory and a fourth wiring that supplies power to the output circuit. Here, the signal retention memory only needs to have the function of retaining a signal voltage, and may be configured to retain a signal by forming a capacitance within the memory Si substrate 1200.

[0058] The signal processing chip 300 includes a signal processing Si substrate 1300 and a signal processing chip wiring structure 1310. The signal processing Si substrate 1300 is a silicon semiconductor substrate and is a third semiconductor layer having a second readout circuit that reads out a signal corresponding to the voltage held in the memory. As examples of elements provided on the signal processing Si substrate 1300, a current source transistor 313 and a switch transistor 314 are shown in FIG.

[0059] The signal processing chip wiring structure 1310 is a third wiring structure formed of metal wiring 105 and contact vias 104, similar to the pixel chip wiring structure 1110, and electrically connected to the second readout circuit. The third wiring structure includes a fifth wiring that supplies power to the second readout circuit, and a sixth wiring that supplies power to the second readout circuit.

[0060] 7, pixel chip wiring structure 1110 of pixel chip 100 and memory chip wiring structure 1210 of memory chip 200 are bonded together so as to face each other, and bonding portion 1-2 is formed at the location where they are electrically connected. Bonding portion 1-2 in Fig. 7 is a so-called CCB, and a Cu pad formed on the lower surface of pixel chip wiring structure 1110 and a Cu pad formed on the upper surface of memory chip wiring structure 1210 are bonded together for connection.

[0061] Furthermore, the memory chip wiring structure 1210 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip 300 are connected via the memory Si substrate 1200. TSVs 106 are formed in the memory Si substrate 1200 and connected to Cu pads prepared on the underside of the memory Si substrate 1200. These Cu pads are joined to Cu pads formed on the upper surface of the signal processing chip wiring structure 1310 to form CCB joints 2-3-1.

[0062] The pixel selection transistor 117 is connected to the switch transistor 217 via junction 1-2. Furthermore, the reference power supply AGND-1 supplied to the column signal processing circuit is connected to the switch transistor 217 arranged in the memory chip via junction 2-3-2. That is, the power supply wiring that supplies the reference power supply AGND-1 arranged in the memory chip 200 and the power supply wiring that supplies the reference power supply AGND-1 arranged in the signal processing chip 300 are common power supply wiring with junction 2-3-2 sandwiched between them. It can also be said that the fourth wiring that supplies power to the output circuit and the sixth wiring that supplies power to the second readout circuit are connected between the second chip and the third chip.

[0063] 3, by supplying the reference power supply AGND-1 to the memory chip 200 and the signal processing chip 300 through a common power supply wiring, it is possible to reduce the wiring resistance to 1 / 2 compared to when separate wiring is provided for each chip. Below, it will be explained that reducing the resistance of the power supply wiring has an important meaning for the performance of the photoelectric conversion device.

[0064] First, current flows through the power supply wiring supplying the reference power supply AGND-1 due to the current source transistors 216 and 313. For example, when reading out a signal voltage stored in the FD, a current flows through the power supply wiring supplying the reference power supply AGND-1 for each pixel memory 40 operating simultaneously. Similarly, when reading out a signal voltage from the signal storage memory to the signal line VLOUT, a current flows through the power supply wiring supplying the reference power supply AGND-1 for each column signal processing circuit 50 operating simultaneously. When a current flows through the power supply wiring supplying the reference power supply, the voltage fluctuates due to the wiring resistance of each reference power supply, reducing the dynamic range of each circuit. Reducing the dynamic range of the pixel amplifier transistor 111 and memory amplifier transistor 211 that perform the signal readout operation reduces the dynamic range of the signal voltage relative to the amount of incident light, thereby degrading the performance of the photoelectric conversion device. Furthermore, while power supply fluctuations can be reduced by reducing the number of pixel memories 40 and column signal processing circuits 50 operating simultaneously, reducing the number of pixel memories 40 and column signal processing circuits 50 operating simultaneously reduces the frame rate of the photoelectric conversion device.

[0065] Furthermore, as the pixel density of photoelectric conversion devices increases, the pixels 30 become smaller and the pitch between the lines becomes narrower. This increases the parasitic capacitance between the signal voltage readout path and the reference power supply line. Voltage fluctuations in the power supply line that supplies the reference power supply propagate to the signal line, potentially degrading image quality.

[0066] By reducing the power supply wiring resistance, it is possible to suppress power supply fluctuations regardless of the number of pixels 30 that simultaneously perform signal readout operations, and therefore an improvement in frame rate can also be expected.

[0067] In the present embodiment, the fourth wiring and the sixth wiring are connected between the second chip and the third chip, but the combination of the connected wiring and the common reference power supply (voltage) is not limited to this. As long as the voltage magnitude relationship described above is satisfied, it is sufficient that at least two wirings from the first wiring to the sixth wiring are connected between at least two chips among the first chip, the second chip, and the third chip.

[0068] As a modification of the photoelectric conversion device according to this embodiment, a configuration for further reducing wiring resistance is shown in Fig. 8. In addition to the configuration in Fig. 7, the configuration shown in Fig. 8 has a junction 1-2 between the pixel chip 100 and the memory chip 200, and also has a power supply wiring for supplying the reference power supply AGND-1 arranged in the pixel chip wiring structure 1110. In this configuration, the reference power supply AGND-1 is supplied to the three chips, the pixel chip 100, the memory chip 200, and the signal processing chip 300, through a common wiring, which can further reduce wiring resistance.

[0069] Generally, the power supply wiring that supplies the reference power supply is used as shield wiring to prevent crosstalk between signal lines. In stacked chips, signal paths are formed in the depth direction of each chip, so in order to prevent crosstalk between signal lines, it is preferable to provide shield wiring that spans the pixel chip 100, memory chip 200, and signal processing chip 300. In the configuration of Figure 8, a common wiring is formed across the three chips, which is also expected to have the effect of preventing crosstalk between output signals between adjacent pixels 30.

[0070] 9 shows the arrangement of the junctions in FIG. 7 as viewed from above on the pixel chip 100. Four pixels 30 arranged in 2 rows and 2 columns are shown, and junctions 1-2 and 2-3-1, which serve as paths for outputting signals, are arranged in each pixel 30. In consideration of signal crosstalk between adjacent pixels 30, it is desirable that junctions 1-2 and 2-3-1 be arranged at the same pitch.

[0071] Furthermore, TSVs generally tend to have larger diameters than CCBs. Therefore, it is more difficult to narrow the pitch of the junctions when using TSVs than when using CCBs. Therefore, as shown in Figure 9, the junctions 2-3-2 (see Figure 3) may be placed in the center of the 2-row x 2-column pixel array, or if the TSVs can be configured with a diameter small enough relative to the pixel 30, they may be placed in the center of each pixel.

[0072] 10 and 11 show plan views in which the TSV 106 is connected outside the pixel region 110. FIG.

[0073] 10, when the photoelectric conversion device is viewed from above, the pixel region 110, memory region 210, and signal processing unit 310 are arranged to overlap, and each pixel 30 is provided with overlapping junctions 1-2 and 2-3-1. On the other hand, junctions 1-2 and 2-3-1 are not required outside the pixel region 110 and memory region 210. Therefore, it is possible to provide many junctions 2-3-2 for the memory region 210.

[0074] 11, the diameter of the junction 2-3-2 may be larger than the diameter of the junction 2-3-1 in the area that overlaps the memory area 210 in a plan view. Also, one junction 2-3-2 may be shared by multiple column signal processing circuits 50. The number of pixel columns that share the junction and the area of ​​the junction 2-3-2 are not limited.

[0075] As another modification of the photoelectric conversion device according to this embodiment, a cross-sectional view of a photoelectric conversion device in which the stacking direction of the memory chip 200 is different is shown in FIG.

[0076] 12, the pixel chip wiring structure 1110 of the pixel chip 100 and the Si substrate 1200 of the memory chip 200 are bonded to face each other. Also, the memory chip wiring structure 1210 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other.

[0077] A joint 1-2 is formed by bonding a Cu pad provided on pixel chip wiring structure 1110 of pixel chip 100 to a Cu pad arranged on the upper surface of memory Si substrate 1200. The Cu pad on the upper surface of memory Si substrate 1200 is connected to memory chip wiring structure 1210 via TSV 106 that penetrates memory Si substrate 1200. Furthermore, a joint 2-3-2 is formed by bonding a Cu pad arranged on the lower surface of memory chip wiring structure 1210 to a Cu pad provided on the upper surface of signal processing chip wiring structure 1310.

[0078] Even with this configuration, the power supply wiring that supplies the reference power supply AGND-1 can be a common wiring for the memory chip 200 and the signal processing chip 300, and the wiring resistance of the power supply wiring that supplies the reference power supply AGND-1 can be reduced.

[0079] Figure 13 shows the planar arrangement of the junctions 1-2, 2-3-1, and 2-3-2 in the configuration of Figure 12. The plan view of Figure 13 shows a region of this photoelectric conversion device with four pixels 30 arranged in two rows and two columns. The CCB junctions 2-3-1 and 2-3-2 can be made smaller in diameter than the junctions 1-2 formed by TSV. Therefore, unlike Figure 9, the junctions 2-3-2 can be arranged for each pixel 30. In this configuration, the power supply wiring supplying the reference power supply AGND-1 is shared between the memory chip 200 and the signal processing chip 300, thereby achieving low resistance. Therefore, a configuration in which one junction 2-3-2 is arranged for multiple pixels 30 may be used.

[0080] 14 will be used to explain the placement of the junctions 2-3-2 when they are formed in an area that does not overlap with the area where the memory area 210 is arranged. Because the junctions 2-3-2 are CCBs, the pitch of the junctions can be narrower than when the junctions are formed using TSVs. As shown in FIG. 14, multiple junctions 2-3-2 may be placed for one column signal processing circuit 50. Also, as shown in FIG. 11, the area of ​​the junctions 2-3-2 may be increased so that multiple column signal processing circuits 50 share one junction 2-3-2.

[0081] 15 shows an example of a configuration in which the power supply wiring that supplies the reference power supply AGND-1 is shared between the memory chip 200 and the signal processing chip 300, and the power supply wiring that supplies the reference power supply AVDD-1 and the power supply wiring that supplies the reference power supply MVDD are also shared. The power supply wiring that supplies the reference power supply AVDD-1 and the power supply wiring that supplies the reference power supply MVDD are connected by a junction 2-3-3. It can also be said that the third wiring that supplies power to the signal retention memory and the fifth wiring that supplies power to the second readout circuit are connected between the second chip and the third chip.

[0082] With this configuration, the resistance of the wiring that supplies the reference power supply AVDD-1 can also be reduced, and similarly to the reference power supply AGND-1, it is possible to reduce the compression of the dynamic range of the signal voltage due to voltage drop and the noise that propagates to the signal line due to power supply fluctuations. With this configuration, it is possible to reduce the number of pads for supplying the reference power supply that are arranged on the memory chip 200, which is advantageous in terms of reducing the chip size.

[0083] Furthermore, the pads for the reference power supply AGND-1 and the reference power supply AVDD-1 may be provided on the memory chip 200. In this case, the current flowing through each pad can be dispersed.

[0084] (Second embodiment) The photoelectric conversion device according to the second embodiment will be described with reference to Figures 16 to 20. Explanations of the same aspects as the first embodiment will be omitted, and differences from the first embodiment will be mainly described.

[0085] An example circuit of the photoelectric conversion device according to this embodiment is shown in Fig. 16. In this embodiment, the reference power supply SGND supplied to the pixel region 110 is supplied as a reference power supply to the signal retention memories Nmem, Smem-A, and Smem-AB in the memory region 210.

[0086] At this time, the source of switch transistor 217 is connected to the power supply wiring that supplies the reference power supply MGND, and the source of switch transistor 314 is connected to the power supply wiring that supplies the reference power supply AGND-1. The power supply for each chip is the same as in the first embodiment, and the reference power supply MGND is supplied to the current source 230 of memory chip 200 as shown in Fig. 4. In this embodiment, it can also be said that the first wiring that supplies power to the photoelectric conversion unit and the third wiring that supplies power to the signal retention memory are connected between the first chip and the second chip.

[0087] FIG. 17 shows the connection structure of the pixel chip 100, memory chip 200, and signal processing chip 300 of this embodiment.

[0088] 17, the pixel chip wiring structure 1110 of the pixel chip 100 and the memory chip wiring structure 1210 of the memory chip 200 are bonded to face each other. Also, the memory Si substrate 1200 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip 300 are bonded to face each other.

[0089] A power supply wiring (SGND wiring) that supplies a reference power supply SGND is arranged on the pixel chip 100. The SGND wiring is connected to the pixel Si substrate 1100 through contact vias 104, and is supplied as a reference power supply to PD 115, PD 116, and FD. The pixel chip 100 and the memory chip 200 form a joint 1-2-2 where Cu pads are bonded together. The reference power supply SGND is connected to a signal retention memory arranged in the memory chip wiring structure 1210 through the joint 1-2-2.

[0090] The memory chip 200 and the signal processing chip 300 are connected to the joint 2-3 via the TSV 106 that penetrates the memory Si substrate 1200. The joint 2-3 is formed by bonding Cu pads together, and the reference power supply SGND is connected to the circuits arranged on each chip using common wiring between the pixel chip 100 and the memory chip 200.

[0091] In this embodiment, as in the first embodiment, the effect of reducing power supply fluctuations can be achieved by reducing the wiring resistance of the power supply wiring that supplies the reference power supply SGND.

[0092] In this embodiment, the reference power supply for the FD capacitor and the reference power supplies for the signal retention memories Nmem, Smem-A, and Smem-AB are a common power supply. This reduces noise propagating from the reference power supply when writing the output of the amplifier transistor 111 corresponding to the FD capacitor to each signal retention memory. If the reference power supply for the FD capacitor is SGND and the reference power supply for the signal retention memory is MGND, as in the first embodiment, different noises propagate from the reference power supplies SGND and MGND, which are supplied as separate power supplies. When writing the output of the amplifier transistor 111 corresponding to the FD capacitor to the signal retention memories Nmem, Smem-A, and Smem-AB, the fluctuations in the reference power supply for the FD capacitor and the fluctuations in the reference power supply for the signal retention capacitor differ from each other. This means that the signal written to the signal retention capacitor contains a power supply fluctuation component, which is one factor that degrades image quality.

[0093] In addition to noise propagating from the power supply, magnetic noise propagating through the wiring within the chip also has a similar effect on image quality. For example, when a photoelectric conversion device is installed in a camera, the coils used in the lens's stepping motor, etc., generate magnetism. The wiring of each chip may be affected by induced electromotive force, causing voltage fluctuations. Because the pixel chip 100, memory chip 200, and signal processing chip 300 each have different wiring structures, the propagation of this magnetic noise differs depending on the reference power supply connected to them.

[0094] Therefore, if the reference power supply for the FD capacitor and the reference power supply for the signal retention memory are separate power supplies, the signal voltage will be more susceptible to noise. However, in this embodiment, the power supply wiring for both is connected via a joint in close proximity within one pixel area, and the reference power supply for the FD capacitor and the reference power supply for the signal retention memory are the same power supply (reference power supply SGND). This makes the reference power supply fluctuations when writing the signal voltage to the signal retention memory in phase with the FD capacitor and the signal retention memory, reducing the impact of noise on the signal voltage.

[0095] Furthermore, in this embodiment, the reference power supply (reference power supply MGND) that serves as the path of the current flowing from the current source transistor 216 is separate from the reference power supply for the signal retention memory. This prevents fluctuations in the reference power supply MGND from propagating to the signal retention memory when reading out a signal from the pixel 30, that is, when a constant current is flowing through the reference power supply MGND, and suppresses fluctuations in the signal voltage.

[0096] FIG. 18 shows four pixels 30 arranged in two rows and two columns when the photoelectric conversion device of FIG. 7 is viewed from the top surface side of the pixel chip 100.

[0097] The diameters of the junctions 1-2-1 and 1-2-2 can be smaller than that of the junction 2-3 corresponding to the TSV 106 because they are CCBs. Therefore, it is possible to arrange junctions in each pixel 30 as shown in FIG.

[0098] A single junction 1-2-2 may be provided for multiple pixels 30. However, the length of the wiring affects fluctuations in the reference power supply due to magnetism. The greater the distance from the magnetic source to the junction 1-2-2, the greater the magnetic fluctuations in the signal voltage. Therefore, providing a junction 1-2-2 for each pixel 30 is more effective in suppressing signal voltage fluctuations.

[0099] 19 shows a cross-sectional view of a photoelectric conversion device according to a modified example of the present embodiment, in which the power supply wiring for supplying the reference power supply SGND is a common wiring between the pixel chip 100 and the memory chip 200. In the photoelectric conversion device shown in FIG. 19, the stacking direction of the memory chip 200 is different from that of the photoelectric conversion device shown in FIG.

[0100] 19, the pixel chip wiring structure 1110 of the pixel chip 100 and the Si substrate 1200 of the memory chip 200 are bonded to face each other. Also, the memory chip wiring structure 1210 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other.

[0101] The chips are connected by bonding Cu pads. The power supply wiring that supplies the reference power supply SGND is connected to the memory chip wiring structure 1210 via TSV 106 that penetrates the memory Si substrate. As in Figure 17, by using a common power supply wiring that supplies the reference power supply SGND for the pixel chip 100 and the memory chip 200, it is possible to reduce signal voltage fluctuations during the signal write operation to the signal retention memory.

[0102] In the photoelectric conversion device of FIG. 19, four pixels 30 arranged in two rows and two columns when viewed from the top surface side of the pixel chip 100 are shown in FIG.

[0103] The junctions 1-2-1 and 1-2-2 may have a larger area than the CCB junction 2-3 because they are formed by the TSVs 106 that penetrate the memory chip 200. Therefore, for example, one junction 1-2-2 may be provided for multiple pixels 30, as shown in FIG.

[0104] As mentioned above, power supply noise and magnetic noise are superimposed on the reference power supply SGND, but there is also a risk of noise propagating through parasitic capacitance. Therefore, the parasitic capacitance between the power supply wiring and the signal output (wiring) must be minimized. It is desirable to configure the junctions 1-2-1 and 1-2-2 of each pixel 30 so that they are far apart. Therefore, the junctions 1-2-2 may be positioned in the center of the junctions 1-2-1 of the four pixels 30 arranged in a 2-row x 2-column array.

[0105] (Third embodiment) 21 to 26, a photoelectric conversion device according to the third embodiment will be described. Explanations common to the first and second embodiments will be omitted, and differences from the first embodiment will be mainly described.

[0106] 21 shows an example circuit of a photoelectric conversion device according to this embodiment. In this embodiment, a reference power supply SVDD is supplied to the memory chip 200 via junction 1-2-2 and is used as a power supply voltage for the pixel memory 40. Furthermore, a reference power supply AGND-1 of the ADC 311 and the source of the switch transistor 314 are provided by separate power supplies, and a reference power supply MGND-2 supplied to the memory chip 200 is supplied to the source of the switch transistor 314 via junction 2-3-2. It can also be said that a second wiring that supplies power to the first readout circuit and a fourth wiring that supplies power to the output circuit are connected between the first chip and the second chip.

[0107] FIG. 22 shows the configuration of the current source 230 and the current source 330 according to this embodiment.

[0108] The source of the bias generation transistor 231 of the current source 230 is connected to the reference power supply MGND-2 supplied from the memory chip 200, and the drain of the bias generation transistor 231 is connected to the reference current source 232. Similarly, the source of the bias generation transistor 331 of the current source 330 is connected to the reference power supply MGND-2 supplied from the memory chip 200, and the drain of the bias generation transistor 331 is connected to the reference current source 332. The reference current sources 232 and 332 are connected to the reference power supply SVDD supplied from the pixel chip 100.

[0109] At this time, the reference power supply SVDD is supplied to the memory chip 200 and the signal processing chip 300 via the junctions 1-2 and 2-3. The reference power supply MGND-2 is supplied from the memory chip 200 to the signal processing chip 300 via the junctions 2-3 and 2-3-2.

[0110] FIG. 23 shows an example of power supply to each chip of the photoelectric conversion device according to this embodiment.

[0111] The pixel chip 100 is provided with a pad for a reference power supply SVDD and a pad for a reference power supply SGND.

[0112] The memory chip 200 is provided with pads for the reference power supplies MVDD-1 and MVDD-2.

[0113] The signal processing chip 300 is provided with pads for the reference power supplies AVDD-1, AVDD-2, AGND-1, AGND-2, DVDD, and DGND.

[0114] In this embodiment, compared to the wiring structure of FIG. 6 according to the first embodiment, power supply wiring for the reference power supplies MVDD and AVDD-1 to the current source 230 and current source 330 is not required, which simplifies the routing of the power supply wiring and improves the circuit integration efficiency of each chip.

[0115] FIG. 24 shows a cross-sectional view of the photoelectric conversion device according to this embodiment.

[0116] 24, the pixel chip wiring structure 1110 of the pixel chip 100 and the memory chip wiring structure 1210 of the memory chip 200 are bonded to face each other. Also, the Si substrate 1200 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other.

[0117] A Cu pad arranged on the lower surface of the pixel chip wiring structure 1110 and a Cu pad arranged on the upper surface of the memory chip wiring structure 1210 are bonded together to form a junction 1-2-2. A reference power supply SVDD is supplied from the pixel chip 100 to the memory chip 200 via the junction 1-2-2. A reference power supply MGND-2 is supplied from the memory chip 200 to the signal processing chip 300 via a TSV 106 that penetrates the memory Si substrate 1200, a Cu pad arranged on the memory Si substrate 1200, and a Cu pad arranged on the signal processing chip wiring structure 1310. The junctions 1-2 and 2-3 that supply power to the current source 230 and the current source 330 shown in FIG. 22 are also configured using CCBs and TSVs, similar to the junction 1-2-2.

[0118] As in the first embodiment, the above configuration can reduce the resistance of the power supply wiring of the current path flowing through the current source transistor 216 and the current source transistor 313 when reading out the signal voltage, and can suppress voltage fluctuations of the reference power supply.

[0119] The configuration of this embodiment also makes it possible to suppress voltage fluctuations at the drain of the pixel amplifier transistor 111 and the drain of the memory amplifier transistor 211. In this embodiment, the reference power supply MVDD of the first embodiment is shared with the reference power supply SVDD, thereby reducing the number of reference power supplies by one, leading to simplification of the imaging system using the photoelectric conversion device.

[0120] Furthermore, because the reference power supplies AGND-1 and MGND-2 of the ADC311 are separated, the ADC311 is not affected by voltage fluctuations in the reference power supply MGND-2 during read operations. This ensures the dynamic range of the ADC311's operation. VBIAS1 and VBIAS2 fluctuate in conjunction with fluctuations in the reference power supply MGND-2. However, the reference power supplies for the current source 230, current source 330, current source transistor 216, and current source transistor 313 are common to the reference power supply MGND-2. Therefore, the gate-source voltages of the current source transistor 216 and current source transistor 313 and the gate-source voltages of the bias generation transistor 231 and bias generation transistor 331 are always tracked. This reduces current fluctuations during read operations and improves operational stability.

[0121] 21, the reference power supply SVDD is connected to the drain of the pixel reset transistor 112 and the drain of the memory reset transistor 212, but the drains of both transistors may be connected to different reference power supplies. The reference power supply MGND-2 may be supplied from the signal processing chip 300.

[0122] 25, the power supply wiring that supplies the reference power supply MGND-2 may be arranged in the pixel chip wiring structure 1110. In this case, a joint 1-2 is formed to supply the reference power supply MGND-2 to the memory chip 200 in the same way as the reference power supply SVDD. A Cu pad provided on the lower surface of the pixel chip wiring structure 1110 and a Cu pad arranged on the upper surface of the memory chip wiring structure 1210 are bonded together to form the joint 1-2.

[0123] Although the reference power supply MGND-2 is not supplied to the circuit of the pixel chip 100, by using part of the area of ​​the pixel chip wiring structure 1110 as the wiring area for the reference power supply MGND-2, it is possible to further reduce the wiring resistance of the reference power supply MGND-2.

[0124] As a modification of the photoelectric conversion device according to this embodiment, a cross-sectional view of a photoelectric conversion device in which the stacking direction of the memory chip 200 is different is shown in FIG.

[0125] 26, the pixel chip wiring structure 1110 of the pixel chip 100 and the Si substrate 1200 of the memory chip 200 are bonded to face each other. Also, the memory chip wiring structure 1210 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other. A Cu pad arranged on the upper surface of the signal processing chip wiring structure 1310 and a Cu pad arranged on the lower surface of the memory chip wiring structure 1210 are bonded together to form a bonding portion 2-3-2. A reference power supply MGND-2 provided in the wiring of the memory chip wiring structure 1210 is supplied to the signal processing chip 300 via the bonding portion 2-3-2.

[0126] Furthermore, TSVs 106 arranged to penetrate the memory Si substrate 1200 are connected to Cu pads arranged on the upper surface of the memory Si substrate 1200. The Cu pads arranged on the upper surface of the memory Si substrate 1200 are further connected to Cu pads arranged on the lower surface of the pixel chip wiring structure 1110, and the reference power supply SVDD is supplied from the pixel chip 100 to the memory chip 200. The reference power supply MGND-2 is supplied to both the memory chip 200 and the signal processing chip 300 via common wiring for both. This makes it possible to reduce the wiring resistance of the reference power supply SVDD wiring and the reference power supply MGND-2 wiring, which form the current path when reading out the signal voltage, and to suppress voltage fluctuations of each reference power supply.

[0127] (Fourth embodiment) 27 to 32, a photoelectric conversion device according to the fourth embodiment will be described. Explanations common to the first embodiment will be omitted, and differences from the first embodiment will be mainly described.

[0128] An example circuit of the photoelectric conversion device according to this embodiment is shown in Figure 27. In this embodiment, the reference power supply SGND supplied to the pixel chip 100 is connected to the memory chip 200 and the signal processing chip 300 via junctions 1-2-2 and 2-3-2. In other words, the reference power supply SGND serves as a power supply wiring common to all layers of the pixel chip 100, the memory chip 200, and the signal processing chip 300. It can also be said that the first wiring that supplies power to the photoelectric conversion unit and the third wiring that supplies power to the signal retention memory are connected between the first chip and the second chip, and the third wiring and the fifth wiring that supplies power to the second readout circuit are connected between the second chip and the third chip.

[0129] 28 shows the configurations of the current source 230 and the current source 330. The reference power supply SGND supplied from the pixel chip 100 is supplied to the current source 230 via the junction 1-2. Similarly, the reference power supply SGND is supplied to the current source 330 via the junction 2-3.

[0130] FIG. 29 shows an example of power supply to each chip of the photoelectric conversion device according to this embodiment.

[0131] The pixel chip 100 is provided with a pad for a reference power supply SVDD and a pad for a reference power supply SGND.

[0132] The memory chip 200 is provided with a pad for the reference power supply MVDD.

[0133] The signal processing chip is equipped with pads for the reference power supply AVDD-1, reference power supply AVDD-2, reference power supply AGND-2, reference power supply DVDD, and reference power supply DGND.

[0134] 6, in this embodiment, the PAD that supplies the reference power supply MGND to the memory chip and the PAD that supplies the reference power supply AGND-1 to the signal processing chip 300 can be eliminated. That is, the power supply wiring for the memory chip 200 and the signal processing chip 300 can be simplified. Here, the PAD that supplies the reference power supply SGND may be provided in the memory chip 200 or the signal processing chip 300 instead of in the pixel chip 100.

[0135] FIG. 30 shows a cross-sectional view of the photoelectric conversion device according to this embodiment.

[0136] 30, the pixel chip wiring structure 1110 of the pixel chip 100 and the memory chip wiring structure 1210 of the memory chip 200 are bonded to face each other. Also, the Si substrate 1200 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other.

[0137] A wiring for a reference power supply SGND provided in the pixel chip wiring structure 1110 is connected to a Cu pad arranged on the underside of the pixel chip wiring structure 1110 via a contact via 104. The Cu pad is bonded to a Cu pad arranged on the upper surface of the memory chip wiring structure 1210 to form a joint 1-2-2. A TSV 106 penetrating the memory Si substrate 1200 is connected to the Cu pad arranged on the underside of the memory Si substrate 1200. The Cu pad arranged on the underside of the memory Si substrate 1200 is further connected to a Cu pad arranged on the upper surface of the signal processing chip wiring structure 1310, and the reference power supply SGND is supplied from the memory chip wiring structure 1210 to the signal processing chip 300. The reference power supply SGND serves as a common reference power supply for the pixel chip wiring structure 1110, the memory chip wiring structure 1210, and the signal processing chip wiring structure 1310, making it possible to reduce the wiring resistance of the reference power supply SGND.

[0138] By reducing the resistance of the power supply wiring for the reference power supply SGND, it is possible to reduce voltage fluctuations in the reference power supply SGND. In addition, because the reference power supply connected to the FD capacitor and the reference power supply connected to the signal retention memory are a common reference power supply SGND, signal voltage fluctuations due to noise superimposed on the reference power supply can be suppressed, as shown in the second embodiment.

[0139] As a modification of the photoelectric conversion device according to this embodiment, a cross-sectional view of a photoelectric conversion device in which the stacking direction of the memory chip 200 is different is shown in FIG.

[0140] 31, the pixel chip wiring structure 1110 of the pixel chip 100 and the Si substrate 1200 of the memory chip 200 are bonded to face each other. Also, the memory chip wiring structure 1210 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other.

[0141] A Cu pad arranged on the upper surface of the signal processing chip wiring structure 1310 and a Cu pad arranged on the lower surface of the memory chip wiring structure 1210 are bonded together to form a joint 2-3-1. A TSV 106 penetrating the memory Si substrate 1200 is connected to a Cu pad arranged on the upper surface of the memory Si substrate. This Cu pad is bonded to a Cu pad on the lower surface of the pixel chip wiring structure 1110 to form a joint 2-3-2. As a result, the reference power supply SGND becomes a common reference power supply for the pixel chip wiring structure 1110, the memory chip wiring structure 1210, and the signal processing chip wiring structure 1310, and it is possible to reduce the resistance of the wiring for the reference power supply SGND.

[0142] FIG. 32 shows four pixels 30 arranged in two rows and two columns when the photoelectric conversion device of FIG. 30 is viewed from the top surface side of the pixel chip 100.

[0143] The reference power supply SGND is supplied through a common power supply wiring for the entire chip, so junctions 1-2-2 and 2-3-2 are necessary. Arranging these junctions for each pixel 30 would impose significant area constraints. Therefore, as shown in FIG. 32, for example, junctions 1-2-2 and 2-3-2 are arranged in the center of four pixels arranged in two rows and two columns. In this case, junctions 1-2-2 and 2-3-2 are arranged between junctions 1-2-1 and 2-3-1, which are the paths through which the signal voltages of each pixel are output. Furthermore, as shown in FIG. 30, the power supply wiring that supplies the reference power supply SGND runs from the pixel chip 100 through the memory chip 200 and then through the signal processing chip 300. This wiring also functions as a shielding wiring to prevent crosstalk of signal voltages between adjacent pixels 30.

[0144] When the configuration shown in Figure 31 is adopted, the area of ​​joints 2-3-1 and 2-3-2 is smaller than that of joints 1-2-1 and 1-2-2, but joints 1-2-2 and 2-3-2 are arranged between joints 1-2-1 and 2-3-1 as shown in Figure 32.

[0145] In addition to this configuration, the reference power supplies SVDD, MVDD, and AVDD-1 may be a common reference power supply that uses common wiring. In that case, a junction 1-2 that connects the reference power supply SVDD and MVDD is provided on the junction surface between the pixel chip 100 and the memory chip 200, similar to the supply path of the reference power supply SGND. Furthermore, a junction 2-3 that connects the reference power supply MVDD and AVDD-1 is provided on the junction surface between the memory chip 200 and the signal processing chip 300, similar to the supply path of the reference power supply SGND. This makes it possible to reduce the number of pads that supply the reference power supplies MVDD and AVDD-1 shown in FIG. 29, thereby further simplifying the wiring structure.

[0146] (Fifth embodiment) 33 to 37, a photoelectric conversion device according to the fifth embodiment will be described. Explanations common to the first embodiment will be omitted, and differences from the first embodiment will be mainly described.

[0147] An example circuit of a photoelectric conversion device according to this embodiment is shown in Fig. 33. In this embodiment, a pixel drive buffer 121 for controlling the gates of the pixel reset transistors 112 of the pixels 30 in the nth row via a control wiring pres[n] is disposed in the vertical scanning circuit. Also, a memory drive buffer 221 for driving the gates of the memory reset transistors 212 of the pixels 30 in the nth row via a control wiring mres[n] is disposed in the memory vertical scanning circuit.

[0148] The reference power supply VRESH and the reference power supply VRESL supplied to the pixel driving buffer 121 are supplied from the pixel chip 100 and are supplied to the memory driving buffer 221 via the junctions 1-2-2 and 1-2-3.

[0149] 34 shows circuit examples of the pixel drive buffer 121 and memory drive buffer 221. Each of the pixel drive buffer 121 and memory drive buffer 221 has an inverter configuration in which a P-type transistor and an N-type transistor are connected vertically, with the source of the P-type transistor connected to a reference power supply VRESH and the source of the N-type transistor connected to a reference power supply VRESL. A signal input to the terminal where the gates of the P-type transistor and the N-type transistor are connected to each other is output as control wiring pres[n] and control wiring mres[n].

[0150] An example of power supply to each chip of the photoelectric conversion device according to this embodiment is shown in FIG.

[0151] A pad for a reference power supply VRESH and a pad for a reference power supply VRESL are arranged on the pixel chip 100. The reference power supply VRESH and the reference power supply VRESL are supplied to a pixel drive buffer 121. Note that the pads for the reference power supply VRESH and the reference power supply VRESL may be provided on the memory chip 200.

[0152] The signal processing chip 300 may be supplied with power from any PAD, and therefore a detailed explanation will be omitted.

[0153] A cross-sectional view of the photoelectric conversion device according to this embodiment is shown in Fig. 36. In the photoelectric conversion device according to Fig. 36, the pixel chip wiring structure 1110 of the pixel chip 100 and the memory chip wiring structure 1210 of the memory chip 200 are bonded to face each other. Also, the Si substrate 1200 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other.

[0154] The Cu pads arranged on the lower surface of the pixel chip wiring structure 1110 and the Cu pads arranged on the upper surface of the memory chip wiring structure are bonded together to form joints 1-2-2 and 1-2-3. As a result, the power supply wiring of the pixel chip 100 and the power supply wiring of the memory chip 200 are connected by the joints to form a common power supply wiring. In other words, the reference power supplies VRESH and VRESL supplied from the pads provided on the pixel chip or memory chip can be used as a common reference power supply for the pixel chip 100 and the memory chip 200.

[0155] When the pixel reset transistor 112 and the memory reset transistor 212 are driven by the control lines pres[n] and mres[n], the voltage is changed between the reference power supply VRESH and the reference power supply VRESL. Therefore, current flows from the power supply wiring for the reference power supply VRESH and the power supply wiring for the reference power supply VRESL. The power supply wiring for the reference power supply VRESH and the reference power supply VRESL is shared between the pixel chip 100 and the memory chip 200, reducing the wiring resistance. This reduces voltage fluctuations and ensures the driving stability of the pixel reset transistor 112 and the memory reset transistor 212. When considering the entire device, the current required to drive these transistors increases as the number of pixels 30 and pixel memories 40 increases. Therefore, increasing the number of pixels in a photoelectric conversion device requires reducing the resistance of the power supply wiring that supplies the reference power supply to the driving buffer. Therefore, the configuration of this embodiment is advantageous for increasing the number of pixels.

[0156] Note that a color filter 102 is formed on the light incident surface side of the photoelectric conversion device shown in Figure 36, but a microlens 103 is not provided. This is because the circuit described in this embodiment is arranged outside the pixel area. The color filter 102 is not essential, but is shown here because the color filter 102 may be arranged over the entire light incident surface of the photoelectric conversion device. Similar to the color filter 102, a microlens 103 may also be provided in the configuration of Figure 36.

[0157] As a variation of the photoelectric conversion device according to this embodiment, a cross-sectional view of a photoelectric conversion device in which the stacking direction of the memory chip 200 is different is shown in Figure 37. In the photoelectric conversion device according to Figure 37, the pixel chip wiring structure 1110 of the pixel chip 100 and the Si substrate 1200 of the memory chip 200 are bonded so as to face each other. Also, the memory chip wiring structure 1210 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded so as to face each other.

[0158] Power supply wiring provided in pixel chip wiring structure 1110 for supplying reference power supply VRESH is connected to a Cu pad arranged on the underside of pixel chip wiring structure 1110 via contact via 104. Similarly, power supply wiring provided in pixel chip wiring structure 1110 for supplying reference power supply VRESL is connected to a Cu pad arranged on the underside of pixel chip wiring structure 1110 via contact via 104. Furthermore, memory chip wiring structure 1210 is connected to a Cu pad arranged on the upper surface of memory Si substrate 1200 via TSV 106 that penetrates memory Si substrate 1200. These Cu pads are bonded together to form joints 1-2-2 and 1-2-3.

[0159] The power supply wiring of the pixel chip 100 and the memory chip 200 is connected by junctions 1-2-2 and 1-2-3 to form a common power supply wiring, and the reference power supply VRESH and the reference power supply VRESL each serve as a common reference power supply for the pixel chip 100 and the memory chip 200. This makes it possible to reduce the wiring resistance in the power supply wiring that supplies the reference power supply VRESH and the power supply wiring that supplies the reference power supply VRESL.

[0160] (Sixth embodiment) 38 to 42, a photoelectric conversion device according to the sixth embodiment will be described. Explanations common to the first embodiment will be omitted, and differences from the first embodiment will be mainly described.

[0161] In this embodiment, a description will be given of the logic circuits arranged on each chip, the counter circuit 317 included in the column signal processing circuit 50, and the reference power supply DVDD and reference power supply DGND supplied to the digital processing unit 318. The logic circuits include, for example, the pixel control circuit 20, the memory control circuit 21, and the signal processing control circuit 22. These circuits are configured with general digital circuits, and therefore, the specific circuit configuration is not limited.

[0162] The method of supplying power to each chip is shown in Figure 38. A PAD that supplies the reference power supply DVDD and a PAD that supplies the reference power supply DGND are arranged in the signal processing chip 300. The reference power supply DVDD and the reference power supply DGND are supplied to the counter circuit 317 and the digital processing unit 318 of the signal processing unit 310. The reference power supply DVDD and the reference power supply DGND are also supplied to the signal processing digital circuit unit 350, which includes the signal processing control circuit 22 and the column control circuit 320.

[0163] In the memory chip 200, a reference power supply DVDD and a reference power supply DGND are supplied to the memory digital circuit section 250 via the joint section 2-3. The memory digital circuit section 250 includes a memory control circuit 21 and a memory vertical scanning circuit 220.

[0164] In the pixel chip 100, a reference power supply DVDD and a reference power supply DGND are supplied to a pixel digital circuit unit 150 via a joint 1-2. The pixel digital circuit unit 150 includes a pixel control circuit 20 and a vertical scanning circuit 120.

[0165] A cross-sectional view of a photoelectric conversion device according to this embodiment is shown in Fig. 39. In the photoelectric conversion device of Fig. 39, the pixel chip wiring structure 1110 of the pixel chip 100 and the memory chip wiring structure 1210 of the memory chip 200 are bonded to face each other. Also, the Si substrate 1200 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other.

[0166] The reference power supply DVDD and the reference power supply DGND are supplied to the signal processing chip 300 via PADs provided in the signal processing chip wiring structure 1310. Corresponding Cu pads arranged on the underside of the memory Si substrate 1200 are bonded to the respective Cu pads provided on the signal processing chip wiring structure 1310, forming joints 2-3. The Cu pads arranged on the underside of the memory Si substrate 1200 are connected to the memory chip wiring structure 1210 via TSVs 106 that penetrate the memory Si substrate 1200, and the wiring of the memory chip 200 is connected to the Cu pads arranged on the upper side via contact vias 104. These Cu pads are each bonded to a Cu pad arranged on the pixel chip wiring structure, forming joints 1-2.

[0167] By forming the junctions 1-2 and 2-3 in this way, the reference power supply DVDD and the reference power supply DGND become common reference power supplies for all of the pixel chip 100, the memory chip 200, and the signal processing chip 300. This makes it possible to reduce the pads of the pixel chip 100 and the memory chip 200.

[0168] Furthermore, digital circuits generally tend to generate noise in signal voltages. Therefore, if the reference power supply supplied to the signal voltage readout circuit has parasitic capacitance, noise may propagate to the signal voltage. In this embodiment, it is possible to reduce the power supply wiring that supplies the reference power supply DVDD and the reference power supply DGND from the PAD of the pixel chip 100 or the memory chip 200 to the circuits within each chip, thereby reducing the propagation of noise from the reference power supply DVDD and the reference power supply DGND.

[0169] As a modification of the photoelectric conversion device according to this embodiment, a cross-sectional view of a photoelectric conversion device in which the stacking direction of the memory chip 200 is different is shown in FIG.

[0170] 40, the pixel chip wiring structure 1110 of the pixel chip 100 and the Si substrate 1200 of the memory chip 200 are bonded to face each other. Also, the memory chip wiring structure 1210 of the memory chip 200 and the signal processing chip wiring structure 1310 of the signal processing chip are bonded to face each other.

[0171] The reference power supply DVDD and the reference power supply DGND are each supplied to the signal processing chip 300 via a pad provided in the signal processing chip wiring structure 1310. The power supply wiring for the reference power supply DVDD and the power supply wiring for the reference power supply DGND in the signal processing chip wiring structure 1310 are each connected via a contact via 104 to a Cu pad arranged on the upper surface of the signal processing chip wiring structure 1310. These Cu pads and Cu pads arranged on the lower surface of the memory Si substrate 1200 are bonded together to form joints 2-3.

[0172] The wiring of the memory chip wiring structure 1210 is connected to a Cu pad arranged on the memory Si substrate 1200 via a TSV 106 that penetrates the memory Si substrate 1200. This Cu pad is bonded to a Cu pad arranged on the pixel chip wiring structure 1110, forming a joint 1-2.

[0173] This allows the reference power supply DVDD and the reference power supply DGND to be a common reference power supply for the pixel chip 100, the memory chip 200, and the signal processing chip 300. In other words, similar to the photoelectric conversion device in Fig. 39, it is possible to obtain the effect of reducing the propagation of noise from the reference power supply DVDD and the reference power supply DGND.

[0174] 41 will now be used to explain a photoelectric conversion device in which power supply wiring for supplying the reference power supply DVDD and the reference power supply DGND to the memory chip 200 is not provided. For example, a configuration is assumed in which the memory digital circuit unit 250 is integrated into the pixel digital circuit unit 150 or the signal processing digital circuit unit 350, and the reference power supply DVDD and the reference power supply DGND are not provided on the memory chip 200.

[0175] 41 differs from the photoelectric conversion device shown in Fig. 39 in that the Cu pad constituting bonding portion 1-2 and the Cu pad constituting bonding portion 2-3 are connected by TSV 106 that penetrates memory Si substrate 1200 and memory chip wiring structure 1210. The photoelectric conversion device of Fig. 41 allows the power supply wiring that supplies reference power supply DVDD and the power supply wiring that supplies reference power supply DGND to be common wiring in pixel chip wiring structure 1110 and signal processing chip wiring structure 1310.

[0176] 41 can reduce the number of digital circuits in the memory chip 200, thereby suppressing noise from the digital circuits from propagating to the reference power supply in the memory chip 200. This is expected to have the effect of improving the quality of the signal voltage.

[0177] As a variation of the photoelectric conversion device of FIG. 41, a cross-sectional view of a photoelectric conversion device in which the stacking direction of memory chips 200 is different is shown in FIG.

[0178] In FIG. 42, similarly to FIG. 41, a TSV 106 penetrating the memory Si substrate 1200 and the memory chip wiring structure 1210 is arranged to connect the Cu pad constituting the junction 1-2 and the Cu pad constituting the junction 2-3. The pixel chip wiring structure 1110 and the signal processing chip wiring structure 1310 can share the power supply wiring via junctions 1-2 and 2-3 to provide a common reference power supply for the reference power supply DVDD and the reference power supply DGND. In other words, similar to the photoelectric conversion device of FIG. 41, noise reduction and improved signal voltage quality can be achieved. Furthermore, propagation of noise from the digital circuit to the reference power supply within the memory chip 200 can be suppressed, which is expected to improve the quality of the signal voltage.

[0179] (Seventh embodiment) The seventh embodiment can be applied to any of the first to sixth embodiments. FIG. 43(a) is a schematic diagram illustrating a device 9191 including a semiconductor device 930 of this embodiment. The photoelectric conversion device of each of the above-described embodiments can be used for the semiconductor device 930. The device 9191 including the semiconductor device 930 will be described in detail. In addition to the semiconductor device 910, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device 910.

[0180] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0181] The portion including at least one of the processing device 960, the display device 970, the storage device 980, and the mechanical device 990 is a processing unit having the function of processing the signal from the semiconductor device 930 and generating an image.

[0182] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0183] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0184] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0185] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0186] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0187] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0188] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 43(b) and 43(c).

[0189] FIG. 43(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device (image capture device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0190] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0191] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear.

[0192] 43(c) shows a photoelectric conversion system when capturing an image of the area ahead of the vehicle (image capturing range 850). A vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0193] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0194] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0195] The disclosure of this embodiment includes the following configurations and methods.

[0196] (Configuration 1) The photoelectric conversion device includes a first chip including a first semiconductor layer having a photoelectric conversion unit and a first readout circuit that reads out a signal based on the photoelectric conversion of the photoelectric conversion unit, and a first wiring structure electrically connecting the photoelectric conversion unit and the first readout circuit. The photoelectric conversion device includes a second chip including a second semiconductor layer having a memory that holds a voltage corresponding to the signal and an output circuit that outputs the voltage held by the memory, and a second wiring structure electrically connecting the memory and the output circuit. The photoelectric conversion device includes a third chip including a third semiconductor layer having a second readout circuit that reads out a signal corresponding to the held voltage, and a third wiring structure electrically connected to the second readout circuit. The first wiring structure includes a first wiring that supplies power to the photoelectric conversion unit and a second wiring that supplies power to the first readout circuit. The second wiring structure includes a third wiring that supplies power to the memory and a fourth wiring that supplies power to the output circuit. The third wiring structure includes a fifth wiring that supplies a first power supply to the second readout circuit and a sixth wiring that supplies a second power supply different from the first power supply to the second readout circuit. At least two wirings among the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring are connected between at least two chips among the first chip, the second chip, and the third chip.

[0197] (Configuration 2) 2. The photoelectric conversion device according to configuration 1, wherein the first wiring and the third wiring are connected.

[0198] (Configuration 3) 3. The photoelectric conversion device according to configuration 2, wherein the third wiring and the fifth wiring are connected.

[0199] (Configuration 4) 4. The photoelectric conversion device according to claim 1, wherein the second wiring and the fourth wiring are connected to each other.

[0200] (Configuration 5) 5. The photoelectric conversion device according to configuration 4, wherein the fourth wiring and the sixth wiring are connected.

[0201] (Configuration 6) The photoelectric conversion device described in any one of structures 1 to 5, characterized in that the first semiconductor layer has a pixel region in which the photoelectric conversion unit is arranged, and a junction to which the at least two wirings are connected is arranged in a region that overlaps the pixel region in a planar view.

[0202] (Configuration 7) The photoelectric conversion device according to configuration 2, wherein the first semiconductor layer has a pixel amplification transistor that amplifies a signal output from the photoelectric conversion unit, and the second semiconductor layer has a memory amplification transistor that amplifies a signal output from the memory, the first wiring supplies power to the pixel amplification transistor, and the third wiring supplies power to the memory amplification transistor.

[0203] (Configuration 8) 8. The photoelectric conversion device according to any one of Structures 1 to 7, wherein the third wiring supplies power to both the memory and a current source that supplies a reference current to the memory.

[0204] (Configuration 9) The photoelectric conversion device according to any one of configurations 1 to 8, wherein the at least two wirings connected between the first chip and the second chip are disposed on the third chip.

[0205] (Configuration 10) A photoelectric conversion device described in any one of configurations 1 to 7, characterized in that the wiring arranged in the first wiring structure and the wiring arranged in the third wiring structure are connected via a through electrode that penetrates the second semiconductor layer.

[0206] (Configuration 11) 11. A photoelectric conversion system comprising: the photoelectric conversion device according to any one of configurations 1 to 10; and a processing unit that generates an image using a signal output by the photoelectric conversion device.

[0207] (Configuration 12) A moving object including the photoelectric conversion device according to any one of configurations 1 to 10, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device. [Explanation of symbols]

[0208] 10 Photoelectric conversion device 20 Pixel control circuit 21 Memory control circuit 22 Signal processing control circuit 30 pixels 40 pixel memory 50 Column signal processing circuit 1-2 Joint 2-3 Joint

Claims

1. a first semiconductor layer having a photoelectric conversion unit and a first readout circuit that reads out a signal based on photoelectric conversion of the photoelectric conversion unit; a first chip including a first wiring structure electrically connected to the photoelectric conversion unit and the first readout circuit; a second semiconductor layer having a memory that holds a voltage corresponding to the signal and an output circuit that outputs the voltage held in the memory; a second chip including a second wiring structure electrically connected to the memory and the output circuit; a third semiconductor layer having a second readout circuit that reads out a signal corresponding to the held voltage; a third chip including a third wiring structure electrically connected to the second readout circuit, the first wiring structure includes a first wiring that supplies power to the photoelectric conversion unit and a second wiring that supplies power to the first readout circuit; the second wiring structure includes a third wiring that supplies power to the memory and a fourth wiring that supplies power to the output circuit; the third wiring structure includes a fifth wiring that supplies a first power supply to the second readout circuit, and a sixth wiring that supplies a second power supply different from the first power supply to the second readout circuit; A photoelectric conversion device characterized in that at least two of the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring are connected between at least two of the first chip, the second chip, and the third chip.

2. 2. The photoelectric conversion device according to claim 1, wherein the first wiring and the third wiring are connected to each other.

3. 3. The photoelectric conversion device according to claim 2, wherein the third wiring and the fifth wiring are connected to each other.

4. The photoelectric conversion device according to claim 1 , wherein the second wiring and the fourth wiring are connected to each other.

5. 5. The photoelectric conversion device according to claim 4, wherein the fourth wiring and the sixth wiring are connected to each other.

6. the first semiconductor layer has a pixel region in which the photoelectric conversion unit is arranged, 2. The photoelectric conversion device according to claim 1, wherein a junction portion where the at least two wirings are connected is disposed in a region that overlaps the pixel region in a plan view.

7. the first semiconductor layer has a pixel amplification transistor that amplifies a signal output from the photoelectric conversion unit, the second semiconductor layer has a memory amplifying transistor that amplifies a signal output from the memory; the first wiring supplies power to the pixel amplification transistor; 3. The photoelectric conversion device according to claim 2, wherein the third wiring supplies power to the memory amplification transistor.

8. 2. The photoelectric conversion device according to claim 1, wherein the third wiring supplies power to both the memory and a current source that supplies a reference current to the memory.

9. 2. The photoelectric conversion device according to claim 1, wherein the at least two wirings connected between the first chip and the second chip are disposed on the third chip.

10. The photoelectric conversion device according to claim 1, wherein the wiring arranged in the first wiring structure and the wiring arranged in the third wiring structure are connected via a through electrode that penetrates the second semiconductor layer.

11. The photoelectric conversion device according to any one of claims 1 to 10; a processing unit that generates an image using a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

12. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 10, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

Images