Photoelectric conversion device and instrument

Abstract

To provide a photoelectric conversion device having higher performance.SOLUTION: A photoelectric conversion device comprises a first substrate having a pixel array, a second substrate having a memory array that holds analog signals output from the pixel array, and a third substrate having an analog-to-digital (AD) conversion circuit that converts the analog signals output from the memory array into digital signals. The second substrate includes at least one memory control circuit for controlling the memory array, and the first substrate or the third substrate includes at least one pixel control circuit for controlling the pixel array.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and equipment. [Background technology]

[0002] Patent Document 1 proposes an image sensor equipped with a so-called global shutter function that has a charge storage section that temporarily stores signal charge and transfers signal charge from the photoelectric conversion section to the charge storage section simultaneously for multiple pixels. By using the global shutter function, it is possible to align the signal accumulation timing in the photoelectric conversion section for multiple pixels, thereby suppressing distortion of the subject image when photographing a fast-moving subject. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-51548 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the image sensor with a global shutter function disclosed in Patent Document 1, Patent Document 1 does not take into consideration that simultaneously driving multiple pixels may affect the operation of other circuits that are operating at the same time.

[0005] An object of the present invention is to provide a photoelectric conversion device with higher performance. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device comprising: a first substrate having a pixel array; a second substrate having a memory array that holds analog signals output by the pixel array; and a third substrate having an analog-to-digital (AD) conversion circuit that converts the analog signals output by the memory array into digital signals, wherein the second substrate has at least one memory control circuit that controls the memory array, and the first substrate or the third substrate has at least one pixel control circuit that controls the pixel array. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a photoelectric conversion device with higher performance. [Brief explanation of the drawings]

[0008] [Figure 1] Schematic diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 3] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 4] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 5] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 6] 1 is a driving timing chart illustrating a photoelectric conversion device according to a first embodiment; [Figure 7] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first modification of the first embodiment. [Figure 8] FIG. 10 is a block diagram illustrating a photoelectric conversion device according to a second modification of the third embodiment. [Figure 9] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 10] 10 is a driving timing chart illustrating a photoelectric conversion device according to a second embodiment. [Figure 11] FIG. 10 is a block diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 12] FIG. 10 is a schematic diagram illustrating a device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar components are given the same reference numerals, and redundant description will be omitted. Also, in the following embodiments, an imaging sensor will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an imaging sensor and can be applied to other examples of photoelectric conversion devices. Examples include an imaging device, a range finder (a device for measuring distance using focus detection or TOF (Time Of Flight)), and a photometric device (a device for measuring the amount of incident light).

[0010] In this specification, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is acceptable as long as they are electrically connected.

[0012] In this specification, "plane" refers to a surface parallel to the main surface of a substrate. The main surface of a substrate may be the light incident surface of a substrate including a photoelectric conversion element, a surface on which multiple ADCs are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device. Furthermore, "planar view" refers to a view from a direction perpendicular to the main surface of the substrate. Furthermore, "cross section" refers to a surface perpendicular to the light incident surface of a semiconductor layer. Furthermore, "cross section" refers to a view from a direction parallel to the main surface of the substrate.

[0013] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals. Furthermore, the wiring and pads shown here are merely examples of metallic components used in photoelectric conversion devices and may also be applied to other metallic components.

[0014] First Embodiment A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG.

[0015] FIG. 1 is a schematic diagram of an example of a photoelectric conversion device according to this embodiment.

[0016] 1, the photoelectric conversion device 10 includes three substrates: a first substrate 100, a second substrate 200, and a third substrate 300. The photoelectric conversion device 10 has a three-dimensional structure formed by bonding these three substrates together. The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order.

[0017] The first substrate 100, the second substrate 200, and the third substrate 300 may each be a semiconductor substrate such as a silicon substrate. The first substrate 100, the second substrate 200, and the third substrate 300 may be approximately equal in size. The relationship of "approximately equal" here will be explained. Although they are designed to be equal, slight differences may occur due to manufacturing errors. This slight difference caused by manufacturing errors is included in the term "approximately equal."

[0018] FIG. 2 is an example of a block diagram of the photoelectric conversion device according to this embodiment.

[0019] As shown in Fig. 2, the first substrate 100 has a pixel array 101, a pixel control circuit 102, and a control line 103. The pixel array 101 has a plurality of pixels 110 that perform photoelectric conversion, and the plurality of pixels 110 are arranged across a plurality of rows and a plurality of columns within the pixel array 101. Each of the plurality of pixels 110 includes a photoelectric conversion element that generates and accumulates a signal charge according to the amount of received light, and outputs a pixel signal according to the amount of incident light. Note that the pixel signal output from the pixel 110 is an analog signal.

[0020] In this specification, the horizontal direction in the drawings is referred to as the row direction, and the vertical direction is referred to as the column direction. The number of rows and the number of columns of the multiple pixels 110 arranged in the pixel array 101 are not particularly limited. The multiple pixels 110 may include effective pixels that output pixel signals according to the amount of incident light, as well as optical black pixels whose photoelectric conversion elements are shielded from light, dummy pixels that do not output signals, and the like.

[0021] Additionally, a plurality of control lines 103 are arranged in each row of the pixel array 101, extending in the row direction. Each of the plurality of control lines 103 is connected to a plurality of pixels 110 arranged in the row direction. One control line 103 commonly controls the plurality of pixels 110 arranged in each row. A pixel control circuit 102 supplies a control signal to each pixel 110 via the control line 103. A voltage SVDD serving as a power supply voltage and a voltage SGND serving as a reference voltage are supplied to the pixel array 101 and the pixel control circuit 102.

[0022] The second substrate 200 has a memory array 201, a memory control circuit 202, and a control line 203. The memory array 201 has a plurality of memory circuits 210 that hold pixel signals output from a plurality of pixels 110, and the plurality of memory circuits 210 are arranged across a plurality of rows and a plurality of columns within the memory array 201. Note that a pixel signal output from a pixel 110 arranged in a certain row and a certain column may be held by a memory circuit 210 arranged in the same row and column as the row and column in which the pixel 110 is arranged.

[0023] Furthermore, a plurality of control lines 203 are arranged in each row of the memory array 201, extending in the row direction. Each of the plurality of control lines 203 is connected to a plurality of memory circuits 210 arranged in the row direction. One control line 203 commonly controls the plurality of memory circuits 210 arranged in each row. The memory control circuit 202 supplies a control signal to each memory circuit 210 via the control line 203. The memory array 201 and the memory control circuit 202 are supplied with a voltage MVDD, which is a power supply voltage, and a voltage MGND, which is a reference voltage.

[0024] The third substrate 300 has a signal processing circuit 301, a column memory circuit 302, a horizontal scanning circuit 303, a column circuit control circuit 304, a timing control circuit 305, an output circuit 306, a control line 307, and a horizontal output line 308. The signal processing circuit 301 includes a column circuit 310 corresponding to each pixel column. The column circuit 310 performs predetermined signal processing, such as amplification and analog-to-digital (AD) conversion, on pixel signals read out from the memory circuit 210 arranged in the corresponding column. The AD conversion method can be any of various methods, such as slope-type AD conversion, successive approximation-type AD conversion, and ΔΣ-type AD conversion.

[0025] Furthermore, the signal processing circuit 301 is provided with control lines 307 extending in the row direction. The control lines 307 are connected to a plurality of column circuits 310 arranged in the row direction. The control lines 307 commonly control the plurality of column circuits 310. The column circuit control circuit 304 supplies control signals to each column circuit 310 via the control lines 307. The column memory circuit 302 holds the pixel signals after the column circuits 310 have processed them.

[0026] The horizontal scanning circuit 303 includes logic circuits such as a shift register and an address decoder. The horizontal scanning circuit 303 generates control signals for reading pixel signals from the column memory circuits 302 and supplies the control signals to the column memory circuits 302. The horizontal scanning circuit 303 sequentially scans the column memory circuits 302 and inputs the pixel signals held in the column memory circuits 302 to the output circuit 306 via horizontal output lines 308. The timing control circuit 305 supplies control signals to the pixel control circuit 102, the memory control circuit 202, the column memory circuits 302, the horizontal scanning circuit 303, the column circuit control circuit 304, and the output circuit 306. The signal processing circuit 301 is supplied with a voltage AVDD which is a power supply voltage and a voltage AGND which is a reference voltage.

[0027] The output circuit 306 includes a buffer amplifier, a differential amplifier, etc., and performs predetermined signal processing on pixel signals output from the pixels 110 in the column selected by the horizontal scanning circuit 303, and outputs the processed image data. Examples of signal processing performed by the output circuit 306 include correction processing using correlated double sampling (CDS) and amplification processing. The output circuit 306 also includes an LVDS (Low Voltage Differential Signal) serial output circuit, and outputs the processed digital signal to the outside of the photoelectric conversion device at high speed and with low power consumption. Note that the output method is not limited to LVDS, and other methods may be used.

[0028] FIG. 3 is an example of a block diagram of the pixel control circuit 102 included in the photoelectric conversion device according to this embodiment.

[0029] As shown in FIG. 3, the pixel control circuit 102 includes a pixel row selection circuit 120 and a pixel output circuit 121. The pixel output circuit 121 includes a first pixel buffer circuit 122, a second pixel buffer circuit 123, and a third pixel buffer circuit 124. Control signals PRES, PTX, and PSEL are input to the pixel control circuit 102 from the timing control circuit 305. An address signal ADDP is input to the pixel row selection circuit 120 from the timing control circuit 305. The pixel row selection circuit 120 inputs a row selection signal to the pixel output circuit 121 based on the address signal ADDP. The first pixel buffer circuit 122, the second pixel buffer circuit 123, and the third pixel buffer circuit 124 supply the control signals PRES, PTX, and PSEL to the pixels 110 arranged in the row selected by the row selection signal via the control lines 103, respectively. A voltage SVDD and a voltage SGND are supplied to the pixel control circuit 102, which become the high-level voltage and the low-level voltage in the control signals output by the pixel output circuit 121, respectively. Note that when the control signal is at the high level, each corresponding transistor is in the on state, and when the control signal is at the low level, each corresponding transistor is in the off state. Note that the low-level voltage is not limited to the voltage SGND, and a negative voltage may be supplied. For example, the control signal PTX supplied to the gate of the transfer transistor may have a high level of voltage SVDD and a low level of voltage VTXL (VTXL < GND). In this case, the transfer transistor can be more surely turned off.

[0030] FIG. 4 is an example of a block diagram of a memory control circuit 202 included in the photoelectric conversion device according to the present embodiment.

[0031] As shown in FIG. 4, the memory control circuit 202 includes a memory row selection circuit 220 and a memory output circuit 221. The memory output circuit 221 includes a first memory buffer circuit 222, a second memory buffer circuit 223, a third memory buffer circuit 224, a fourth memory buffer circuit 225, and a fifth memory buffer circuit 226. The memory control circuit 202 receives control signals PTS, PTN, PSEL2, PSEL3, and PCM from the timing control circuit 305. The memory row selection circuit 220 receives an address signal ADDM from the timing control circuit 305. The memory row selection circuit 220 inputs a row selection signal to the memory output circuit 221 based on the address signal ADDM. The first memory buffer circuit 222 and the second memory buffer circuit 223 supply control signals PTS and PTN, respectively, via control line 203 to the memory circuits 210 arranged in the row selected by the row selection signal. Furthermore, the third memory buffer circuit 224, the fourth memory buffer circuit 225, and the fifth memory buffer circuit 226 respectively supply control signals PSEL2, PSEL3, and PCM to the memory circuits 210 arranged in the row selected by the row selection signal via the control line 203. The memory control circuit 202 is supplied with voltages MVDD and MGND, which respectively become the high-level voltage and the low-level voltage of the control signal output by the memory output circuit 221. When the control signal is at a high level, the corresponding transistor is turned on, and when the control signal is at a low level, the corresponding transistor is turned off.

[0032] FIG. 5 is an example of a circuit diagram of the pixels 110, memory circuits 210, and column circuits 310 included in the photoelectric conversion device according to this embodiment. FIG. 5 shows two rows of pixels 110 (first pixels arranged in a first pixel row and second pixels arranged in a second pixel row) and two rows of memory circuits 210 (first memory circuits arranged in a first memory row and second memory circuits arranged in a second memory row) arranged in the same column. Note that, in this specification, the row in which the pixels 110 are arranged may be referred to as a pixel row, and the row in which the memory circuits 210 are arranged may be referred to as a memory row. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors. Note that identical components in the first and second rows are numbered the same. The components arranged in the first row will be mainly described, and a description of the components arranged in the second row may be omitted.

[0033] As shown in FIG. 5, the pixel 110 has a photoelectric conversion element 115, a transfer transistor 113, and a floating diffusion 114. Hereinafter, in this specification, the floating diffusion 114 may be referred to as FD114 (FD is an abbreviation for Floating Diffusion). The FD114 may also be referred to as a floating diffusion region 114. The pixel 110 also has a reset transistor 112 for resetting the FD114, an amplifier transistor 116 for amplifying a signal, and a selection transistor 111. The photoelectric conversion element 115 is electrically connected to a voltage SGND node (reference voltage node) and is supplied with a reference voltage. The reset transistor 112 and the amplifier transistor 116 are electrically connected to a voltage SVDD node (power supply voltage node) and are supplied with a power supply voltage.

[0034] Note that the transfer transistor 113, the reset transistor 112, the amplification transistor 116, and the selection transistor 111 may each be an N-type MOS transistor or a P-type MOS transistor. In this embodiment, a case will be described in which electrons, of electron-hole pairs generated in the photoelectric conversion element 115 by incident light, are used as signal charges. When electrons are used as signal charges, each transistor included in the pixel 110 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, each transistor included in the pixel 110 may be configured as a P-type MOS transistor different from that described in this embodiment.

[0035] The photoelectric conversion element 115 is, for example, a photodiode. The photoelectric conversion element 115 is not limited to a photodiode and may be, for example, a photoelectric conversion film. The photoelectric conversion element 115 receives light incident on the pixel 110, generates signal charges corresponding to the incident light, and accumulates the signal charges. The reset transistor 112 is driven by a control signal PRES. When the reset transistor 112 is turned on, the FD 114 is reset to a voltage based on the power supply voltage. When the reset transistor 112 is turned off, the FD 114 is released from the reset state. The transfer transistor 113 is driven by a control signal PTX. When the transfer transistor 113 is turned on, the signal charges generated in the photoelectric conversion element 115 are transferred to the FD 114. The FD 114 temporarily holds the signal charges input from the photoelectric conversion element 115 and functions as a charge-voltage converter that converts the held signal charges into a voltage signal. The amplification transistor 116 amplifies the pixel signal converted by the FD 114. The selection transistor 111 is driven by a control signal PSEL1 to connect the amplification transistor 116 to the memory circuit 210 and output the pixel signal amplified by the amplification transistor 116 to the memory circuit 210.

[0036] 5 is an example, and the pixel 110 may further include a transistor. For example, a transistor that changes the capacitance value of the FD 114 or a transistor that discharges signal charge from the photoelectric conversion element 115 may further be provided. Alternatively, the pixel 110 may be configured not to include the selection transistor 111, and the selected / non-selected state may be changed by the voltage input from the reset transistor 112 to the FD 114.

[0037] The memory circuit 210 includes an amplifier transistor 211, a reset transistor 212, an N-signal transistor 213, and an S-signal transistor 214. The memory circuit 210 further includes a pixel selection transistor 215, a current source 216, a memory selection transistor 217, an N-signal memory circuit (first capacitance element) 23, and an S-signal memory circuit (second capacitance element) 24. Here, the N-signal is a reset level signal of the pixel 110, and the S-signal is a photoelectric conversion signal of the pixel 110. Each transistor operates based on a control signal supplied by the memory control circuit 202. The current source 216 supplies a current to the amplifier transistor 116. The current source 216 and the amplifier transistor 116 function as a source follower circuit and output a pixel signal.

[0038] Each transistor may be an N-type MOS transistor or a P-type MOS transistor. In this embodiment, a case will be described in which electrons of electron-hole pairs generated in the photoelectric conversion element 115 by incident light are used as signal charges. When electrons are used as signal charges, each transistor included in the memory circuit 210 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, each transistor included in the pixel 110 may be configured as a P-type MOS transistor different from that described in this embodiment.

[0039] The column circuit 310 has an AD conversion circuit 311 and a current source 312. In this embodiment, a plurality of pixels 110 and memory circuits 210 arranged in two rows share one AD conversion circuit 311, but the AD conversion circuit 311 may be shared by a plurality of pixels 110 and memory circuits 210 arranged in three or more rows.

[0040] The first substrate 100 and the second substrate 200 may be bonded by hybrid bonding. The term "hybrid bonding" will be explained below. The first substrate 100 has a first metal portion 11 and a first insulating film, and the second substrate 200 has a second metal portion 21 and a second insulating film. The bonding surface between the first substrate 100 and the second substrate 200 includes a bonding portion between the first metal portion 11 and the second metal portion 21 and a bonding portion between the first insulating film and the second insulating film. The second substrate 200 and the third substrate 300 may also be bonded by hybrid bonding. Specifically, the second substrate 200 includes a third metal portion 22 and a third insulating film, and the third substrate 300 includes a fourth metal portion 31 and a fourth insulating film. The bonding surface between the second substrate 200 and the third substrate 300 includes a bonding portion between the third metal portion 22 and the fourth metal portion 31 and a bonding portion between the third insulating film and the fourth insulating film. In a plan view of the first substrate 100, the junction between the first metal portion 11 and the second metal portion 21 may be arranged so as to overlap at least a portion of the pixel array 101. In addition, the junction between the third metal portion 22 and the fourth metal portion 31 may be arranged so as to overlap at least a portion of the pixel array 101.

[0041] FIG. 6 is an example of a drive timing chart for the photoelectric conversion device according to this embodiment. In FIG. 6, the horizontal axis represents time and the vertical axis represents voltage, and the timing of each drive pulse (each control signal) is schematically shown. FIG. 6 also shows the timing for reading out pixel signals corresponding to the two rows of pixels 110 and memory circuit 210 shown in FIG. 5. This embodiment illustrates a simultaneous operation of all rows, so-called global shutter drive. FIG. 6 does not illustrate the driving of pixels 110 arranged in the third pixel row and subsequent pixels, such as the pixels 110 (third pixels) arranged in the third pixel row and the pixels 110 (fourth pixels) arranged in the fourth pixel row. However, in global shutter drive, the pixels 110 arranged in the third pixel row and subsequent pixels are driven in the same manner as the pixels 110 arranged in the first and second pixel rows shown in FIG. 6. 6 does not illustrate the driving of memory circuits 210 arranged in the third memory row and beyond, such as the memory circuit (third memory circuit) 210 arranged in the third memory row and the memory circuit (fourth memory circuit) 210 arranged in the fourth memory row. However, in global shutter driving, the memory circuits 210 arranged in the third memory row and beyond are driven in the same manner as the memory circuits 210 arranged in the first and second memory rows shown in FIG.

[0042] 6, the period from time t101 to time t201 corresponds to one frame, and the period after time t201 corresponds to the next frame. Note that the control signals shown in FIG. 6 correspond to the control signals shown in FIGS. 3, 4, and 5.

[0043] At time t101, the control signals PSEL1-1 and PSEL1-2 change from low to high, selecting all rows in which multiple pixels 110 are arranged. Note that the control signal PSEL1-1 indicates the control signal PSEL1 of the first row, and the control signal PSEL1-2 indicates the control signal PSEL1 of the second row, and the other control signals are expressed similarly. Also, at time t101, the control signals PSEL2-1 and PSEL2-2 change from low to high, causing the amplification transistor 116 to operate as a source follower circuit.

[0044] At time t102, the control signals PSEL1-1 and PSEL1-2 change from high to low, ending the period in which all rows in which multiple pixels 110 are selected. During the period from time t101 to time t102, the control signals PRES-1 and PRES-2 change from low to high, and then the control signals PTN-1 and PTN-2 change from low to high. After that, during the period from time t101 to time t102, the control signals PTX-1 and PTX-2 change from low to high, and then the control signals PTS-1 and PTS-2 change from low to high.

[0045] When the control signals PRES-1 and PRES-2 change from low to high, the FDs 114 included in each of the pixels 110 arranged in all rows are reset. Then, when the control signals PTN-1 and PTN-2 change from low to high, the reset-level signal output from the FDs 114 is held in the N signal memory circuit 23. Then, when the control signals PTX-1 and PTX-2 change from low to high, the photoelectric conversion signal accumulated in the photoelectric conversion element 115 is transferred to the FDs 114. Then, when the control signals PTS-1 and PTS-2 change from low to high, the photoelectric conversion signal is held in the S signal memory circuit 24. This driving completes the write operation to the memory circuit 210 at time t102.

[0046] At time t103, the control signal PSEL3-1 changes from low level to high level, starting a read operation from the memory circuit 210 arranged in the first memory row. Also, at time t104, the control signal PSEL3-1 changes from high level to low level, ending the read operation from the memory circuit 210 arranged in the first memory row.

[0047] During the period from time t103 to time t104, the control signal PCM-1, the control signal PTN-1, and the control signal PTS-1 sequentially change from low level to high level. When the control signal PCM-1 changes from low level to high level, the gate of the amplification transistor 211 is reset. Thereafter, when the control signal PTN-1 changes from low level to high level, the N signal held in the N signal memory circuit 23 is read out to the downstream AD conversion circuit 311 and converted into a digital signal. The N signal converted into a digital signal is then held in the column memory circuit 302. Thereafter, when the control signal PTS-1 changes from low level to high level, the S signal held in the S signal memory circuit 24 is read out to the downstream AD conversion circuit 311 and converted into a digital signal. The S signal converted into a digital signal is then held in the column memory circuit 302. The horizontal scanning circuit 303 sequentially selects the column memory circuits 302 that hold the N and S signals, and the N and S signals are output to the outside of the photoelectric conversion device 10 via the output circuit 306 .

[0048] At time t105, the control signal PSEL3-2 changes from low level to high level, and a read operation from the memory circuits 210 arranged in the second memory row begins. At time t108, the control signal PSEL3-2 changes from high level to low level, and a read operation from the memory circuits 210 arranged in the second memory row ends. From time t105 to time t108, a read operation from the memory circuits 210 in the second memory row is performed by driving similarly to the read operation from the memory circuits 210 in the first memory row performed from time t103 to time t104. From time t201 onwards, the operation from time t101 to time t108 is repeated.

[0049] As described above, the first period during which the pixels 110 in the first pixel row output analog signals to the memory circuits 210 in the first memory row overlaps at least a portion of the second period during which the pixels 110 in the second pixel row output analog signals to the memory circuits 210 in the second memory row. The memory circuits 210 in the first memory row and the memory circuits 210 in the second memory row sequentially output analog signals to the AD conversion circuit 311. The third period during which the pixels 110 in the third pixel row output analog signals to the memory circuits 210 in the third memory row overlaps at least a portion of the fourth period during which the pixels 110 in the fourth pixel row output analog signals to the memory circuits 210 in the fourth memory row. The memory circuits 210 in the third memory row and the memory circuits 210 in the fourth memory row sequentially output analog signals to the AD conversion circuit 311. Furthermore, the first period overlaps at least a portion of the third period. This type of driving is known as global shutter driving. Typically, the starts of the first, second, third, and fourth periods are controlled collectively. The ends of the first, second, third, and fourth periods are also controlled collectively. In other words, the start times of the first, second, third, and fourth periods are approximately the same. The end times of the first, second, third, and fourth periods are also approximately the same.

[0050] Note that, during the period from time t106 to time t107, the control signals PRES-1, PRES-2, PTX-1, and PTX-2 are all at high level. Then, a reset operation of the photoelectric conversion elements 115 is performed for all rows simultaneously. This operation resets the signal charges accumulated in the photoelectric conversion elements 115 and starts charge accumulation in the photoelectric conversion elements 115. In FIG. 6 , the photoelectric conversion elements 115 accumulate signal charges from time t107 until the control signals PTX-1 and PTX-2 change from low level to high level after time t107 and pixel signal readout is restarted. This operation from time t106 to time t107 is a so-called global shutter operation, and the global shutter operation can be performed during the pixel signal readout period, as shown in FIG. 6 . That is, the pixel output circuit 121 that supplies control signals to the pixels 110 is driven during the pixel signal readout period. In this case, the power supply voltage and reference voltage can fluctuate due to factors such as through-current, affecting pixel signals during the readout period. For example, if the pixel signals corresponding to the first and second pixel rows are at the same level, the S signal of the second row will be affected by the global shutter operation and will be degraded compared to the S signal of the first row. As a result, horizontal stripes of noise can appear in the resulting image.

[0051] In this embodiment, the pixel control circuit 102 is arranged on the first substrate 100, which is a substrate different from the second substrate 200 on which the memory circuit 210 is arranged. With this configuration, even if fluctuations in the power supply voltage and the reference voltage occur during global shutter operation, the effect on the signal readout operation of the memory circuit 210 can be reduced, thereby improving the quality of the obtained image.

[0052] The pixel array 101 and the pixel control circuit 102 may be electrically separated from the memory array 201 and the memory control circuit 202. For example, a voltage SVDD node electrically connected to the pixel control circuit 102 may be electrically separated from a voltage MVDD node electrically connected to the memory control circuit 202. For example, a voltage SGND node electrically connected to the pixel control circuit 102 may be electrically separated from a voltage MGND node electrically connected to the memory control circuit 202. For example, the voltage SVDD node and the voltage SGND node electrically connected to the pixel control circuit 102 may be electrically separated from a voltage MVDD node and a voltage MGND node electrically connected to the memory control circuit 202. The pixel array 101 and the pixel control circuit 102 may be electrically separated from the signal processing circuit 301. For example, a voltage SVDD node electrically connected to the pixel control circuit 102 may be electrically separated from a voltage AVDD node electrically connected to the signal processing circuit 301. Furthermore, for example, the voltage SGND node electrically connected to the pixel control circuit 102 may be electrically separated from the voltage AGND node electrically connected to the signal processing circuit 301. Furthermore, for example, the voltage SVDD node and voltage SGND node electrically connected to the pixel control circuit 102 may be electrically separated from the voltage AVDD node and voltage AGND node electrically connected to the signal processing circuit 301. The above configuration can reduce the effect on the signal read operation of the memory circuit 210 even if fluctuations in the power supply voltage and reference voltage occur during the global shutter operation, thereby further improving the quality of the obtained image.

[0053] In the global shutter operation of this embodiment, the pixels 110 arranged in all rows may be driven collectively, or the pixels 110 arranged in multiple rows out of all rows may be divided into multiple blocks and driven.

[0054] In other words, the start and end of the accumulation period for the multiple pixels 110 included in one block are the same. On the other hand, the start and end of the accumulation period for one block differ from that for another block. Such partial global shutter operation on a block-by-block basis is also possible. For example, driving is performed so that the first period and the third period described above do not overlap. The method of dividing the blocks can be changed as appropriate. For example, one block may be multiple pixels 110 in one row and all columns. Alternatively, one block may be multiple pixels 110 in some rows and some columns of the pixel array 101.

[0055] Furthermore, the operation may be switched between driving all rows at once and driving each block separately as appropriate.

[0056] A photoelectric conversion device according to a first modified example of the first embodiment of the present invention will be described with reference to Fig. 7. Note that components similar to those in the first embodiment are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0057] The modification of the first embodiment differs from the first embodiment in that it has a configuration in which a plurality of pixel control circuits 102 and a plurality of memory control circuits 202 are arranged. Fig. 7 is an example of a block diagram of a photoelectric conversion device 10 according to this modification.

[0058] As shown in Fig. 7, the first substrate 100 has a plurality of pixel control circuits 102. Furthermore, the second substrate 200 has a plurality of memory control circuits 202. As an example, Fig. 7 shows two pixel control circuits 102 arranged on both sides of the pixel array 101, and two memory control circuits 202 arranged on both sides of the memory array 201. In this configuration, by supplying control signals from both sides of the control line 103 and the control line 203, the pixels 110 and the memory circuits 210 can be controlled at higher speed.

[0059] A photoelectric conversion device according to a second modified example of the first embodiment of the present invention will be described with reference to Fig. 8. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0060] The second modified example of the first embodiment differs from the first embodiment in the position where the pixel control circuit 102 is provided. Fig. 8 is an example of a block diagram of a photoelectric conversion device 10 according to this modified example.

[0061] 8, the third substrate 300 has a pixel control circuit 102. In such a configuration, there is no need to arrange the pixel control circuit 102 on the first substrate 100. Therefore, the components (such as pixels 110) arranged on the first substrate 100 can be configured using N-type MOS transistors instead of P-type MOS transistors. This simplifies the process steps for forming the first substrate 100, enabling cost reduction.

[0062] Second Embodiment A photoelectric conversion device 10 according to a second embodiment of the present invention will be described with reference to Figures 9 and 10. Note that components similar to those in the first embodiment are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0063] This embodiment differs from the first embodiment in that the pixel 110 has a configuration in which the pixel 110 has multiple photoelectric conversion elements. FIG. 9 is an example of a circuit diagram of the pixel 110, memory circuit 210, and column circuit 310 included in the photoelectric conversion device according to this embodiment. FIG. 9 shows two rows of pixels 110 (first pixels arranged in a first pixel row and second pixels arranged in a second pixel row) arranged in the same column and two rows of memory circuits 210 (first memory circuits arranged in a first memory row and second memory circuits arranged in a second memory row). Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors. Note that identical components in the first and second rows are numbered the same. The components arranged in the first row will be mainly described, and a description of the components arranged in the second row may be omitted.

[0064] As shown in FIG. 9 , the pixel 110 includes a photoelectric conversion element 115, a second photoelectric conversion element 118, a transfer transistor 113, a second transfer transistor 117, and an FD 114. Hereinafter, in this specification, the photoelectric conversion element 115 may be referred to as a first photoelectric conversion element 115, and the transfer transistor 113 may be referred to as a first transfer transistor 113. The pixel 110 also includes a reset transistor 112 for resetting the FD 114, an amplifier transistor 116 for amplifying a signal, and a selection transistor 111. The first photoelectric conversion element 115 and the second photoelectric conversion element 118 are electrically connected to a voltage SGND node (reference voltage node) and are supplied with a reference voltage. The reset transistor 112 and the amplifier transistor 116 are electrically connected to a voltage SVDD node (power supply voltage node) and are supplied with a power supply voltage.

[0065] Note that the first transfer transistor 113, the second transfer transistor 117, the reset transistor 112, the amplification transistor 116, and the selection transistor 111 may each be an N-type MOS transistor or a P-type MOS transistor. In this embodiment, a case will be described in which electrons, of electron-hole pairs generated in the photoelectric conversion element 115 by incident light, are used as signal charges. When electrons are used as signal charges, each transistor included in the pixel 110 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, each transistor included in the pixel 110 may be configured as a P-type MOS transistor different from that described in this embodiment.

[0066] The first photoelectric conversion element 115 and the second photoelectric conversion element 118 are, for example, photodiodes. The first photoelectric conversion element 115 and the second photoelectric conversion element 118 are not limited to photodiodes and may be, for example, photoelectric conversion films. The first photoelectric conversion element 115 and the second photoelectric conversion element 118 receive light incident on the pixel 110, generate signal charges corresponding to the incident light, and accumulate the signal charges. The reset transistor 112 is driven by a control signal PRES. When the reset transistor 112 is turned on, the FD 114 is reset to a voltage based on the power supply voltage. When the reset transistor 112 is turned off, the FD 114 is released from the reset state. The first transfer transistor 113 is driven by a control signal PTXA. When the first transfer transistor 113 is turned on, the signal charges generated in the first photoelectric conversion element 115 are transferred to the FD 114. The second transfer transistor 117 is driven by a control signal PTXB. When the second transfer transistor 117 is turned on, the signal charge generated in the second photoelectric conversion element 118 is transferred to the FD 114. The FD 114 temporarily holds the signal charge input from at least one of the first photoelectric conversion element 115 and the second photoelectric conversion element 118 and functions as a charge-voltage converter that converts the held signal charge into a voltage signal. The amplification transistor 116 amplifies the pixel signal converted by the FD 114. The selection transistor 111 is driven by a control signal PSEL1 to connect the amplification transistor 116 to the memory circuit 210 and output the pixel signal amplified by the amplification transistor 116 to the memory circuit 210. Note that, hereinafter, in this specification, a photoelectric conversion signal output from the pixel 110 corresponding to the first charge (first signal charge) generated in the first photoelectric conversion element 115 may be referred to as an A signal. Also, a photoelectric conversion signal output from the pixel 110 corresponding to the second charge (second signal charge) generated in the second photoelectric conversion element 118 may be referred to as a B signal.

[0067] 9 is just an example, and the pixel 110 may further include a transistor. For example, a transistor that changes the capacitance value of the FD 114, or a transistor that drains signal charge from at least one of the first photoelectric conversion element 115 and the second photoelectric conversion element 118 may further be provided. Alternatively, the pixel 110 may be configured not to include the selection transistor 111, and the selected / non-selected state may be changed by the voltage input from the reset transistor 112 to the FD 114.

[0068] The memory circuit 210 includes an amplification transistor 211, a reset transistor 212, an N-signal transistor 213, an S-signal transistor 214, and a second S-signal transistor 218. The memory circuit 210 further includes a pixel selection transistor 215, a current source 216, a memory selection transistor 217, an N-signal memory circuit 23, an S-signal memory circuit 24, and a second S-signal memory circuit 25. Hereinafter, in this specification, the S-signal transistor 214 may be referred to as the first S-signal transistor 214, and the S-signal memory circuit 24 may be referred to as the first S-signal memory circuit 24. Here, the N-signal is a reset level signal of the pixel 110, and the S-signal is a photoelectric conversion signal of the pixel 110. Each transistor operates based on a control signal supplied by the memory control circuit 202.

[0069] Each transistor may be an N-type MOS transistor or a P-type MOS transistor. In this embodiment, a case will be described in which electrons of electron-hole pairs generated in the first photoelectric conversion element 115 and the second photoelectric conversion element 118 by incident light are used as signal charges. When electrons are used as signal charges, each transistor included in the memory circuit 210 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, each transistor included in the pixel 110 may be configured as a P-type MOS transistor different from that described in this embodiment.

[0070] FIG. 10 is an example of a drive timing chart for the photoelectric conversion device according to this embodiment. In FIG. 10, the horizontal axis represents time and the vertical axis represents voltage, and the timing of each drive pulse (each control signal) is schematically shown. FIG. 10 also shows the timing for reading out pixel signals corresponding to the two rows of pixels 110 and memory circuit 210 shown in FIG. 9. This embodiment illustrates a simultaneous operation of all rows, known as global shutter drive. FIG. 10 does not illustrate the driving of pixels 110 arranged in the third pixel row and subsequent pixels, such as the pixels 110 (third pixels) 110 arranged in the third pixel row and the pixels 110 (fourth pixels) 110 arranged in the fourth pixel row. However, in global shutter drive, the pixels 110 arranged in the third pixel row and subsequent pixels are driven in the same manner as the pixels 110 arranged in the first and second pixel rows shown in FIG. 10. 10 does not illustrate the driving of memory circuits 210 arranged in the third memory row and beyond, such as the memory circuit (third memory circuit) 210 arranged in the third memory row and the memory circuit (fourth memory circuit) 210 arranged in the fourth memory row. However, in global shutter driving, the memory circuits 210 arranged in the third memory row and beyond are also driven in the same manner as the memory circuits 210 arranged in the first and second memory rows shown in FIG.

[0071] 10, the period from time t101 to time t201 corresponds to one frame, and the period after time t201 corresponds to the next frame. Note that the control signals shown in FIG. 10 correspond to the control signals shown in FIGS. 3, 4, and 9.

[0072] At time t101, the control signals PSEL1-1 and PSEL1-2 change from low to high, selecting all rows in which multiple pixels 110 are arranged. Note that the control signal PSEL1-1 indicates the control signal PSEL1 of the first row, and the control signal PSEL1-2 indicates the control signal PSEL1 of the second row, and the other control signals are expressed similarly. Also, at time t101, the control signals PSEL2-1 and PSEL2-2 change from low to high, causing the amplification transistor 116 to operate as a source follower circuit.

[0073] At time t102, the control signals PSEL1-1 and PSEL1-2 change from high to low, ending the period in which all rows in which multiple pixels 110 are selected. From time t101 to time t102, the control signals PRES-1 and PRES-2 change from low to high, and then the control signals PTN-1 and PTN-2 change from low to high. Then, from time t101 to time t102, the control signals PTXA-1 and PTXA-2 change from low to high, and then the control signals PTSA-1 and PTSA-2 change from low to high. Then, from time t101 to time t102, the control signals PTXA-1, PTXA-2, PTXB-1, and PTXB-2 change from low to high. Thereafter, in the period from time t101 to time t102, the control signal PTSB-1 and the control signal PTSB-2 change from low level to high level.

[0074] When the control signals PRES-1 and PRES-2 change from low to high, the FDs 114 included in each of the pixels 110 arranged in all rows are reset. Then, when the control signals PTN-1 and PTN-2 change from low to high, the reset-level signal output from the FDs 114 is held in the N signal memory circuit 23. Then, when the control signals PTXA-1 and PTXA-2 change from low to high, the A signal accumulated in the first photoelectric conversion element 115 is transferred to the FDs 114. Then, when the control signals PTSA-1 and PTSA-2 change from low to high, the A signal output from each of the pixels 110 arranged in all rows is held in the first S signal memory circuit 24. Then, when the control signals PTXA-1, PTXA-2, PTXB-1, and PTXB-2 change from low to high, the A signal and B signal output from each of the pixels 110 arranged in all rows are transferred to the FDs 114. That is, FD 114 holds the signal obtained by adding together signal A and signal B. Thereafter, control signals PTSB-1 and PTSB-2 change from low level to high level, causing the sum of signal A and signal B to be held in second S signal memory circuit 25. With this driving, the write operation to memory circuit 210 is completed at time t102.

[0075] At time t103, the control signal PSEL3-1 changes from low level to high level, starting a read operation from the memory circuit 210 arranged in the first memory row. Also, at time t104, the control signal PSEL3-1 changes from high level to low level, ending the read operation from the memory circuit 210 arranged in the first memory row.

[0076] During the period from time t103 to time t104, the control signal PCM-1, the control signal PTN-1, the control signal PTSA-1, and the control signal PTSB-1 sequentially change from low level to high level. When the control signal PCM-1 changes from low level to high level, the gate of the amplification transistor 211 is reset. When the control signal PTN-1 then changes from low level to high level, the N signal held in the N signal memory circuit 23 is read out to the downstream AD conversion circuit 311 and converted into a digital signal. The digitally converted N signal is then held in the column memory circuit 302. When the control signal PTSA-1 then changes from low level to high level, the A signal held in the first S signal memory circuit 24 is read out to the downstream AD conversion circuit 311 and converted into a digital signal. The digitally converted A signal is then held in the column memory circuit 302. Thereafter, when the control signal PTSB-1 transitions from low to high, the sum of the A and B signals stored in the second S signal memory circuit 25 is read out to the downstream AD conversion circuit 311 and converted into a digital signal. The converted digital sum of the A and B signals is then stored in the column memory circuit 302. The horizontal scanning circuit 303 sequentially selects the column memory circuits 302 that respectively store the N signal, the A signal, and the sum of the A and B signals, and outputs the N signal, the A signal, and the sum of the A and B signals to the outside of the photoelectric conversion device 10 via the output circuit 306. Furthermore, in signal processing performed downstream, the B signal is obtained by subtracting the A signal from the sum of the A and B signals. Then, the A and B signals are compared to perform focus detection using phase difference detection.

[0077] At time t105, the control signal PSEL3-2 changes from low level to high level, and a read operation from the memory circuits 210 arranged in the second memory row begins. At time t108, the control signal PSEL3-2 changes from high level to low level, and a read operation from the memory circuits 210 arranged in the second memory row ends. From time t105 to time t108, a read operation from the memory circuits 210 in the second memory row is performed by driving similarly to the read operation from the memory circuits 210 in the first memory row performed from time t103 to time t104. From time t201 onwards, the operation from time t101 to time t108 is repeated.

[0078] As described above, the first period during which the pixels 110 in the first pixel row output analog signals to the memory circuits 210 in the first memory row overlaps at least a portion of the second period during which the pixels 110 in the second pixel row output analog signals to the memory circuits 210 in the second memory row. The memory circuits 210 in the first memory row and the memory circuits 210 in the second memory row sequentially output analog signals to the AD conversion circuit 311. The third period during which the pixels 110 in the third pixel row output analog signals to the memory circuits 210 in the third memory row overlaps at least a portion of the fourth period during which the pixels 110 in the fourth pixel row output analog signals to the memory circuits 210 in the fourth memory row. The memory circuits 210 in the third memory row and the memory circuits 210 in the fourth memory row sequentially output analog signals to the AD conversion circuit 311. Furthermore, the first period overlaps at least a portion of the third period. This type of driving is known as global shutter driving. Typically, the starts of the first, second, third, and fourth periods are controlled collectively. The ends of the first, second, third, and fourth periods are also controlled collectively. In other words, the start times of the first, second, third, and fourth periods are approximately the same. The end times of the first, second, third, and fourth periods are also approximately the same.

[0079] In this embodiment, the pixel control circuit 102 is arranged on the first substrate 100, which is a substrate different from the second substrate 200 on which the memory circuit 210 is arranged. With this configuration, even if fluctuations in the power supply voltage and the reference voltage occur during global shutter operation, the effect on the signal readout operation of the memory circuit 210 can be reduced, thereby suppressing image quality degradation.

[0080] Furthermore, in this embodiment, the pixel 110 has a first photoelectric conversion element 115 and a second photoelectric conversion element 118, and focus detection can be performed by phase difference detection.

[0081] Although the present embodiment has been described as an example in which focus detection is performed by global shutter operation, the pixels 110 arranged in each row may be controlled to sequentially transfer signals A and B to the memory circuit 210. In other words, signal transfer from the pixels 110 to the memory circuit 210 may be performed by rolling shutter operation. In rolling shutter operation, it is only necessary to set high the control signals corresponding to the multiple rows to which signals are to be transferred simultaneously, and therefore the current that flows in a short period of time can be reduced compared to global shutter operation.

[0082] If focus detection is not required, the first transfer transistor 113 and the second transfer transistor 117 may be driven at the same timing, and a global shutter operation may be performed in which only the sum of the signals A and B is read out without reading out the signal A. Furthermore, if focus detection is not required, a rolling shutter operation may be performed in which only the sum of the signals A and B is read out without reading out the signal A, thereby reducing the current that flows in a short period of time.

[0083] The pixel array 101 and the pixel control circuit 102 may be electrically separated from the memory array 201 and the memory control circuit 202. For example, a voltage SVDD node electrically connected to the pixel control circuit 102 may be electrically separated from a voltage MVDD node electrically connected to the memory control circuit 202. For example, a voltage SGND node electrically connected to the pixel control circuit 102 may be electrically separated from a voltage MGND node electrically connected to the memory control circuit 202. For example, the voltage SVDD node and the voltage SGND node electrically connected to the pixel control circuit 102 may be electrically separated from a voltage MVDD node and a voltage MGND node electrically connected to the memory control circuit 202. The pixel array 101 and the pixel control circuit 102 may be electrically separated from the signal processing circuit 301. For example, a voltage SVDD node electrically connected to the pixel control circuit 102 may be electrically separated from a voltage AVDD node electrically connected to the signal processing circuit 301. Furthermore, for example, the voltage SGND node electrically connected to the pixel control circuit 102 may be electrically separated from the voltage AGND node electrically connected to the signal processing circuit 301. Furthermore, for example, the voltage SVDD node and voltage SGND node electrically connected to the pixel control circuit 102 may be electrically separated from the voltage AVDD node and voltage AGND node electrically connected to the signal processing circuit 301. The above configuration can reduce the effect on the signal read operation of the memory circuit 210 even if fluctuations in the power supply voltage and reference voltage occur during the global shutter operation, thereby more effectively suppressing image quality degradation.

[0084] In the global shutter operation of this embodiment, the pixels 110 arranged in all rows may be driven collectively, or the pixels 110 arranged in multiple rows out of all rows may be divided into multiple blocks and driven.

[0085] In other words, the start and end of the accumulation period for the multiple pixels 110 included in one block are the same. On the other hand, the start and end of the accumulation period for one block differ from that for another block. Such partial global shutter operation on a block-by-block basis is also possible. For example, driving is performed so that the first period and the third period described above do not overlap. The method of dividing the blocks can be changed as appropriate. For example, one block may be multiple pixels 110 in one row and all columns. Alternatively, one block may be multiple pixels 110 in some rows and some columns of the pixel array 101.

[0086] Furthermore, the operation may be switched between driving all rows at once and driving each block separately as appropriate.

[0087] Third Embodiment A photoelectric conversion device 10 according to a third embodiment of the present invention will be described with reference to Fig. 11. Note that components similar to those in the first and second embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0088] This embodiment differs from the first and second embodiments in the location where the memory control circuit 202 is provided. Fig. 11 is an example of a block diagram of a photoelectric conversion device 10 according to this embodiment.

[0089] As shown in FIG. 11 , the third substrate 300 has a pixel control circuit 102 and a memory control circuit 202. The pixel array 101 and the pixel control circuit 102 are electrically isolated from the memory array 201 and the memory control circuit 202. For example, the voltage SVDD node electrically connected to the pixel control circuit 102 may be electrically isolated from the voltage MVDD node electrically connected to the memory control circuit 202. For example, the voltage SGND node electrically connected to the pixel control circuit 102 may be electrically isolated from the voltage MGND node electrically connected to the memory control circuit 202. For example, the voltage SVDD node and the voltage SGND node electrically connected to the pixel control circuit 102 are electrically isolated from the voltage MVDD node and the voltage MGND node electrically connected to the memory control circuit 202. With this configuration, even if fluctuations in the power supply voltage and the reference voltage occur during the global shutter operation, the effect on the signal read operation of the memory circuit 210 can be reduced, thereby improving the quality of the obtained image.

[0090] The pixel array 101 and the pixel control circuit 102 may be electrically isolated from the signal processing circuit 301. For example, a voltage SVDD node electrically connected to the pixel control circuit 102 may be electrically isolated from a voltage AVDD node electrically connected to the signal processing circuit 301. For example, a voltage SGND node electrically connected to the pixel control circuit 102 may be electrically isolated from a voltage AGND node electrically connected to the signal processing circuit 301. For example, the voltage SVDD node and voltage SGND node electrically connected to the pixel control circuit 102 may be electrically isolated from the voltage AVDD node and voltage AGND node electrically connected to the signal processing circuit 301. The above configuration can reduce the effect on the signal read operation of the memory circuit 210 even if fluctuations in the power supply voltage and reference voltage occur during global shutter operation, thereby further improving the quality of the obtained image.

[0091] Furthermore, in this embodiment, there is no need to arrange the pixel control circuit 102 on the first substrate 100. Therefore, the components (such as the pixels 110) arranged on the first substrate 100 can be configured using N-type MOS transistors instead of P-type MOS transistors. This simplifies the process steps for forming the first substrate 100, enabling cost reduction.

[0092] In the global shutter operation of this embodiment, the pixels 110 arranged in all rows may be driven collectively, or the pixels 110 arranged in multiple rows out of all rows may be divided into multiple blocks and driven.

[0093] In other words, the start and end of the accumulation period for the multiple pixels 110 included in one block are the same. On the other hand, the start and end of the accumulation period for one block differ from that for another block. Such partial global shutter operation on a block-by-block basis is also possible. For example, driving is performed so that the first period and the third period described above do not overlap. The method of dividing the blocks can be changed as appropriate. For example, one block may be multiple pixels 110 in one row and all columns. Alternatively, one block may be multiple pixels 110 in some rows and some columns of the pixel array 101.

[0094] Furthermore, the operation may be switched between driving all rows at once and driving each block separately as appropriate.

[0095] Fourth Embodiment The fourth embodiment can be applied to any of the first to third embodiments. FIG. 12(a) is a schematic diagram illustrating a device 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device according to any of the above-described embodiments can be used as the semiconductor device 930. The device 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 can include a semiconductor device 910. The semiconductor device 930 can include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0096] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0097] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0098] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0099] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0100] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft (drone, aircraft). The mechanical device 990 in the transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0101] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0102] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0103] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 12(b) and 12(c).

[0104] FIG. 12(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 1. The photoelectric conversion device 1 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 1, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 10, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 10. For example, the multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The multiple photoelectric conversion units receive light beams that have passed through different positions on the pupil of the optical system, and the photoelectric conversion device 10 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate the parallax using the output image data. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be realized by dedicated hardware or a software module. It may also be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or a combination thereof.

[0105] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0106] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear. Fig. 12(c) shows the photoelectric conversion system 8 when capturing an image of the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 1. This configuration can further improve the accuracy of distance measurement.

[0107] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system 8 can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generator that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generator can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0108] As used herein, expressions such as "A or B," "at least one of A and B," "at least one of A or / and B," "one or more of A or / and B," and the like, include all possible combinations of the listed items unless expressly defined otherwise. That is, the above expressions are understood to disclose all cases, including cases containing at least one A, cases containing at least one B, and cases containing both at least one A and at least one B. This applies equally to combinations of three or more elements.

[0109] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0110] The disclosure of this embodiment includes the following configurations.

[0111] (Configuration 1) A photoelectric conversion device comprising a first substrate having a pixel array, a second substrate having a memory array that stores analog signals output by the pixel array, and a third substrate having an analog-to-digital (AD) conversion circuit that converts the analog signals output by the memory array into digital signals, wherein the second substrate has at least one memory control circuit that controls the memory array, and the first substrate or the third substrate has at least one pixel control circuit that controls the pixel array.

[0112] (Configuration 2) A photoelectric conversion device comprising a first substrate having a pixel array, a second substrate having a memory array that stores analog signals output by the pixel array, and a third substrate having an analog-to-digital (AD) conversion circuit that converts the analog signals output by the memory array into digital signals, wherein the photoelectric conversion device has at least one memory control circuit that controls the memory array, and at least one pixel control circuit that controls the pixel array, and wherein at least one of a power supply voltage node electrically connected to the pixel control circuit and a power supply voltage node electrically connected to the memory control circuit, and a reference voltage node electrically connected to the pixel control circuit and a reference voltage node electrically connected to the memory control circuit are electrically isolated.

[0113] (Configuration 3) A photoelectric conversion device according to configuration 1 or 2, characterized in that at least one of a power supply voltage node electrically connected to the pixel control circuit and a power supply voltage node electrically connected to the memory control circuit, and a reference voltage node electrically connected to the pixel control circuit and a reference voltage node electrically connected to the memory control circuit are electrically isolated.

[0114] (Configuration 4) A photoelectric conversion device described in any one of configurations 1 to 3, characterized in that the pixel control circuit includes a pixel output circuit that outputs a control signal for controlling the pixel array, and the memory control circuit includes a memory output circuit that outputs a control signal for controlling the memory array.

[0115] (Configuration 5) A photoelectric conversion device described in any one of configurations 1 to 4, characterized in that the pixels included in the pixel array have a photoelectric conversion element that generates an electric charge in response to incident light, a floating diffusion that converts the electric charge into a signal, and an amplification transistor that amplifies the signal, and the analog signal output by the pixel array is the signal output by the amplification transistor.

[0116] (Configuration 6) A photoelectric conversion device described in any one of configurations 1 to 5, characterized in that the analog signal output by the pixel array is a signal output by a current source that supplies current to the amplifying transistor and a source follower circuit that includes the amplifying transistor.

[0117] (Configuration 7) A photoelectric conversion device described in any one of configurations 1 to 6, characterized in that the pixel array has a plurality of pixels arranged in a plurality of rows and a plurality of columns, the memory array has a plurality of memory circuits arranged in a plurality of rows and a plurality of columns, and each of the plurality of memory circuits holds the analog signal output from each of the plurality of pixels.

[0118] (Configuration 8) A photoelectric conversion device described in any one of configurations 1 to 7, characterized in that the pixel control circuit controls at least one pixel among the plurality of pixels to output the analog signal to the memory array, and the memory control circuit controls at least one memory circuit among the plurality of memory circuits to output the analog signal to the AD conversion circuit.

[0119] (Structure 9) The photoelectric conversion device described in any one of structures 1 to 8, characterized in that the third substrate has a control circuit that controls the pixel control circuit and the memory control circuit, the multiple pixels include first pixels arranged in a first pixel row and second pixels arranged in a second pixel row, the multiple memory circuits include first memory circuits arranged in the first memory row and second memory circuits arranged in the second memory row, the control circuit controls the pixel control circuit so that, during one frame, a first period in which the first pixels output the analog signals to the first memory circuit overlaps with at least a portion of a second period in which the second pixels output the analog signals to the second memory circuit, and the control circuit controls the memory control circuit so that, during the one frame, the first memory circuit and the second memory circuit sequentially output the analog signals to the AD conversion circuit.

[0120] (Configuration 10) The photoelectric conversion device described in any one of configurations 1 to 9, wherein the plurality of pixels include third pixels arranged in a third pixel row and fourth pixels arranged in a fourth pixel row, the plurality of memory circuits include third memory circuits arranged in the third memory row and fourth memory circuits arranged in the fourth memory row, the control circuit controls the pixel control circuit so that, during the one frame, a third period in which the third pixels output the analog signals to the third memory circuits overlaps with at least a portion of a fourth period in which the fourth pixels output the analog signals to the fourth memory circuits, and the control circuit controls the memory control circuit so that, during the one frame, the first memory circuit, the second memory circuit, the third memory circuit, and the fourth memory circuit sequentially output the analog signals to the AD conversion circuit, and the first period overlaps with at least a portion of the third period.

[0121] (Configuration 11) The photoelectric conversion device described in any one of configurations 1 to 10, wherein the plurality of pixels include third pixels arranged in a third pixel row and fourth pixels arranged in a fourth pixel row, the plurality of memory circuits include third memory circuits arranged in a third memory row and fourth memory circuits arranged in a fourth memory row, the control circuit controls the pixel control circuit and the memory control circuit so that, during the one frame, a third period in which the third pixels output the analog signals to the third memory circuits overlaps with at least a portion of a fourth period in which the fourth pixels output the analog signals to the fourth memory circuits, and the control circuit controls the memory control circuit so that, during the one frame, the first memory circuit, the second memory circuit, the third memory circuit, and the fourth memory circuit sequentially output the analog signals to the AD conversion circuit, and the first period does not overlap with the third period.

[0122] (Structure 12) A photoelectric conversion device described in any one of structures 1 to 11, characterized in that the first pixel and the second pixel each have a photoelectric conversion element that generates a charge in response to incident light and a transfer transistor that transfers the charge, and the control circuit controls the pixel control circuit so that, during the one frame, the period during which the transfer transistor of the first pixel is on in the first period overlaps with at least a portion of the period during which the transfer transistor of the second pixel is on in the second period.

[0123] (Structure 13) The photoelectric conversion device described in any one of structures 1 to 12, characterized in that the first pixel and the second pixel each have a first photoelectric conversion element that generates a first charge in response to incident light, a first transfer transistor that transfers the first charge, a second photoelectric conversion element that generates a second charge in response to incident light, and a second transfer transistor that transfers the second charge, and the control circuit controls the pixel control circuit so that during the one frame, the period during which the first transfer transistor and the second transfer transistor of the first pixel are on overlaps with at least a portion of the period during which the first transfer transistor and the second transfer transistor of the second pixel are on in the second period.

[0124] (Configuration 14) A photoelectric conversion device described in any one of configurations 1 to 13, characterized in that the pixels included in the pixel array have a plurality of photoelectric conversion elements that generate charges in response to incident light, and the memory array holds the analog signal corresponding to the charge obtained by adding up the multiple charges generated by each of the plurality of photoelectric conversion elements.

[0125] (Configuration 15) A photoelectric conversion device described in any one of configurations 1 to 14, characterized in that the analog signal includes a reset level signal and a photoelectric conversion signal, and the memory circuit included in the memory array has a first capacitive element that holds the reset level signal and a second capacitive element that holds the photoelectric conversion signal.

[0126] (Structure 16) A photoelectric conversion device described in any one of structures 1 to 15, characterized in that, in a planar view of the first substrate, a joint between the first substrate and the second substrate is arranged at a position that overlaps with at least a portion of the pixel array.

[0127] (Structure 17) A photoelectric conversion device described in any one of structures 1 to 16, characterized in that the first substrate has a first metal portion and a first insulating film, the second substrate has a second metal portion and a second insulating film, and at the bonding surfaces of the first substrate and the second substrate, a bonding portion between the first metal portion and the second metal portion and a bonding portion between the first insulating film and the second insulating film are arranged.

[0128] (Configuration 18) The photoelectric conversion device according to any one of configurations 1 to 17, wherein the second substrate has a plurality of the memory control circuits.

[0129] (Configuration 19) The photoelectric conversion device according to any one of configurations 1 to 18, wherein the first substrate or the third substrate has a plurality of the pixel control circuits.

[0130] (Configuration 20) An apparatus comprising a photoelectric conversion device according to any one of configurations 1 to 19, further comprising at least one of an optical device that guides light to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes signals output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. [Explanation of symbols]

[0131] 100 First substrate 101 pixel array 102 pixel control circuit 200 Second board 201 Memory Array 202 Memory control circuit 300 Third board 311 Analog-to-Digital (AD) Conversion Circuit

Claims

1. a first substrate having a pixel array; a second substrate having a memory array for storing analog signals output by the pixel array; a third substrate having an analog-to-digital (AD) conversion circuit that converts the analog signal output by the memory array into a digital signal; A photoelectric conversion device comprising: the second substrate has at least one memory control circuit that controls the memory array; The first substrate or the third substrate has at least one pixel control circuit that controls the pixel array. A photoelectric conversion device characterized by:

2. a first substrate having a pixel array; a second substrate having a memory array for storing analog signals output by the pixel array; a third substrate having an analog-to-digital (AD) conversion circuit that converts the analog signal output by the memory array into a digital signal; A photoelectric conversion device comprising: at least one memory control circuit that controls the memory array; and at least one pixel control circuit that controls the pixel array; At least one of a power supply voltage node electrically connected to the pixel control circuit and a power supply voltage node electrically connected to the memory control circuit, and a reference voltage node electrically connected to the pixel control circuit and a reference voltage node electrically connected to the memory control circuit are electrically isolated from each other. A photoelectric conversion device characterized by:

3. The photoelectric conversion device according to claim 1, characterized in that at least one of a power supply voltage node electrically connected to the pixel control circuit and a power supply voltage node electrically connected to the memory control circuit, and a reference voltage node electrically connected to the pixel control circuit and a reference voltage node electrically connected to the memory control circuit are electrically isolated.

4. 3. The photoelectric conversion device according to claim 1, wherein the pixel control circuit includes a pixel output circuit that outputs a control signal for controlling the pixel array, and the memory control circuit includes a memory output circuit that outputs a control signal for controlling the memory array.

5. 3. The photoelectric conversion device according to claim 1, wherein the pixels included in the pixel array each have a photoelectric conversion element that generates an electric charge in response to incident light, a floating diffusion that converts the electric charge into a signal, and an amplification transistor that amplifies the signal, and the analog signal output by the pixel array is the signal output by the amplification transistor.

6. 6. The photoelectric conversion device according to claim 5, wherein the analog signal output from the pixel array is a signal output from a source follower circuit including a current source that supplies a current to the amplifying transistor and the amplifying transistor.

7. 3. The photoelectric conversion device according to claim 1, wherein the pixel array has a plurality of pixels arranged in a plurality of rows and a plurality of columns, the memory array has a plurality of memory circuits arranged in a plurality of rows and a plurality of columns, and each of the plurality of memory circuits holds the analog signal output from each of the plurality of pixels.

8. The photoelectric conversion device according to claim 7, characterized in that the pixel control circuit controls at least one pixel among the plurality of pixels to output the analog signal to the memory array, and the memory control circuit controls at least one memory circuit among the plurality of memory circuits to output the analog signal to the AD conversion circuit.

9. the third substrate has a control circuit that controls the pixel control circuit and the memory control circuit, the plurality of pixels include first pixels arranged in a first pixel row and second pixels arranged in a second pixel row; the plurality of memory circuits include a first memory circuit arranged in a first memory row and a second memory circuit arranged in a second memory row; the control circuit controls the pixel control circuit so that a first period during which the first pixel outputs the analog signal to the first memory circuit overlaps with at least a part of a second period during which the second pixel outputs the analog signal to the second memory circuit during one frame; The photoelectric conversion device according to claim 7, characterized in that the control circuit controls the memory control circuit so that the first memory circuit and the second memory circuit sequentially output the analog signals to the AD conversion circuit during the one frame.

10. the plurality of pixels include a third pixel arranged in a third pixel row and a fourth pixel arranged in a fourth pixel row; the plurality of memory circuits include a third memory circuit arranged in a third memory row and a fourth memory circuit arranged in a fourth memory row; the control circuit controls the pixel control circuit such that a third period during which the third pixel outputs the analog signal to the third memory circuit overlaps with at least a part of a fourth period during which the fourth pixel outputs the analog signal to the fourth memory circuit, during the one frame; the control circuit controls the memory control circuit so that the first memory circuit, the second memory circuit, the third memory circuit, and the fourth memory circuit sequentially output the analog signals to the AD conversion circuit during the one frame; 10. The photoelectric conversion device according to claim 9, wherein the first period overlaps with at least a part of the third period.

11. the plurality of pixels include a third pixel arranged in a third pixel row and a fourth pixel arranged in a fourth pixel row; the plurality of memory circuits include a third memory circuit arranged in a third memory row and a fourth memory circuit arranged in a fourth memory row; the control circuit controls the pixel control circuit and the memory control circuit so that a third period during which the third pixel outputs the analog signal to the third memory circuit overlaps with at least a part of a fourth period during which the fourth pixel outputs the analog signal to the fourth memory circuit, during the one frame; the control circuit controls the memory control circuit so that the first memory circuit, the second memory circuit, the third memory circuit, and the fourth memory circuit sequentially output the analog signals to the AD conversion circuit during the one frame; 10. The photoelectric conversion device according to claim 9, wherein the first period does not overlap with the third period.

12. the first pixel and the second pixel each include a photoelectric conversion element that generates a charge in response to incident light and a transfer transistor that transfers the charge; The photoelectric conversion device according to claim 9, characterized in that the control circuit controls the pixel control circuit so that, during the one frame, the period during which the transfer transistor of the first pixel is on in the first period overlaps with at least a portion of the period during which the transfer transistor of the second pixel is on in the second period.

13. the first pixel and the second pixel each include a first photoelectric conversion element that generates a first charge in response to incident light, a first transfer transistor that transfers the first charge, a second photoelectric conversion element that generates a second charge in response to incident light, and a second transfer transistor that transfers the second charge; The photoelectric conversion device according to claim 9, characterized in that the control circuit controls the pixel control circuit so that, during the one frame, the period during which the first transfer transistor and the second transfer transistor of the first pixel are on in the first period overlaps with at least a portion of the period during which the first transfer transistor and the second transfer transistor of the second pixel are on in the second period.

14. The photoelectric conversion device according to claim 1 or 2, characterized in that the pixels included in the pixel array have a plurality of photoelectric conversion elements that generate charges in response to incident light, and the memory array holds the analog signal corresponding to an electric charge obtained by adding up the plurality of electric charges generated by each of the plurality of photoelectric conversion elements.

15. The photoelectric conversion device according to claim 1 or 2, characterized in that the analog signal includes a reset level signal and a photoelectric conversion signal, and the memory circuit included in the memory array has a first capacitive element that holds the reset level signal and a second capacitive element that holds the photoelectric conversion signal.

16. 3. The photoelectric conversion device according to claim 1, wherein a joint between the first substrate and the second substrate is arranged at a position overlapping at least a portion of the pixel array in a plan view of the first substrate.

17. The photoelectric conversion device described in claim 1 or 2, characterized in that the first substrate has a first metal portion and a first insulating film, the second substrate has a second metal portion and a second insulating film, and at the bonding surface of the first substrate and the second substrate, a bonding portion between the first metal portion and the second metal portion and a bonding portion between the first insulating film and the second insulating film are arranged.

18. 3. The photoelectric conversion device according to claim 1, wherein the second substrate has a plurality of the memory control circuits.

19. 3. The photoelectric conversion device according to claim 1, wherein the first substrate or the third substrate has a plurality of the pixel control circuits.

20. An apparatus comprising the photoelectric conversion device according to claim 1 or 2, an optical device that guides light to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

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